歯Chap1-Chap2.PDF

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2 ASIC Chip Chip Chip Proto-Type Chip

3 ASIC Design Flow(Front-End) ASIC VHDL Coding VHDL Simulation Schematic Entry Synthesis Test Vector Gen Test Vector Gen Pre-Simulation Pre-Simulation Timing Verify Timing Verify Fault Simulation Fault Simulation Verified Netlist

4 ASIC Design Flow(Back-End) Verified Netlist P&R Seed File P&R Cap Net Extract Post-Simulation Merge Phantom DRC, LVS GDS File

5 1 #include <stdioh> main( ) { int input,ouput; output=!input; } V out V inv V in (a) C (b) (c) (d) (e) (f)

6 2 main( ) { c=a+b; } C (RT)

7 1) 2) RTL 3) GATE HDL RTL HDL / HDL GATE (Front end) (Back end) 4) Backannotation (P&R) FPLD

8 VHSIC Workshop(Woods Hole, Massachusetts) VHDL Intermetrics, IBM, Texas Instruments (HDL) VHDL Version IEEE Computer Society VHDL Analysis & Standardization Group (VASG) VHDL Intermetrics IEEE VHDL IEEE Std VASG VHDL IEEE VHDL IEEE Std

9 VHDL (Computer Language ), Alphabet, (Comment) --, ( -- ) Line Line ; ; Space( ) Tab, ( : ; :, + ) Data Type User Data Type Synthesizable Coding VHDL Simulation Synthesizable Coding RTL Coding Verilog HDL

10 VHDL (Design Unit) (Design Library) (Package Declaration) / (Package Body) (Entity Declaration), (Architecture Body) (Configuration Declaration)

11 (Design Unit) (Primary Unit) Package Delcaration (Secondary Unit) Package Body Entity Declaration Architecture Body / Configuration Declaration

12 (Design Library) - Working Library : - Resource Library : (Use ) - STDSTANDARD default - STD library : VHDL standard library (STANDARD, TEXTIO) - IEEE library : IEEE standard library ( std_logic_1164, std_logic_arith) - ASIC vendor library : logic gate entity, architecture body - User-defined library : package, entity, architecture body, configuration - WORK library : directory VHDL - LIBRARY library_name ; - (Use Clause) USE library_namepackage_namedeclaration_name ; USE library_namepackage_nameall ; - / (Binding Indication) USE ENTITY library_nameentity_name(architecture_body_name) ; USE CONFIGURATION library_nameconfiguration_name ;

13 (Package Declaration & Package Body) (Package Declaration) - / / - USE (Package Body) - (Deferred constant) Package STD (VHDL ) STANDARD; TEXTIO - IEEE : STD_LOGIC_1164 : STD_LOGIC_ARITH; STD_LOGIC_UNSIGNED Microwave : WAVES_1164_DECLARATIONS; WAVES_INTERFACE; WAVES_1164_FRAMES; WAVES_1164_UTILITIE; WAVES_OBJECTS VITAL (ASIC ) : VITAL_timing; VITAL_Primitives

14 Entity Component,, Type Architecture Data Signal, Data Type Entity COMP is port( a, b: in bit; c: out bit ); end COMP; Port : Entity Design Block in, out, inout, buffer, linkage In : Input Out : Output Read( ) Inout: Bidirection ( ) Buffer: Out Read ( ) linkage:

15 (Mode) IN OUT INOUT : : : BUFFER :, LINKAGE : VHDL

16 Architecture Body( ) Architecture Entity Port Entity Architecture (1) Behavioral Style Architecture : Function Process if, for, case Design, Sequential Logic Architecture BEHAVE of COMP is begin process(a, b) begin if (a = b) then c <= 1 ; else c <= 0 ; end if ; end process ; end BEHAVE; (2) Dataflow Style Architecture : RTL(Register Transfer Level) Design

17 Architecture RTL of COMP is begin c <= not (a xor b); end RTL; (3) Structural Style Architecture Netlist Block Component Top Level Architecture STRUCTURE of COMP is signal I : bit ; component XOR2 port (x, y : in bit; z : out bit); end component; component INV port(x : in bit; z : out bit); end component; begin u0 : XOR2 port map (x => a, y => b, z => I); u1 : INV port map (x => I, z => c); end;

18 Configuration Declaration VHDL File Design Unit( Design Block) Top level Configuration Entity Architecture Component Entity, Architecture Simulator Link Test Bench Coding Architecture arch_add of adder is signal a, b, p : bit ; for u0 : and2 use entity workand(comp) ; begin u0: and2 port map(a, b, p) ;

19 Reserved Word abs access after alias all allow and architecture array assert attribute begin block body buffer bus case component configuration constant disconnect downto element else elsif end entity exit file for function generate generic group guarded if impure in initial inout is label library linkage literal loop map mod nand new next nor not null of on open or others out package port postponed private procedure process pure range record register reject rem report return rol ror select severity signal shared sla sll sra srl subtype then to transport type unaffected units until use variable wait when while with xnor xor

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21 Figure 1-1 : Example of a symbol used in a schematic (2-input, 2-output)

22 Figure 1-2 : Example of a schematic for an RSFF

23 Symbol vs Entities Entity rsff IS PORT ( set, reset : IN BIT; q, qb: INOUT BIT); END rsff; Schematic vs Architectures (Structural Model) ARCHITECTURE netlist OF rsff IS COMPONENT nand2 PORT ( a, b : IN BIT; c : OUT BIT); END COMPONENT; BEGIN U1 : nand2 PORT MAP (set, qb, q); U2 : nand2 PORT MAP (reset, q, qb); END netlist;

24 Behavioral Descriptions (Execute parallel(concurrently, not serially) ARCHITECTURE behave OF rsff IS BEGIN q <= NOT(qb AND set) AFTER 2 ns; qb <= NOT(q AND reset) AFTER 2 ns; END behave;

25 Sequential Behavior ARCHITECTURE sequential OF rsff IS BEGIN PROCESS (set, reset) BEGIN IF set = 1 AND reset = 0 THEN q <= 0 AFTER 2 ns; qb <= 1 AFTER 4 ns; ELSIF set = 0 AND reset = 1 THEN q <= 1 AFTER 4 ns; qb <= 0 AFTER 2 ns; ELSIF set = 0 AND reset = 0 THEN q <= 1 AFTER 2 ns; qb <= 1 AFTER 2 ns; END IF; END PROCESS; END sequential;

26 Configuration Statement (Architecture to use in a given simulation You can create simulatable model) CONFIGURATION rsffcon1 OF rsff IS FOR netlist FOR U1, U2 : nand2 USE ENTITY WORKmynand(version1); END FOR; END FOR; END rsscon1; WORK: library name mynand: entity version1: architecture

27 4 Behavioral Modeling o Most basic form of behavioral modeling in VHDL is signal assignment statement a <= b; a <= b after 10ns; o AND gate modeling ENTITY and2 IS PORT ( a, b : IN BIT; c : OUT BIT); END and2; ARCHITECTURE and2_behav OF and2 IS BEGIN c <= a AND b AFTER 5 ns; END and2_behav;

28 o Four-input Multiplexer modeling LIBRARY IEEE; USE IEEEstd_logic_1164ALL; ENTITY mux4 IS PORT ( i0, i1, i2, i3, a, b : IN std_logic; q : OUT std_logic); END mux4; ARCHITECTURE mux4 OF mux4 IS SIGNAL sel : INTEGER; BEGIN WITH sel SELECT q <= i0 AFTER 10 ns WHEN 0, i1 AFTER 10 ns WHEN 1, i2 AFTER 10 ns WHEN 2, i3 AFTER 10 ns WHEN 3, X AFTER 10 ns WHEN OTHERS; sel <= 0 WHEN a = 0 AND b = 0 ELSE 1 WHEN a = 1 AND b = 0 ELSE 2 WHEN a = 0 AND b = 1 ELSE 3 WHEN a = 1 AND b = 1 ELSE 4 ; END mux4;

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30 Transport Versus Inertial Delay o Inertial Delay( )

31 LIBRARY IEEE; USE IEEEstd_logic_1164ALL; ENTITY buf IS PORT (a : IN std_logic; b : OUT std_logic); END buf; ARCHITECTURE buf OF buf IS BEGIN b <= a AFTER 20 ns; END buf;

32 o Transport Delay

33 LIBRARY IEEE; USE IEEEstd_logic_1164ALL; ENTITY delay_line IS PORT (a : IN std_logic; b : OUT std_logic); END delay_line; ARCHITECTURE delay_line OF delay_line IS BEGIN b <= TRANSPORT a AFTER 20 ns; END delay_line ;

34 Simulation Deltas Delta Delay - Event B <= A; C<= B; D <= C; t t t T n t

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36 ENTITY reg IS PORT (a, clock : IN std_logic; d : OUT std_logic); END reg; ARCHITECTURE test OF reg IS SIGNAL b, c : BIT BEGIN b <= NOT(a); c <= NOT(clock AND b); d <= c AND b; END test ;

37 Drivers ARCHITECTURE test OF test IS BEGIN a <= b AFTER 10ns; a <= c AFTER 10ns; END test ; o Bad Multiple Driver Model USE WORKstd_logic_1164ALL; ENTITY mux IS PORT (i0, i1, i2, i3, a, b : IN std_logic; q : OUT std_logic); END mux; ARCHITECTURE bad OF mux IS BEGIN q <= i0 WHEN a = 0 AND b = 0 ELSE 0 ; q <= i1 WHEN a = 1 AND b = 0 ELSE 0 ; q <= i2 WHEN a = 0 AND b = 1 ELSE 0 ; q <= i3 WHEN a = 1 AND b = 1 ELSE 0 ; END bad ;

38 ARCHITECTURE better OF mux IS BEGIN q <= i0 WHEN a = 0 AND b = 0 ELSE i1 WHEN a = 1 AND b = 0 ELSE i2 WHEN a = 0 AND b = 1 ELSE i3 WHEN a = 1 AND b = 1 ELSE X ; END better;

39 Generics Entity Architecture ENTITY sample IS GENERIC(width : INTEGER := 8; bit_size : INTEGER); PORT(di : IN BIT_VECTOR(width 1 DOWNTO 0); do : OUT BIT_VECTOR(bit_size 1 DOWNTO 0); END sample; width INTGER 8 bit_size Parameter

40 Block Statement (Block Statement) (Guarded Signal) (BLOCK ) / (Guarded Signal) GUARD Register Bus blk : BLOCK (clk = 1 ) -- guarded condition BEGIN s1 <= GUARDED d WHEN enable=1 ELSE 0 ; -- Guarded Signal Assignment END BLOCK;

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42 VHDL Synthesis Synthesis VHDL, Synthesis VHDL Critical Path, Gate Count Simulation VHDL Source Code Synthesis RTL Code Synthesis Synthesis VHDL Top-Down Test Bench Synthesis Simulation Tool Synthesis, Tool Testable Design Toggle Rate Fault Simulation Synthesis Synthesis

43 VHDL Coding Synthesis D Flip Flop Entity D_FF is port (b, c : in bit; qout : out bit; end D_FF; architecture arch_d_ff of D_FF is begin process begin wait until clk event and clk = 1 ; qout <= b ; end process ; end arch_d_ff ; b c D clk Q qout

44 Latch Entity Latch is port (b, c : in bit; and_out : out bit); end Latch; architecture arch_latch of Latch is begin process(b, c) begin if (c = 1 ) then and_out <= b ; end if; end process; end arch_latch; b c D Enable Q And_out

45 Signal Variable - Simulation Signal Update Delta Time Variable - Variable Simulation Glitch - Variable Simulation VHDL Coding - buffer - if Synthesis if - Latch Synthesis if, case Coding - Reset if Clock - Reset if Clock