구리 전해도금 후 열처리에 따른 미세구조의 변화와 관련된 Electromigration 신뢰성에 관한 연구

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1 工學碩士學位論文 Electromigration-resistance related microstructural change with rapid thermal annealing of electroplated copper films 2005 年 2 月仁荷大學校大學院金屬工學科朴賢皒 - 1 -

2 工學碩士學位論文 Electromigration-resistance related microstructural change with rapid thermal annealing of electroplated copper films 2005 年 2 月指導敎授李鍾武論文工學碩士學位論文提出仁荷大學校大學院金屬工學科朴賢皒

3 論文朴賢皒碩士學位論文認定年 2 月主審副審委員

4 Abstract 목 차 I Ⅱ Cu 배선의특성 구리배선의우수성 1-2. 구리배선의 electromigration 신뢰성 wafer contaminant Electroplating Cu metallization Cu deposition 4-2 Barrier metal 4-3 low k material 4-4 Cu CMP 5. Cu Integration Damascene process 5-2. Cu line Ⅲ Ⅳ

5 국문초록 - 1 -

7 Abstract Electromigration is now a primary concern regarding reliability of ULSI because of increasing current density in miniatured devices. Effects of rapid thermal annealing (RTA) treatment on the microstructural parameters on the electromigration-resistance of electroplated Cu films using scanning electron microscopy (SEM), atomic force microscopy (AFM) and X-ray diffraction (XRD) analysis techniques. Also electron backscattered diffraction (EBSD) patterns were used to characterize the texture of the Cu thin films. It has been found that the electromigration-resistance of the electroplated Cu film is enhanced with increasing the annealing temperature in the temperature range from 200 to 500. Nitrogen is more favorable than vacuum as RTA atmosphere since nitrogen atmosphere offers lower resistivity and smoother film surface. Also the dependence of the bamboo structure on the annealing temperature and the line-width of the Cu interconnect is discussed. When the line-width is a quarter micron, a bamboo structure obtained by the RTA treatment at temperatures higher than 500. On the other hand, if it is less than 0.1μm, RTA at any temperature above 200 will result in the bamboo structure

8 Ⅰ. 서론 Year of first DRAM Shipment Minimum feature size ( μm ) Memory (Bits/Chip) Maximum number of wiring levels - logic Maximum substrate diameter (mm) Maximum interconnect length-logic(meters/chip) Metal effective resistivity (μωㆍcm) M 1 G 4 G 16 G 64 G 6 6~ ~8 8~ ,480 2,160 2,840 5,140 10, <

9 Fig. 1. Delay time vs. feature size - 2 -

10 Cost of ownership ($) Electrodeposited layer Seed layer ( CVD Cu, PVD Ti/TiN ) Electrodeposition Chemicals and consumables Full-Fill CVD 10,000A 4,000A (single via) System, fab space and labor Solid State Technology March 1998 Fig. 2. Cost-of-ownership compson for copper fill by CVD vs. copper fill by electroplating [17] - 3 -

11 (1) where S : median grain size σ : lognormal standard deviation of the grain size I 111 and I 200 are X-ray intensities of (111) and (200) diffractions, respectively

12 - 5 -

13 Ⅱ. 이론적배경 - 6 -

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15 V d = F e μ = Z eff * ee(d/kt) = Z * ej e ρ(d/kt) (2) - 8 -

16 (3) - 9 -

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20 NH 4OH H 2O 2 HF HCl H 2SO μm μm Procuction Application DRAM Design Rule ( μm ) Maximum particle size ( μm ) 16 M DRAM 24 M DRAM 256 M DRAM ~

21 Y = exp(-da) (4)

22 Chemical Brands Al Cr Cu Fe Ni H 2 O A B (31 %) C NH 4 OH A B (28 %) C H 2 SO A B (96 %) C A HCl (36 %) B HF (49 %) A

23 Power e - e - supply Anode + M M + + M M M + M M M M M Cathode Electrolyte Fig. 3. Principle of electroplating

24 - 17 -

25 전류밀도 i p i a T on T off i p : 펄스전류밀도, i a : 평균전류밀도 T on : 펄스통전시간 (on time), T off : 전류중단시간 (off time), T on +T off : 주기, T on /(T on +T off ): 듀티 (duty) 시간 Fig. 4. 정전류펄스파형

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32 Fig. 5. Cu dual damascene process: (a) low-k deposition and photolithography & etch for via and trench, (b) deposition of barrier and seed layer and Cu electroplating,and (c) chemical mechanical polishing (CMP)

33 - 26 -

34 - 27 -

35 Planarity R(um) θ Surface Smoothing 0.1~2.0 >30 Local Planarization 2.0~100 30~0.5 Global Planarization >/=100 </=

36 Fig. 6. Measurement of planarity

37 Fig. 7. Schematic represention of a wafer polishing tool. (a) Polish table with carrier assembly, and (b) Schematic view of wafer-slurry-pad system

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40 ILD Si Barrier Cu Single Level Damascene Dual Damascene Fig. 8. Comparison of single level damascene and dual damascene

41 Ⅲ. 실험방법

42 Table 8. Experimental condition Fig. 9. Process flow for the specimen preparation and characterization

43 Ⅲ. 결과및고찰 (5)

44 - 37 -

45 T m

46 W/S 0.5 Bamboo 구조 0.5 W/S 2.0 near-bamboo 구조 2.0 W/S polycrystalline 구조

47 - 40 -

48 Fig. 10. Scanning electron micrographs of the copper films after rapid thermal annealing (RTA) in vacuum for 15 sec at (a) 200, (b) 300, (c)400 and (d)

49 Fig. 11. Scanning electron micrographs of the copper films after rapid thermal annealing in N 2 for 15 sec at (a) 200, (b) 300, (c) 400 and (d)

50 Fig. 12. X-ray diffraction patterns of the copper films after rapid thermal annealing (RTA) for 15 sec at (a) 200, (b) 300, (c) 400 and (d)

51 Fig. 13. X-ray diffraction patterns of the copper films after rapid thermal annealing in N 2 for 15 sec at (a) 200, (b) 300, (c) 400 and (d)

52 - 45 -

53 Fig. 14. The X-ray diffraction peak intensity ratio of intensity I (111) / I (200) (the degree of preferred orientation) for the electroplated Cu film as a function of rapid thrmal annealing (RTA) temperature for different annealing atmospheres

54 Fig. 15. Grain size distributions of the electroplated Cu their films annealed at different temperatures : (a) 200, (b) 300, (c) 400, (d)

55 Fig. 16. The geometrical factor G of the electroplated Cu thin films as a function of RTA temperature

56 Fig. 17. Dependence of the line width / grain size ratio (W/S) of the electroplated Cu thin film on the RTA temperature for different line widths

57 (011) (111) (001) Fig. 18 : OIM mapping of the copper surface for RTN-treated (at 400 ) film

58 Fig. 19. The resistivity of the Cu thin film as a function of the RTA temperature

59 Fig. 20. The RMS surface roughness for different annealing atmospheres

60 Ⅴ. 결론

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63 참고문헌

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