Quartus-Manual_Kor.PDF

Transcription

1 (Technical) Document No: MJL-LD-Manual_Quartus Author: Version: 10 Date: Subject: Quartus Manual Start the Tutorial To start the tutorial, click one of the following tutorial icons : Module: Design Entry Compilation Timing Analysis Simulation Programming Description:! Block Editor top-level Block Design File ( bdf ) MegaWizard Plug-In Manager lower-level Verilog (v) Compiler Compiler, resource logic option assignments floorplan Timing requirements multiclock Simulation Vector Waveform File (vwf) Simulator Altera Quartus II Programmer

2 Design Entry Quartus II, assignment files,,, Entry fir_filter lower-level Block Block File (bdf), lower-level Verilog (v) lower-level megafunction Entry top-down design Session 1: Create a Project Quartus II New Project wizard New Project wizard, : 1 New Project wizard ( )! New Project wizard New Project wizard, Introduction ; New Project wizard Next 2 Browse( ) d:\qdesigns\fir_filter Browse 3 project name box, fir_filter 4 top-level design entity box top-level design entity filtref Default top-level Design Entity, top-level design entity

3 5! New Project wizard

4 6 Add All fir_filter,, Browse( ), Add! 7! Summary page Summary, EDA,,,, wizard 8 Finish! Quartus II APEX 20KE, APEX 20K OK! Top-level Design Entity Project Navigator Hierarchies

5 Session 2: Create a Block Diagram Top-level Design Entity Block diagram Top-level Design Entity (filtrefbdf) Tutorial Alteraprovided Tutorial Quartus II Block Editor, Altera -provided Copying Altera -Provided Files! 1 Create a New Block Design File filtrefbdf BDF fir_filter top-level design Entity BDF, : 1 New( )! 2 Block Diagram/Schematic File! 3 OK! Block Editor window 4 Save As ( )!

6 Save As 5 BDF! Save As ( d:\qdesigns\fir_filter) 6 File filtref! 7 Add 8 Save 2 Create the taps Block Follow these steps to create the taps block in the filtrefbdf file : filtrefbdf 1 Block Editor, Block Tool! 2 Block Editor Block Tool!

7 Undo Redo ( ) 3! 4,! Block Properties dialog box 5 General tab! 6 Name, block name Tabs instance Name box inst, default instance name 7 I/Os tab! 8 clk! 9 Add! clk Existing block I/Os

8 Add Name: clk (already entered) Reset sel[10] Newt d[70] x[70] Type: INPUT INPUT INPUT INPUT INPUT OUTPUT 11 OK! Tabs block

9 12 taps block! 13 AutoFit ( )! 3 Create the state_m, hvalues, and acc Blocks filtrefbdf state_m, hvalues, acc : state_m, hvalues, acc Block state_m : Name: Clk Reset Newt sel[10] Next First Type: INPUT INPUT INPUT OUTPUT OUTPUT OUTPUT hvalues block : Name: Type:

10 sel[10] h[20] INPUT OUTPUT acc block : Name: Xh[100] Clk First yn[70] Type: INPUT INPUT INPUT OUTPUT 2 Save (File menu) 4 Enter Primitive Symbols BDF tutorial block symbols ordinary schematic symbols Quartus II functions Symbol ; Block Editor Primitives, Library of Parameterized Modules(LPM) megafunctions filtrefbdf DFF(D flipflop) : 1 Block Editor window Symbol dialog box 2 Libraries + d:\quartus\libraries,, Storage 3 storage dff primitive Symbol Symbol

11 As an alternative to steps 2 and 3, you can simply type dff in the Name box 4 OK DFF symbol 5 DFF Block Editor 6 filtrefbdf DFFE Symbol 1 ~5 5 Enter a Megafunction Symbol Symbol lpm_mult megafunction Multiplier Symbol MegaWizard Plug-In Manager MegaWizard Plug-In Manager Altera Library of Parameterized Modules ( LPM ) megafunctions ( ) MegaWizard Plug-In customization Wizard Port Wizard Multilplier mult Symbol MegaWizard Plug-In Manager, 1 Block Editor window Symbol dialog box

12 2 Symbol dialog box MegaWizard Plug-In Manager MegaWizard Plug-In Manager 3 MegaWizard Plug-In Manager, Create a new custom megafunction variation Next > 4 4 In the Available Megafunctions list, click the + icon to expand the arithmetic folder, and then select LPM_MULT 4 Megafunctions,!, +, LPM_MULT 5 5 Specify the following responses to the remaining wizard prompts : 5! : Wizard Prompt: Which type of output file do you want to create? What name do you want for the output file? How wide should the dataa input bus be? How wide should the datab input bus be? Response: Verilog HDL d:\qdesigns\fir_filter\multv Symbol, Finish Symbol Symbol dialog box

13 7 OK! mult 8 To place the symbol, click the location you want the mult symbol to appear in the Block Editor window Symbol, mult Symbol Block Editor window 9 Save (File menu) 6 Arrange the Blocks, Primitives, and Megafunction Block Editor Window,, Megafunction Selection Tool Selection Tool ECS, ( ) megafunction

14 7 Change the Block Editor Display Options Block Editor display Block Editor, 1 (Tools )! Options 2 Block/Symbol Editor Category General 3 General, preference On/Off 4 Block Editor window Category Colors or Fonts tab 5 Ok zoom, zoom in, zoom out, fit

15 8 Enter Input & Output Pin Symbols, : 1 toolbar Symbol Tool button DFF DFFE, - Repeat-insert, ESC ( ) 2 Symbol dialog box Libraries + + d:\quartus\libraries,, 3 pin input primitive 4 OK 5 5 INPUT BDF 5! pin_name<number> Esc 6 3 OUTPUT 1 5

16 7 Save (File menu) 9 Name the Pins Pin 1!

17 2 Pin name, Pin,, pin_name clkx2! 3 OK 4 Pin 1 3 Pin Type: INPUT Rename As: clkx2 (already entered) Description: Derived clock for the FIR filter INPUT Clk Base clock for the FIR filter INPUT d[70] Data input to the FIR filter INPUT reset Reset signal for the FIR filter INPUT newt Input signal that loads the data input d[70] into the taps function

18 OUTPUT yn_out[70] The FIR filter output data OUTPUT yvalid Indicates that the yn[70] filter output of the acc function is valid OUTPUT next Indicates that the FIR filter is ready for the next 8-bit data input 5 Move the INPUT and OUTPUT pin symbols so they line up with the appropriate symbols or blocks, as shown in the following illustration: 6 Save (File menu) Session 3: Connect Symbols & Blocks BDF Symbol Blocks Selection Tool node, buses, conduit Conduits Block bus

19 Selection Tool pinstub Block linedrawing pointer, pinstub Orthogonal Node Tool pointer (Bus) Quartus II conduit Conduits Overview : Mapping filtrefbdf : 1 Connect Symbols & Blocks To draw the appropriate bus and conduit lines, follow these steps: 1 Toolbar Orthogonal Bus Tool button 2 clk pinstub!, "mapper" symbol

20 mapper I/O map 3 Symbol Block 1 2 Node Node, Orthogonal Node Tool Orthogonal Bus Tool button " Dot Draw Line From: INPUT pin clk Bus connecting INPUT pin clk to taps block INPUT pin d[70] INPUT pin reset INPUT pin newt state_m block To: taps block (already entered) state_m block Bus connecting taps block to state_m block Bus connecting taps block to state_m block Bus connecting taps block to state_m block OUTPUT pin next

21 Q output of DFFE primitive acc block OUTPUT pin yn_out[70] D input of the DFFE symbol 4 5 Tabs Block hvalues "Mapper" bus Tabs hvalues : Draw Line From: taps block Bus connecting taps block to hvalues block Bus connecting INPUT pin clk to taps block state_m block taps block To: hvalues block (already entered) state_m block acc block acc block dataa[70] input of mult symbol

22 hvalues block result[100] output of mult symbol datab[20] input of mult symbol acc block 7 tool Orthogonal Node Tool button 8 DFF D state_m

23 state_m DFF D conduit ;,, 2 View Conduit Properties properties of a conduit : 1 taps block INPUT pin clk bus, Properties( )! Conduit Properties dialog box 2 Signals tab! Connections conduit

24 3 OK 3 Draw Node Lines, 1! 2 DFF Q pinstub OUTPUT yvalid pinstub Pin Primitives 1 2

25 Draw Line From: Q output of DFF primitive INPUT pin clkx2 enable (ENA) input of the DFFE primitive To: OUTPUT pin yvalid (already entered) clock input of the DFFE primitive Node connecting the Q output of the DFF primitive to the OUTPUT pin yvalid 4 DFF clock 5 Choose Save (File menu) Overview: Mapping Signals between Blocks Quartus II : Mapping Method: "Smart" Description: I/O,

26 mapping I/O, Assigning names to nodes or buses (including "connection by name") I/O,,, ( ), 2 2 Using "mappers" to specify mappings explicitly I/O, block I/O Block I/O filtrefbdf smart mapping Quartus II smart mapping ; From: INPUT pin clk To: Block I/Os named clk in blocks that are connected to the clk pin INPUT pins d[70] INPUT pin reset Block I/Os that are named d[70] in the taps block Block I/Os named reset in the taps and state_m blocks

27 INPUT pin newt Block I/O named sel[10] in the taps block Block I/O named first in the state_m block Block I/O named next in the state_m block Block I/Os named newt in the taps and state_m blocks Block I/Os named sel[10] in the hvalues and state_m blocks Block I/Os named first in the acc block OUTPUT pin next 4 Map Signals by Name mapping : 1 Selection Tool, state_m DFF D Conduit 2 Propertie s( )! Conduit Properties dialog box General tab 3 Conduit,!

28 4 OK! conduit conduit state_m DFF D 5 DFF Primitive Clock 1 4 clk, INPUT Pin clk DFF Clo ck, 6 ( )! 5 Map Signals Explicitly Quartus II mult, 4 mapping

29 mapping, : 1 mult dataa[70], mapper mapper, Mapper Properties dialog box General tab 2,

30 3 Mappings tab 4 I/O on block x[70] 5 Signals in conduit box dataa[70] 6 To map the connection, click The mapping appears in the Existing mappings list mapping Add Mapping lisy

31 7 OK dataa[70] mapping mapper dataa[70] mapper Mapping dataa[70] mult Port

32 8 map Map Signals Explicitly 1 7 Connection: Type: I/O on Block: Signals in Conduit: Bus from the taps block to the dataa[70] input of the mult symbol (already entered) Bus from the hvalues block to the datab[20] input of the mult symbol Bus from the result[100] output of the mult symbol to the acc block Bus from the acc block to the D input of the DFFE primitive OUTPUT x[70] dataa[70] OUTPUT h[20] datab[20] INPUT xh[100] result[100] BIDIR yn[70] yn[70] 9 Save (File menu) BDF

33 Session 4: Create Verilog Design Files, Quartus II Verilog HDL, Copying Altera -Provided Files 1 Create a New Verilog Design File for the hvalues block hvalues Verilog Design File framework, 1 hvalues block 2 Create Design File from Selected Block( ) Create Design File Create Design File from Selected Block 3 File type Verilog HDL 4 5 fir_filter hvaluesv

34 6 OK Quartus II Quartus II, : Quartus II-generated Altera "! ", Verilog HDL, 7 Add the following lines to the hvaluesv file to implement the design Insert these lines just before the endmodule statement: hvaluesv endmodule reg [2:0]h; case (sel) 2'b 00 : h = 3'b 111; 2'b 01 : h = 3'b 101; 2'b 10 : h = 3'b 011; 2'b 11 : h = 3'b 001; ndcase

35 8 Save (File menu) 9 Text Editor Close (File menu) 2 Copy Verilog Design Files for Other Blocks, state_m, acc Verilog Files tapsv, state_mv, \qdesigns\fir_filter \qdesigns\tutorial accv 1 Open (File menu) Open dialog box 2 Files of type list Device Design Files 3 \qdesign\tutorial Altera -provided, tapsv, state_mv, accv! 4 Open 5 Save As (File menu) Save As dialog box 6 Save in target directory \qdesigns \fir_filter 7 Add file to current project 8 Save

36 9 Session 5: Create a Design File with the MegaWizard Plug-In Manager accv 12, lpm_add_sub accv accum MegaWizard Plug-In, Copying Altera-Provided Files MegaWizard Plug-In Altera -provided MegaWizard Plug-In lpm_add_sub Verilog HDL,! 1 MegaWizard Plug-In Manager ( ) MegaWizard Plug-In Manager 2 MegaWizard Plug-In, Create!, megafunction Next

37 3 Megafunctions, + LPM_ADD_SUB 4 : Wizard Prompt: Which type of output file do you want to create? What name do you want for the output file? How wide should the dataa and datab input buses be? Which operating mode do you want for the adder/subtractor? Is the dataa or datab input bus value a constant? Do you want any optional inputs or outputs? Do you want to pipeline the function? Response: Verilog HDL d:\qdesigns\fir_filter\accumv 12 Addition only No, both values vary Make sure all options are turned off No 5 Finish Wizard accumv, 2 Add Wizard-Generated Files to the Project fir_filter accumv multv 1 Add Files to Project (Project menu) General Settings dialog box Add Files tab 2 File name box accumv file Browse () Add 3 multv, 2

38 4 OK fir_filter, Compilation Compilation Quartus II,, Altera, ( ), Compiler,

39 timing-driven Compiler, Compilation Report Compiler Quartus II Altera Compilation Compiler,,, Last Compilation floorplan, Embedded System Block (ESB), Session 6: Specify Compiler Settings Quartus II,, Quartus II, Compiler Compiler Compiler Compiler, Compiler Settings Wizard ( ) Compiler 1 View the Compiler General Settings The General tab of the Compiler Settings dialog box allows you to select an existing group of Compiler settings for use during compilation, define and save a new group of Compiler settings, specify the compilation focus, and delete existing settings,,

40 To view the default Compiler general settings created for the current project, follow these steps:, 1 To make sure you are in Compile mode, select Compile Mode (Processing menu), Compile Mode( ) 2 Choose Compiler Settings (Processing menu) The General tab of the Compiler Settings dialog box appears automatically ( ) At this point in the tutorial, the General tab displays only the default Compiler general settings created by the Quartus II software when the project was initially created These default settings are given the name of the top-level design entity in the project, filtref, Quartus II filtref

41 2 Specify the Target Device Compiler Settings Chips & Devices 1, & 2 Family list APEX20K 3, Quartus II Yes 4 Target device Specific device selected in "Available devices" list 5 Show in "Available devices" list : a In the Package list, select PQFP b In the Pin count list, select 208 c In the Speed grade list, select 1 6 Available devices EP20K100QC208-1

42 7 Apply 3 Specify the Compiler Mode Compiler Settings Mode,,, 1 Compiler Settings dialog box Mode tab 2 Compilation level Full compilation 3 Compilation speed/disk, Smart compilation/more 4 Preserve

43 4 Specify Compiler Synthesis & Fitting Settings Compiler Settings Synthesis & Fitting Fitter 1 Compiler Settings dialog box Synthesis & Fitting tab 2 APEX Fitter Standard Fitter 3 Timing-driven, Optimize, Optimize I/O, Normal :

44 5 Specify Compiler Verification Settings Compiler Settings /, : 1 Compiler Settings dialog box Verification tab 2 Run timing analyses 3 OK, filtref Compiler Compiler, Compiler

45 Session 7: Create a Resource Assignment, MegaLAB ( bdf ) MegaLABs APEX 1 (, ROW A), 1 filtrefbdf block diagram Open (File menu) Open dialog box 2 Files of type list Device Design Files 3 Files filtrefbdf 4 Open 5 filtrefbdf block diagram taps block 6 Assignment Organizer (right button pop-up menu) Assignment Organizer, Edit, Name

46 7 Assignment Categories + 8 Locations MegaLAB row 9 Assignment MegaLAB row name list A 10 Zone, Whole 11 Add Assignment Categories list assignment 12 Ok taps block row A 13 filtrefbdf, ( ) Session 8: Compile the Design During, the The Compiler automatically locates and uses all non-design files associated with the current compilation focus, such as Include Files (inc) containing AHDL Function Prototype Statements; Memory Initialization Files (mif) or Hexadecimal Intel-format Files (hex) containing the initial content of memories; and Project, Entity, and Compiler Settings Files (psf, esf, and csf) containing project and setting information During compilation, the Compiler generates information, warning, and error messages that appear automatically in the Messages window current Compiler settings control design processing Compilation (mif) Hexadecimal - (hex) ; Project, Entity,

47 AHDL Compiler Settings Files(psf, esf, csf) (inc) ; 1 Run the Compiler filtref, 1 Start Compilation (Processing menu) Compiler filtref,, filtref Compiler, Status, Compilation Report comp uter ; Quartus II software ;, 2 Messages, errors or warnings OK Compiler Help ( ) Messages

48 (s) Locate ( ) 2 Locate the Source of a Message, Messages Processing Messages Compiler-generated, 1 Messages,!, + D:\qdesigns\fir_filter\< > \accv Found ! : acc accv /, message ; Module Declaration ;

49 3, Text Editor window Overview: Viewing the Compilation Report, Compilation Report Compilation Report 1, Summary?? The final status of the compilation?? The APEX Fitter type used?? The timing requirements, if any?? The name of the design entity compiled?? The total number of logic cells, pins, and memory used in the device Compilation Report :?? Compiler floorplan?? pin, logic cell, global, control signal, interconnect usage?? (fmax),, pin-to-pin???? The time required to process the design :

50 3 View the Compilation Report Compilation Report, : 1 Compilation Report pane + Report 2 Report, Report Quartus II : Session 9: View the Fit in the Last Compilation Floorplan Quartus II floorplan 2?? Assignments floorplan resources location assignments?? non-editable Last Compilation floorplan Compiler Each of these floorplans allows you to view information organized by interior logic cells, interior LABs, interior MegaLAB structures, and the device package top and bottom

51 floorplans, LABs, MegaLAB, 1 Open the Last Compilation Floorplan, Last Compilation floorplan Last Compilation floorplan Compiler Altera floorplan, 1 COpen Last Compilation Floorplan (Processing menu) LABs logic cell Floorplan logic cell view, neccessary Floorplan Editor 2, ( )

52 2 Display Routing Information fan-in fan-out, 1 Routing > Show Node Fan-In & Fan-Out (View menu) 2 LAB1, Logic cell, ; 3 routing delays Routing > Show Routing Delays (View menu) routing delays floorplan 4 fan-in fan-out parh, Routing > Hide Routing (View menu) 3 Display Equation Information

53 Equations window fan-in fan-out cell Equations Floorplan Editor pin, : 1,, ( ) 2 Last Compilation floorplan pin Equations pin Fan-Out 3 a Fan-Out, b Go To Equations c Equations, 4 Display the MegaLAB View floorplan MegaLAB MegaLAB (1 ESB), MegaLAB Floorplan Editor MegaLABs,

54 1 MegaLABs ( ) Floorplan Editor MegaLABs, 2 1, row A + MegaLAB_A1 MegaLAB LABs 3 Interior Cells (View menu) 4 floorplan Close (File menu) Session 10: Assign Logic to an ESB Quartus II ESB ESB APEX, ARM -based Excalibur, Mercury, MIPS -based, (RAM, ROM, FIFO, CAM), back-annotate, Compiler 1 Back-Annotate Assignments

55 , Compiler back-annotation Back-annotation back-annotate pin device 1 Back-Annotate Assignments (Processing menu) The Back- Annotate Assignments dialog box 2 Assignment(s) to back-annotate, Pin & device assignments 3 OK 2 Verify the Back-Annotated Assignments back-annotation Current Assignments floorplan, 1 Open Current Assignments Floorplan (Processing menu) Chip Current Assignments floorplan Compiler EP20K100QC208-1 Current Assignments floorplan! back-annotation, 2 Floorplan, Close (File menu) 3 Create a Logic Option Assignment

56 ESB state_m:inst1, 1 Project Navigator Hierarchies tab Project Quartus II,, 2 Hierarchies tab filtref 3 filtref hierarchy state_m:inst1 entity 4 Assignment Organizer( ) Assignment Organizer dialog box Edit, Name state_m:inst1 5 Assignment Categories list Options for Entities Only 6 Click here to add a new assignment text 7 Assignment, Name list Technology Mapper -- APEX 20K/20KE/20KC 8 Setting list Product Term

57 9 Add 10 OK Assignment Categories 4 Recompile the Design : 1 Start Compilation (Processing menu) 2, OK 5 View the Implementation of the Assignment in the Floorplan Last Compilation floorplan,

58 1 Open Last Compilation Floorplan (Processing menu) pin -out Fit 2, 3 Selection Tool, ESB A " " state_m ESB " state_m " Timing Analysis Quartus II Timing Analyzer Compiler Floorplan Editor, Quartus II,, Compilation Report Timing Analyses

59 Timing Analysis Compilation Report,, multiclock, multicycle Entry Compilation,, 11: Session 11: View Timing Analysis Results, Compilation Report, ( fmax ), registerto-register, (tsu), (th), clock-to-output ( tco ), pin -to-pin ( tpd )

60 , 1 View the f MAX Timing Analysis Report Compilation Report fmax Compilation Report fmax, 1,, ( ) 2, + 3 Timing Analyses folder fmax fmax section 4 + clk, 10 Quartus II 2 List the f MAX Timing Paths fmax 1, + fmax 1, 10

61 2 1 3 List Paths (right button pop-up menu),, Messages 4 Messages, Internal fmax + Clock< > (Smallest Clock ), Micro, Micro

62 5 + 3 Locate a Timing Path in the Floorplan Editor Last Compilation floorplan, 1 Messages, 2 Locate ( ) floorplan,

63 4 View the t SU Timing Analysis Report tsu Compilation Report tsu Compilation Report tsu, 1, + 2 Timing Analyses folder tsu section 3 pin + 4 ( ) Compilation Report Quartus II

64 Session 12: Specify Timing Requirements pin, (tsu), (th), clock-to-output (tco), pin-to-pin (tpd), (fmax),,,, Compiler Timing Settings ( ),,, Assignment Organizer ( ), Fitter timing-driven, Timing Wizard ( ) 1 Specify the Default Required f MAX fmax, fmax f MAX, : 1 Timing Settings (Project menu) Timing Settings dialog box Clock Settings tab 2 fmax 3 Default required fmax box 45 list MHz

65 fmax 2 Cut Timing Paths Timing Settings ( ) Requirements & Options, Assignment Organizer ( ) Cut Timing Path node-by-node I/O pin, : 1 Timing Settings dialog box Other Requirements & Options tab 2 Cut off feedback from I/O pins 3 OK

66 Session 13: Perform Multiclock Timing Analysis Quartus II, multiclock,, ( ) ( ) Quartus II,, 1 Create Absolute Clock Settings, 1 Timing Settings (Project menu) Timing Settings dialog box Clock Settings tab 2 Specify circuit frequency as Settings for individual clock signals 3 New New Clock Settings dialog box 4 Clock settings name box clock seeting clocka 5 ( Relationship) Independent 6 (Required fmax ) fmax 50 MHz :

67 7 OK clocka Existing 2 Create Derived Clock Settings, : 1 Timing Settings dialog box New New Clock Settings dialog box 2 Clock settings name box clockb 3 Relationship to other clock settings Based on list clocka 4, Derived Clock Requirements Derived Clock Requirements dialog box 5 2 Multiply base absolute clock fmax by 2 6 To offset Offset from base absolute clock fmax 05 list ns

68 7 OK 8 New Clock Settings dialog box Existing clock settings list clockb clock settings OK 9 Timing Settings dialog box OK 3 Assign the Clock Settings to a Pin, (s) Quartus II, Assignment Organizer ( ),, clk pin clocka, : 1 Assignment Organize r (Tools menu) Assignment Organizer dialog box By Node tab 2 Mode Edit specific entity and node settings for

69 3 Mode Name box Browse () Node Finder dialog box 4 Node Finder dialog box Filter list Pins: all Start

70 5 Nodes Found list, clk pin 6 Assignment Organizer dialog box clk pin Node Finder, OK 7 Assignment Organizer dialog box Assignment Categories list Timing 8 Click here to add a new assignment text 9 Assignment Name list make sure Clock Settings is selected 10 pin clocka Settings list 11 Add Assignment Categories list

71 12 Mode Name box Browse () Node Finder dialog box 13 from the Selected Nodes list clk pin Remove all nodes (<<) 14 Node Finder dialog box clock settings clkx2 pin Start 15 Nodes Found list clkx2 pin name 16 Assignment Organizer dialog box clkx2 pin Node Finder dialog box OK 17 clkx2 pin clockb Assignment Organizer dialog box OK Quartus II

72 4 Rerun the Timing Analysis To rerun timing analysis: 1 Start Timing Analysis (Processing menu) 2 Quartus II ( ) Quartus II timing-driven,, 3 Quartus II, OK Messages 5 View the Clock Requirements Timing Analysis Section, Timing Analyzer fmax section clock signal Clock Requirement section Clock Requirement section speed performance slack timing requirement margin positive slack( ) negative slack requirement Clkx2 Clock Requirement section : 1 Compilation Report window pane Timing Analyses folder + 2 Timing Analyses clkx2 Clock Requirement section,

73 clkx2 Clock Requirement section f MAX requirement slack multicycle path Session 14: Specify a Multicycle Path fir_filter clockb clock settings 05 ns offset requirements tutorial Multicycle timing assignment default setup, clocks registers Timing Analyzer setup Timing Analyzer register latch multiple clocks clock latch edge source register launching edge delay requirement fir_filter destination register latch edge Timing Analyzer capture

74 edge launch edge maximum delay requirement You can use the to specify a path that requires more than one to propagate Assigning a of 2 to all clocked by clkx2 allows you to override the relationship and delay the by one clock cycle, thus achieving the specified 1 clock cycle Multicycle timing assignment clkx2 registers 2 Multicycle default setup 1 latch edge timing requirements

75 1 Create a Multicycle Timing Assignment You can make individual to a single or to a path between a source and destination point When you make a to the path between two, the is automatically applied to all register-toregister paths between the two To add the to all register-to-register paths between the and clkx2 pins, follow these steps: node timing assignments 2 clock pins point-to-point assignment, assignment 2 clocks register-to-register clk clkx2 Multicycle assignment register-to-register, : 1 filtrefbdf block diagram Open (File menu) Open dialog box 2 In the Files of type list, select Device Design Files 3 Files list filtrefbdf 4 Click Open 5 filtrefbdf block diagram input pin clkx2 6 Assignment Organizer ( ) The Assignment Organizer dialog box Edit specific entity & node settings for option, Name box hierarchical path name clkx2 7 Assignment Categories list Timing + 8 Click here to add new assignment text 9 Assignment Name list Multicycle

76 10 Setting box 2 clock cycles multicycle path 2 11 Fed by box point-to-point assignment source point clk, Browse () Node Finder dialog box 12 Click Add The assignment appears in the Assignment Categories list 13 Click OK 2 Rerun Timing Analysis To rerun timing analysis: 1 Start Timing Analysis (Processing menu) 2 Quartus II, No 3 Quartus II OK timing requirements 3 View the Clock Requirements Timing Analysis Section Timing analysis Multicycle assignment timing requirements, 1 Compilation Report window Timing Analyses 2 Timing Analyses clkx2 Clock Requirement section Clock Requirement section timing requirements slack timing requirements

77 Simulation device program configure Quartus II Simulator Simulator programmed,, (vwf),,

78 Session 15: Create a Waveform File for Simulation Quartus II Waveform Editor (vwf) VWFs text-based Vector (vec) Quartus II text waveform 1 Create a New Vector Waveform File To create a VWF, follow these steps: 1 Choose New (File menu) The New dialog box appears 2 To select VWF as the file type, click the Other Files tab and select Vector Waveform File 3 Click OK The Waveform Editor opens, displaying an empty waveform file 4 To change the end time for the file, choose End Time (Time menu) 5 In the Time box, type 700 and select ns in the list 6 Click OK 7 To save the file as firvwf, choose Save As (File menu) The Save As dialog box appears 8 In the Save in list, select the fir_filter directory 9 In the File name box, type fir 10 Click Save

79 2 Add Input & Output Nodes to the File VWF Node, : 1 Auxiliary Windows > Node Finder (View menu) The Node Finder 2 Node Finder Filter list Pins: all 3 VWF Node, Start 4 Nodes Found list VWF Name column clk, clkx2, d, newt, reset, yvalid, next, and yn_out pins Shift+Click multiple contiguous names Ctrl+Click multiple non-contiguous names 5 Node Finder, Auxiliary Windows > Node Finder (View menu) 3 Edit the clk Input Node Waveform logic level behavior To edit the clk input node waveform, follow these steps:

80 1, toolbar Selection Tool button 2 clk input node "handle" of the clk node Selection Tool 3 Clock (Value menu) Clock dialog box 4 Base waveform on Clock settings list clocka

81 5 OK clk clocka clock settings 4 Edit the clkx2 Input Node Waveform clkx2 : 1 toolbar Selection Tool button 2 clkx2 input node "handle" of the clkx2 node Selection Tool 3 Choose Clock (Value menu) The Clock dialog box appears 4 Under Base waveform on, select Clock settings and select clockb in the list 5 OK clkx2 clockb clock

82 5 Edit the d Input Node Waveform To edit the d input bus waveform, follow these steps: 1 d input bus "handle" of the d bus Selection Tool bus 2 Arbitrary Value (Value menu) Arbitrary Value dialog box 3 Radix list Unsigned Decimal 4 Numeric or named value list 16 5 OK d radix, Yes d unsigned decimal 16

83 6 Edit the newt Input Node Waveform To edit the newt input node waveform, follow these steps: 1 newt waveform's handle Selection Tool 2 Clock (Value menu) Clock dialog box 3 Base waveform on Time period 4 Period box 80 ns 5 Duty Cycle list 25 6 OK newt 25% duty cycle 80 ns

84 7 Edit the reset Input Node Waveform reset : 1 reset 0 ns Selection Tool 20 ns Value > Forcing Low ( ) 2 Click the at time 20 ns on the reset input waveform and drag the pointer to time 40 ns reset 20 ns Selection Tool 40 ns

85 3 Value > Forcing High( ) 4, Fit in Window (View menu) 5 reset 40 ns Selection Tool stimulus file 6 Value > Forcing Low( ) 7 To save the file, choose Save (File menu) Session 16: Specify Simulator Settings Quartus II simulation focus entity,,, Quartus II Simulator

86 1 View the Simulator General Settings Simulator Settings dialog box (Processing menu) General tab,, Simulator, 1 Simulate Mode (Processing menu) Simulate mode Yes 2 Simulator Settings (Processing menu) Simulator Settings dialog box General tab General tab Quartus II default Simulator general settings 2 Specify Simulator Time & Vectors Settings Simulator Settings dialog box Time/Vectors tab the source of vector stimuli time period VWF

87 VEC, Tcl Console window vector stimuli To specify the simulation time period and the source of vector stimuli, follow these steps: 1 Simulator Settings dialog box, Time/Vectors tab 2 Simulation period Start time box 0 list ns 3 End time Run simulation until all vector stimuli are used 4 Vectors Source of vector stimuli D:\qdesigns\fir_filter\firvwf Browse (), Simulator Simulator source (vwf, vec tbl), Simulator vector source 5 Vectors Automatically add pins to simulation output waveforms

88 3 Specify Simulator Mode Settings Simulator Settings dialog box Mode 2 netlists netlist, 1 Simulator Settings dialog box Mode tab 2 Simulation mode list Timing Description :

89 4 Specify Simulator Options Simulator Settings dialog box Options tab, 1 Simulator Settings dialog box Options tab 2 Simulation coverage reporting :

90 3 OK, filtref Simulator Simulator, Simulator Session 17: Simulate the Design To run the simulation, follow these steps: 1 Run Simulation (Processing menu) Simulator filtref filtref Simulator firvwf

91 Simulator,, Status, Simulation Report Simulator computer Quartus II software, 2, Messages, OK error-free VWF Simulator Messages, (s) Locate ( ), Help ( ) Session 18: Analyze the Simulation Results, Simulation Report, Simulation Waveforms Simulation Report Simulation Report Simulator,, 1 View the Simulation Waveforms Section, Simulation Waveforms :

92 1,, Simulation Waveforms Report 2, Fit in Window (View menu) Waveform Editor :??, Properties ( ), Radix?? Master Bar Master Time Bar?? Toolbar Zoom Tool button Zoom In, Zoom Out, Fit in Window, and Zoom commands (View menu) zoom in/out?? 2 create a Time bar Bar 2 Create a Time Bar To create a time bar, follow these steps: 1 Selection Tool, Master Time Bar handle rising edge of the clk signal window Master Time Bar box 300 ns ns Pointer 1600 ns

93 , 1300 (Master Time Bar Selection Tool location ) 3! ) 4 Time box 160 Insert Time Bar ( Insert Time Bar dialog box list ns 5 OK Waveform time bar 1600 ns time bar Master Time Bar time bar ns time bar Programming Quartus II, Altera APEX, ARM-based Excalibur, FLEX 6000, Mercury, MIPS-based,,, blank-

94 check (MasterBlaster ByteBlasterMV ), Quartus II Compiler 1 1 MasterBlaster ByteBlasterMV Passive Serial JTAG JTAG 1 top-to-bottom, Entry, Compilation, Timing Analysis, Simulation,, (, ) 19:, Altera Session 19: Program an Altera Device,, (cdf) JTAG Passive Serial 1 CDF 1 Open the Programmer Window To open the Programmer window and create a CDF, follow these steps: 1 New (File menu) New dialog box 2 New dialog box Other Files tab 3 Other Files tab Chain Description File

95 4 CDF, OK, CDF 5 Save As (File menu) Save As dialog box 6 Save As dialog box File name box fir_filtercdf e Save as type list Chain Description File 7 CDF, Yes! Open Programmer (Processing menu)

96 2 Set Up a Passive Serial Chain Passive Serial, 1 In the Mode list of the Programmer window, select Passive Serial 2 Programming Hardware Setup Hardware Setup dialog box 3 Hardware Type list ByteBlasterMV MasterBlaster, Port and Baud rate lists port baud rate 4 Click OK 5 Click Add File The Select File dialog box appears 6 Specify the filtrefsof file, located in the project's directory, in the File name box 7 Click Open : 8 Choose Save (File menu), 5 4, 3 Configure the Device To configure the device(s), follow these steps: 1 PC, 1 :

97 MasterBlaster, PC UNIX RS- 232 RS-232 MasterBlaster!, USB PC USB or ByteBlasterMV, DB25-to-DB25 ByteBlasterMV! 2 Start, OK PC UNIX & & Quartus II Quartus II 4 Change Programming Modes APEX 20K, JTAG Passive Serial JTAG,, APEX 20K JTAG

98 5 Add a Device to a Chain JTAG Passive Serial, Examine, (pof),, options, Verify, Blank-Check, Examine To add a device to a JTAG chain, follow these steps: 1 In the Programmer window, click Add Device The Select Device dialog box appears 2 In the Select Device dialog box, select the device you want to add in the Devices list 3 Click OK 4 Choose Save (File menu) 1 3