MAX+plus II Getting Started - 무작정따라하기

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혁권 포
4 years ago
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2 / Version 20-2

3 0 MAX+plus II Digital, Schematic Capture MAX+plus II, IC, CPLD FPGA (Logic) ALTERA PLD FLEX10K Series EPF10K10QC208-4 MAX+plus II Project, Schematic, Design Compilation, Simulation - 3

4 - 4

5 1 MAX+plus II MAX+plus II Directory Folder MAX+plus II Directory C: D:, C:\max2work\exp D:\max2work\exp Directory L:\max2work\exp Directory Directory "4-Bit Binary Up/Down Counter with Synchronous Load (LDN), Asynchronous Clear, and Asynchronous Load (SETN)" 8-Bit Binary Counter - 5

PC MAX+plusII 101 1 Windows 95/98/NT/2000 ->

6 PC MAX+plusII Windows 95/98/NT/2000 -> (P) -> Altera -> MAX+plus II 101 MAX+plus II - 6

7 Figure 1 MAX+plus II MAX+plus II 2 Project 2 "Untitled1" - 7

8 Figure 2 MAX+plus Toolbar MAX+plus II 2 Toolbar Figure 3 MAX+plus II Toolbar - 8

9 2 Graphic Design File 2 (Schematic Capture) Project Graphic Editor 1 (Project name) 2 (New file) 3 Schematic 4 Logic (Symbol) 5 Symbol 6 (input pin) (output pin) 7 Node Bus 8 Pin 9 10 Target Device 11 File Compiler Error Check (Design Rule Check ) 12 File Close 4 Project - 9

10 Figure 4 Project 4 Name Project 5 Project - 10

$Figure 5 Project "Drives:" "Directories:" (L:\max2work\exp)$

11 Figure 5 Project "Drives:" "Directories:" (L:\max2work\exp) "Project Name:" Project 8counter Figure 6 Project (8count) OK 7 Project - 11

12 Figure 7 [MAX+plus II] Submenu [Graphic Editor] Schematic File 7 MAX+plus II Submenu Graphic Editor 8-12

13 Figure 8 Graphic Editor Graphic Editor Menu [File] [Save As ] - 13

14 Figure 9 GDF File Project, gdf 8countgdf OK 10 Graphic Editor - 14

15 Figure 10 8countgdf Schematic Graphic Editor Symbol Graphic Editor 11 [Symbol] [Enter Symbol Double Click], Graphic Editor 4-Bit Binary Up/Down Counter Symbol Name 4count Enter Key OK - 15

16 Figure 11 [Symbol] [Enter Symbol Double-Click] - 16

$Enter Symbol MAX+plus II Symbol Name Symbol Libraries Symbol Name Symbol Name Gate 12 Symbol Libraries \maxplus2\max2lib\prim \maxplus2\max2lib\mf \maxplus2\max2lib\mega_lpm Symbol$

17 Enter Symbol MAX+plus II Symbol Name Symbol Libraries Symbol Name Symbol Name Gate 12 Symbol Libraries \maxplus2\max2lib\prim \maxplus2\max2lib\mf \maxplus2\max2lib\mega_lpm Symbol Libraries Symbol Libraries Symbol Name Symbol Files: Symbol symbol MAX+plus II HELP Menu Megafunctions/LPM, Old-Style Macrofunctions, Primitives Figure 12 Symbol Name 12 \maxplus2\max2lib\prim 13-17

18 Figure 13 Primitives Libraries Symbol 13 Symbol Files Symbol Symbol File Box Symbol Symbol OK Graphic Editor Symbol 13 Symbol Files Box Gate \maxplus2\max2lib\prim symbol - 18

$Figure 14 "\maxplus2\max2lib\prim" symbol 14 AND Port 2 AND Gate AND2, 2 OR Gate OR2 D Flip-Flop DFF, JK Flip-Flop JKFF 12 13 Symbol Name * Symbol OK Symbol Symbol Symbol 14 INPUT PLD$

19 Figure 14 "\maxplus2\max2lib\prim" symbol 14 AND Port 2 AND Gate AND2, 2 OR Gate OR2 D Flip-Flop DFF, JK Flip-Flop JKFF Symbol Name * Symbol OK Symbol Symbol Symbol 14 INPUT PLD PIN Port OUTPUT PLD PIN Port BIDIR Data bus High, Low, High Impedace TRI state PLD PIN PIN GND "0" VCC "1" XOR TRI TRI state buffer 3 Symbol Files Box \maxplus2\max2lib\mf 15 Symbol - 19

20 Figure 15 "\maxplus2\ max2lib\mf" symbol - 20

21 Symbol Name 4count OK 16 Figure 16 4count 4count Copy Paste, 4count Ctrl Key 4count Symbol, Drag ( ) - 21

22 Figure 17 4count input 3 output

Figure 18 Line 8count Port + + 19 - - - - (Connection dot) - Symbol

23 Figure 18 Line 8count Port (Connection dot) - Symbol (Rubberbanding function on) - Symbol (Rubberbanding function off) - 23

24 Figure 19 Graphic Editor 19 INPUT PORT OUTPUT PORT Port PIN_NAME Button PIN_NAME cin, dndp, clk q1, q2, q3, q4, q5, q6, q7, q8, cout Pin 20 Figure 20 Pin Name - 24

25 PIN_NAME 20 Edit Pin Name PIN_NAME Pin Name PIN_NAME 21 Figure 21 Pin Name - 25

26 Figure 22 PLD DEVICE Device Device Family AUTO 22 Assign Device 23 Device FLEX10K Series EPF10K10QC208-4 OK Figure 23 DEVICE - 26

, 23 EPF10KQC208-4 EPF10KQC208-3 24 Fastest Speed Grades Figure 24 Device Option 23 "Show Only Fastest Speed Grades" Disable EPF10KQC208-4 EPF10KQC208-4 OK

27 , 23 EPF10KQC208-4 EPF10KQC Fastest Speed Grades Figure 24 Device Option 23 "Show Only Fastest Speed Grades" Disable EPF10KQC208-4 EPF10KQC208-4 OK FLEX10K10 Series EPF10K10QC208-3 Speed EPF10K10QC208-4 Performance Chip Schematic 25 Design Rule Check Figure 25 Design Rule Check File -> Project -> Save & Check - 27

28 26 27 Figure 26 Design Rule Check Figure 27 Design Rule Check Error Warning Message Message Processor Message Error, Warning Message Warning Warning - 28

29 3 Compiler Design Fitting Graphic Editor Figure 28 Compiler MAX+plus II (Module) Utility Project (Error) Logic Synthesize Project ALTERA Chip Fitting Project Design File File Compiler 29-29

30 Figure 29 Compiler Start Project Compiler Utility Compile - Design Binary Compiler Netlist (cnf) - - node - Project Device Device - Logic function Logic cell - Timing data Timing Simulation Data File - Fitter (Logic cell), Pin Device Programmer Object File (pof) SRAM Object File (sof) - 30

31 - Compiler 30 Figure 30 Compiler 30 Compiler Partition Module 31 Windows Figure 31 Compile, (warning) (error) ALTERA Help 31 Design Rule Check Compile - Compile Timing SNF Extractor Icon ( Simulation Stimulus ) - 31

32 - Compile Assembler Icon PLD Download Configuration Programmer - 32

33 4 Timing Simulation 32 Waveform Editor 33 Figure 32 Waveform Editor - 33

34 Figure 33 Waveform Editor Node, Node -> Insert Node ; Node Name, Node -> Enter nodes from SNF ; SNF file Node 35 Window Figure 34 Node Enter Node From SNF - 34

35 Figure 35 Enter Node From SNF Window List Button node "=>" Button Node OK Button Waveform Node Port Available Nodes & Groups: Pin Node Simulation Type Check (List ) Node Port Port "=>" Button Node File menu "Save as" <Project Name>scf In/Out Node Waveform Editor Window - 35

36 Figure 36 / Icon Toolar Pin Stimulus Vector Icon - 36

37 "0" "1" Unknown High Impedance Clock Increase/Decrease Count Value Multi Bit Signal Bus Group Bus Group Single Bit Option Grid Size grid size 30ns, 37 Waveform Waveform Editor Stimulus Grid ( Block Grid, Clock Grid ½ Period ) MAX+plus II Option "Snap to Grid", Grid Clock "Snap to Grid" Check - 37

38 Figure 37 Stimulus Waveform Editing Simulation Waveform, Simulation MAX+plus II S/W Main Menu MAX+plus II -> Simulator Simulation 38 Simulation Timing Simulation, Waveform File Simulation Input: Waveform Start Time: End Time: - 38

39 Figure 38 Simulator Start Button Simulator, Simulation Simulation Open SCF button Simulation Waveform 39 Simulation Timing Simulation Target Device Delay - 39

40 Figure 39 Simulation - 40

41 5 MAX+plus II Compile Hardware FPGA CPLD Configuration Program Hardware ALTERA PLD S/W - 41

42 - 42

43 Revision History Ver 10: Initial Release ( : ) Ver 20:, ( : ) - 43

歯Intro_alt_han_s.PDF

歯Intro_alt_han_s.PDF ALTERA & MAX+PLUS II ALTERA & ALTERA Device ALTERA MAX7000, MAX9000 FLEX8000,FLEX10K APEX20K Family MAX+PLUS II MAX+PLUS II 2 Altera & Altera Devices 4 ALTERA Programmable Logic Device Inventor of the