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1 J. of the Korean Sensors Society Vol. 18, No. 2 (2009) pp y k-x w ý» s w x Á«Á yá½ Á Á *Á w Hardware implementation of a pulse-type neuron chain with a synapse function for hodgkin-huxley model Jinwoo Jung, Bomin Kwon, Juhong Park, Jinsu Kim, Jewon Lee, Yongsu Park*, and Hanjung Song Abstract Integrated circuit of a new neuron chain with a synapse function for Hodgkin-Huxley model which is a good electrical model about a real biological neuron is implemented in a 0.5 µm 1 poly 2 metal CMOS technology. Pulse type neuron chain consist of series connected current controlled single neurons through synapses. For the realization of the single neuron, a pair of voltage mode oscillators using operational transconductance amplifiers and capacitors is used. The synapse block which is a connection element between neurons consist of a voltage-current conversion circuit using current mirror. SPICE simulation results of the proposed circuit show 160 mv amplitude pulse output and propagation of the signal through synapses. Measurements of the fabricated pulse type neuron chip in condition of ±2.5 V power supply are shown and compared with the simulated results. Key Words : Hodgkin-Huxley model, neuron chain, synapse, pulse type, CMOS 1. s w, s l y y w x. y k-x w w yƒ š w [1]. s s»,» ù. ƒ» l š s ww w» w.» w» ý mw [2]. Fig. 1(a) s y w y k-x Table 1 tx, Fig. 1(b) w ù œw (Department of Nano Engeering, Inje University) * w» w (Department of Electronics, Chungcheong University) Corresponding author : (Received : December 23, 2008, Revised : February 02, 2009 Accepted : February 25, 2009) ƒ s y w x š [3]. C dv = G Na n 3 h( V E Na ) G K n 4 ( V E K ) G l ( V E K ) +I ext dt (1) ƒ» y k, ƒ y ƒ š w w. x ¾» w z š z w» z ƒ e, m l y [4,5].» s», summing w ùkü s w. w xkƒ w (step function) (sigmoid) w w ÿ f j-vd(mcculloch-pitts) (Rosenblatt) r p ùkù» w š, w v w ƒ w q, yv w» w ù w xk v 128

2 27 Á«Á yá½ Á Á Á w Fig. 1. Hodgkin-Huxley Model of bio neron. E Na, E K, E 1 : w» G Na, G K, G l : ƒ m ƒ m, h, n : m V : s ü w w C : s I ext : ƒw mw vp x [6,7]. r w y k-x x ƒ xk ùkû. Freeman ù Victor z t w l» w w» w w œm p [8]. w y k-x xk ú z w x w w ƒ Barrenco l (hysteresis) x w z, y Luo p g l s» w z t w [9-11]. ù ¾» w w fq l y z,» s y eš. wz w 6 fulù l mw, œ, œ ƒ w w y k-x xy w x w e v w ƒ w [12]. y k-x r x s Fig. 2. Single neuron model using 2 OTAs and negative resistor. wz 18«2y,

3 호지킨-헉슬리 모델을 위한 시냅스 기능을 지닌 신경세포 체인의 하드웨어 구현 Fig. 5. Synapse circuit and simulation result. Fig. 3. Pulse type neuron chain with 3 neurons and 2 synapses for signal propagation. 28 SPICE simulation results of the pulse type neuron chain in Fig. 2.. Micro photograph of the fabricated pulse type neuron chain circuit in Fig. 3. Fig. 4. Fig. 6 델의 새로운 하드웨어적 구현을 제안한다. 트랜스콘덕 턴스 증폭회로와 커패시터, 전하공급 소자 등을 이용하 여 새로운 취합 기능을 지닌 펄스생성회로를 구현하고, 신경세포간 연결 시냅스는 전압-전류 변환 회로를 제 안한다. 3개의 신경세포 체인을 설계하여 SPICE 모의 실험을 통하여 그 특성을 살펴본다. 제안하는 신경회로 를 0.5 µm 1중 폴리 2중 금속 CMOS 공정으로 제작하 고 칩 측정결과 및 분석을 보이고 결론을 내린다. 다. 이러한 시냅스는 신경세포 펄스 출력으로 나오는 전압파형을 정류된 전류파형으로 변환시켜 입력단의 전 류 총합인 Isum에 연결되며 임계값 여부에 따라 진동성 출력의 발화 여부가 결정된다. Fig. 3는 시냅스 회로도이며, 전압단자(V+, V-)에 전 압이 인가되면 반파 정류된 특성의 전류가 출력 신호 로 나타나게 된다. 제어전압 Vb에 따라 출력 전압-전류 변환 가중치를 조절할 수 있다. 본 논문에서는 신경세포의 펄스 출력 신호전달 특성 확인을 위하여 3개의 단위신경세포와 2개의 시냅스로 연결되는 신경세포 체인을 Fig. 4와 같이 구성하였다. Fig. 5는 Fig. 4의 신경세포 체인에 대한 SPICE 모의 실험결과로, 입력 신호로서 DC 전류 100 na를 인가하였 을 경우, 첫 번째 단위 신경세포의 출력 Vout1은 240 mv 진폭의 펄스가 생성되고, 이 출력이 시냅스를 거쳐 두 번째 입력으로 인가되어 나타나는 Vout2는 150 mv 펄스 를 발화시키고 있음을 알 수 있다. 두 번째 출력 신호가 시냅스를 거쳐 마지막 신경세포 입력으로 인가되어 최 종 나타나는 출력 Vout3는 140 mv펄스를 발화시켜 정상 적으로 신호전달이 이루어지고 있음을 알 수 있다. 본 논문에서 제안한 펄스형 신경세포 체인 회로는 여러가지 측정용 단위 회로 블록과 함께 0.5 µm 1폴리 2메탈 CMOS 공정을 사용하여 4,500 µm 4,500 µm 크기의 28 pin DIP 패키지 칩 형태로 제작되었다. 2. 펄스형 신경세포 모델의 회로설계 및 칩 제작 호지킨-헉슬리의 펄스 타입 신경세포 모델은 신경회 로의 기본 요소로 사용될 수 있다. 본 논문에서 제안한 신경세포 체인의 기초가 되는 단위 신경세포 회로를 Fig. 2와 같이 구성하고 어떤 동작 특성을 나타내는지 확인하여 보았다. 단위 신경세포는 Fig. 2에 보이듯이 부성저항과 2개의 커패시터로 이루어지는 결합오실레 이터로 구현된다[13]. Fig. 2의 우측 하단의 입력단 (M23) 전류의 크기에 따라서 생성되는 출력전압의 크 기가 제어되며 입력전류의 크기에 따라 출력의 펄스 생 성여부가 결정된다. 출력 펄스 생성에 필요한 최소 입 력전류는 70~80 na정도이다. 신경세포간의 신호전달을 위한 시냅스는 광역 트랜스 콘덕터에 전류 source를 연 결하여 신경세포 펄스 출력의 발화를 유도하도록 하였 130 J. Kor. Sensors Soc., Vol. 18, No. 2, 2009

4 정진우 권보민 박주홍 김진수 이제원 박용수 송한정 29 Fig. 9. Fig. 7. Measured result of the synapse for the signal propagation. Measurement system of the fabricated pulse type neuron chain for output signal.. Measured results of 3 pulse type neuron chain. Fig. 10 Fig. 8. Fig. 9에서 시냅스의 출력 신호 특성을 살펴 보았다. 시냅스 입력에 삼각파 전압을 인가하고, 출력에 1 MΩ Measured results of a pulse type single neuron. Fig. 6은 3개의 단위 신경세포와 2개의 시냅스로 이 루어지는 신경세포 체인의 미세 현미경 사진으로 450 µm 150 µm 크기를 가지며 5 pf 용량의 커패시 터 6개와 트랜스콘덕터 6개, 부성저항 3개를 사용하였 고 입력단자, 신경세포 각각의 출력단자, 전원단자, 전 압조정 단자 등 모두 7개의 핀으로 구성되어 있다. 3. 제작된 칩 측정 및 결과분석 의 저항을 연결하여 출력 전압을 통하여 출력 전류의 파 형을 간접 측정한 결과로, 반파 정류된 형태의 파형이 나타남을 알 수 있다. 마지막으로 3개의 신경세포와 3개의 시냅스로 이루어 진 신경세포 체인의 신호전달 특성을 측정하기 위해 제 작된 Fig. 6의 회로를 측정한 결과가 Fig. 10에 나타나 있다. 순서대로 V, V, V 출력 파형을 나타내며, Y축의 단위 간격당 전압은 각각 160 mv, 20 mv, 10 mv 로 설정되어있다. 그림에서 보듯이 출력 신호감소가 일 어나지만 정상적으로 신호가 전달되는 것을 알 수 있다. 본 논문에서 제안한 펄스형 신경세포 체인의 특성에 대한 측정 결과를 Table 1과 같이 정리하였다. Table 1에서 보듯이 단위 신경세포의 각기 다른 바이어스 조 건에서 DC 입력 전압증가에 따라 발화된 출력신호의 진폭은 증가, 출력 주파수는 감소한다. out1 out2 out3 측정 및 분석은 28 pin DIP 소켓과 브레드 보드를 사용하여 Fig. 7과 같이 오실로스코프 및 반도체 소자 분석기 등을 이용하여 시냅스, 트랜스콘덕터, 부성저항 등 단위블록에 대한 DC 특성 및 신경세포 체인의 펄 스 파형에 대하여 실시하였다. Fig. 8은 신경회로에 사용된 오실레이터의 측정 결과 고찰 및 결론 로 외부 입력전압(V )을 선형 sweep전압을 인가했을 때의 출력파형으로서 SPICE 모의실험에서 확인한대로 본 논문에서, 등가회로에 대한 미분 방정식으로 활 어느 임계값(0.82 V) 이상에서 진동성 출력으로 발화됨 동전위발생을 보여주는 기존의 호지킨-헉슬리 모델을 전자회로로 구현하여 신경 칩의 기본 요소가 되는 펄 을 알 수 있다. 4. b 센서학회지 제 권 제 호 18 2,

5 y k-x w ý» s w x 30 Table 1. Measured result of neuron chain d w d d ý x (I out ) 0A~57µA s x s y p w r x s w. ƒ w w»» v z w w š, w OTA f q l, r y y j s w. - y» ý r x s w š, 0.5 µm CMOS œ w e w. d 0.82 V y k-x r x s 160 mv y y w š, ý ƒ s ƒƒ 160 mv, 20 mv, 10 mv y yƒ p ùkü y. e» y», ƒ w š w ful, œ ƒ l, œ ƒ l, œ zƒ l y q z ƒ». wz ƒ w ý», s q w w û q x», ù ƒ w l x w ƒ w. IDEC (IC Design Education Center) CAD TOOL. š x [1] D. Terman, and D. L. Wang, Global competition and local cooperation in a network of neural, Physica D., vol. 81, pp , [2] C. Mead, Analog VLSI and neural systems, Addison-wesley publishing company, [3] A. L. Hodgkin and A. F Huxley, A quantitative description of memtrane current and its application V b =0.7V V in =- 0.5~0.5V 0 A~1.5µm (I in(th) ) I in =0~5µA ƒ 50 na - (V in(th) s yvj (V out1,2,3 ) Vin = 1 Vp ) V in =0~1V 0.7V 0.82V V out1 = 240 mv V out2 = 150 mv V out3 = 140 mv V out1 = 160 mv V out2 =20mV V out3 =10mV to conduction and excitation in nerve S J. Physiol., vol. 117, pp , [4] K. Judd and K. Aihara, Pulse propagation networks: A neural network model thal uses temporal coding by action potentials, Neural Networks, vol. 6, no. 2, pp , [5] T. Taniguchi, Y. Horio and K. Aihara, An IC implementation of asynchronous pulse neuron model : in Roc, International Symposium on Nonlinear Theory and its applications, pp , Xi'an, China, [6] Y. Ota and B. M. Wilamowski, Analog implementation of pluse-coupled neural, IEEE Transactions on Neural Networks, vol. 10, no. 3, pp , [7] B. Liu and J. F. Frenzel, A CMOS neuron for VLSI circuit implementation of pulsed neural networks, Proceedings of the 28th annual conference of IEEE industrial Electronics society, vol. 4, no. 5-8, pp , Sevilla, Spain, [8] W. J. Freeman, Y. Yao, and B. Burke, Central pattern generating and recognizing in olfactory bulb: A correlation learning rule, Neural Networks, vol. 1, pp , [9] G. Moon, M. Zaghloul, and R. Newcomb, CMOS design of pulse coded adaptive neural processing element using neural-type cells, IEEE International Symposium on Circuits and Systems, pp , San Diego, CA, USA, [10] B. Linares-Barranco, E. Sanchez-Sinencio, A. Rodriguez-Vaquez, and J. L. Huertas, CMOS analog neural network systems based on oscillatory neurons, IEEE International Symposium on Circuits and Systems, pp , San Diego, CA, USA, [11] Y. Ota and B. M. Wilamowski, CMOS implementation of a pulse-coded neural network with a current controlled oscillator, IEEE International Symposium on Circuits and Systems, pp , Atlanta, GA, USA, J. Kor. Sensors Soc., Vol. 18, No. 2, 2009

6 31 Á«Á yá½ Á Á Á w [12] V. M. G. Tavares, J. C. Principe, and J. G. Harris, A silicon olfactory bulb oscillator, IEEE International Symposium on Circuits and Systems, vol. 3, pp , Geneva, Switzerland, [13] H. J. Song, and J. G. Harris, A CMOS neural oscillator using negative resistance, IEEE International symposium on Circuits and Systems, pp , Bangkok, Thailand, w ù œw (œw ) w w ù l œw w « w ù œw (œw ) w w ù l œw w y w ù œw (œw ) w w ù l œw w ½ Ê University of Florida w ù œw (œw ) w w ù l œw w w» œw (œw ) Univ. of Florida œw Univ. of Florida œw 1994 ~1997 Univ. of Florida, Research Assistant 1997 ~1997 Sandia National Laboratory of USA, Contracted Engineer 1998 ~2000 Unaxis, Inc. USA. Senior Process R&D Engineer ~x w ù œw w œw (œw ) w w œw w w œw ~ LG ( ) ~ x w» w wz 18«2y,

7 y k-x w ý» s w x 32 w w w œw (œw ) w w w œw w w w œw ~ p ~ w ~ University of Florida ~ x w ù œw 134 J. Kor. Sensors Soc., Vol. 18, No. 2, 2009

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