DE1-SoC Board

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2 DE1-SoC Board

3 Design Tools - Installation Download & Install Quartus Prime Lite Edition Quartus Prime (includes Nios II EDS) Nios II Embedded Design Suite (EDS) is automatically installed with Quartus Prime This includes Nios II Software Build Tools for Eclipse Embedded Software Device Drivers for Altera IP and HAL API ModelSim-Altera Edition (includes Starter Edition) Devices Cyclone V device support Download & Install University Program Installer for Quartus II 15.1 Download or Copy DE1-SoC_v4.0.1_SystemCD.zip from TAs 3

7 Design Board: DE1-SoC 7

8 Design Board: DE1-SoC 8

9 Design Board: DE1-SoC 9

10 Design Board: DE1-SoC 10

11 Configure the FPGA in JTAG Mode Open the Quartus II programmer and click Auto Detect 11

12 Configure the FPGA in JTAG Mode Select the *.sof file to be programmed into the FPGA device 12

13 Pin Assignment Push-buttons Check Quartus II Assignment Editor Signal Name vs. FPGA Pin# 13

14 Pin Assignment LEDs 14

15 Pin Assignment Switches 15

16 Pin Assignment Other I/Os Refer to DE1 SoC User Manual You should always refer to this manual for pin assignment For circuit outside the FPGA device, i.e. DE1 SoC board schematic, refer to DE1_SoC.pdf in DE1_SoC CD-ROM 16

17 DE1-SoC Computer 17

18 DE1-SoC Computer 18

19 Programming DE1-SoC Computer into the FPGA Connect a DE1-SoC board to your PC Power on the board In Quartus II Tools Programmer In Programmer window, click [AutoDetect] (Device 5CSEMA5) Click File tab in 5CSEMA5 device and select DE1_SoC_Computer.sof You may re-click [AutoDetect] if [Start] button is not activated 19

20 Programming DE1-SoC Computer into the FPGA 20

21 Programming DE1-SoC Computer into the FPGA Browse the DE1-SoC Computer folder There are all the development sources of DE1-SoC Computer Verilog, Qsys system builder results Application software header (address map) Document 21

22 Hello World Programming Launch Eclipse IDE to program the DE1-SoC Computer In Quartus II, [Tools] [NiosII Software Build Tools for Eclipse] In Eclipse, Make a new Project for DE1-SoC Computer [New] [NiosII Application and BSP from Template] SOPC Information File name: c:\altera\14.1\university_program\computer_systems\de1-soc\de1- SoC_Computer\verilog\Computer_System.sopcinfo CPU name: Nios2 Project Name: [NameWhatYouWant] Project template: Hello World Click [Next] [Finish] 22

23 Hello World Programming 23

24 Hello World Programming 24

25 Hello World Programming 25

26 Hello World Programming 26

27 Hello World Programming 27

28 Hello World Programming 28

29 Hello World Programming 29

30 Hello World Programming 생성된 BSP 에서 system.h 읽기 30

31 Homework 1 DE1-SoC User Manual Ch1~Ch3 읽기 DE1-SoC Schematic 을 Pin Assignment 관점에서살펴보기 FPGA device 와 SDRAM 의연결회로찾기 다음 article 의 Chapter 1-2 를읽고다음물음에답하시오. DE1-SoC Computer System with Nios II Embedded Peripheral IP User Guide 에서 PIO Core chapter 를읽고, DE1- SoC Computer System 에서 SW9-0, KEY3-0, LEDR9-0, HEX5-HEX0, Expansion ports 들은 PIO Core 로구성된다. 이들은입출력방향이각각다르게회로로구성되어있는데, 이들의구동시 register 설정방법들이어떻게다른지설명하시오. 31

32 Fixes to the BSP Generated

33 BSP (board support package) an implementation of specific support code (software) for a given board that conforms to a given operating system commonly built with a bootloader that contains the min. device support to load the OS device drivers for all the devices on the board some suppliers also provide a root file system a toolchain for building programs to run on the embedded system utilities to configure the device (while running) 33

34 BSP Editor 34

35 Default BSP : Generated for ARM Cores 35

36 Default BSP : Generated for ARM Cores 36

37 Fixed BSP for NIOS II Cores 37

38 Fixed BSP for NIOS II Cores 38

39 Re-Generate BSP & Compile your Projects 39

40 끝

MAX+plus II Getting Started - 무작정따라하기

MAX+plus II Getting Started - 무작정따라하기 무작정 따라하기 2001 10 4 / Version 20-2 0 MAX+plus II Digital, Schematic Capture MAX+plus II, IC, CPLD FPGA (Logic) ALTERA PLD FLEX10K Series EPF10K10QC208-4 MAX+plus II Project, Schematic, Design Compilation,