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1 Jurnal f the Krean Ceramic Sciety Vl. 7, N. 5, pp. 61~66, 010. DOI:10.191/KCERS Electrical Characteristics f Al /TaAlO / SiO Multi-layer Films by Different Tunnel Oxide Thicknesses and Annealing Treatment Jung Tae Park*, **, Hy June Kim *, and D Jin Chi *, *Department f Materials science and Engineering, Ynsei University, Seul 10-79, Krea **Technlgy Innvatin Grup, Samsung Electr-Mechanics, Suwn 3-73, Krea (Received July 3, 010; Revised August 16, 010; Accepted August 17, 010) l y Ì y Al /TaAlO /SiO d» p w k*, **Á½z *Á *, * w œw **» ( ; ; ) ABSTRACT In this study, Al /TaAlO /SiO (A/TAlO/S) structures with tantalum aluminate charge trap layer were fabricated fr Nand flash memry device. We evaluated the memry windw and retentin characteristic as the thickness f the tunnel xide was varied amng 3 nm, nm, and 5 nm. All tunnel xide thicknesses were measured by ellipsmeter and TEM (Transmissin Electrn Micrscpe). The A/TAlO/S multi-layer film cnsisted f 5 nm tunnel xide shwed the best result f memry windw f 1.57 V and retentin characteristics. After annealing the 5 nm tunnel xide A/TAlO/S multi-layer film at 900 C. The memry windw decreased t 1.3 V. Mrever, the TEM images cnfirmed that the thickness f multi-layer structure decreased 1.3% after annealing and the prgram cnditins f A/TAlO/S multi-layer film decreased frm 13 V t 11 V fr 100 ms. Retentin prperties f bth as-depsited and annealed films stably maintained until t 10 cycles. Key wrds : TaAlO, High-k, MOCVD, Retentin, Annealing 1. v l {, û mw { t š, { s, MP3 { e p ƒw y š. NAND Flash flating-gate w / 0, 1 w w w w.» w flatinggate w Flash 1) cell-interference stress-induced leakage current(silc) ƒ w. ) w w w» w g w flating-gate g y (Si 3 N )ù wv y (HfO ) w w SONOS Crrespnding authr : D Jin Chi drchidj@ynsei.ac.kr Tel : Fax : (Silicn-xide-nitride-xide-silicn) ƒ. 3) w, w w ƒ ƒ š, w w w., w d k y erase speed retentin p š. w w» w high-k w charge trap device ƒ y š. High-k w d w prgram/erase w d ƒ electric field j, retentin p w k. ) Ta O 5 ƒ 5 high-k ƒ w š 5). Wang š, w d Ta O 5 ã, retentin endurance p w g. w, Ta O 5, p ƒ w» j»ƒ p Ta/Al yw y ƒ p p. 6) 61

2 6 ká½z Á k y scaling erase ƒ š, ƒ w. erase, ƒw gate wƒ k y mw w d š, l y»., k y g y (SiO ) w ƒ y (Al ) w, l y w ƒ g erase w. 7) l y SiO w, l y scaling w SILC ƒ», SiO Ì yw w v ƒ. 8) 008 ITRS 9) š w, k y Al 10 nm, w d TaAlO 7nm, l y Ì y p» w l y Ì ƒƒ 3nm, mn, 5nm w. w, yw l y Ì ƒ A/TaAlO/S 900 C w, z» p w.. x Fig. 1 A/TAlO/S d x w. y», (100) n-type g r (SILTRON, Krea) t w» w ƒƒ TCE Acetne k DI water 3min dippingw» w z, 10% HF 0 sec dipping z, DI water 3min dippingw y w. SiO l y j» w Rapid Thermal Oxidatin (RTP, ULVAC MILA 3000) w 850 C g r dry O» ƒƒ 5 min, 10 min, 15 min 3nm, nm, 5nm y g. TaAlO Al chamber ü 00 C, 667 Pa (5 trr)»yw» (MOCVD) w w. TaAlO Al Tantalum tetraethxy acetylacetnate [Ta(OC H 5 ) (CH 3 COCHCOCH 3 ), Stream Chemical Inc., USA] Al-acetylacetnate [Al(CH 3 COCH 3 ) 3, Stream Chemical Inc., USA] w š, carrier gas N w. TaAlO Al MOCVD mw ƒƒ 00 C, 667 Pa (5 trr) min 10 min w 7.5 nm 10 nm y x w. w, (Pt) w, shadw mask w DC magnetrn sputtering w cm. Fig. 1. A schematic diagram f the A/TAlO/S structures with 3 nm, nm, and 5 nm tunnel xide layers. Pt/Al /TaAlO /SiO /Si ƒ Ì d w» w ellipsmeter (Gartner, L117, λ=63.8 nm) w. ƒ Ì d ƒ y w» w š w n x (HRTEM, Tecnai G F0 S-Twin) w. w, memry windw š, rententin p» w eq l p w 1MHz q capacitance vltage (C V) analyzer (Keithley 590) d w. A/TAlO/S I-V d w» w HP 15B d w. RTP z,» p y. 3. x š Fig. 00 C TaAlO w 5nm SiO l y ƒ A/TAlO/S d TEM. TEM Al, TaAlO š SiO Ì ƒƒ 10 nm, 7.5 nm š, 5nm. A/TAlO/S 3 d z ql d k. kƒ w yƒ grain bundary wƒ». Fig. 3 l y Ì ƒƒ 3nm, nm, 5nm w A/TAlO/S d C-V v ùkü. Sweep -3 V 3V¾ y š, -13 V 100 ms ƒw full erase w, w d û w. w, prgram/erase ƒƒ 5V~13V (3ms~ 1,000 ms) -5 V~-13 V (3 ms~1,000 ms) y g, prgram/erase y ü. 3 nm nm l y ƒ A/TAlO/S d prgram/erase ƒƒ 11 V 100ms/-13 V 10 ms 11 V 100 ms/-13 V 100 ms š, memry windw ƒƒ 0.8 V 1.1 V. 3 nm nm l y A/TAlO/S d, l w wz

3 터널링 산화막 두께 변화 및 열처리에 따른 Al O /TaAlO /SiO 다층막의 전기적 특성에 관한 연구 Fig.. HR-TEM image f the A/TAlO/S structure with a 5 nm thick tunnel xide layer depsited n a Si (100) substrate at 00 C. 3 Fig.. 63 Retentin characteristics f the A/TAlO/S multi-layered structures with 3 nm, nm, and 5 nm thick tunnel xide layers. TAlO/S 다층막은 prgram/erase 조건은 13 V 100 ms/-13 V 100 ms였고, Memry windw는 1.57 V였다. Prgram 동 작 시, 인가전압이 V 상승하였고, 3 nm의 터널링 산화 막을 가질 때 보다, prgram/erase의 speed는 저하되었다. 터널링 산화막의 두께가 증가가 prgram/erase의 speed와 prgram 동작 전압을 저하시킨 것을 확인할 수 있었다. 동작 전압은 높고, prgram/erase speed는 떨어지지만, memry windw가 3 nm와 nm의 터널링 산화막을 가지 는 A/TAlO/S 다층막보다는 memry windw가 큰 5 nm의 산화막을 가지는 다층막을 사용하는 것이 retentin 특성 을 개선할 수 있다. 그 이유는 매우 얇은 터널링 산화막 을 사용한다면, 터널링 산화막 (SiO )의 결함을 통하여 전 하를 잃기가 쉬워질 우려가 있으므로, retentin 특성이 저 하될 우려가 있기 때문이다. Fig. 는 prgram/erase를 10 회 cycle 한 후의, retentin 특성을 보여 준다. 각각 3 nm, nm, 5 nm의 터널링 산화 막을 가지는 A/TAlO/S 다층막의 10 회 cycle 후, memry windw는 각각 0.69 V, 1.01 V, 1.51 V였다. 3 nm, nm, 5 nm의 터널링 산화막을 가지는 A/TAlO/S 다층막의 10 회 cycle 후 memry windw는 초기 memry windw와 비교하였을 때, 각각 16%, 1%, % 저하되었다. 이러한, retentin 특성 저하는 prgram/erase 반복에 의한 터널링 산화막의 특성 저하에 기인한다. 일반적으로, Nand flash 메모리의 경우 prgram/erase 시에 Fwler-Nrdheim (F-N) Fig. 3. C-V characteristics f the A/TAlO/S multi-layered structures with 3 nm, nm, and 5 nm thick tunnel xide layers. 화막의 두께가 두꺼워지면 전자의 터널링이 쉽지 않기 때 문에 prgram/erase의 시간이 증가하는 것을 확인할 수 있 었다. 하지만, memry windw의 변화는 크게 일어나지 않음을 알 수 있었다. 5 nm의 터널링 산화막을 가지는 A/ 제 7 권 제 5호(010)

4 박정태 김효준 최두진 6 Fig. 5. HR-TEM image f the A/TAlO/S multi-layered structure with a 5 nm thick tunnel xide after annealing at 900 C. Fig. 6. 전하 터널링 방법을 사용하는데, prgram/erase시에 전 하가 터널링 산화막을 통과하면서 터널링 산화막에 물리 적인 스트레스를 주게 되어, retentin 특성을 저하시킨다. Ham에 의하면, 10년 (10 cycle 후) 후에 memry windw 는 초기 memry windw 보다 60% 정도 저하된다고 하 였다. 5 nm의 터널링 산화막을 가지는 A/TAlO/S 다층 막의 retentin 결과를 Linear fitting을 하였는데, 10 prgram/erase cycle 후, 5% 정도 retentin이 저하되는 것 을 예상할 수 있었다. 그러므로, 이 연구에서 5 nm의 터 널링 산화막을 가지는 A/TAlO/S 다층막은 retentin의 특 성이 뛰어나므로, 앞으로 high-k 전하저장층을 가지는 flash memry 후보군임을 확인할 수 있었다. Fig. 5는 00 C에서 TaAlO 를 증착을 한 5 nm의 SiO 터널링 산화막을 가지는 A/TAlO/S 다층막을 900 C에서 열 처리 한 후의 TEM 이미지을 보여준다. TEM 이미지에서 보여지듯이 Al O, TaAlO 그리고 SiO 두께는 각각 9.1 nm, 6.3 nm, 3.9 nm였고, 열처리를 하기 전 보다 막의 두께가 전체적으로.5 nm에서 19.3 nm로 1.3% 정도 감 소한 것을 확인할 수 있었다. A/TAlO/S 다층막의 3개층의 동시에 회절패턴을 보았고, 패턴에서 보여 지듯이 다층막 은 비정질 상태임을 확인할 수 있었다. 일반적으로, Ta O 의 경우는 00 nm의 두께에서 800 C에서 열처리를 하였 을 경우 결정화된다는 보고가 있었다. 하지만, 우리가 증 착한 TaAlO 전하저장층은 7.5 nm 박막이므로 nucleatin 장벽이 높고, 알루미늄을 혼합함으로써 열적 안정성을 10) 8 11) 8 3 1) 13) 한국세라믹학회지 5 C-V characteristics f the A/TAlO/S multi-layered structure with a 5 nm thick tunnel xide after annealing at 900 C. 확보하여, 결정화 되지 않은 것으로 생각된다. Fig. 6은 터널링 산화막의 두께를 5 nm로한 A/TAlO/S 다층막을 900 C에서 열처리 한 C-V 그래프를 나타낸다. 열처리된 5 nm의 터널링 산화막을 가지는 A/TAlO/S 다층 막의 prgram/erase 조건은 11 V 100 ms/-13 V 10 ms였다. 그리고, memry windw는 1.3 V로 열처리 전 memry windw 1.57 V와 비교하여 볼 때, 크게 변하지 않았다. 열 처리 하기 전과 후의 시편을 비교하였을 경우, prgram 13 V에서 11 V로 동작 전압이 V 감소하였고, erase time 은 100 ms에서 10 ms로 개선되었다. 이것은 열처리를 통 하여 터널링 산화막의 두께가 줄어 들면서, 전하의 터널 링이 쉽게 일어나기 prgram/erase가 쉬워지기 때문이다. Fig. 7을 보면, 터널링 산화막의 두께를 5 nm한 A/TAlO/ S 다층막을 900 C에서 열처리 한 후, retentin 특성을 보 여 준다. 10 회 cycle 한 후의, memry windw는 1.6 V 였다. 5 nm의 터널링 산화막을 가지는 A/TAlO/S 다층막 의 10 회 cycle 후 memry windw는 초기 memry windw 와 비교하였을 때, %가 저하되었다. Retentin 저하율은 열처리 전과 후가 크게 차이가 없었다. Memry windw 는 1.57 V에서 1.3 V로 변화가 크게 일어 나지 않았고, retentin 특성은 초기 memry windw와 비교할 때 동일 한 % 수준으로 유지하였고, 소자의 prgram의 동작 전 압과 erase의 speed가 개선되었기 때문에, 5 nm의 900 C 에서 열처리된 A/TAlO/S 다층막은 사용이 가능할 것으로 보인다.

5 l y Ì y Al /TaAlO /SiO d» p w 65 Fig. 7. Retentin characteristics f the A/TAlO/S multi-layered structure with a 5 nm thick tunnel xide after annealing at 900 C.. A/TAlO/S d z 1V ƒƒ A/cm A/cm. z A/TAlO/S d l y ̃» ƒ y w. 007 ITRS 1), 1V 10-1 A/cm rder¾ ƒ w, A/TAlO/S d flash ƒ w.. w d TaAlO w ƒ p p w p. z, SiO l y Ì ƒƒ 3nm, nm, 5nmw A/TAlO/S d» p r. l y ̃ prgram/erase speed w, retentin p w. 5 nm l y ƒ A/TAlO/S d ƒ memry windwƒ 1.57 V š, retentin p wƒ» memry windw % w p ƒ w. w, mw A/TAlO/S d Ì, w d w, û prgram/erase w š, erase speed w w. z 1V 10 - A/cm. Acknwledgment 010 w 1 w. REFERENCES Fig. 8. Leakage current densities as a functin f the applied vltage f as-depsited and annealed A/TAlO/S structures with a 5 nm thick tunnel xide layer. Fig. 8 l y Ì 5nmw A/TAlO/ S d 900 C w» z 1. K. Kim and S.Y. Lee, Memry Technlgy in the Future, Micrelectrn. Eng., 8 [9-10] (007).. M. H. White, D. A. Adams and J. Bu, On the G with SONOS, IEEE Circ. Dev. Mag., 16 [] -31 (000). 3. C. T. Swift, G. L. Chindalre, K. Harber, Harp T. S., A. Hefler, C. M. Hng, and Ingersll P. A., An Embedded 90 nm SONOS Nnvlatile Memry Utilizing Ht Electrn Prgramming and Unifrm Tunnel Erase, IEDM Tech. Dig., (00).. Y. N. Tan, W. K. Chim, B. J. Ch, and W. K. Chi, Over- Erase Phenmenn in SONOS-type Flash Memry and Its Minimizatin Using a Hafnium Oxide Charge Strage Layer, IEEE T. Electrn. Dev., 51 [7] (00). 5. X. Wang and D. L. Kwng, A Nvel High-k SONOS Memry Using TaN/Al /Ta O 5 /HfO /Si Structure fr Fast Speed and Lng Retentin Operatin, IEEE T. Electrn Dev., 53 [1] 78-8 (003). 7«5y(010)

6 66 ká½z Á 6. B. Sen, H. Wng, J. Mlina, H. Iwai, J. A. Ng, K. Kakushima, and C. K. Sarkar, Trapping Characteristics f Lanthanum Oxide Gate Dielectric Film Explred frm Temperature Dependent Current-vltage and Capacitancevltage Measurements, Slid-State Electrnics., 51 [3] (007). 7. S. H. Jen, J. H. Han, and J. H. Lee, High Wrk-functin Metal Gate and High-k Dielectrics fr Charge Trap Flash Memry Device Applicatins, IEEE T. Electrn. Dev., 5 [1] (005). 8. H. J Kim, S. Y. Cha, and D. J. Chi, A Study n the Electrical Prperties f Al /La /Al Multi-Stacked Films Using Tunnel Oxide Annealed at Varius Temperatures, J. Ceram. Sc. Jpn, 117 [5] (009). 9. Frnt-end prcessing, in Internatinal Technlgy Radmap fr Semicnductr (ITRS) (008). 10. R. Bez, E. Camerlenghi, A. Mdelli, and A. Viscnti, Intrductin t Flash memry, Prc IEEE, 91 [] (003). 11. H. C. Ham, J. H. He, C. W. Kim, and I. Chung, Characterizatin f Prgram and Erase Prperties Using Fwler nrdheim Tunneling in the 30 nm Silicn xide nitride xide silicn Transistr, Mater. Sci. Eng. B-Slid, 1-5 [SUPPL.] (005). 1. J. C. Zhu, D. T. Lu, Y. Z. Li, and Z. Liu, Effect f Sputtering Pressure and Rapid Thermal Annealing n Optical Prperties f Ta O 5 Thin Films, Trans. Nnferrus Met. Sc. China, 19 [] (009). 13. J. H. Jun, C. H. Wang, D. J. Wn, and D.J. Chi, Structural and Electrical Prperties d a La Thin Film as a Gate Dielectric, J. Kr. Phys. Sc., 1 [6] (00). 1. Frnt-end prcessing, in Internatinal Technlgy Radmap fr Semicnductr (ITRS) (007). w wz

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