. 서론,, [1]., PLL.,., SiGe, CMOS SiGe CMOS [2],[3].,,. CMOS,.. 동적주파수분할기동작조건분석 3, Miller injection-locked, static. injection-locked static [4]., 1/n 그림

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1 THE JOURNAL OF KOREAN INSTITUTE OF ELECTROMAGNETIC ENGINEERING AND SCIENCE Feb.; 27(2), ISSN (Print)ISSN X (Online) Analysis of Input/Output Transfer Characteristic to Transmit Modulated Signals through a Dynamic Frequency Divider 류성헌 박영철 Sungheon RyuYoungcheol Park 요약,.,,. 1,400 MHz, 700 MHz GHz, 2.3 GHz 1.4 GHz 14.5 dbm. V DD=2.5 V V PP=136 mv 20 mw, GHz 700 MHz. Abstract In order to transmit baseband signals through frequency dividing devices, we studied the transfer function of the device in the term of the baseband signal distortion. From the analysis, it is shown that the magnitude of the envelope signal is related to the mixer gain and the insertion loss of the low pass filter whilst the phase is the additional function with the 1/2 of the phase delay. For the purpose of the verification of the study, we designed a dynamic frequency divider at 1,400 MHz. The operating frequency range of the device is closely related to the conversion gain of mixers and the amplitude of input signal, and becomes wide as the conversion gain of mixers increases. The designed frequency divider operates between 0.9 GHz and 3.2 GHz, for 14.5 dbm input power. The circuit shows 20 mw power dissipation at V DD =2.5 V, and the simulation result shows that an amplitude modulated signal at 1,400 MHz with the modulation index of 0.9 was successfully downconverted to 700 MHz. Key words: CMOS, Miller Frequency Divider, Dynamic Frequency Divider (NRF-2014R1A2A1A ). (Department of Electronics Engineering, Hankuk University of Foreign Studies) Manuscript received August 24, 2015 ; Revised December 7, 2015 ; Accepted January 5, (ID No ) Corresponding Author: Youngcheol Park ( 170 c Copyright The Korean Institute of Electromagnetic Engineering and Science. All Rights Reserved.

2 . 서론,, [1]., PLL.,., SiGe, CMOS SiGe CMOS [2],[3].,,. CMOS,.. 동적주파수분할기동작조건분석 3, Miller injection-locked, static. injection-locked static [4]., 1/n 그림 1. Fig. 1. Block diagram of the dynamic frequency divider.,. (dynamic) 1,.,. (steady state),,, cos cos (1). cos cos cos cos (2), A.. cos (3) 171

3 THE JOURNAL OF KOREAN INSTITUTE OF ELECTROMAGNETIC ENGINEERING AND SCIENCE. vol. 27, no. 2, Feb (1) (3) [5]., (1) (3). 1/2, 1/2. cos (6). (7) (4) (5),.. 동적주파수분할기설계 1.4 GHz 700 MHz 1/2 m CMOS [6],[7]. 2, M1, M2-M3, M4-M7, M8-M9, M10-M11, M12-M15, m, m, m, m, m. V DD 2.5 V, V PP=136 mv I total =16.1 ma, 20 mw. 1,,. (10) (8) (10), 1/2,.,.,, (6). cos (9) 그림 2. Fig. 2. Schematic of the dynamic frequency divider. 172

4 , RC LC., (10). bias. M4-M7 1.3 pf, M8-M9 0.6 pf 1.9 pf, 700 MHz 27 nh., 27 nh layout M4-M6, M5-M7 3.5 pf 9.5 nh. 3 m m., 4. S GHz 2.39 db, DC 8.5 db DC S 21,. 5 ( ) 1.4 GHz, V PP =136 mv ( ) 0.7 GHz, V PP = 그림 4. Fig. 4. Frequency response of the band-pass filter. 그림 5. Fig. 5. Transient response of the dynamic frequency divider. 286 mv, 6.4 db 1/2.. 모의실험및분석 그림 3. Fig. 3. Layout of the dynamic frequency divider GHz 1 V db. 7 input sensitivity. 1.4 GHz 14.5 dbm, 0.9 GHz 3.2 GHz 1/2 2.3 GHz. 173

5 THE JOURNAL OF KOREAN INSTITUTE OF ELECTROMAGNETIC ENGINEERING AND SCIENCE. vol. 27, no. 2, Feb ,. [8].. 결론 그림 6. Fig. 6. Output spectrum of the dynamic frequency divider. 그림 7. input sensitivity Fig. 7. Input sensitivity of the dynamic frequency divider tone 8. 그림 8. Fig. 8. Input and output modulated waveform of the frequency divider., m CMOS LC 1.4 GHz. 0.9 GHz 3.2 GHz 1/2 2.3 GHz., V DD =2.5 V 20 mw, 1.4 GHz 14.5 dbm. 1/2 700 MHz, tone. References [1] Youngcheol Park, "Class-F technique as applied to active frequency multiplier designs", IEEE Transactions on Microwave Theory and Techniques, vol. 57, no. 12, pp , Dec [2] R. L. Miller, "Fractional-frequency generators utilizing regenerative modulation", Proc. Inst. Radio Eng., vol. 27, pp , Jul [3] J. Mullrich, W. Klein, R. Khlifi, and H. M. Rein, "SiGe regenerative frequency divider operating up to 63 GHz", Electronics Letters, 30th, vol. 35, no. 20, pp , Sep [4] Harsh Joshi, Sanjeev M. Ranjan, and Vijay Nath, "Design 174

6 of high speed flip-flop based frequency divider for GHz PLL system: theory and design techniques in 250 nm CMOS technology", IJECSE, vol. 1, no. 3, pp , Aug [5] J. Lee, B. Razavi, "A 40 GHz frequency divider in 0.18 um CMOS technology", IEEE J. Solid-State Circuits, vol. 39, no. 4, pp , Apr [6] Sebastien Chartier, Liu Liu, Gerhard Fischer, Srdjan Glisic, Holger Hohnemann, Andreas Trasser, and Hermann Schumacher, "SiGe millimeter-wave dynamic frequency divider with enhanced sensitivity incorporating a trans-impedance stage", European Microwave IC Conference, pp , Oct [7] Z. Gu, A. Thiede, "18 GHz low-power CMOS static frequency divider", Electronics Letters, 2nd Ed., vol. 39, no. 20, pp , Oct [8] Y. Park, H. Yoon, "Time- and frequency-domain optimization of sparse multisine coefficients for nonlinear amplifier characterization", J. of Electromagnetic Eng. and Science, vol. 15, no. 1, pp , Jan [9],, "MOSFET 700 MHz dynamic frequency divider ",, 38(6), [10],, "Miller AM ",, 25(24), : () 2015: () [ 주관심분야 ], RF Power Amplifier, : ( ) : : Georgia Inst. Tech. () : : [ 주관심분야 ],,,, / 175

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