SW_faq2000번역.PDF

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1 FREUENTLY ASKED UESTIONS ON SPEED2000 Table of Contents EDA signal integrity tool (vias) (via) /, SI, / SPEED2000 SPEED2000 EDA signal integrity tool, ( (via),, / ), EDA,

2 1,, / 2 FEM, PEEC, MOM, FDTD EM 3 EM,, 4 SPEED2000 1),, ( / ) 2),,

3 3) partial inductances / IBM, Electrical Performance of Electronic Packaging (EPEP) Electronic Components and Technology Conference (ECTC) ECTC, pp , Measurement and Simulation of Si-multaneous Switching Noise in the M ulti-reference-plane Package EPEP, pp ,, A New Approach to Signal Integrity Analysis of High-Speed Packag-ing PSPICE SPEED2000

4 (vias) (via),,,,, Significance of Electromagneti c Coupling Through Vias in Electronics Packaging, Validity of Mutual Inductor Model for Electromag netic Coupling between Vias in Integrated-Circuit Packages and Printed Circuit Boards, SPEED2000 /, SI, / / /,, / /,, SPEED2000 / SPEED2000 /, /

5 SPEED2000 /, / / / /, /,,,, / /, IC/Package Desi-gn Integration 1998 Shorting Via A-rrays for the Elimination of Pack age Resonance to Red-uce Power Supply Noise in Multi-layered Area Array IC Packages EMI SPEED2000 SPEED2000 SPEED2000,,,

6 SPEED2000, SPEED2000 Simulation Package for Electrical Evaluation & Design

7 uestions and Answers, SPEED97/2000

8 25-1 Tel: Fax: : DECAP(DECOUPLING CAPACITOR) SELECTION, PAPER ON WEB > Sigrity >, > >,? [Fang], SPEED2000,, AC short-circuit,,,,, 2 : PROBABILITY DISTRIBUTION > (Y)? >? , power/ ground noise 10mV 1V, nbar=100 10mV (nbar SPDSIM ), mV~60mV, ( ) 1 Y Y Decap, noise 3 : PEAK/AVERAGE DISTRIBUTION BUTTON IN SPDSIM > case study, peak/average button/ >function 3D? SPDSIM, SPDSIM SPDSIM Setup : Distribution, Distribution 4 : USE ORIGIN 50 TO IMPORT SPDSIM SCUR DATA FILE > Origin cur? SPDSIM cur Origin, File : Import : ASCII Options ASCII Import Options, 1 Skip main header, number of lines: 1 2 Specify known subheader lines, 3 3 When non-numeric is found in numeric fields Start new worksheet/column WWWCMS-TECHCOKR

25-1 Tel: 031-711-8292 Fax: 031-711-8431 E-mail:webmaster@cms-techcokr 4 # of

9 25-1 Tel: Fax: # of column 2, Import, 5 : HOW TO MODEL CIRCUIT ACROSS THE EDGE OF THE PLANES >, PCB > SPEED2000, (a),, / >? (a), (a) ckt (b),, () 1/4 1/2 (a) (b) : (a) Ckt (b) (1) Open circuit Open circuit (2) Short circuit Ckt, (b) ckt (3) Lumped component WWWCMS-TECHCOKR

10 25-1 Tel: Fax: : WHY USE GAUSSIAN SOURCE TO CALCULATE INPUT IMPEDANCE >?,, ( (smooth)),, 0, (3D, ) spd,, 7 : HOW TO MODEL A DECOUPLING CAPACITOR CONNECTING TWO SPLIT PLANES > Decap, decap >? Figure 1, SPEED2000 Figure 2 SPEED2000,,,, Figure 1 a, b 0 a, b,, SPEED2000 SPEED2000 Figure 2 Figure 1,, a, b WWWCMS-TECHCOKR

25-1 Tel: 031-711-8292 Fax: 031-711-8431 E-mail:webmaster@cms-techcokr 8 : A SMALL POWER ISLAND ON MY GROUND PLANE > B A A B A ( ), B SPEED2000, B A B ( ) A, A, / - 9 : HOW TO CALCULATE IR DROP ON

11 25-1 Tel: Fax: : A SMALL POWER ISLAND ON MY GROUND PLANE > B A A B A ( ), B SPEED2000, B A B ( ) A, A, / - 9 : HOW TO CALCULATE IR DROP ON THE PLANE? > enable initial DC analysis, DC? enable initial DC analysis DC (node), IR (DC ) IR, (step function), (flu ctuation) DC 10 : IS THE VIA-HOLE CONSIDERED IN SPEED2000? > SPDGEN via-hole? SPEED2000, via-hole, via-hole WWWCMS-TECHCOKR

25-1 Tel: 031-711-8292 Fax: 031-711-8431 E-mail:webmaster@cms-techcokr (14mil via 40mil anti-pad PCB 01pF ) TDR 40ps 200ps via-hole Via-hole full-wave EM field, SPEED2000 via-hole,, C L, SPEED2000 11

12 25-1 Tel: Fax: (14mil via 40mil anti-pad PCB 01pF ) TDR 40ps 200ps via-hole Via-hole full-wave EM field, SPEED2000 via-hole,, C L, SPEED : DIELECTRIC LAYER ON TOP OF THE TOP LAYER > SPEED2000 >, 1, >, > Case 1 : without specifying an air layer Case 2 : with an air layer specified SPDGEN,, Case 1 Case 2 12 : HOW TO COMBINE A CHIP PACKAGE WITH A BOARD INTO A SINGLE SPD MODEL > Cadence APD MCM, > Allegro BRD PCB SPEED2000 >? [Answer] SPDGEN2000 SPEED97 : 1,, Allegro EMBEDDED_PLANE 2 BRD extractexe packagerul TEXT (SPEED97 B ) WWWCMS-TECHCOKR

13 25-1 Tel: Fax: SPEED97 brd2spdexe,, TEXT SPD, SPEED97 B 4,, : 1, EMBEDDED_PLANE 2 3 extractexe packagerul(speed97 B ), MCM TEXT 4 SPEED97 brd2spdexe,, TEXT SPD, SPEED97 B 5,, SPD : nodes, traces, vias, via radius 4 SPD : 1 SPD SPDGEN 2 / 3, 13 : CAPACITIVE COUPLING BETWEEN VIAS > SPEED97 SSO, > long via, > ANSOFT uick 3D Parameter Extractor >3 200mil, 20mil S11, S21 Pin notation: >ANSOFT uick 3D Parameter Extractor L11 247nH, L12 115nH, L13 >094nH C pF, C pF S-parameter > 1 (1,2), 2 (3,2), > > 2, >ANSOFT PI-networked CLC, >S11 SPEED97 S12 >SPEED97, >, SPEED97 ANSOFT > WWWCMS-TECHCOKR

14 25-1 Tel: Fax: >, >, >, S12 [Answer] 1,,,, 2 SPEED97/2000,,, SPEED97 /2000 capactive coupling 1~15,,, 1~15, SPEED97/2000,, tool 3, 200mil 50mil SPEED97/2000 CLC S12, 200mil 50mil, SPEED97 tool 4,, uick3d 5, 1~15, SPEED97/2000, 14 : VIAS IN RELIEF > 3 relief, >? conductivity > [Fang] Relief relief SPEED2000, relief ( ), relief relief 15 :?? [Answer],,,,,, SPEED97/ dx > 4R (4R) (dx), dx > 4R WWWCMS-TECHCOKR

15 25-1 Tel: Fax: dx < 4R (4R) (dx), (dx<4r),, 70 70, dx 25R,, 51, 49, 45, 37,, 4 16 : WHY USE GAUSSIAN SOURCE TO MODEL THE EDGE CONNECTOR? >, > >? 6, App5spd 0V , 17 : HOW TO ESTIMATE THE SIMULATION MEMORY REUIREMENT? >,? / Memory(in bytes) = Mesh_X * Mesh_Y * Number_of_Plane_Pair * 32 * 8 : , 4, 3 plane pair : 300*150*3*32*8 = bytes, 35M WWWCMS-TECHCOKR

ApplicationKorean.PDF

ApplicationKorean.PDF Sigrity Application Notes Example 1 : Power and ground voltage fluctuation caused by current in a via passing through two metal planes Example 2 : Power/ground noise and coupling in an integrated-circuit