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1 Preliminary Datasheet High-Performance Processor Advanced Digital Chips, Inc. adstar-l Hardware Manual December 5, 217 Subject to Change Without Notice. 215 Advanced Digital Chips, Inc. All right reserved. No part of this document may be reproduced in any form without written permission from Advanced Digital Chips, Inc. Advanced Digital Chips, Inc. reserves the right to change in its products or product specification to improve function or design at any time, without notice. Office Korea (Headquarters) 22F, Bldg A, Keumkang Penterium IT Tower, 81 Gwanyang-dong, Dongan-gu, Anyang-si, Gyeonggi-do, 431-6, Korea T : / F : [email protected] China Peak Microtech Co., Ltd 北京芯首电子科技有限公司 [email protected]

2 Contents 1 DESCRIPTIONS AND FEATURES General Description Features BLOCK DIAGRAM & PIN DESCRIPTIONS Block Diagram Pin Layout Pin Definition Pin Description MEMORY ARCHITECTURE AND BOOTING MODES Memory Map Embedded Memories Internal SRAM for Instruction Internal SRAM for Data Internal SRAM Registers Internal SRAM Register Setting Peripheral Memory Map Boot Modes Debugger Mode Boot Mode Serial Flash Boot NAND Flash Boot SWD Seleciton SYSTEM CONTROL Reset Control System Reset Power On Start Time Clock control Main oscillator RTC oscillator (32KHz) PLL PLL PLLx Clock Change Clock gating Additional Clock Divider USB Clock TFT LCD Clock Sound Mixer Clock Protection Mechanism Power modes RUN mode Sleep mode Stop mode Shutdown mode Static mode System Control Registers System Control Global Lock Register (GLOCK) System Control Write Enable Register (WREN) Halt Register Halt Status Register Interrupt Wake up Enable Register Event Wake up Enable Register PMC Status Register OSC Stable Counter Register Clock Control Register (CLKCON) PLL Control Register (PLLCON) Clock Divider Control Register (CLKDCON) AHB Clock Enable Register (HCLKEN) APB Clock Enable Register (PCLKEN) USB PHY Control Register (USBPHYCON) Boot mode status register(bmst) Boot mode config register(bmct) HCLK clock divide register(hclkdiv) CLK16_ clock divide register(clk16div) Contents Copyright 215, Advanced Digital Chips, Inc.

3 CLK16_1 clock divide register(clk16div1) LCD clock divide register(lcddiv) Sound Mixer clock divide register(smdiv) PLL1 Control Register (PLLCON1) SPI FLASH MEMORY CONTROLLER Introduction Feature Functional Description Register Interface Memory Interface Internal Flash Memory Internal Flash Memory Commands Flash Status Register Chip Erasing Flash memory Sector/Block Erasing Flash memory Programing Flash memory Reading Flash memory Power Down and Release Power Down Flash Mode Register (FLMOD) Flash Baudrate Register (FLBRT) Flash Chip Select High Pulse Width Register (FLCSH) Flash WIP Check Period Register (FLWCP) Flash Clock Delay Register (FLCKDLY) Register Description Flash Mode Register (FLMOD) Flash Baudrate Register (FLBRT) Flash Chip Select High Pulse Width Register (FLCSH) Flash Performance Enhance Mode Register (FLPEM) Flash Command Register (FLCMD) Flash Status Register (FLSTS) Flash Sector Erase Address Register (FLSEA) Flash Block Erase Address Register (FLBEA) Flash Data Register (FLDAT) Flash WIP Check Period Register (FLWCP) Flash Clock Delay Register (FLCKDLY) Flash 2nd Status Register (FLSTS2) Flash ID Read Register (FLIDR) Flash Memory Size Write Register (SFMSIZE) GPIO (GENERAL PURPOSE I/O) Features Block Diagram Functional Description Port Control Port Edge Detect Register Description Port Direction Registers ( GPxDIR ) Port Direction Output Mode Setting Registers ( GPxODIR ) Port Direction Input Mode Setting Registers ( GPxIDIR ) Port Output Data Level Registers ( GPxOLEV ) Port Output Data Registers ( GPxDOUT ) Port Output Data High Level Setting Registers ( GPxOHIGH ) Port Output Data Low Level Setting Registers ( GPxOLOW ) Port Input Data Level Registers ( GPxILEV ) Port Pull-up Status Registers ( GPxPUS ) Port Pull-up Enable Registers ( GPxPUEN ) Port Pull-up Disable Registers ( GPxPUDIS ) Port Rising Edge Detect Registers ( GPxRED ) Port Falling Edge Detect Registers ( GPxFED ) Port Edge Detect Status Registers ( GPxEDS ) Port Open Drain Mode Control Registers ( GPxODM ) Port Schmitt Input Enable Registers ( GPxSHMT ) Port Pull-down Status Registers ( GPxPDS ) Port Pull-down Enable Registers ( GPxPDEN ) Port Pull-down Disable Registers ( GPxPDDIS ) PIN MUX Pin Mux register INTERRUPT CONTROLLER Features Copyright 215, Advanced Digital Chips, Inc. 3 Contents

4 8.2 Functional Description Interrupt Vector and Priority External Interrupt (EIRQx) Internal Interrupt Mode Interrupt Pending and Interrupt Pending Clear Interrupt Enable Interrupt Mask Set/Clear Register Register Description Interrupt Pending Clear Register (INTPENDCLR) External Interrupt Mode and External PIN Level Register (EINTMOD) Internal Interrupt Mode Register (IINTMODn) Interrupt Pending Register (INTPENDn) Interrupt Enable Register (INTENn) Interrupt Mask Status Register (INTMASKn) Interrupt Mask Set Register (INTMASKSETn) Interrupt Mask Clear Register (INTMASKCLRn) CORE TIMER Features bit Pre-scaler with clock source selection Timer/Counter Timer Control Registers Timer Reset Control Register (TMRST) Timer Control Registers (TMCON) Timer Counter Registers (TMCNT ) Timer Interrupt waveform WATCHDOG TIMER Register Description Watchdog Timer Control Register (WDTCTRL) Watchdog Timer Counter Value Register (WDTCNT) Watchdog Timer Lock Value Register (WDTLOCK) Operational Flow Diagrams TIMERS Features Functional Description bit Pre-scaler with clock source selection Timer/Counter Pulse Width Modulation (PWM) Capture Register Description Timer Pre-scale Control Registers ( TPxCTRL ) Timer Control Registers ( TMxCTRL) Timer Counter / PWM Period Registers ( TMxCNT ) Capture Counter Registers / PWM Duty Registers ( TMxDUT ) PWM Pulse Count Registers ( TMxPUL ) REAL TIMER CLOCK RTC Features RTC diagram RTC Calibration (function diagram) Real Time Counter Control Register Real Time Counter Control Register (RTCCON_1) Real Time Counter Control Register (RTCCON_2) Real Time Counter Register Real Time Counter Sec Register (RSEC) Real Time Counter Min Register (RMIN) Real Time Counter Hour Register (RHOUR) Real Time Counter Day Register (RDAY) Real Time Counter Week Register (RWEEK) Real Time Counter Month Register (RMONTH) Real Time Counter Year Register (RYEAR) Real Time Alarm Register Real Time Alarm Register (RALM_S) Real Time Alarm Register (RALM_M) Real Time Alarm Register (RALM_H) Real Time Alarm Register (RALM_D) Real Time Alarm Register (RALM_MO) Real Time Back up Register Real Time Back up Register (BACKUP_) Real Time Back up Register (BACKUP_1) Contents Copyright 215, Advanced Digital Chips, Inc.

5 Real Time Back up Register (BACKUP_2) Real Time Back up Register (BACKUP_3) Real Time Back up Register (BACKUP1_) Real Time Back up Register (BACKUP1_1) Real Time Back up Register (BACKUP1_2) Real Time Back up Register (BACKUP1_3) Real Time Back up Register (BACKUP2_) Real Time Back up Register (BACKUP2_1) Real Time Back up Register (BACKUP2_2) Real Time Back up Register (BACKUP2_3) Real Time Back up Register (BACKUP3_) Real Time Back up Register (BACKUP3_1) Real Time Back up Register (BACKUP3_2) Real Time Back up Register (BACKUP3_3) Real Time PMU Controller Register (PMUCON) RTC interrupt timing diagram Alarm interrupt operation sec interrupt operation /2 interrupt operation /4 interrupt operation COPROCESSOR Features Coprocessor Description Coprocessor Control Registers System Coprocessor Status Register (SCPR15) Master Command Register (SCPR15) Supervisor Stack Point Register (SCPR14) User Stack Point Register (SCPR13) Vector Base Register (SCPR12) Invalidate Cache Line and Lock Register (SCPR11) Memory Bank Configuration Register (SCPR9) General Access Point Data Register (SCPR4) General Access Point Index Register (SCPR3) UART Features Block Diagram Functional Description Serial Data Format UART Baud Rate Register Summery Register Description UART Channel Receiver Buffer Registers ( UxRB ) UART Channel Transmitter Holding Registers ( UxTH ) UART Channel Interrupt Enable Registers ( UxIE ) UART Channel Interrupt Identification Register ( UxII ) UART Channel FIFO Control Register ( UxFC ) UART Channel Line Control Register ( UxLC ) UART Channel Line Status Register ( UxLS ) UART Channel Divisor Latch LSB Register ( UxDLL ) UART Channel Divisor Latch MSB Register ( UxDLM ) UART Channel Fractional Divider Register ( UxFDR ) DMA Features Block Description Functional Description DMA Operation Linked List Operation Auto Reload Operation Peripheral Interface Register Description DMA Interrupt Status ( DMAIntStatus ) DMA Terminal Count Interrupt Status ( DMATCIntStatus ) DMA Terminal Count Interrupt Clear ( DMATCIntClr ) DMA Error Interrupt Status ( DMAErrorIntStatus ) DMA Error Interrupt Clear ( DMAErrorIntClr ) DMA Block Interrupt Status ( DMABlockIntStatus ) DMA Block Interrupt Clear ( DMABlockIntClr ) DMA Raw Terminal Count Interrupt Status ( DMARawTCIntStatus ) DMA Raw Error Interrupt Status ( DMARawErrorIntStatus ) DMA Enabled Channel Status ( DMAEnbldChn ) Copyright 215, Advanced Digital Chips, Inc. 5 Contents

6 DMA Software Burst Request ( DMASoftBReq ) DMA Software Single Request ( DMASoftSReq ) DMA Software Last Burst Request ( DMASoftLBReq ) DMA Software Last Single Request ( DMASoftLSReq ) Channel Source Address Register ( ChnSrcAddr ) Channel Destination Address Register ( ChnDstAddr ) Channel Linked List Item Register ( ChnLLI ) Channel Control Register ( ChnCntl ) Channel Configuration Register ( ChnCfg ) Channel Source Gather Address Register ( ChnSrcGaAddr ) Channel Destination Scatter Address Register ( ChnDstScaAddr ) Channel Auto Reload Count Register ( ChnAutoReloadCnt ) Program Guide Sumary of Register Programming Sequence Program Consideration LOCAL MEMORY CONTROLLER Register Description SDRAM Control Register (MEMCON) SDRAM Clock Delay Register (MEMCLKCON) SDRAM Refresh Control Register (MEMREFCON) NAND FLASH CONTROLLER Features Functional Description Data Read/Write DMA Operation ECC Operation ECC Encoding ECC Decoding by S/W ECC Decoding by H/W (Auto ECC Decoding) Register Description NAND Flash Memory Control Register (NFCTRL) NAND Flash Memory Command Set Register (NFCMD) NAND Flash Memory Address Register (NFADR) NAND Flash Memory Data Register (NFDATA) NAND Flash Memory Operation Status Register (NFSTAT) NAND Flash Memory ECC(Error Correction Code) Register (NFECC) NAND Flash Memory Configuration Register (NFCFG) NAND Flash Memory ECC Code for LSN data (NFECCL) NAND Flash Memory Error Corrected Data Register (NFECD) NAND Flash Memory Spare Address Register (NFSPADR) NAND Flash Memory MLC ECCn Register (NFECCn) NAND Flash Memory Error Location n Register (NFERRLOCn) NAND Flash Memory Error Pattern n Register (NFERRPTNn) NAND Flash Memory ID Register (NFMID) SD HOST CONTROLLER Features Block Diagram SD Card Protocol Register Description SDHC Control Register (SDHCCON) SDHC Status Register (SDHCSTAT) SDHC Clock Divide Register (SDHCCD) SDHC Response Time Out Register (SDHCRTO) SDHC Read Data Time Out Register (SDHCRDTO) SDHC Block Length Register (SDHCBL) SDHC Number of Block Register (SDHCNOB) SDHC Interrupt Enable Register (SDHCIE) SDHC Command Control Register (SDHCCMDCON) SDHC Command Argument Register (SDHCCMDA) SDHC Response FIFO Access Register (SDHCRFA) SDHC Data FIFO Access Register (SDHCDFA) SPI LCD CONTROLLER Features Register Description SPI LCD control Register (CTRL) SPI LCD Baud Rate Register (BAUD) SPI LCD DMA Configuration Register (SPI_LCD_DMA) Contents Copyright 215, Advanced Digital Chips, Inc.

7 SPI LCD ChipSelect Register (CSx) SPI LCD Status Register (SPI_LCD_STAT) LCD Data Register (SPI_LCD_DATA) LCD Interrupt Mask Register (SPI_LCD_INT) SPI (SERIAL PERIPHERAL INTERFACE) Features Block Diagram Functional Description SPI Pins SPI Operating Modes Data Transfer Timing SCK Phase and Polarity Control SPI Serial Clock Baud Rate Open-Drain Output for Wired-OR Transfer Size and Direction Write Collision MODE Fault Interrupt Register Description SPI Control Register (SPICTRL) SPI Baud Rate Register (SPIBR) SPI Status Register (SPISTAT) SPI Data Register (SPIDATA) SPI nss Control Register (nssctrl) SPI Interrupt Mask Register (SPIINT) TWI (TWO WIRED INTERFACE) Features Block Diagram Functional Description DATA TRANSFER FORMAT START AND STOP CONDITION ACK SIGNAL TRANSMISSION READ-WRITE OPERATION BUS ARBITRATION PROCEDURES ABORT CONDITIONS Operational Flow Diagrams Register Description TWI Control Register (TWICTRL) TWI Status Register (TWISTAT) TWI Address Register(TWIADR) TWI Data Register (TWIDATA) TWI Baud-Rate Register (TWIBR) TWI Baud-Rate 1 Register (TWIBR1) SOUND MIXER Features Block Diagram Low Pass Filter for Digital Modulator Sound Mixer clock Mixer Block Diagram Register Description Mixer Control Register (MIXER_ CON) Mixer Volume Register (MIXER_VOL) Mixer Buffer Status Register (MIXER_BST) Mixer Data Register (MIXER_DAT) Mixer Out Register (MIXER_OUT) Mixer Interrupt Status Register (MIX_IST) ADC CONTROLLER Features Register Description ADC Control Register (ADCCTRL) ADC Data Register (ADCDATA) ADC FIFO Register (ADCFIFO) ADC Status Register (ADCSTAT) ADC Control Register2 (ADCCTRL2) TFT LCD CONTROLLER Introduction Features Copyright 215, Advanced Digital Chips, Inc. 7 Contents

8 Functional Description LCD clock source and divider Double buffering LCD Interrupt HSYNC, VSYNC DISPEN (Hor.active) VGA Timings Color Bar Test Pattern Generation Block Register Description LCD Horizontal Total Register(LCDHT) LCD Horizontal Sync. Start / End Register(LCDHS) LCD Horizontal Active Start / End Register(LCDHA) LCD Vertical Total Register(LCDVT) LCD Vertical Sync. Start / End Register(LCDVS) LCD Vertical Active Start / End Register(LCDVA) LCD Display Current X / Y Position Register(LCDXY) LCD Status Register(LCDSTAT) LCD Control Register(LCDCON) LCD Base Address Register (LCDBADR) LCD Base Address 1 Register (LCDBADR1) LCD Frame Sync. Count Register (LCDFRAMECNT) LCD Horizontal Width Register (LCDHWIDTH) LCD Flip Control Register (LCDFCTL) LCD Base Address 2 Register (LCDBADR2) LCD Base Address 3 Register (LCDBADR3) JPEG DECODER Features Block Description Functional Description Register Description JPEG Decoder Quantization Scale Control Register (JDQSC) JPEG Decoder Command Control Register (JDCC) JPEG Decoder Y DC Node Table (JDYDCNT) JPEG Decoder Y DC Leaf Table (JDYDCLT) JPEG Decoder Y AC Node Table (JDYACNT) JPEG Decoder Y AC Leaf Table (JDYACLT) JPEG Decoder UV DC Node Table (JDUVDCNT) JPEG Decoder UV DC Leaf Table (JDUVDCLT) JPEG Decoder UV AC Node Table (JDUVACNT) JPEG Decoder UV AC Leaf Table (JDUVACLT) JPEG Decoder Status Register (JDSTAT) JPEG Decoder IRQ Status Register (JDIRQSTAT) JPEG Decoder Data FIFO Status Register (JDDFSTAT) JPEG Decoder Enable Register (JDENA) JPEG Decoder FIFO Clear Register (JDFCLR) JPEG Decoder FIFO Control Register (JDFCON) JPEG Decoder Waite Control Register (JDWCON) JPEG Decoder Software Reset Register (JDSRST) JPEG Decoder Version Information Register (JDVERINFO) JPEG Decoder CSC Base Address Register (JDCSCBASEADDR) JPEG Decoder Stride Size Register (JDCSTRID) JPEG Decoder RGB565 mode and Timeout count enable (JDCRGBTIMEOUT) JPEG Decoder Timeout counter Register (JDCTIMEOUTCNT) JPEG Decoder Timeout counter clear (JDCTIMEOUTCLR) JPEG Decoder Input Data FIFO Register (JDIDF) USB DEVICE Features Register Summary USB Function Address Register USB Power Management Register USB Interrupt Registers USB Interrupt Enable Registers Frame Number Registers Index Register MAXP Register EP Control Register IN Control Registers Out Control Registers Out Write Count Registers Endpoint FIFO Access Registers Register Description Contents Copyright 215, Advanced Digital Chips, Inc.

9 USB Function Address Register (USBFA) USB Power Management Register (USBPM) USB Endpoint Interrupt Register (USBEPI) USB Interrupt Register (USBINT) Endpoint Interrupt Enable Register (USBEPIEN) USB Interrupt Enable Register (USBINTEN) USB Low Byte Frame Number Register (USBLBFN) USB High Byte Frame Number Register (USBHBFN) USB Index Register (USBIND) USB MAXP Register (USBMP) USB EP Control Register (USBEPC) USB IN Control 1 Register (USBIC1) USB IN Control 2 Register (USBIC2) USB Out Control Register 1 (USBOC1) USB OUT Control Register 2 (USBOC2) USB Low Byte Out Write Count Register (USBLOWC) USB High Byte Out Write Count Register (USBHBOWC) EP FIFO Data Register (USBEP) EP1 FIFO Data Register (USBEP1) EP2 FIFO Data Register (USBEP2) EP3 FIFO Data Register (USBEP3) EP4 FIFO Data Register (USBEP4) USB HOST CONTROLLER Features Operational Registers ELECTRICAL CHARACTERISTIC DC Electrical Characteristic Operating Conditions LDO Electrical Specification POR Electrical Specification PLL Electrical Specification ADC Electrical Specification RTC Operation Voltage Power Consumption PACKAGE DIMENSION Copyright 215, Advanced Digital Chips, Inc. 9 Contents

10 Figures Figure 2-1 adstar-l Block Diagram Figure 2-2 adstar-l Pin Layout Figure 3-1 Memory Map Figure 4-1 Reset Figure 4-2 Power On Start Time Diagram Figure 4-3 Clock Scheme Figure 4-4 Main Oscillator Circuit Figure KHz Oscillator Circuit Figure 4-6 PLL with External Filter Figure 4-7 PLL1 with External Filter Figure 4-8 Additional Clock Divider Figure 4-9 USB Clock Figure 4-1 TFT LCD Clock Figure 4-11 Sound Mixer Clock Figure 4-12 Wake-up process from Sleep mode Figure 4-13 Wake-up process from Stop mode Figure 4-14 Power Off for Shutdown/Static mode Figure 4-15 Wake-up process from Standby mode Figure 4-16 Wake-up process from Static mode Figure 5-1 Flash Memory Controller Block Diagram Figure 5-2 Internal Serial Flash Memory Figure 5-3 Serial Flash Memory Status Register Figure 5-4 Serial Flash Memory Status Register Figure 5-5 SCK and CS timing Figure 5-6 Flash Clock Delay Timing Figure 5-7 Access Two Flash Figure 6-1 GPIO Block Diagram Figure 8-1 External Interrupt Mode Figure 9-1 Pre-scaler Block Diagram Figure 9-2 Timer Operation Figure 9-3 core timer interrupt waveform Figure 1-1 Operational flow Figure 11-1 Pre-scaler Block Diagram Figure 11-2 Timer Operation Figure 11-3 PWM Operation Figure 11-4 Capture Mode Operation Figure 12-1 RTC Block Diagram Figure 12-2 Calibration Function Diagram Figure 12-3 Alarm Interrupt Operation Figure sec Interrupt Operation Figure /2 Interrupt Operation Figure /4 Interrupt Operation Figure 14-1 UART Block Diagram Figure 14-2 UART LCR Register Setting and Serial Data Format Figure 15-1 DMA Block Diagram Figure 15-2 DMA Transfer hierarchy Figure 15-3 Linked list Figure 15-4 Multi Block Transfer Figure 15-5 Gathering by using LLI Figure 15-6 Auto Reload Operation Transfer Hierarchy Figure 15-7 Scatter with Auto Reload Operation Figure 15-8 Gather with Auto Reload Operation Figure 15-9 DMA Handshake Signals Figure 15-1 Time Diagram of DMA Request Figure 17-1 NAND Flash Controller Block Diagram Figure 17-2 Read/Write Timing Diagram of NAND Flash Memory Figure 18-1 SDHC Block Diagram Figure 2-1 SPI Block Diagram Figure 2-2 Transfer Timing when CPHA = Figure 2-3 Transfer Timing when CPHA = Figure 2-4 SCK Phase and Polarity Figure Byte Transfer vs. Status and Interrupt Figure 2-6 n-bytes Transfer vs. Status and Interrupt Figure 21-1 TWI Block Diagram Figure 21-2 TWI-Bus Interface Data Format Figure 21-3 Data Transfer on the TWI-Bus Figure 21-4 Acknowledgement of TWI Figure 21-5 Bus arbitration 1 of TWI Figures Copyright 215, Advanced Digital Chips, Inc.

11 Figure 21-6 Bus arbitration Figure 21-7 TWI Initialization Flow Char Figure 21-8 Master Transmit Flow Char Figure 21-9 Master Receive Flow Char Figure 21-1 Master combined format Flow Char Figure Slave Mode Flow Chart (Polling) Figure Slave Mode Flow Chart (Interrupt) Figure Tcf interrupt wave form Figure SCL Hold wave form Figure 22-1 Mixer Block Diagram Figure 22-2 Low pass filter for digital modulator Figure 22-3 Sound Mixer Pre-Scaler Figure 22-4 Sound Mixer output diagram Figure 23-1 ADC Block Diagram Figure 24-1 LCD Controller Block Diagram Figure 24-2 LCD Clock Figure 24-3 Flipping Structure with double buffering Figure 24-4 LCDC Horizontal, Vertical Sync / Active Signal Timing Figure 24-5 Horizontal Timing Figure 24-6 Vertical Timing Figure 25-1 JPEG Decoder Block Diagram Figure 25-2 Decoder Core Block Diagram Figure 29-1 Package Dimension Copyright 215, Advanced Digital Chips, Inc. 11 Figures

12 Tables Table 2-1 adstar-l Pin Definitions 1-Pin... 2 Table 3-1 Peripheral Memory Map Table 3-2 Signals for boot mode... 3 Table 5-1 Instruction Set Table 1 (Erase, Program Instructions) Table 5-2 Instruction Set Table 2 (Read Instructions) Table 5-3 Instruction Set Table 3 (ID, Security Instructions) Table 5-4 Serial Flash Memory Status Register Description... 6 Table 6-1 Internal Pull-up Resistance Characteristics Table 8-1 Interrupt Vector & Priority Table 13-1 Real Memory map Table 13-2 Coprocessor Register Description Table 14-1 UART Baud Rate Table 14-2 UART Fractional Baud Rate Table 14-3 UART Register Summery Table 14-4 UART Interrupt Control Function Table 2-1 SPI Pin Functions Table 24-1 Typical VGA Timings... 2 Table 24-2 Register Values for VGA timing Table 24-3 LCD Controller Registers Table Table 26-1 Endpoint List Table 26-2 USB Core Register List Table 27-1 USB Host Register List Table 28-1 I/O DC Electrical Characteristic Table 28-2 I/O Recommended Operating Conditions Table 28-3 LDO Electrical Specifications Table 28-4 POR Specification (Unless otherwise specified, Topr=25 C, VDD=1.8V) Table 28-5 PLL DC Characteristics (Unless otherwise specified, Topr=25 C, VDD=1.8V) Table 28-6 PLL Input Frequency (Unless otherwise specified, Topr=25 C, VDD=1.8V) Table 28-7 ADC Recommended operating conditions Table 28-8 ADC DC Characteristics (Unless otherwise specified, Topr=25 C, VDD=1.8V) Table 28-9 Power Consumption from different conditions Tables Copyright 215, Advanced Digital Chips, Inc.

13 History Ver 1. June 29, 217 Ver 1.1 December 5, 217 1st version released Correct the description of the ADC Copyright 215, Advanced Digital Chips, Inc. 13 History

14 14 History Copyright 215, Advanced Digital Chips, Inc.

15 1 DESCRIPTIONS AND FEATURES 1.1 General Description adstar-l 은최대 12MHz 의빠른동작속도를가진 32 비트마이크로컨트롤러이며특히칩내부에 내장되는메모리가기존의플래시메모리뿐만아니라 SDRAM 까지내장되어다양한어플리케이션에적용할 수있다. PART NAME FLASH SDRAM adstar-l8m - 8MB adstar-l8mf KB 8MB adstar-l16m - 16MB adstar-l16mf KB 16MB adstar-l 은칩외부에연결되거나내부에내장된 Quad Flash 로동작하게된다. Flash 는프로그램코드와 데이터용도로같이사용가능하며, 설정에의해 Quad 데이터비트를사용하여매우빠른접근이가능하다. 또한 Serial Debugger 를통하여빠른프로그램다운로드가가능하다. CPU 는프로그램메모리와데이터메모리를액세스하기위한버스를독립적으로구현되어있으며 ( 하버드 구조 ), 5 단파이프라인의 EISC 구조로매우빠른명령처리를수행한다. 별도의하드웨어로구성된 LCD Controller 는 RGB888 또는 RGB565 출력을지원하며동급최대 8x6 의해상도를지원하고 Hardware JPEG Decoding 을지원한다. 그리고, Graphic Library 을제공함으로써 adstar-l 칩하나만으로도 LCD 를사용하는스마트어플리케이션에최적의솔루션이된다. 이외에제공되는 MP3 Decoding Library 와 Sound Mixer 는음성, 효과음, 배경음등으로활용할수있으며 4 채널 12 비트 ADC(1MSPS) 는센서나외부데이터를활용할수있게한다. 또한외부에 FLASH Memory, SD Card 를확장할수있고특히 NAND FLASH 의경우 SLC Type 뿐만 아니라 24bit ECC 채용으로 MLC Type 을사용할수있으므로전체적인시스템단가를낮출수있다. 다양한통신수단으로는 USB 1.1 Full-Speed Device/Host, 2 채널 UART, 1 채널 SPI_LCD, 1 채널 SPI, TWI 등을제공하며 6 채널 DMA 는보다빠른수행을할수있게한다. 또한, 파워다운모드를지원한다. adstar-l 는스마트가전등의스마트어플리케이션, LCD 를사용하여 G.U.I 환경의공장자동화시스템, 출입통제시스템, 스마트그리드, 사인패드, 각종프린터, POS, 바코드시스템, POP 모니터등에적용할수 있다. 개발환경으로는 GCC 기반의컴파일러와소스편집및다운로드, 디버깅환경을제공하는 EISC STUDIO, 레퍼런스회로도, 각종 Library, 예제소스코드를에이디칩스홈페이지 ( 자료실에서아무런제약없이다운로드할수있으며, 개발보드와다운로드 / 디버깅툴인 E-con 은저렴한가격에판매를하고있다. 양산툴로는조립전의칩을 8 개의소켓이있는갱라이터로 WRITE 하는방법과칩이조립된상태의타겟보드의전원을이용하여 stand alone 타입의 EISC HANDY 로하나씩다운로드하는방법을제공한다 General Description 1 Descriptions and Features Copyright 215, Advanced Digital Chips, Inc.

16 1.2 Features High-performance, Low-power 32-bit EISC Microprocessor 32-bit EISC Architecture AE32C-Lucida Harvard Architecture 5-Stage Pipelining 1 Cycle 32bit MAC Up to 12MIPS Throughput at 12MHz 8KB 2-way Instruction Cache 8KB 2-way Data Cache Serial Wire Debugger Embedded Memory 2KBytes Internal SRAM for Instruction 1KBytes Internal SRAM for Data 8/16Mbytes SDRAM Optional 512KBytes Flash (More than 1, erase/program cycles) External Memory Interface 8-bit NAND Flash Interface supports SLC and MLC (4/24-bit ECC) type Boot Modes NAND Flash Booting Serial Flash Booting SWD Interface Extensive On-chip Debug Support Programming of Serial Flash, other Ram LCD Controller RGB 888 or 565 output Supports up to 8 x 6 resolution display in RGB mode SPI_LCD Interface Support 9bit data transfer for lcd control USB 1.1 Full-Speed Device/Host Compatible Supports Full-speed Data Rate 12Mbps SD-Card Interface Supports single/quad Sound Mixer 4ch mixing 1-ch PWM output for Stereo or 2-ch PWM output for mono (1-CH Digital Modulator) RTC Support RTC counter (hour, minute, second) and calendar counter (year, month, day, week) Support Alarm counter (month, day, hour, minute, second) Support periodic time tick interrupt with 14 period options 1/4sec, 1/2sec, 1sec, 2sec, 4sec, 12sec, 1min, 2min,4min, 16min, 1hour, 2hour, 4hour, 24hour Support wake-up function 16 1 Descriptions and Features 1.2 Features Copyright 215, Advanced Digital Chips, Inc.

17 Other Peripherals 32-bit Watchdog Timer 6-ch DMA Interrupt Controller with 2 External IRQ 2 Channel 16-bit Timer/Counter with 15-bit Pre-scaler, Capture, PWM 2 Channel UART with 16Bytes FIFO, Functionally compatible with the 1655, with 1Channel IrDA 1 Channel Master/Slave SPI with 8Bytes FIFO 1 Channel TWI Auto ECC NAND Flash Controller: 4-bit/24-bit ECC Support, Auto Booting with ECC Support 55-Port In/Out with open drain mode 55-Port GPIO JPEG Decoder Analog IPs 12-bit 1MSPS SAR ADC with 4 analog input channels POR (Power On Reset) LDO PLL x 2 Operating frequency Up to 12MHz Power 3.V to 3.6V Operating Temperature -4 / +85 Package 1-Pin QFP (14mm x 14mm) Features 1 Descriptions and Features Copyright 215, Advanced Digital Chips, Inc.

18 Bus 2 AHB Bus 3 APB Bus 4 APB adstar-l 2 BLOCK DIAGRAM & PIN DESCRIPTIONS 2.1 Block Diagram INTC GPIO Core Timer Fast IO SWD AC32C I-SPM 2KB I Cache 2-Way 8KB D Cache 2-Way 8KB D-SPM 1KB Bus 1 AHB # 2 512K Flash L8M, L16M Serial Flash Cntl # 1 512K Flash L8M_F512, L16M_F512 APB Bridge Sound Mixer SPI CRTC 12-bit ADC 4 Memory (8MB, 16MB) AHB Bridge DMA Controller JPEG TWI NAND Flash Cntl Timer 2ch. SDHC SPI_LCD APB Bridge URAT 2ch. Watchdog Timer USB Host 1.1 PINMUX USB PHY RTC_Ctrl USB Dev 1.1 RTC Figure 2-1 adstar-l Block Diagram 18 2 Block Diagram & Pin Descriptions 2.1 Block Diagram Copyright 215, Advanced Digital Chips, Inc.

19 2.2 Pin Layout GP. 21 GP QFP 1-pin 14mm x 14mm GP GP GP GP GP GP GP3. 62 GP GP VDD18 G[4] G[3] G[2] G[1] / DBG_SDA G[] / DBG_SCK GND VDD33 R[7] R[6] R[5] R[4] R[3] R[2] R[1] R[] VBAT RTC_XOUT RTC_XIN PWR_DN WAKEUP GND (RTC, LDO, BOD) VIN VOUT VDD18 SPI_LCD_CS# NAND_D[7] / SPI_LCD_SDI NAND_D[6] / SPI_LCD_SDO NAND_D[5] / SPI_LCD_SCL SD_CLK / NAND_D[4] SD_D[3] / NAND_D[3] / SPI_MOSI SD_D[2] / NAND_D[2] / SPI_MISO SD_D[1] / NAND_D[1] / SPI_CS# SD_D[] / NAND_D[] / SPI_SCL VDD33 GND NAND_WE# / SF_HOLD# NAND_ALE / SF_CLK NAND_CLE / SF_DI NAND_CE# / SF_CS1# NAND_RE# / SF_WP# NAND_BUSY# / SF_DO GND TWI_SDA TWI_SCL TX RX VDD VDD33 PMW1_N PMW1_P PWM_N PWM_P GND DOTCLK_I / TM_O[1] HSYNC DOTCLK AGND33 AVDD33 USB_AVDD33 USB_DM USB_AGND33 PLL_AVDD18 PLL_VCTR PLL_AGND18 PLL1_AVDD18 PLL1_VCTR1 PLL1_AGND18 TEST# RESET# GND DISP_EN VDD33 GND B[7] B[6] B[5] B[4] B[3] B[2] B[1] / EIRQ[1] B[] / EIRQ[] G[7] G[6] G[5] GND VREF AIN[3] AIN[2] AIN[1] AIN[] USB_DP VDD18 VDD33 XIN GP6.6 GP.2 GP6.5 GP6.4 GP.3 GP.4 GP6.3 GP.5 GP.6 GP6.2 GP.7 GP6.1 GP GP GP GP4. 72 GP SD_CMD / SF_CS# VSYNC / TM_O[] CFG[] CFG[1] CAP[] / TX1 CAP[1] / RX1 XOUT GP6. GP1.1 GP5.7 GP1.2 GP5.6 GP1.3 GP5.5 GP1.4 GP5.4 GP1.5 GP5.3 GP1.6 GP5.2 GP1.7 GP5.1 GP2. GP5. GP2.1 GP4.7 GP4.6 GP2.2 GP4.5 GP2.3 GP4.4 CFG[2] CFG[3] CFG[4] GP2.4 GP4.3 GP2.5 USB_HOST_I USB_HOST_O Figure 2-2 adstar-l Pin Layout Pin Layout 2 Block Diagram & Pin Descriptions Copyright 215, Advanced Digital Chips, Inc.

20 2.3 Pin Definition No. Pin Name Alt CFG Table 2-1 adstar-l Pin Definitions 1-Pin Description. 1 AGND33 ADC power ground In 2 VREF ADC analog voltage input reference In 3 AIN[3] ADC analog voltage input channel 3 In 4 AIN[2] ADC analog voltage input channel 2 In 5 AIN[1] ADC analog voltage input channel 1 In 6 AIN[] ADC analog voltage input channel In 7 AVDD33 ADC power supply 3.3 V In 8 USB_AVDD33 USB power supply 3.3 V In 9 USB_DP USB DP - data+ pin Bidi 1 USB_DM USB DM - data- pin Bidi 11 USB_AGND33 USB power ground In 12 PLL_AVDD18 PLL power supply 1.8V In 13 PLL_VCTR Vco control voltage of pll, corresponding LPF should be connected here In 14 PLL_AGND1 8 Power ground In 15 PLL1_AVDD18 PLL1 power supply 1.8V In 16 PLL1_VCTR Vco control voltage of pll1, corresponding LPF should be connected here In 17 PLL1_AGND1 8 Power ground In 18 TEST# Test mode entrance active low In 19 RESET# Reset of system active low In UART_TX1 Uart tx [1] 2 CAP_IN 1 Timer capture [] CFG[] 3 Booting Mode Select [] Bidi GP. General Purpose I/O UART_RX1 Uart rx [1] 21 CAP_IN1 1 Timer capture [1] CFG[1] 3 Booting Mode Select [1] In GP.1 General Purpose I/O 22 VDD18 Core power supply 1.8V In 23 VDD33 IO power supply 3.3V In 24 XIN Oscillator xin In 25 XOUT Oscillator xout Out 26 GND Power gournd Out SPI_LCD_CS# SPI_LCD chip select signal [1] 27 CFG[2] 3 Booting mode Select [2] In GP.2 General purpose I/O SPI_LCD_SDI SPI data input [1] 28 NAND_D[7] 1 Nand flash data [7] GP.3 General purpose I/O SPI_LCD_SD O SPI_LCD data output [1] 29 NAND_D[6] 1 Nand flash data [6] CFG[3] 3 Booting mode Select [3] GP.4 General purpose I/O SPI_LCD_SCL SPI_LCD clock [1] 3 NAND_D[5] 1 Nand flash data [5] CFG[4] 3 Booting mode select [4] GP.5 General purpose I/O NAND_D[4] 1 Nand flash data [4] 31 SD_CLK 2 SD card clock GP.6 General purpose I/O SPI_MOSI When SPI is configured to Master, It used for Data output, otherwise, Data input 32 NAND_D[3] 1 Nand flash data [3] SD_DATA[3] 2 SD card data [3] GP.7 General purpose I/O 33 SPI_MISO When SPI is configured to Master, It used for Data input, otherwise, Data output Type Bidi Bidi Bidi Bidi Bidi Bidi Output Drive Current 8mA 8mA 8mA 8mA 8mA 8mA Pull-Up / Pull- Down up, down or disable up, down or disable up, down or disable up, down or disable up, down or disable up, down or 2 2 Block Diagram & Pin Descriptions 2.3 Pin Definition Copyright 215, Advanced Digital Chips, Inc.

21 NAND_D[2] 1 Nand flash data [2] disable SD_DATA[2] 2 SD card data [2] GP1. General purpose I/O 34 SPI_CS# SPI chip select signal [] up, NAND_D[1] 1 Nand flash data [1] Bidi 8mA down or SD_DATA[1] 2 SD card data [1] disable GP1.1 General purpose I/O 35 SPI_SCL SPI clock [] up, NAND_D[] 1 Nand flash data [] Bidi 8mA down or SD_DATA[] 2 SD card data [] disable GP1.2 General purpose I/O 36 VDD33 IO power supply 3.3V In 37 GND IO power ground In SF_HOLD# Serial flash hold signal 38 NAND_WE# 1 Nand write enable Bidi GP1.3 General purpose I/O SF_CLK Serial flash clock up, 39 NAND_ALE 1 Nand address latch enable Bidi 8mA down or GP1.4 General purpose I/O disable SF_DI Serial flash data Input up, 4 NAND_CLE 1 Nand command latch enable Bidi 8mA down or GP1.5 General purpose I/O disable SF_CS1# Serial flash chip select 1 up, 41 NAND_CE# 1 Nand chip enable down or GP1.6 General purpose I/O disable SF_WP Serial flash write protection signal up, 42 NAND_RE# 1 Nand read enable Bidi 8mA down or GP1.7 General purpose I/O disable SF_DO Serial flash data out. data output signal. up, 43 NAND_BUSY 1 Nand busy check Bidi down or GP2. General purpose I/O disable SF_CS# Serial flash chip select up, 44 SD_CMD 1 SD card command Bidi down or GP2.1 General purpose I/O disable 45 GND Power ground Bidi 46 TWI_SDA TWI data line up, USB_HOST_I 1 USB host input Bidi 8mA down or N disable GP2.2 General purpose I/O 47 TWI_SCL TWI clock line up, USB_HOST_O 1 USB host output Bidi down or UT disable GP2.3 General purpose I/O up, UART_TX Uart tx [] 48 Bidi 8mA down or GP2.4 General purpose I/O disable UART_RX Uart rx [] up, 49 Bidi 8mA down or GP2.5 General purpose I/O disable 5 VDD33 IO power supply 3.3V In 51 VDD18 Core power supply 1.8V In 52 VOUT LDO voltage output 1.8V Out 53 VIN LDO voltage input 3.3V In 54 GND Power ground In 55 WAKEUP System wake up signal In 56 PWR_DN System power down signal Out 57 RTC_XIN RTC oscillator xin In 58 RTC_XOUT RTC oscillator xout Out 59 VBAT Battery voltage input In up, R[] LCD red out [] 6 Bidi 8mA down or GP2.6 General purpose I/O disable up, R[1] LCD red out [1] 61 Bidi 8mA down or GP2.7 General purpose I/O disable up, R[2] LCD red out [2] 62 Bidi 8mA down or GP3. General purpose I/O disable 63 R[3] LCD red out [3] Bidi 8mA up, Pin Definition 2 Block Diagram & Pin Descriptions Copyright 215, Advanced Digital Chips, Inc.

22 GP3.1 General purpose I/O down or disable up, R[4] LCD red out [4] 64 Bidi 8mA down or GP3.2 General purpose I/O disable up, R[5] LCD red out [5] 65 Bidi 8mA down or GP3.3 General purpose I/O disable R[6] LCD red out [6] up, 66 Bidi 8mA down or GP3.4 General purpose I/O disable up, R[7] LCD red out [7] 67 Bidi 8mA down or GP3.5 General purpose I/O disable 68 VDD33 IO power supply 3.3V In 69 GND Power ground In G[] LCD green out [] up, 7 DBG_SCK 1 Debugger clock Bidi 8mA down or GP3.6 General purpose I/O disable G[1] LCD green out [1] up, 71 DBG_SDA 1 Debugger data Bidi 8mA down or GP3.7 General purpose I/O disable up, G[2] LCD green out [2] 72 Bidi 8mA down or GP4. General purpose I/O disable up, G[3] LCD green out [3] 73 Bidi 8mA down or GP4.1 General purpose I/O disable G[4] LCD green out [4] up, 74 Bidi 8mA down or GP4.2 General purpose I/O disable 75 VDD18 Core power supply 1.8V In 76 GND Power ground In up, G[5] LCD green out [5] 77 Bidi 8mA down or GP4.3 General purpose I/O disable up, G[6] LCD green out [6] 78 Bidi 8mA down or GP4.4 General purpose I/O disable up, G[7] LCD green out [7] 79 Bidi 8mA down or GP4.5 General purpose I/O disable B[] LCD blue out [] up, 8 EIRQ 1 External interrupt [] Bidi 8mA down or GP4.6 General purpose I/O disable B[1] LCD blue out [1] up, 81 EIRQ1 1 External interrupt [1] Bidi 8mA down or GP4.7 General purpose I/O disable B[2] LCD blue out [2] up, 82 Bidi 8mA down or GP5. General purpose I/O disable up, B[3] LCD blue out [3] 83 Bidi 8mA down or GP5.1 General purpose I/O disable B[4] LCD blue out [4] up, 84 Bidi 8mA down or GP5.2 General purpose I/O disable up, B[5] LCD blue out [5] 85 Bidi 8mA down or GP5.3 General purpose I/O disable B[6] LCD blue out [6] up, 86 Bidi 8mA down or GP5.4 General purpose I/O disable up, B[7] LCD blue out [7] 87 Bidi 8mA down or GP5.5 General purpose I/O disable 88 GND Power ground In 89 VDD33 IO power 3.3V In 9 DOTCLK LCD clock output Bidi 8mA up, 22 2 Block Diagram & Pin Descriptions 2.3 Pin Definition Copyright 215, Advanced Digital Chips, Inc.

23 GP5.6 General purpose I/O DISP_EN Display enable 91 Bidi GP5.7 General purpose I/O HSYNC Signal for horizontally synchronization 92 Bidi GP6. General purpose I/O VSYNC Signal for vertically synchronization 93 TM_OUT 1 Timer pwm output [] Bidi GP6.1 General purpose I/O LCD_CLK_IN Clock input (lcd controller) 94 TM_OUT1 1 Timer pwm output [1] Bidi GP6.2 General purpose I/O 95 GND Power ground In PWM_P GP6.3 (sound pwm positive output channel ) 96 Bidi GP6.3 General purpose I/O PWM_N GP6.4 (sound pwm negative output channel ) 97 Bidi GP6.4 General purpose I/O PWM1_P GP6.5 (sound pwm positive output channel 1) 98 Bidi GP6.5 General purpose I/O PWM1_N GP6.6 (sound pwm negative output channel 1) 99 Bidi GP6.6 General purpose I/O 1 VDD33 IO power supply 3.3V In * Alt CFG 는 pin mux 설정값에해당하는숫자이다. 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA down or disable up, down or disable up, down or disable up, down or disable up, down or disable up, down or disable up, down or disable up, down or disable up, down or disable Pin Definition 2 Block Diagram & Pin Descriptions Copyright 215, Advanced Digital Chips, Inc.

24 2.4 Pin Description VDD33, AVDD33, USB_AVDD33 : 3.3V Supply voltage 에연결하며서로연결되지않는독립전원이어야한다. PLL_AVDD18, PLL1_AVDD18 : 1.8V Supply voltage VDD18 : 1.8v supply voltage AGND33 : ADC Power Ground USB_AGND : USB Power Ground PLL_AGND, PLL1_AGND : PLL Power Ground GND : Power Ground TEST# : Chip Test pin (Low active) Chip test를위한핀이다. 이핀이 이면모든핀들이 Pin Mux 의 3rd 핀으로할당되어 Test Mode로진입하게된다. TEST# 은 active-low 테스트핀이고, 정상적인동작동안 high를유지한다. CFG[4:] : Booting Mode Select (3.4 Boot Mode 참고 ) Flash Booting, NAND Flash Booting 등을선택할수있다. AIN[3:] : ADC 에입력되는아날로그전압레벨이며디지털값으로변환된다. 4 채널 VREF : AIN 입력레벨에대한 Reference 이다. USB Pins: USB Device 와 Host 가공유. ( USB PHY Control Register 참고 ) USB_DP : USB Data+ I/O USB_DM : USB Data- I/O EIRQ, EIRQ1 : External Interrupt Request Input Pins (8 Interrupt Controller 참고 ) 외부에서인터럽트를요청해야할경우사용. Serial Flash (5 SPI Flash Memory Controller 참고 ) SF_CS#, SF_CS1# : Serial Flash Chip Select SF_CLK, : Serial Flash Clock SF_DI : Serial Flash Data Input. Command, Address, Data 를입력받는신호. SF_DO : Serial Flash Data Out. Data 를출력하는신호. SF_WP : Serial Flash write protection 신호. SF_HOLD : Serial Flash hold 신호. NAND Flash (17 NAND Flash Controller 참고 ) NAND_CE: NAND Flash Chips Enable. NAND Flash 를활성화할때사용 NAND_ALE : NAND Flash Address Latch Enable. NAND Flash 에 address 를전송할때사용 NAND_CLE: NAND Flash Command Latch Enable. NAND Flash 에 command 를전송할때사용 NAND_WE# : NAND Flash Write Enable. NAND Flash 에 data 를저장할때사용 NAND_RE# : NAND Flash Read Enable. NAND Flash 에서 data 를읽을때사용 NAND_BUSY# : NAND Flash Busy signal input pin. NAND Flash 가 Busy 상태일때. NAND_D[7:] : NAND Flash 8-bit Data I/O Block Diagram & Pin Descriptions 2.4 Pin Description Copyright 215, Advanced Digital Chips, Inc.

25 LCD Controller : RGB 최대 888 출력. 최대 8x6 지원 (24 TFT LCD Controller 참고 ) CRTC_CLK_IN : LCD Controller 에서사용하는 Clock Input VSYNC : 수직동기신호 HSYNC : 수평동기신호 DISP_EN : Display Enable CRTC_CLK_OUT : LCD Clock Output R[7:] : Red Output 8-bit G[7:] : Green Output 8-bit B[7:] : Blue Output 8-bit PWM/Capture : 2 channels. (11 Timer 참고 ) TM_OUT, TM_OUT1 : PWM Output. CAP_IN, CAP_IN1 : Capture Input. 외부신호의주기나펄스폭을측정하기위한입력핀 SPI : 1 channel. (2 SPI 참고 ) SPI_CS# : SPI Chip select signal SPI_SCK : SPI Clock pin SPI_SDI : SPI 가 Master 일때 Data input, Slave 일때 Data output 으로사용 SPI_SDO : SPI 가 Master 일때 Data output, Slave 일때 Data input 으로사용 SPI_LCD : 1 channel. (19 SPI_LCD 참고 ) 9bit SPI 인터페이스방식의 LCD 모듈제어 SPI_LCD_CS# : SPI Chip select signal SPI_LCD_SCK : SPI Clock pin SPI_LCD_SDI : SPI Data input SPI_LCD_SDO : SPI Data output TWI (21 TWI 참고 ) TWI_SCL : TWI Serial Clock TWI_SDA : TWI Serial Data UART : 2 channels. Channel 은 UART only. Channel 1 은 IrDA 를지원. UART_RX : UART RX UART_TX : UART TX UART_RX1 : UART RX with IrDA supported UART_TX1 : UART TX with IrDA supported Sound Mixer : Digital Modulator 2 channels. (22 Sound Mixer 참고 ) SPWM_P, SPWM_N, SPWM1_P, SPWM1_N : Sound Mixer Digital Modulator PWM 출력. Sound Mixer 의출력에할당되어 Mono 일때 2channel, Stereo 일때 1channel 에해당한다. XIN, XOUT : 외부에서 2Mhz crystal 을연결한다 Pin Description 2 Block Diagram & Pin Descriptions Copyright 215, Advanced Digital Chips, Inc.

26 3 MEMORY ARCHITECTURE AND BOOTING MODES 3.1 Memory Map 메모리영역은아래의표와같이할당되어있다. (figure 3-1) xffff3fff xffff xbfffffff FIO Bus Reserved 2nd Bus xa x9fffffff 1st Bus x8 x4fffffff x4 x2fffffff Reserved Serial Flash Reserved SDRAM 8MB/16MB x2 x183ff x18 x17ff x1 xfffffff x Reserved Internal SRAM 1KB for Data Reserved Internal SRAM 2KB for Instruction Boot Area (NAND Boot: Internal SRAM 2KB, Serial Flash Boot) Figure 3-1 Memory Map 26 3 Memory Architecture and Booting modes 3.1 Memory Map Copyright 215, Advanced Digital Chips, Inc.

27 3.2 Embedded Memories 2KB Internal SRAM for Instruction 1KB Internal SRAM for Data Internal SRAM for Instruction adstar-l 은 Instruction 을위한 2KB SRAM 메모리가내장되어있다. 명령어또는데이터를저장하는용도로사용할수있으며주로명령어를저장하게된다. 명령어를읽는경우 1cycle 접근이가능하며데이터를읽는경우는 3 cycle 이소요된다 Internal SRAM for Data adstar-l 은 Data 를위한 1KB SRAM 메모리가내장되어있다. 주로데이터를저장하는데사용되며, 데이터를읽는경우 1cycle 접근이가능하다 Internal SRAM Registers Internal SRAM 전체를관장하는 1 개의 Global Control Register 를갖는다. 또한 Internal SRAM 은내부에 여러개의 Bank 로구성될수있으므로 Global Register 의 Configuration 에의해결정되는 Bank 개수만큼 Local Register Set 을갖는다. Local Register Set 는다음과같은 3 개의 32bit Register 로구성된다. - Local Internal SRAM Control Register - Local Internal SRAM Start Address - Local Internal SRAM End Address Internal SRAM Global Control Register Address : x7 - Global Control Register Bit R/W Description Default 31 : 28 R Exception Status h 4 b1 : DATA Access Violation 4 b1 : Instruction Access Violation 27 : 24 R Reserved h 23 : 2 R ibank Size: isram에서각 bank의 physical Memory 크기 4 h : 1 KB 4 h1 : 2 KB 4 h2 : 4 KB 4 h3 : 8 KB 4 h4 : 16 KB 4 h5 : 32 KB 4 h6 : 64 KB 4 h7 : 128 KB 4 h8 : 256 KB 19 : 16 R/W isram Configuration 4 h : 사용자에게 1 개의메모리덩어리로보임 4 h1 : Reserved h 4 h2 : 사용자에게 4 개의메모리덩어리로보임 (4개를넘는경우는현재구현되어있지않음 ) 15 : 12 R isram Enable 4 b1 : SRAM Enable 4 b : SRAM Disable 11 : 8 R dbank Size: dsram에서각 bank의 physical Memory 4 h : 1 KB 4 h1 : 2 KB 4 h2 : 4 KB 4 h3 : 8 KB 4 h4 : 16 KB 4 h5 : 32 KB 4 h6 : 64 KB 4 h7 : 128 KB 4 h8 : 256 KB h Embedded Memories 3 Memory Architecture and Booting modes Copyright 215, Advanced Digital Chips, Inc.

28 7 : 4 R/W dsram Configuration 4 h : 사용자에게 1 개의메모리덩어리로보임 4 h1 : Reserved 4 h2 : 사용자에게 4 개의메모리덩어리로보임 (4개를넘는경우는현재구현되어있지않음 ) 3 : R dsram Enable 4 b1 : SRAM Enable 4 b : SRAM Disable h h Internal SRAM Local Control Register Address : x71, x711 - Local isram Control Register Address : x74 - Local dsram Control Register Bit R/W Description Default 31 : 12 R Reserved h 11 : 8 R External Access: BUS 접근권한 4 h : External Access Not Support 4 h1 : External Access Support 7 : 4 R/W Privilege Mode: 사용자권한 4 h : Supervisor only Access 4 h1 : Supervisor/User Access 3 : R Enable 4 b1 : Local SRAM Enable 4 b : Local SRAM Disable h h Internal SRAM Local Start Address Register Address : x72, x712 - Local isram Start Register Address : x75 - Local dsram Start Register Bit R/W Description Default 31 : R/W SRAM Start Address h Internal SRAM Local End Address Register ADDRESS : x73, x713 - Local isram End Register ADDRESS : x76 - Local dsram End Register Bit R/W Description Default 31 : R/W SRAM End Address h Internal SRAM Register Setting Internal SRAM 레지스터의설정은 GAP 를이용하기때문에 co-processor 레지스터접근명령어인 MVTC 와 MVFC 를사용하게된다. 예제. //#################################################### //## Internal SRAM Global Register Setting //#################################################### asm( ldi x7, %r ); asm( mvtc x, %r3 ); asm( ldi x2121, %r ); //#ON //#Num of Memory Bank: 4 asm( mvtc x, %r4 ); 28 3 Memory Architecture and Booting modes 3.2 Embedded Memories Copyright 215, Advanced Digital Chips, Inc.

29 3.3 Peripheral Memory Map Register 영역은 8_h 부터존재하며각기능 Block 당 1Kbyte 씩할당되어있다. Memory mapped I/O 의형태로자세한내용은아래와같다 (Table 3-1) Table 3-1 Peripheral Memory Map Offset Address Block BUS Remark x8_ Flash Controller x8_4 SDRAM Controller x8_8 Reserved 1st x8_c Reserved AHB x8_1 Reserved x8_14 DMA Controller x82_ Watchdog Timer x82_4 Timer 2 Channels x82_8 UART (2nd ch. IrDA) 2 Channels x82_c ~x82_17ff Reserved x82_18 TWI x82_1c Reserved ~x82_23ff 1st x82_24 CRTC APB x82_28 ~x82_33ff Reserved x82_34 Pin Mux x82_38 RTC x82_3c System Control x83_ ~x83_ffff Reserved Offset Address Block BUS Remark xa_ USB Host xa_4 Reseved xa_8 SPI LCD 2nd xa_c NAND Flash Controller AHB xa_1 SDHC xa_14 Reserved xa_18 USB Device xa2_1 SPI xa2_14 Reserved xa2_18 Reserved xa2_1c Sound Mixer xa2_2 2nd Reserved ~xa2_37ff APB xa2_38 ADC Controller 12-bit ADC xa2_3c Reserved xa3_ ~xa3_ffff Reserved xffff_ (1) Interrupt Controller xffff_1 (1) Core Timer xffff_3 (1) GPIO (1) 녹색영역은 CPU 에의해내부적으로디코딩되고, 실제로버스에연결되어있지않다. 그래서 다른마스터에의해 access 되지않는다 Peripheral Memory Map 3 Memory Architecture and Booting modes Copyright 215, Advanced Digital Chips, Inc.

30 3.4 Boot Modes 외부 External Reset 이풀리는순간 CFG[4:] 핀의전압 Level 을통하여 booting 모드를 결정하고해당모드로부팅하게된다. Configuration 핀의할당순서는다음과같다. Table 3-2 부팅모드별로외부신호를나열하고각각의기능을설명. Table 3-2 Signals for boot mode Pin Functional Name Pin Name (refer to datasheet for pin numbers) CFG[] #2_GP. Debugger Mode or Boot Mode CFG[1] #21_GP.1 Boundary Scan or SWD logic selection CFG[2] #27_GP.2 Serial Flash Boot or Nand Flash Boot CFG[3] #29_GP.4 CFG[4] #3_GP Debugger Mode CFG[]= 인경우에 Debugger mode 로부팅된다. 이모드에서는 CPU 는정지상태에놓여있으며사용자가 Debugger 를통하여 CPU 의프로그램수행동작을제어하게된다 Boot Mode CFG[]=1 인경우에 Normal mode 로부팅된다. 이모드에서 CPU 는일반적인프로그램수행동작을진행한다. 부팅메모리는 CFG[4:2] 에의해정해진다 Serial Flash Boot CFG[4:2] = 111 인경우에 Serial Flash 로부팅된다 NAND Flash Boot CFG[4:2] 이 111 이나 11 이아닌경우에 NAND Flash 로부팅된다. 이모드에서는최초 NAND Flash 의 부트코드가내부 2KB 크기의 Internal SRAM 에복사가되며, 복사가끝나면 CPU 가복사된프로그램을 수행하게된다. CFG[4:2] NAND Boot Mode NAND Flash Type Small type 3-Cycle NAND Flash Small type Address 3 cycles 1 Small type 4-Cycle NAND Flash Small type Address 4 cycles 1 Large type 4-Cycle NAND Flash Large type Address 4 cycles 11 Large type 5-Cycle NAND Flash Large type Address 5 cycles 1 MLC 4-Bit ECC NAND Flash MLC type 4-bit ECC 11 MLC 24-Bit ECC NAND Flash MLC type 24-bit ECC SWD Seleciton CFG[1] 핀을사용하여 PinMux 설정없이 JTAG, SWD 핀을선택할수있다. CFG[1] = 인경우 PinMux 설정은 JTAG(Boundary scan용 ) 이설정된다. CFG[1] = 1 인경우 PinMux 설정은 SWD(Debug 용 ) 가설정된다. 3 3 Memory Architecture and Booting modes 3.4 Boot Modes Copyright 215, Advanced Digital Chips, Inc.

31 4 SYSTEM CONTROL System control 는 reset control, clock control, power control, and low-power modes 를포함한다. 4.1 Reset Control Reset controller 는 External Reset, Power on Reset, Debugger Reset 그리고 Watchdog Reset 으로구성되어 있다. 아래그림에전체 reset 들이표시되어있다. RESET# pin 은외부리셋신호에응답 (active LOW). device 는 reset 상태를벗어나면실행을시작한다. reset 중부트모드가결정되며, device 는부트모드를실행하기시작한다. config_done int_resetx ext_clk ext_resetx por_resetx wdt_resetx dbg_resetx all_resetx reset counter poc_resetx boot_resetx config_done sys_resetx Figure 4-1 Reset 시스템의 debugger reset 은 SWD 내부레지스터에 write 함으로써실행된다 System Reset System Reset은다음과같은사항에서발생한다. 1. External Reset 2. Debugger Reset 3. Watchdog Reset 4. POR Reset Reset Control 4 System Control Copyright 215, Advanced Digital Chips, Inc.

32 Power On Start Time VDD33 에 3.3V 전원이인가되고, 내부 LDO 출력을통해 VDD18 에 1.8V 가안정적으로인가되면, POR Reset 이 release 된다. 이때, External Reset 이 release 되면, External Clock 으로동작하는 Startup 회로가동작하게된다. 이 Startup 회로는 Xin 이안정화되기전의오동작을방지하며, 내부 logic 에동시에 system reset 을 release 시켜준다. System reset 은 POR Reset 과 External Reset 이 release 되고 Xin clock 기준 124-cycle 이지난후 release 된다. 3.3V VDDIO (VDD33) CoreVDD (VDD18).9V 1.62V 1.8V 75ms 3ms POR Resetn External Resetn External Clock (Xin) Internal System Resetx Startup counter 124 cycles of Xin Figure 4-2 Power On Start Time Diagram 32 4 System Control 4.1 Reset Control Copyright 215, Advanced Digital Chips, Inc.

33 4.2 Clock control Device 는두개의 on-chip PLL, 두개의 on-chip oscillators 를가지고있다. 세가지기본 clock source 가있다. 첫번째 clock input 은 main oscillator 에의해생성되고, 두번째 clock input 은선택사항으로 GP6.2(DOTCLK_I) input 이고, LCD module 등에사용된다. 세번째 clock 은 RTC oscillator clock input(32.768khz) 으로 RTC module 에사용된다. device 는두개의 PLL 이있다. 각각의 PLL 은 PLLCONx 레지스터에의해제어된다. PLL reference clock 은 XIN pin 으로부터받고, PLL1 reference clock 은외부 XIN input pin(dotclk_i input pin) 이고, 내부 clk16_ 은외부 XIN input pin(dotclk_i input pin) 으로부터온다. 모든 PLL 은 reset 후, power down 이된다. hclk_src_sel g hclk_cpu hclk_div_val[3:] g hclk_sdrctrl XIN #24 #25 XOUT Main OSC PLL 1 pll_clk 1/1~ 1/16 HCLK Max. 12MHz 1/2 PCLK Max. 6MHz g g g g g hclk_sdram hclk_intc hclk_gpio hclk_dma hclk_sf #94 GP6.2 (DOTCLK_I) clk16 sel[1:] clk16 div_val[3:] g g hclk_spi9 hclk_jpeg pll_clk 1/1 ~ 1/16 clk16_ g g hclk_usbd hclk_usbh g hclk_lcd clk16_1_sel[1:] clk16_1_div_val[3:] 1/1 ~ 1/16 clk16_1 g g g hclk_nand hclk_sdhc hclk_sys pll1_src_sel[1:] g g pclk_wd pclk_tm RTC_XIN #57 RTC OSC clk16_ PLL1 RTC Block pll1_clk g g g g g g g pclk_uart pclk_spi pclk_spi1 pclk_twi pclk_pmux (Digital Amp) pclk_lcd pclk_rtc #58 RTC_XOUT g pclk_sys Figure 4-3 Clock Scheme 대부분의경우, PLL 은높은성능을선정하지만, 전력소모의증가를초래할수있다. 낮은성능및전력 소비를줄이기위해, crystal clock 이선택될수있다. main crystal clock 과 PLL 는 HCLK and PCLK peripherals reference clock sources 로써사용된다 Clock control 4 System Control Copyright 215, Advanced Digital Chips, Inc.

34 HCLK 과 PCLK 은각각 AHB 영역과 APB 영역에클럭을공급한다. 두클럭은동일한위상이며 2:1 의 주파수비의관계를갖고있다. HCLK 의최대주파수는 12Mhz 이며 PCLK 의최대주파수는 6Mhz 이다. HCLK 도메인은 CPU 와 AHB peripherals 에사용된다. PCLK domain 은 APB peripherals 에사용된다. HCLK 와 PCLK reference 는 main crystal clock 또는 PLL clock output 이될수있습니다. PCLK 은실제로 HCLK 도메인에서분주됩니다. 그래서, PCLK 과 HCLK 은 synchronous 이다. 모든 APB peripheral 은 PCLK 을사용하며, PCLK 도메인으로간주된다 Main oscillator main oscillator 는 PLL 및 PLL1 대한 clock 소스로사용될수있다. 내부 PLL 를사용하지않는경우의 main oscillator 의주파수는 32 KHz 에서 27MHz. 이다. 내부의 PLL 을 사용하는경우 crystal 은 6KHz 부터 2.25MHz 의주파수범위이어야한다. main oscillator clock 을생성하기 위해사용될때, Figure 4-4 와같이 2 개의부하 capacitors 와함께외부크리스털 XIN 및 XOUT 핀사이에 연결할필요가있다. main oscillator 입력은대부분의내부모듈에사용된다. # 24 XIN # 25 XOUT 1M ~ 1M 32KHz ~ 27MHz 6KHz ~ 2.25MHz for PLL 1pf ~ 3pf 1pf ~ 3pf Figure 4-4 Main Oscillator Circuit RTC oscillator (32KHz) RTC oscillator 는 RTC 블럭의 clock source 로사용된다. RTC oscillator 는 Static mode 를제외한모든 전력모드에서사용할수있다. Figure 4-5 에도시된바와같이 oscillator 는 RTC clock 을생성하는외부 크리스털회로가필요하다 # 57 RTC_XIN # 58 RTC_XOUT Rf 1Mohm Rd 6Kohm C1 8pF X-tal KHz C2 8pF Figure KHz Oscillator Circuit 34 4 System Control 4.2 Clock control Copyright 215, Advanced Digital Chips, Inc.

35 PLL PLL 은 reference 클럭으로 Main oscillator 를받는다. PLL 은 6KHz 에서 2.25MHz 범위의입력 clock 주파수를사용한다. PLL 은소프트웨어에의해사용할수있다. 프로그램으로 PLL 를활성화해야합니다. PLL lock 을기다린다음 clock 소스로 PLL 에연결한다. External LPF C1 47 nf # 13 PLL_VCTR C2 1.3 uf R2 68 Ω # 12 PLL_AVDD18 Main OSC CLK XIN 6KHz~ 2.25MHz PLL FOUT pll_clk PD OD[1:] R[3:] N[11:] PLLCON [28] [25:24] [19:16] [11:] Figure 4-6 PLL with External Filter PLL 가활성화되기전에올바르게설정해야합니다. 주요 OSC clock 은 PLL reference clock 의 source 이다. PLL 출력주파수는다음식으로부터계산된다 : Fout = XIN N R OD R 은입력분주비이고, 이는 R[3:] 에의해조절될수있다 : R[3:] Input Divider Ratio (R) N 은피드백루프의분할비율을나타낸다 (multiplier). 이는 N[11:] 에의해조절될수있다 N[11:] Feedback Divider Ratio (N),,1 2,, ,1111, ,1111, ,1111, Clock control 4 System Control Copyright 215, Advanced Digital Chips, Inc.

36 OD 출력분배기이고, 이는 OD[1:] 에의해조절될수있다 OD[1:] Output Divider Ratio (OD) Normal operation 1 divide by 2 1 divide by 4 11 divide by 8 예를들어, 만약 XIN이 1MHz이고, R[3:] 은 1, N[11:] 은 1, OD[1:] is 11 이면, Fout = = 16 MHz 8 PLL을설정 ( PLL는 PLLCON 레지스터의 PLL power down bit를 으로 write하여사용할수있다 ) PLL1 PLL1 은 6KHz 에서 2.25MHz 범위의입력 clock 주파수를사용한다. PLL1 은 disabled 은 reset 에 powered off 된다. External LPF C1 47 nf # 16 PLL1_VCTR C2 1.3 uf R2 68 Ω # 15 PLL1_AVDD18 pll1_src_sel[1:] clk_sel Main OSC clk GP6.2 XIN PLL 1 FOUT pll1_clk System clock clk 16_ 6KHz ~ 2.24MHz PD OD[1:] R[5:] N[11:] Main OSC clk PLLCON1 [28] [25:24] [21:16] Figure 4-7 PLL1 with External Filter PLL1 소스선택필드 (pll1_src_sel) 는레퍼런스클럭의소스를선택한다. 출력주파수의계산에대한자세한내용은 PLL 섹션을참조. [11:] PLLx Clock Change 사용자는 System이동작하는중간에도 PLL clock의주파수를변경할수있다. PLL Clock Source를변경하거나 PLL 설정을변경하면 PLL Clock의주파수는변경된다. 그런데동작중에 PLL 주파수를변경하는것은시스템을불안정하게만들기때문에안정적인변경을위해서는시스템클럭을 External clock 동작시킨후에 PLL의주파수를변경해야한다. External Clock 과 PLL Clock 사이에변경은 Glitch Free Mux를통해이루어지므로언제든안정적인변경이가능하다. PLL 의설정을변경하게되면 PLL 에서변경된주파수의 Clock 이나오기까지 Lock time 이소요된다. Lock time 은 Max 2ms 이다. 사용자는 PLL 변경한후 Lock time 이지난후에시스템클럭을 PLL 클럭으로변경해야한다 System Control 4.2 Clock control Copyright 215, Advanced Digital Chips, Inc.

37 Clock gating 각각의주변장치는개별클럭과시스템제어기및 HCLKEN PCLKEN 레지스터비트를이용하여게이트 on/off 할수있다. 이비트는모든 reset 후삭제된다. Clock off 전에, peripheral 이실행되지않았는지확인 한다. 비활성화된클럭을가지고어떤버스액세스가 peripheral 에에러종료를생성한다 Additional Clock Divider 각고정된디바이더의정수값또는분별값으로입력기준주파수를분할하는기능을갖는다. 레퍼런스클럭주파수는원하는출력주파수를달성하도록선택되어야한다. clk15_sel[1:] clk25_sel[1:] main osc clk GP6.2 input pll_clk pll1_clk 1/1.5 clk15 main osc clk GP6.2 input pll_clk pll1_clk 1 / 2.5 clk25 clk45_sel[1:] clk5_sel[1:] main osc clk GP6.2 input pll_clk pll1_clk 1 / 4.5 clk45 main osc clk GP6.2 input pll_clk pll1_clk 1 / 5 clk5 clk256_sel[1:] main osc clk GP6.2 input pll_clk pll1_clk 1 / 256 clk256 Figure 4-8 Additional Clock Divider Clock control 4 System Control Copyright 215, Advanced Digital Chips, Inc.

38 USB Clock USB Host/Device 는 Figure 4-9 에도시된바와같이두개의 clock source 에서 clock 이공급된다. usb_clk_sel usb_clk_div_val pll_clk pll1_clk 96MHz 1/2 48MHz 48MHz A B Z usb48_clk g g usb48_clk device usb48_clk host 48MHz 96MHz 1/4 1/8 12MHz 12MHz A B Z usb12_clk g g usb12_clk device usb12_clk host Figure 4-9 USB Clock Figure 4-9 에도시된바와같이, USB 클럭에대한두가지소스는두개의 PLL 에서각각 clock 을 받는다. usb48_clk 주파수는 48MHz 로해야하며, usb12_clk 주파수는작동을위해 12MHz 로해야한다 TFT LCD Clock LCD 컨트롤러는세가지기본클럭을사용한다 : hclk_lcd, pclk_lcd, DOTCLK. hclk_lcd 과 DOTCLK 은비동기이다 LCD module 은 Figure 4-1 에도시된바와같다. lcd_clk_sel[2:] clk16_ clk16_1 clk15 clk25 clk45 clk5 clk256 main osc clk lcd_clk_div_val[3:] 1/1~ 1/16 g A Z B A S DOTCLK LCDCON[22] Figure 4-1 TFT LCD Clock LCD Controller SPI 9bit clk Z GP5.6 (DOTCLK) #9 Figure 4-1 에도시된바와같이, DOTCLK 에대한 8 개의가능한소스가있다. 선택된클럭은추가로 LCD 모듈에가기전에 1 ~ 1/16 까지모든비율로분할될수있다. DOTCLK 또한핀에출력된다 System Control 4.2 Clock control Copyright 215, Advanced Digital Chips, Inc.

39 Sound Mixer Clock Sound Mixer module 은 Figure 4-11 에도시된바와같이 clock 을생성할수있다. clk16_ clk16_1 clk15 clk25 clk45 clk5 clk256 main osc clk dm_clk_sel[2:] dm_clk_div_val[3:] 1/1~ 1/16 g MCLK Figure 4-11 Sound Mixer Clock Sound Mixer Clock Figure 4-11 에도시된바와같이, MCLK 를위한 8 개의가능한소스가있다. 선택된클럭은추가로음향 믹서모듈가기전에 1 ~ 1/16 까지모든비율로분할될수있다 Protection Mechanism adstar-l 은시스템제어레지스터에 write 접근하기위해두단계절차를필요로한다. 첫번째는절차는 GLOCK 레지스터에 xe5511acc 값을 write 하여 unlock 을시켜야한다. 이것은모듈의 모든레지스터들을해제한다. (GLOCK 레지스터는시스템제어모듈에서중요한레지스터에우발적인쓰기를방지하기위해필요하다.) 두번째절차는필요한각각의레지스터를 write 하려면 WREN 레지스터의각각의비트를활성화하여야 한다 Clock control 4 System Control Copyright 215, Advanced Digital Chips, Inc.

40 4.3 Power modes 전력관리컨트롤러의다수의전원옵션은사용자가필요한사용자애플리케이션에대한전력소비를 최적화할수있도록제공한다. 파워모드는인수로모드인덱스번호를취하는정지명령에의해선택된다. Modes CPU Clock Main OSC Main domain Power RTC OSC RTC domain power Sleep(Halt3) Off On On On On RESET#, Interrupt Source Stop(Halt2) Off Off On On On RESET# Event Source, Wake-up Shutdown(Halt1) Off Off Off On On RTC Alarm Wake-up Reboot from Power-up Static(Halt) Off Off Off Off On Wake-up Reboot from Power-up Exit RUN mode Run mode 는칩에대한정상작동모드이다. 이모드는모든리셋후입력된다. RUN mode 는모든 clocks 을활성화하고, 소프트웨어실행및주변동작을허용한다. 이모드에서전력소비를줄여야한다면, 사용하지않는클럭은그에상응하는클럭의제어에서사용하지않도록레지스터를설정하여전력소모를줄일수있다. (AHBCLKEN, APBCLKEN) Sleep mode Halt3 명령은 CPU 와 SPM 의 memorys 을중단한다. CPU clock 은정지하고, 칩의나머지는동작을수행한다 wake up 소스는인터럽트이다. 인터럽트는 active high level 이어야 wake up 소스로사용할수있다. - CPU is disabled. - SPM is disabled. Wake-up from Sleep mode(halt3) 4 4 System Control 4.3 Power modes Copyright 215, Advanced Digital Chips, Inc.

41 debug irq cap over irq rtc alarm irq rtc irq wdt irq dma irq[5] or GP3 or GP6 irq dma irq[4] or GP2 or GP5 irq dma irq[3] uart irq[1] INTC Interrupt CPU GP1 or GP4 irq adc irq dma irq[2] pmc irq timer irq[1] dma irq[1] : no effect 1 : Wake-up bit-wise AND Main Power Management Controller (MPMC) Wake-up process from Sleep mode uart irq[] GP irq IWEFH3R dma irq[] timer irq[] EIRQ[] Figure 4-12 Wake-up process from Sleep mode Stop mode 모든 clock 은정지하지만 RTC oscillator 와 RTC block 은동작한다. Wake up 소스는 RTC 또는외부입력 핀이다. - The PLLs are disabled - The Main OSC is disabled - RAM is retention Wake-up from Stop mode(halt2) #55 WAKEUP pin usb rx rtc alarm irq GP6.2 GP6.1 GP4.7 / EIRQ[1] GP4.6 / EIRQ[] GP3.7 / DBG SDA GP2.5 / UART RX GP2.2 / TWI SDA GP.1 / UART RX1 Polarity/ Mask EWEFH2R Main Power Management Controller (MPMC) PMC irq Figure 4-13 Wake-up process from Stop mode INTC CPU Power modes 4 System Control Copyright 215, Advanced Digital Chips, Inc.

42 Shutdown mode 메인전력도메인의전력이제거되고, 누설전류를감소한다. RTC 발진기, RTC 로직블록을포함하여소량의전원만유지한다. 외부전압조정기가파워다운과함께사용되는경우에만, shutdown 모드가가능하다. RTC 블록은 VBAT 에의해구동. 장치가셧다운모드에진입하면, 외부레귤레이터는턴오프된다. adstar-l VDD_SDRAM VDD_Flash Main Power Domain VDDIO Power Supply IN OUT 3.3V VDDIN LDO PD 3.3V Regulator off on VDDOUT VDDCORE 1.8V wakeup event Power Management PIN_rpd off on External Wakeup signal PIN_rwake RTC Power Doamin VDD_RTC 1.8V~3.6V Backup Battery + - Figure 4-14 Power Off for Shutdown/Static mode Wake-up sources 는 RTC interrupts, external wake-up pin 이다 Wake-up from Shutdown mode (Halt1) #55 WAKEUP pin rtc irq RTC Power Management Controller Power-up Power-on Reset CPU Booting rtc alarm irq * Do not use both rtc_irq and rtc_alarm_irq simultaneously. One of them must be used as wake-up signal. Figure 4-15 Wake-up process from Standby mode 42 4 System Control 4.3 Power modes Copyright 215, Advanced Digital Chips, Inc.

43 Static mode RTC 발진기및 RTC 블록을포함한모든클럭은중지된다. Wake up 소스는외부 wake up pin 이다. - RTC OSC is disabled. Wake-up from Static mode (Halt) #55 WAKEUP pin RTC Power Management Controller Power-up Power-on Reset CPU Booting * Both rtc_irq and rtc_alarm_irq should be de-active when using Halt Figure 4-16 Wake-up process from Static mode 4.4 System Control Registers system register 에접근하기위해서는해당비트를셋해줘야한다 System Control Global Lock Register (GLOCK) Address : x82_3c 31: W xe5511acc 를 write 하면 unlock 이된다. Unlock 된상태여야다른레지스터에쓰기가허용된다. Lock 은그외값을쓰게되면 lock 상태가된다. R Read 동작은 lock 상태인지를확인할수있다. : lock 상태 1 : unlock System Control Registers 4 System Control Copyright 215, Advanced Digital Chips, Inc.

44 System Control Write Enable Register (WREN) Address : x82_3c4 31:2 R Reserved - 19 R/W DM Clock Divider register 18 R/W LCD Clock Divider register 17 R/W CLK16_1 Divider register 16 R/W CLK16_ Divider register 15 R/W HCLK Divider register 14 R Reserved - 13 R/W USB PHY Control Register Write Enable 12 R/W PCLK Control Register Write Enable 11 R/W HCLK Control Register Write Enable 1 R/W Sound Clock Control Register Write Enable 9 R/W PLL Control Register Write Enable 8 R/W Clock Control Register Write Enable 7:4 R Reserved - 3 R/W OSC stable counter Register Write Enable - 2 R/W Interrupt Wakeup Enable register 1 R/W Reserved - R/W halt register enable (Effective CPU halt instruction enable bit) 1 - Disable write protection for the corresponding register. - Enables write protection for the corresponding register * 이레지스터를사용하려면, GLOCK 레지스터의잠금을해제해야한다. * CPU 의 Halt 명령으로 PMC 를제어하기위해서는 bit[] 를 1 로 set 해야한다. * Halt 명령으로 sleep mode 가된 core 를깨우려면, 인터럽트를발생시켜야한다 Halt Register Address : x82_3c8 31:5 R Reserved - 4: W 1 : halt 11 : halt1 12 : halt2 13 : halt3 (cpu, spm clock off) PCLK 의 one pulse 신호이다. write 된 data 가유지되지않는다. * 이레지스터를사용하려면, WREN register 에 halt register enable 비트를 enable 시켜줘야한다. * CPU halt 명령어도이 register 를접근하기때문에, 쓰기접근이활성화되어있어야한다. * Halt 명령으로 sleep mode 가된 core 를깨우려면, 인터럽트를발생시켜야한다 System Control 4.4 System Control Registers Copyright 215, Advanced Digital Chips, Inc.

45 Halt Status Register Address : x82_3cc 31:11 R Reserved - 1 R PMC IRQ 인터럽트발생유무를알수있다. PMU Status reg[] 에서도확인할수있다. 9 R RTC wakeup event latch. Halt나 Halt1에서깨어났음을알수있다. 8 R/W Cpu only clock disable during halt3 : cpu, spm clock off when halt3 excuting 1 : cpu only clock off 7:5 R Reserved. - 4: R 12 : halt2 13 : halt3 수행된 halt 모드를알수있다. Main 파워가 off 되는 halt 와 halt1 은상태를알수없다. 모두 clear 가되기때문이다. * 이레지스터를사용하려면, WREN register 에해당하는비트를 enable 시켜줘야한다 System Control Registers 4 System Control Copyright 215, Advanced Digital Chips, Inc.

46 Interrupt Wake up Enable Register Address : x82_3c1 Halt 3 모드에서만, - Wakeup 시사용할 Interrupt 종류를선택한다. IRQ 는 reg 순서와동일하다. 깨어날때사용할 IRQ 를선택하면된다. (debug irq 가포함 ) PMC irq 도포함. RTC irq RTC wakeup irq 여기서활성화된인터럽트에의해서만 CPU 의 HCLK 가살아나게됨. 인터럽트처리와는무관하다. CPU 클럭만살린다. 해당하는인터럽트에의해서 Halt3 이후 ISR 처리를위해서는인터 럽트컨트롤러를적절히설정해야지만처리가된다. 이 register 단지 cpu 클럭만깨우는데관여한다. ISR 과는무관하다. 31 R/W SWD Interrupt Use edge method Clock_ctrl_r[] 3 R/W MJPEG 1 Interrupt 29 R/W Capture Over Interrupt 28 R/W SPI LCD Interrupt 27 R/W RTC Alarm Interrupt 26 R/W RTC Interrupt 25 R/W TWI Interrupt 24 R/W NAND Interupt 23 R/W WDT Interrupt 22 R/W DMA CH5 Interrupt, GPIO 3 interrupt, GPIO 6 interrupt 21 R/W SDCard Interrupt 2 R/W DMA CH4 Interrupt, GPIO 2 Interrupt, GPIO 5 Interrupt 19 R/W MJPEG Interrupt 18 R/W SPI Interrupt 17 R/W DMA CH3 Interrupt 16 R/W UART 1 Interrupt 15 R/W GPIO 1 Interrupt, GPIO 4 Interrupt 14 R/W USB host interrupt, Device Interupt 13 R/W ADC Interrupt 12 R/W DMA CH2 Interrupt 11 R/W PMC interrupt 1 R/W Timer 1 Interrupt 9 R/W DMA CH1 Interrupt 8 R/W UART Interrupt 7 R/W GPIO Interrupt 6 R/W DMA CH Interrupt 5 R/W LCD Frame sync Interrupt 4 R/W EIRQ1 Interrupt 3 R/W Sound Mixer Interrupt 2 R/W Timer Interrupt 1 R/W Core timer Interrupt R/W EIRQ Interrupt (Highest Priority) * 이레지스터를사용하려면, WREN register 에해당하는비트를 enable 시켜줘야한다. * halt3 (sleep mode) 상태에서 wakeup 할때, 어떤 interrupt 에의해 wakeup 할지결정해주는 register 이다 System Control 4.4 System Control Registers Copyright 215, Advanced Digital Chips, Inc.

47 Event Wake up Enable Register Address : x82_3c14 31:27 R Always awake by the RTC wakeup signal. This is not an option - 26 R/W SWD interrupt mask : mask 1: unmask 25 R/W Usb receive data mask : mask 1: unmask 24 R/W Rtc alarm interrupt mask : mask 1: unmask 23 R/W Gp6.2 mask : mask 1: unmask 22 R/W GP6.1 mask : mask 1: unmask 21 R/W GP4.7 mask : mask 1: unmask 2 R/W GP4.6 mask : mask 1: unmask 19 R/W GP3.7 mask : mask 1: unmask 18 R/W GP2.5 mask : mask 1: unmask 17 R/W GP2.2 mask : mask 1: unmask 16 R/W GP.1 mask : mask 1: unmask 15:11 R Reserved _ 1 R/W SWD interrupt Polarity : active low 1: active high 9 R/W Usb receive data Polarity : active low 1: active high 8 R/W Rtc alarm interrupt Polarity : active high 1: active low 7 R/W GP6.2 Polarity : active low 1: active high 6 R/W GP6.1 Polarity : active low 1: active high 5 R/W GP4.7 Polarity : active low 1: active high 4 R/W GP4.6 Polarity : active low 1: active high 3 R/W GP3.7 Polarity : active low 1: active high 2 R/W GP2.5 Polarity : active low 1: active high 1 R/W GP2.2 Polarity : active low 1: active high R/W GP.1 Polarity : active low 1: active high * 이레지스터를사용하려면, WREN register 에해당하는비트를 enable 시켜줘야한다 * halt2 (stop mode) 상태에서 wakeup 할때, 어떤 interrupt 에의해 wakeup 할지결정해주는 register 이다. * 이신호는 PCM_IRQ 로통합된다. PMC ISR 루틴이수행된다. 그리고이 register 를읽으면어떤 wake up source 에의해 wake up 이발생했는 지알수있다. Halt2 상태로진입중에발생한 wake up event 는무시가된다. 진입이완벽하게이뤄진뒤에 wake up event 가발생하면, 깨어나기시작한다 System Control Registers 4 System Control Copyright 215, Advanced Digital Chips, Inc.

48 PMC Status Register Address : x82_3c18 31:2 R Reserved. - 1 R/W RTC s/w reset : release reset(normal operation state) 1 : reset asserted R/W PMC IRQ clear bit Read 하면 IRQ 발생유무확인 1 을 Write 하면 clear 함.( write 할필요없음, 자동 clear 됨 ) PMC IRQ 는 halt2, halt1, halt 에서발생한다. Halt3 에서는발생하지않는다. Halt 3 에서는 Wake 를한블록의 irq 를고려하면된다 OSC Stable Counter Register Address : x82_3c1c 31:11 R Reserved. - 1 : R/W Wake 시사용될 osc stable coutner 의 value 이다. 11 h7ff * 이레지스터를사용하려면, WREN register 에해당하는비트를 enable 시켜줘야한다 Clock Control Register (CLKCON) Address : x82_3c2 31:24 R Reserved. - 23:2 R/W ADC Clock divider : System Clock 1: System Clock / 2 1: System Clock / 3 11: System Clock / 4 111: System Clock / : System Clock / 16 12:8 R/W PLL Lock Counter value for halt2 5 h1f 7:4 R Reserved. - 5 : 4 R/W PLL1 clock source select. These bits select the PLL1 clock source. :xin clock selected 1:GPIO clock selected 1x:clk16_ clock selected 3 R/W USB Clock Enable : USB clock is off 1: USB clock is on 2 R/W USB Clock divider. USB requires 48MHz clock. : USB Source Clock (when source clock is 48MHz) 1: USB Source Clock / 2 (when source clock is 96MHz) 1 R/W USB Source Clock Select. : pll_clk selected 1: pll1_clk selected R/W Select clock source for HCLK domain : XIN input selected 1: PLL clock selected * 이레지스터를사용하려면, WREN register 에해당하는비트를 enable 시켜주고, GLOCK register 를해제 시켜줘야한다 48 4 System Control 4.4 System Control Registers Copyright 215, Advanced Digital Chips, Inc.

49 PLL Control Register (PLLCON) Address : x82_3c24 31 : 29 Reserved - 28 R/W PLL Power Down 1 : normal operation 1 : power down 27 : 26 R Reserved - 25 : 24 R/W OD (Output divider). These bits set the output divider value for the PLL. : divide by 1 1 : divide by 4 1 : divide by 2 11 : divide by 8 23 : 2 R Reserved - 19 : 16 R/W R (Input divider). These bits set the input divider value for the PLL. 2h R must be >=2 or unpredictable operation results. 15 : 12 R Reserved - 11 : R/W N (Multiplier). These bits set the multiplier value for the PLL. N must be >=2 or unpredictable operation results. 2h * 이레지스터를사용하려면, WREN register 에해당하는비트를 enable 시켜주고, GLOCK register 를해제 시켜줘야한다 * FOUT = (XIN*N)/(R*OD) System Control Registers 4 System Control Copyright 215, Advanced Digital Chips, Inc.

50 Clock Divider Control Register (CLKDCON) Address : x82_3c28 31:28 R Reserved - 27:25 R/W DM clock source select. : clk16_ 1: clk16_1 1: clk15 11: clk25 1: clk45 11: clk5 11: clk : XIN 24:22 R/W LCD clock source select. : clk16_ 1: clk16_1 1: clk15 11: clk25 1: clk45 11: clk5 11: clk : XIN 21:2 R/W CLK16_1 clock source select. : XIN 1 : GPIO 1 : PLL1 19:18 R/W CLK16_ clock source select. : XIN 1 : GPIO 1 : PLL 17:16 R/W CLK256 clock source select. : xin 1: GPIO clock 1: pll 11: pll1 15:14 R/W CLK5 clock source select. : xin 1: GPIO clock 1: pll 11: pll1 13:12 R/W CLK45 clock source select. 1 : xin 1: GPIO clock 1: pll 11: pll1 11:1 R/W CLK25 clock source select. : xin 1: GPIO clock 1: pll 11: pll1 9:8 R/W CLK15 clock source select. : xin 1: GPIO clock 1: pll 11: pll1 7: R Reserved - * 이레지스터를사용하려면, WREN register 에해당하는비트를 enable 시켜주고, GLOCK register 를해제 시켜줘야한다. 5 4 System Control 4.4 System Control Registers Copyright 215, Advanced Digital Chips, Inc.

51 AHB Clock Enable Register (HCLKEN) Address : x82_3c2c 31 R/W bus clock enable 1 3:16 R Reserved R/W SD Card IO clock enable 1 14 R/W NAND clock enable 1 13 R/W CRTC clock enable 1 12 R/W USB Host Clock Enable 1 (12MHz, 48MHz, bus clock) 11 R/W USB Device Clock Enable 1 (12MHz, 48MHz, bus clock) 1 R Reserved. - 9 R Reserved. - 8 R/W H/W JPEG AHB Clock Enable 1 7 R/W SPI LCD Clock Enable 1 6 R/W Flash Controller Clock Enable 1 5 R/W DMA Clock Enable 1 4 R/W GPIO Clock Enable 1 3 R/W Interrupt Controller Clock Enable 1 2 R/W SDRAM Clock Enable 1 1 R/W SDRAM Controller Clock Enable 1 R Reserved. 1 * 이레지스터를사용하려면, WREN register 에해당하는비트를 enable 시켜주고, GLOCK register 를해제 시켜줘야한다 APB Clock Enable Register (PCLKEN) Address : x82_3c3 31 R/W Bus clock Enable 1 PMU block signal. Power management is not available without this clock.(halt3) 3:16 R Reserved R/W RTC interface clock enable 1 13 R/W CRTC clock enable 1 12 R/W Pin MUX Clock Enable 1 11 R/W ADC APB Clock Enable 1 1 R Reserved. - 9 R Reserved. - 8 R/W Sound Mixer APB Clock Enable 1 7 R/W TWI Clock Enable 1 6 R/W Reserved. 1 5 R/W SPI Clock Enable 1 4 R/W UART Clock Enable 1 3 R/W Timer Clock Enable 1 2 R/W Watch Dog Timer Clock Enable 1 1 R Reserved. - R Reserved. - * 이레지스터를사용하려면, WREN register 에해당하는비트를 enable 시켜주고, GLOCK register 를해제 시켜줘야한다 System Control Registers 4 System Control Copyright 215, Advanced Digital Chips, Inc.

52 USB PHY Control Register (USBPHYCON) Address : x82_3c34 31:18 R Reserved - 17 R/W Reserved 1 16 R/W Reserved 15: 9 R Reserved - 8 R/W USB Function Select bit : USB Device 1: USB Host 7 R USB PHY suspend bit : No effect 1: Suspend 6 R/W D- Pull-down Enable bit : Pull-down Disable 1: Pull-down Enable 5 R/W D+ Pull-down Enable bit : Pull-down Disable 1: Pull-down Enable 4 R/W Receive Enable bit : USB PHY 가외부신호를받아들이지않는다. 1: USB PHY가외부신호를받아들인다. 3 R/W D- Weak Pull-up Enable bit : Pull-up Disable 1: Pull-up Enable 2 R/W D- Pull-up Enable bit : Pull-up Disable 1: Pull-up Enable 1 R/W D+ Weak Pull-up Enable bit : Pull-up Disable 1: Pull-up Enable R/W D+ Pull-up Enable bit : Pull-up Disable 1: Pull-up Enable * 이레지스터를사용하려면, WREN register 에해당하는비트를 enable 시켜주고, GLOCK register 를해제 시켜줘야한다 Boot mode status register(bmst) Address : x82_3c38 31:1 R Reserved - R Boot mode : normal mode or debug mode.. etc 1: nandboot mode 1 * 이레지스터를사용하려면, WREN register 에해당하는비트를 enable 시켜주고, GLOCK register 를해제 시켜줘야한다 Boot mode config register(bmct) Address : x82_341c (pin mux register) 31:5 R Reserved - 4 : 2 R : NAND Boot Small 3C 111b 1 : NAND Boot Small 4C 1 : NAND Boot Large 4C 11 : NAND Boot Large 5C 1 : NAND Boot MLC 4-bit 11 : NAND Boot MLC 24-bit 11 : Serial Flash boot 111 : Serial Flash boot 1 R Reserved 1 R : Debug boot 1 : Normal boot System Control 4.4 System Control Registers Copyright 215, Advanced Digital Chips, Inc.

53 HCLK clock divide register(hclkdiv) Address : x82_3c3c 31:5 R Reserved - 4 R/W Synchronization bit 1로설정하면 synch 가되고, 다시 으로반드시설정해준다. 3: R/W AHB Clock Select : Source Clock 1: Source Clock / 2 1: Source Clock / 3 11: Source Clock / 4 111: Source Clock / : Source Clock / 16 * 이레지스터를사용하려면, WREN register 에해당하는비트를 enable 시켜주고, GLOCK register 를해제 시켜줘야한다 CLK16_ clock divide register(clk16div) Address : x82_3c4 31:5 R Reserved - 4 R/W Synchronization bit 1로설정하면 synch 가되고, 다시 으로반드시설정해준다. 3: R/W CLK16_ Clock Select : Source Clock 1: Source Clock / 2 1: Source Clock / 3 11: Source Clock / 4 111: Source Clock / : Source Clock / 16 * 이레지스터를사용하려면, WREN register 에해당하는비트를 enable 시켜주고, GLOCK register 를해제 시켜줘야한다 CLK16_1 clock divide register(clk16div1) Address : x82_3c44 31:5 R Reserved - 4 R/W Synchronization bit 1로설정하면 synch 가되고, 다시 으로반드시설정해준다. 3: R/W CLK16_1 Clock Select : Source Clock 1: Source Clock / 2 1: Source Clock / 3 11: Source Clock / 4 111: Source Clock / : Source Clock / 16 * 이레지스터를사용하려면, WREN register 에해당하는비트를 enable 시켜주고, GLOCK register 를해제 시켜줘야한다 LCD clock divide register(lcddiv) Address : x82_3c48 31:5 R Reserved - 4 R/W Synchronization bit 1로설정하면 synch 가되고, 다시 으로반드시설정해준다. 3: R/W LCD Clock Select : Source Clock 1: Source Clock / 2 1: Source Clock / 3 11: Source Clock / 4 111: Source Clock / : Source Clock / 16 * 이레지스터를사용하려면, WREN register 에해당하는비트를 enable 시켜주고, GLOCK register 를해제 시켜줘야한다 System Control Registers 4 System Control Copyright 215, Advanced Digital Chips, Inc.

54 Sound Mixer clock divide register(smdiv) Address : x82_3c4c 31:5 R Reserved - 4 R/W Synchronization bit 1로설정하면 synch 가되고, 다시 으로반드시설정해준다.. 3: R/W DM Clock Select : Source Clock 1: Source Clock / 2 1: Source Clock / 3 11: Source Clock / 4 111: Source Clock / : Source Clock / 16 * 이레지스터를사용하려면, WREN register 에해당하는비트를 enable 시켜주고, GLOCK register 를해제 시켜줘야한다 PLL1 Control Register (PLLCON1) Address : x82_3c5 31 : 29 Reserved - 28 R/W PLL Power Down 1 : normal operation 1 : power down 27 : 26 R Reserved - 25 : 24 R/W OD (Output divider) 에대한 PLL1 출력분주값을설정. : divide by 1 1 : divide by 4 1 : divide by 2 11 : divide by 8 23 : 2 R Reserved - 19 : 16 R/W R (Input divider). 에대한입력 PLL1 디바이더값을설정. 2h R must be >=2 or unpredictable operation results. 15 : 12 R Reserved - 11 : R/W N (Multiplier) PLL1 승수값을설정. N must be >=2 or unpredictable operation results. 2h * 이레지스터를사용하려면, WREN register 에해당하는비트를 enable 시켜주고, GLOCK register 를해제 시켜줘야한다. * FOUT = (XIN*N)/(R*OD) 54 4 System Control 4.4 System Control Registers Copyright 215, Advanced Digital Chips, Inc.

55 A H B B U S adstar-l 5 SPI FLASH MEMORY CONTROLLER 5.1 Introduction Flash 메모리는메모리의용량제한은 512k bytes 이며, 메모리의동작속도는최대 8Mhz 까지이지만 Flash Memory Controller 는 AHB clock 을분주하여사용하므로최대시스템 clock 의 2 분주로동작하게된다. Flash controller 는 2 개의 bus interface 가존재한다 : [memory interface & register interface] Memory interface 는 CPU 와 DMA 가직접접근하여, flash memory 의 data 를 read 또는 write 한다. XIP (execute In Place) Register interface 는 SPI flash mode 를설정하거나, flash memory 에 read/write/erase 를수행할수있다. _h ~ FFF_FFFFh Memory Access MEM_IF CLK_GEN CLK 4_h ~ 4FFF_FFFFh DAT_BUF SDIO[3:] Internal/ External SPI Flash Memory 8_h ~ 8_3FFh Register Access REG_IF SF_CTRL CSx Figure 5-1 Flash Memory Controller Block Diagram 5.2 Feature SPI flash controller 의주요기능 - Single, Double 및 Quad mode - H / W 및 S / W 통한 flash erase 및 flash program - XIP 제공 (execute In Place) Introduction 5 SPI Flash Memory Controller Copyright 215, Advanced Digital Chips, Inc.

56 5.3 Functional Description Register Interface register interface 를통해 operation mode selection register 및 command/data register 를설정할수있다. Register interface 기능 - Flash erase operation - Flash program operation - Read/Write status operation. - Read data operation Memory Interface memory interface range 안에서, flash memory 에직접 read/write 를수행한다. (XIP mode) read 동작이수행되면, controller 는 read 가완료될때까지, next access 를하지않으며, wait 상태를유지 한다. Memory interface 기능 - Flash program operation - Read data operation Internal Flash Memory Internal flash memory 기능 - 4M-bit/512K-byte byte per programmable page - Uniform 4KB Sectors, 32KB & 64KB Blocks - More than 1, erase/write cycles - More than 2-year data retention SFDP Register Security Register 1-3 h xxffh xxfh xxefh xxeh xxdfh xxdh Sector 15 (4KB) Sector 14 (4KB) Sector 13 (4KB) FFh xxffffh xxfffh xxefffh xxeffh xxdfffh xxdffh 3h 2h 1h 7FFh 7h Block 7 (64KB) 3FFh 2FFh 1FFh 7FFFFh 7FFh xx2fh xx2h xx1fh xx1h xxfh xxh Sector 2 (4KB) Sector 1 (4KB) Sector (4KB) xx2fffh xx2ffh xx1fffh xx1ffh xxfffh xxffh 4FFh 4h 3FFh 3h FFh h Figure 5-2 Internal Serial Flash Memory Block 4 (64KB) Block 3 (64KB) Block (64KB) 4FFFFh 4FFh 3FFFFh 3FFh FFFFh FFh 56 5 SPI Flash Memory Controller 5.3 Functional Description Copyright 215, Advanced Digital Chips, Inc.

57 Internal Flash Memory Commands Instruction NAME Table 5-1 Instruction Set Table 1 (Erase, Program Instructions) BYTE 1 (CODE) BYTE2 BYTE3 BYTE4 BYTE5 BYTE6 Write Enable Write Enable for Volatile Status Register Write Disable 6h 5h 4h Read Status Register-1 5h (S7-S) Read Status Register-2 35h (S15-S8) Write Status Register 1h S7-S S15-S8 Page Program 2h A23-A16 A15-A8 A7-A D7-D Quad Page Program 32h A23-A16 A15-A8 A7-A D7-D, Sector Erase (4KB) 2h A23-A16 A15-A8 A7-A Block Erase (32KB) 52h A23-A16 A15-A8 A7-A Block Erase (64KB) D8h A23-A16 A15-A8 A7-A Chip Erase Erase / Program Suspend Erase / Program Resume Power-down Continuous Read Mode Reset C7/6h 75h 7Ah B9h FFh FFh Functional Description 5 SPI Flash Memory Controller Copyright 215, Advanced Digital Chips, Inc.

58 Instruction NAME Release Power Down/ Device ID Manufacturer/ Device ID Manufacturer/Device ID by Dual I/O Manufacturer/Device ID by Quad I/O JEDEC ID Table 5-2 Instruction Set Table 2 (Read Instructions) BYTE 1 BYTE2 BYTE3 BYTE4 BYTE5 BYTE6 (CODE) ABh dummy dummy dummy (ID7-ID) 9h dummy dummy h (MF-MF) (ID7-ID) 92h 94h 9Fh A23-A8 A23-A, M[7:] (MF7-MF) manufacturer A7-A, M[7:] xxx,(mf[7:], ID[7:]) (D15-ID8) Memory Type (MF[7:], ID[7:]) (MF[7:], ID[7:], ) (ID7-ID) Capacity Read Unique ID 4Bh dummy dummy dummy dummy (ID63-ID) Read SFDP Register 5Ah h h A7-A dummy (D7-D) Erase Security Registers Program Security Registers Read Security Registers 44h A23-A16 A15-A8 A7-A 42h A23-A16 A15-A8 A7-A D7-D D7-D 48h A23-A16 A15-A8 A7-A dummy D7-D Instruction NAME Release Power Down/ Device ID Manufacturer/ Device ID Manufacturer/Device ID by Dual I/O Manufacturer/Device ID by Quad I/O JEDEC ID Table 5-3 Instruction Set Table 3 (ID, Security Instructions) BYTE 1 BYTE2 BYTE3 BYTE4 BYTE5 BYTE6 (CODE) ABh dummy dummy dummy (ID7-ID) 9h dummy dummy h (MF-MF) (ID7-ID) 92h 94h 9Fh A23-A8 A23-A, M[7:] (MF7-MF) manufacturer A7-A, M[7:] xxx,(mf[7:], ID[7:]) (D15-ID8) Memory Type (MF[7:], ID[7:]) (MF[7:], ID[7:], ) (ID7-ID) Capacity Read Unique ID 4Bh dummy dummy dummy dummy (ID63-ID) Read SFDP Register 5Ah h h A7-A dummy (D7-D) Erase Security Registers Program Security Registers Read Security Registers 44h A23-A16 A15-A8 A7-A 42h A23-A16 A15-A8 A7-A D7-D D7-D 48h A23-A16 A15-A8 A7-A dummy D7-D 58 5 SPI Flash Memory Controller 5.3 Functional Description Copyright 215, Advanced Digital Chips, Inc.

59 Flash Status Register Flash Status Register (FLSTS) S7 S6 S5 S4 S3 S2 S1 S SRP SEC TB BP2 BP1 BP WEL BUSY STATUS REGISTER PROTECT (non-vlolatile) SECTOR PROTECT (non-vlolatile) TOP/BOTTOM PROTECT (non-vlolatile) BLOCK PROTECT BITS (non-volatile) WRITE ENABLE LATCH ERASE/WRITE IN PROGRESS Figure 5-3 Serial Flash Memory Status Register 1 위의레지스터는플래시상태레지스터의하위 1 바이트를 access 한것이다. 기록동작이완료되지않는것은 [] 번비트 (BUSY) 를사용하여확인한다. Flash 2nd Status Register (FLSTS2) S15 S14 S13 S12 S11 S1 S9 S8 SUS CMP LB3 LB2 LB1 LB QE SRP1 SUSPEND STATUS COMPLEMENT PROTECT (non-vlolatile) SECURITY REGISTER LOCK BITS (non-vlolatile OTP) QUAD ENABLE (non-volatile) STATUS REGISTER PROTECT 1 (non-volatile Figure 5-4 Serial Flash Memory Status Register 2 위의레지스터는플래시상태레지스터의상위 1 바이트에 access 한것이다. 쿼드모드사용은 [1] 번비트를설정하여수행할수있다 (QE). - 플래시상태레지스터 [9] 번비트사용 Functional Description 5 SPI Flash Memory Controller Copyright 215, Advanced Digital Chips, Inc.

60 Table 5-4 Serial Flash Memory Status Register Description Bit Signal Name Description 15 SUS Erase/Program Suspend Status The suspend Status bit is a read only bit in the status register (S15) that is set to 1 after executing a Erase/Program Suspend (75h) instruction. The SUS status bit is cleared to by Erase/Program Resume (7Ah) instruction as well as a power-down, power-up cycle. 14 CMP Complement Protect The Complement Protect bit (CMP) is a non-volatile read/write bit in the status register (S14). It is used in conjunction with SEC, TB, BP2, BP1 and BP bits to provide more flexibility for the array protection. Once CMP is set to 1, previous array protection set by SEC, TB, BP2, BP1 and BP will be reversed. For instance, when CMP=, a top 4KB sector can be protected while the rest of the array is not; when CMP=1, the top 4KB sector will become unprotected while the rest of the array become read-only, Please refer to the Status Register Memory Protection table for details. The default setting is CMP= LB3 LB2 LB1 LB Security Register Lock Bits The Security Register Lock Bits (LB3, LB2, LB1, LB) are non-volatile One Time Program (OTP) bits in Status Register (S13, S12, S11, S1) that provide the write protect control and status to the Security Registers. The default state of LB3- is, security Registers are unlocked. LB3- can be set to 1 individually using the Write Status Register instruction. LB3- are One Time Programmable (OTP), once it s set to 1, the corresponding 256-Byte Security Register will become read-only permanently. 9 QE Quad Enable The Quad Enable (QE) bit is a non-volatile read/write bit in the status register (S9) that allows Quad SPI operation. When the QE bit is set to a state (factory default), the /WP pin and /HOLD are enable. When the QE bit is set to a 1, the Quad IO2 and IO3 pins are enabled. 8 SRP1 Status Register Protect 7 SRP The Status Register Protect bits (SRP1 and SRP) are non-volatile read/write bits in the status register (S8 and S7). The SRP bits control the method of write protection: software protection, hardware protection, power supply lock-down or one time programmable (OTP) protection. 6 SEC Sector/Block Protect The non-volatile Sector/Block Protect bit (SEC) controls if the Block Protect Bits (BP2, BP1, BP) protect either 4KB Sectors (SEC=1) or 64KB Blocks (SEC=) in the Top (TB=) or the Bottom (TB=1) of the array as shown in the Status Register Memory Protection table. The default setting is SEC=. 5 TB Top/Bottom Block Protect The non-volatile Top/Bottom bit (TB) controls if the Block Protect Bits (BP2, BP1, BP) protect from the Top (TB=) or the Bottom (TB=1) of the array as shown in the Status Register Memory Protection table. The factory default setting is TB=. The TB bit can be set with the Write Status Register Instruction depending on the state of the SRP, SRp1 and WEL bits. 4 BP2 Block Protect Bits 3 BP1 2 BP The Block Protect Bits (BP2, BP1, BP) are non-volatile read/write bits in the status register (S4, S3, and S2) that provide Write Protection control and status. Block Protect bits can be set using the Write Status Register Instruction (see tw in AC characteristics).; All, none or a portion of the memory array can be protected from Program and Erase instructions (see Status Register memory Protection table). The factory default setting for the Block Protection Bits is, none of the array protected. 1 WEL Write Enable Latch Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to 1 after executing a Write Enable Instruction. The WEL status bit is cleared to when the device is write disabled. A write disable state occurs upon power-up or after any of the following instructions: Write Disable, Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Erase Security Register and Program Security Register. BUSY BUSY is a read only bit in the status register (S) that is set to a 1 state when the device is executing a Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register or Erase/Program Security Register instruction. During this time the device will ignore further instructions except for the Read Status Register and Erase/Program Suspend instruction (see TW, tpp, tse,tbe, and tce in AC Characteristics). When the program, erase or write status/security register instruction has completed, the BUSY bit will be cleared to a state indicating the device is ready for further instruction. 6 5 SPI Flash Memory Controller 5.3 Functional Description Copyright 215, Advanced Digital Chips, Inc.

61 Chip Erasing Flash memory Using FLCMD register (entire flash memory) - Write 6h command to the FLCMD register. - Write C7h/6h command to the FLCMD register. Using SFDAT register (entire flash memory) - Set the chip select bit in the SFMOD register to x(chip select low). - Write 6h command to the SFDAT register. - Set the chip select bit in the SFMOD register to x1(chip select high). - Set the chip select bit in the SFMOD register to x(chip select low). - Write C7h/6h command to the SFDAT register. - Set the chip select bit in the SFMOD register to x1(chip select high) - Poll the busy status bit of the FLSTS register until this operation has completed (Chip Erase complete) Sector/Block Erasing Flash memory Using FLSEA register (4KB) - Set the address associated with the Flash memory region. Using FLBEA register (64KB) - Set the address associated with the Flash memory region. Using SFDAT register (4KB, 32KB, 64KB) - Set the chip select bit in the SFMOD register to x(chip select low). - Write 6h command to the SFDAT register. - Set the chip select bit in the SFMOD register to x1(chip select high). - Set the chip select bit in the SFMOD register to x(chip select low). - Write 2h(4KB) or 52h(32KB) or D8h(64KB) command to the SFDAT register - Write the target address [23:16] to the SFDAT register. - Write the target address [15:8] to the SFDAT register. - Write the target address [7:] to the SFDAT register. - Set the chip select bit in the SFMOD register to x1(chip select high). - Poll the busy status bit of the FLSTS register until this operation has completed (Sector/Block Erase complete) Programing Flash memory Using SFDAT register - Set the chip select bit in the SFMOD register to x(chip select low). - Write 6h command to the SFDAT register. - Set the chip select bit in the SFMOD register to x1(chip select high). - Set the chip select bit in the SFMOD register to x(chip select low). - Write 2h command to the SFDAT register - Write the target address [23:16] to the SFDAT register. - Write the target address [15:8] to the SFDAT register. - Write the target address [7:] to the SFDAT register - Write a 32-bit, 16-bit or 8-bit data up to 256 byte. - Set the chip select bit in the SFMOD register to x1(chip select high). - Poll the busy status bit of the FLSTS register until this operation has completed (Erase complete) Functional Description 5 SPI Flash Memory Controller Copyright 215, Advanced Digital Chips, Inc.

62 Reading Flash memory Using SFDAT register - Set the chip select bit in the SFMOD register to x(chip select low). - Write 3h command to the SFDAT register. - Write the target address [23:16] to the SFDAT register. - Write the target address [15:8] to the SFDAT register. - Write the target address [7:] to the SFDAT register - Read a 32-bit, 16-bit or 8-bit data up to 256 byte. - Set the chip select bit in the SFMOD register to x1(chip select high) Power Down and Release Power Down Using SFDAT register (Power down) - Set the chip select bit in the SFMOD register to x(chip select low). - Write B9h command to the SFDAT register. - Set the chip select bit in the SFMOD register to x1(chip select high). Using SFDAT register (Release Power down) - Set the chip select bit in the SFMOD register to x(chip select low). - Write ABh command to the SFBAT register. - SFDAT(8bit, 16bit, 32bit access 가능 ) Read - Set the chip select bit in the SFMOD register to x1(chip select high) Flash Mode Register (FLMOD) Flash 동작모드결정 (Single, Dual, Quad) Flash Baudrate Register (FLBRT) Flash baudrate(high pulse 및 low pulse) register Chip Select High Pulse Width CSx SCK High Pulse Width SCK SCK Low Pulse Width Figure 5-5 SCK and CS timing Flash Chip Select High Pulse Width Register (FLCSH) flash memory chip select high time 을설정하는 register 이다. [deselect 시전류의변화는없을것이다.] Program/Erase 후 read 동작시, 또는 read 후다음 read 동작시까지, 5ns 의 deselect time 이필요하다. adstar-l 의 external flash memory 의값은, flash type 마다다르므로, 해당 flash memory deselect time 을 check 해야한다 SPI Flash Memory Controller 5.3 Functional Description Copyright 215, Advanced Digital Chips, Inc.

63 Flash WIP Check Period Register (FLWCP) Flash memory 를 program 하거나 erase 시 hardware 적으로 flash memory 의상태를확인하는 period 를결정하는 register 이다. Status memory 의 bit 와도관련이있으며 flash controller 의 status register 를통해서도확인이가능하다 Flash Clock Delay Register (FLCKDLY) Serial Flash Controller D SET sfclkout Q Serial Flash Memory SCK CLR Q Q SET D sfclkfd Q CLR sfclkout SCK sfclkfd Figure 5-6 Flash Clock Delay Timing 이 register 는 read timing 을정정해준다. register 의값에따라 read clock 이 delay 된다 Functional Description 5 SPI Flash Memory Controller Copyright 215, Advanced Digital Chips, Inc.

64 5.4 Register Description Flash Mode Register (FLMOD) Address : x8_ 31:9 R Reserved - 8 R/W Chip select control 1b 1: Chip select 신호가 H/W 에의해제어 : Chip select 신호를 Low level로고정 7 R/W Bus Error Enable 1: Flash 에 Write 접근이일어날시, Bus Error 를발생 : Flash에 Write 허용 6 R Reserved - 5 R EQIO Mode Flag; Checks whether or not this feature is available in flash memory. 1: EQIO Mode : Normal Mode Command Register 에 EQIO(38h) 를 write 하면 Flash 는 EQIO 모드로 전환된다. 4 R Performance Enhance Mode (Flash 지원여부확인 ) 1: Performance Enhance Mode 가적용. : Normal Mode. 적용되지않음. FLPEM Register 에 1 을 write 하여 Performance Enhance Mode 를 Enable하였을경우, Quad Read이거나 EQIO 모드일때만적용된다. 3 R/W Bus Ready Control : Write 동작의경우, bus ready 를제어. S/W 가 flash 의 status 를확인 할필요없음. 1: Write 동작후, S/W에서 flash의 status를확인하도록설정. 2 R Reserved - 1: R/W Flash Read Mode b : Single Read Mode 1: Dual Read Mode 1: Quad Read Mode 11: Reserved 1b b 64 5 SPI Flash Memory Controller 5.4 Register Description Copyright 215, Advanced Digital Chips, Inc.

65 Flash Baudrate Register (FLBRT) Address : x8_4 31:8 R Reserved - 7:4 R/W SCK High Pulse Width 111b : 1clock 1: 2clocks 1: 3clocks 111: 15clocks 1111: 16clocks 3: R/W SCK Low Pulse Width 111b : 1clock 1: 2clocks 1: 3clocks 111: 15clocks 1111: 16clocks Flash Chip Select High Pulse Width Register (FLCSH) Address : x8_8 31:8 R Reserved - 7: R/W Chip Select High Pulse Width (It need 1ns) FFh Delay in hclk_sf clocks for the length that the chip select output is deasserted between transactions. The minimum delay is always the deselect period to ensure the chip select is never re-asserted within the deselect period. : 1clock 1: 2clocks 1: 3clocks : 255clocks : 256clocks Flash Performance Enhance Mode Register (FLPEM) Address : x8_c 31:1 R Reserved - R/W Performance Enhance Mode 1: Enabled : Disabled b Flash Command Register (FLCMD) Address : x8_1 31:8 R Reserved - 7: R/W Flash Command b Flash Status Register (FLSTS) Address : x8_14 31:8 R Reserved - 7: R/W Flash Status b Flash Sector Erase Address Register (FLSEA) Address : x8_18 31:24 R Reserved - 23: R/W Flash Sector Address to Erase b Register Description 5 SPI Flash Memory Controller Copyright 215, Advanced Digital Chips, Inc.

66 Flash Block Erase Address Register (FLBEA) Address : x8_1c 31:24 R Reserved - 23: R/W Flash Block Address to Erase b Flash Data Register (FLDAT) Address : x8_2 31: R/W Flash Data (8, 16, 32-bit supported) b Flash WIP Check Period Register (FLWCP) Address : x8_24 31: R/W Flash WIP Status Check Period FFFh Flash Clock Delay Register (FLCKDLY) Address : x8_28 31:4 R Reserved - 3: R/W Serial Flash Feed-back Clock Delay Value h Flash 2nd Status Register (FLSTS2) Address : x8_2c 31:8 R Reserved - 7: R Flash 2nd Status (Winbond only) Flash ID Read Register (FLIDR) Address : x8_3 31:24 R Reserved - 23: R Serial Flash JEDEC ID Read h 66 5 SPI Flash Memory Controller 5.4 Register Description Copyright 215, Advanced Digital Chips, Inc.

67 Flash Memory Size Write Register (SFMSIZE) Address : x8_34 31:9 R Reserved - 8 R/W 두개의 Flash 접근방법을결정한다. 1: bit 4 에의해서결정한다. : Flash의사이즈에따라서결정한다. 7:5 R Reserved - 4 R/W 두개의 flash 사용시원하는 flash를선택할수있다. Flash1 의시 작주소는 x 이다. Flash 의시작주소도 x 이다. 1: Flash 1 : Flash 3: R/W 첫번째 flash 의크기를결정한다. 이크기보다큰접근은 4 Flash1 로접근하게된다. :32Kbyte 1: 64Kbyte 1: 128Kbyte 11: 256Kbyte 1: 512Kbyte 11: 1Mbyte 11: 2Mbyte 111: 4Mbyte 1: 8Mbyte 11: 16Mbyte adstar-l 시리즈에서 Flash, Flash1 의의미는다음그림과같다. Chip Select(CS) 신호의기호도주의해서봐야한다. Internal Flash / External Flash External Flash Only L8MF512 / L16MF512 I_cs_n Flash L8M / L16M No flash adstar-l adstar-l CS_n Flash 1 CS_n Flash CS1_n Flash 1 Figure 5-7 Access Two Flash Register Description 5 SPI Flash Memory Controller Copyright 215, Advanced Digital Chips, Inc.

68 6 GPIO (GENERAL PURPOSE I/O) GPIO Ports 는 8-bit 으로구성된 6 개블록과 7-bit 으로구성된 1 개의블록으로총 55 개의 I/O Ports 를 제공한다. 각 Ports 는레지스터설정으로쉽게구성될수있으며, 다양한입출력응용과시스템구성에 사용된다. 6.1 Features GP.x has 8 I/O Ports GP1.x has 8 I/O Ports GP2.x has 8 I/O ports GP3.x has 8 I/O ports GP4.x has 8 I/O Ports GP5.x has 8 I/O Ports GP6.x has 7 I/O ports 6.2 Block Diagram GPxPUS GPxAF Alternate Function (Direction) GPxODIR/GPxIDIR VDD33 Alternate Function (Output) GPxOHIGH/GPxOLOW Alternate Function (Input) 1 GND GPxCMOS GPxSCHMT GPxEDS GPxILEV Edge Detect SYNCHRONIZER Q D Q D F/F Latch G GPxRED GRxFED CLK GPxPDS Figure 6-1 GPIO Block Diagram 68 6 GPIO (General Purpose I/O) 6.1 Features Copyright 215, Advanced Digital Chips, Inc.

69 6.3 Functional Description Port Control GPIO Ports 는 GPxODIR 레지스터를통해각 Port 별로 Output mode 로설정되고또한 GPxIDIR 레지스터에의해각 Port 별로 Input mode 로설정된다. 각 Port 의설정상태는 GPxDIR 레지스터를통해확인할수있다. GPxODIR 레지스터와 GPxIDIR 레지스터설정시 1 인비트만해당동작으로설정되고, 인비트는어떠한영향을미치지못한다. GPIO Ports 의출력레벨은 Output mode 로설정된상태에서 GPxOHIGH 레지스터를통해 High Level 로 설정되고, GPxOLOW 레지스터를통해 Low Level 로설정된다. Output level 의설정상태는 GPxOLEV 레지스터를통해확인할수있다. GPIO Ports 의입력레벨은 GPxILEV 레지스터를통해확인할수있다. 각 Port 에연결된 Pull-up 저항은 외부입력이존재하거나출력인경우에는 Pull-up 을제거하면, 신호레벨이 Low 일때누설전류를줄일수 있다. Table 6-1 Internal Pull-up Resistance Characteristics Parameter Min Typ Max Unit Pull-Up Resistance K Pull-Down Resistance K Port Edge Detect EIRQ 핀을통한외부인터럽트이외에 GPIO 의 Port Edge Detect 을통해각각의그룹별로외부 인터럽트를수행할수있다. Port 들은 Rising Edge, Falling Edge 그리고 Any Edge 모드를지원한다 Functional Description 6 GPIO (General Purpose I/O) Copyright 215, Advanced Digital Chips, Inc.

70 6.4 Register Description Port Direction Registers ( GPxDIR ) Address: xffff_3 / xffff_34 / xffff_38 / xffff_3c / xffff_31 / xffff_314 / xffff_ : 9 R Reserved - 8 R GPx.OMD : GPx. Output Control Mode bit : Control individual ports 1 : Control a group of 8 ports 7 : R GPx.yDIR : GPx.y Direction bit : Input 1 : Output x Port Direction Output Mode Setting Registers ( GPxODIR ) Address: xffff_3 / xffff_34 / xffff_38 / xffff_3c / xffff_31 / xffff_314 / xffff_ : 9 R Reserved - 8 W GPx.OPRT : Output Control by Port Mode Setting bit - 7 W GPx.7ODIR : GPx.7 Direction Output Mode Setting bit - 6 W GPx.6ODIR : GPx.6 Direction Output Mode Setting bit - 5 W GPx.5ODIR : GPx.5 Direction Output Mode Setting bit - 4 W GPx.4ODIR : GPx.4 Direction Output Mode Setting bit - 3 W GPx.3ODIR : GPx.3 Direction Output Mode Setting bit - 2 W GPx.2ODIR : GPx.2 Direction Output Mode Setting bit - 1 W GPx.1ODIR : GPx.1 Direction Output Mode Setting bit - W GPx.ODIR : GPx. Direction Output Mode Setting bit - * Port Direction Output Mode Setting bit : No effect 1 : Set to output mode the corresponding bit Port Direction Input Mode Setting Registers ( GPxIDIR ) Address: xffff_34 / xffff_344 / xffff_384 / xffff_3c4 / xffff_314 / xffff_3144 / xffff_ : 9 R Reserved - 8 W GPx.IPRT : Iutput Control by Port Mode Setting bit - 7 W GPx.7IDIR : GPx.7 Direction Input Mode Setting bit - 6 W GPx.6IDIR : GPx.6 Direction Input Mode Setting bit - 5 W GPx.5IDIR : GPx.5 Direction Input Mode Setting bit - 4 W GPx.4IDIR : GPx.4 Direction Input Mode Setting bit - 3 W GPx.3IDIR : GPx.3 Direction Input Mode Setting bit - 2 W GPx.2IDIR : GPx.2 Direction Input Mode Setting bit - 1 W GPx.1IDIR : GPx.1 Direction Input Mode Setting bit - W GPx.IDIR : GPx. Direction Input Mode Setting bit - * 포트방향입력모드설정비트. :No effect 1 : PxDIR 레지스터의입력모드에해당하는비트를설정 Port Output Data Level Registers ( GPxOLEV ) Address: xffff_38 / xffff_348 / xffff_388 / xffff_3c8 / xffff_318 / xffff_3148 / xffff_ : 8 R Reserved - 7 : R GPx.yOLEV : GPx.y Output Level bit xff : Low Level 1 : High Level 7 6 GPIO (General Purpose I/O) 6.4 Register Description Copyright 215, Advanced Digital Chips, Inc.

71 Port Output Data Registers ( GPxDOUT ) Address: xffff_38 / xffff_348 / xffff_388 / xffff_3c8 / xffff_318 / xffff_3148 / xffff_ : 8 R Reserved - 7 : R/W GPx.DO : GPx.Port Output Data xff * GPxDIR 의 8 번 bit 가 1 인경우, 이 register 를이용해 GPIO Port output 을결정한다 Port Output Data High Level Setting Registers ( GPxOHIGH ) Address: xffff_38 / xffff_348 / xffff_388 / xffff_3c8 / xffff_318 / xffff_3148 / xffff_ : 8 R Reserved - 7 W GPx.7OH : GPx.7 Output Data High Level Setting bit - 6 W GPx.6OH : GPx.6 Output Data High Level Setting bit - 5 W GPx.5OH : GPx.5 Output Data High Level Setting bit - 4 W GPx.4OH : GPx.4 Output Data High Level Setting bit - 3 W GPx.3OH : GPx.3 Output Data High Level Setting bit - 2 W GPx.2OH : GPx.2 Output Data High Level Setting bit - 1 W GPx.1OH : GPx.1 Output Data High Level Setting bit - W GPx.OH : GPx. Output Data High Level Setting bit - * Port Output Data High Level Setting bit (GPxDIR 의 8 번 bit 가 인경우유효하다.) : No effect 1 : output data 에해당하는비트를 high level 설정 Port Output Data Low Level Setting Registers ( GPxOLOW ) Address: xffff_3c / xffff_34c / xffff_38c / xffff_3cc / xffff_31c / xffff_314c / xffff_318c 31 : 8 R Reserved - 7 W GPx.7OL : GPx.7 Output Data Low Level Setting bit - 6 W GPx.6OL : GPx.6 Output Data Low Level Setting bit - 5 W GPx.5OL : GPx.5 Output Data Low Level Setting bit - 4 W GPx.4OL : GPx.4 Output Data Low Level Setting bit - 3 W GPx.3OL : GPx.3 Output Data Low Level Setting bit - 2 W GPx.2OL : GPx.2 Output Data Low Level Setting bit - 1 W GPx.1OL : GPx.1 Output Data Low Level Setting bit - W GPx.OL : GPx. Output Data Low Level Setting bit - * Port Output Data Low Level Setting bit (It is effective only when GPxDIR[8] is.) : No effect 1 : output data 에해당하는비트를 low level 설정 Register Description 6 GPIO (General Purpose I/O) Copyright 215, Advanced Digital Chips, Inc.

72 Port Input Data Level Registers ( GPxILEV ) Address: xffff_31 / xffff_35 / xffff_39 / xffff_3d / xffff_311 / xffff_315 / xffff_ : 8 R Reserved - 7 R GPx.7ILEV : GPx.7 Input Level bit - : Low Level 1 : High Level 6 R GPx.6ILEV : GPx.6 Input Level bit - : Low Level 1 : High Level 5 R GPx.5ILEV : GPx.5 Input Level bit - : Low Level 1 : High Level 4 R GPx.4ILEV : GPx.4 Input Level bit - : Low Level 1 : High Level 3 R GPx.3ILEV : GPx.3 Input Level bit - : Low Level 1 : High Level 2 R GPx.2ILEV : GPx.2 Input Level bit - : Low Level 1 : High Level 1 R GPx.1ILEV : GPx.1 Input Level bit - : Low Level 1 : High Level R GPx.ILEV : GPx. Input Level bit - : Low Level 1 : High Level Port Pull-up Status Registers ( GPxPUS ) Address: xffff_318 / xffff_358 / xffff_398 / xffff_3d8 / xffff_3118 / xffff_3158 / xffff_ : 8 R Reserved - 7 : R GPx.yUP : GPx.y Pull-up Status bit x : Pull-up Disable 1 : Pull-up Enable Port Pull-up Enable Registers ( GPxPUEN ) Address: xffff_318 / xffff_358 / xffff_398 / xffff_3d8 / xffff_3118 / xffff_3158 / xffff_ : 8 R Reserved - 7 W GPx.7PUEN : GPx.7 Pull-up enable bit - 6 W GPx.6PUEN : GPx.6 Pull-up enable bit - 5 W GPx.5PUEN : GPx.5 Pull-up enable bit - 4 W GPx.4PUEN : GPx.4 Pull-up enable bit - 3 W GPx.3PUEN : GPx.3 Pull-up enable bit - 2 W GPx.2PUEN : GPx.2 Pull-up enable bit - 1 W GPx.1PUEN : GPx.1 Pull-up enable bit - W GPx.PUEN : GPx. Pull-up enable bit - * Port Pull-up enable bit : No effect 1 : 해당하는비트의 pull_up 을설정한다 Port Pull-up Disable Registers ( GPxPUDIS ) Address: xffff_31c / xffff_35c / xffff_39c / xffff_3dc / xffff_311c / xffff_315c / xffff_319c 31 : 8 R Reserved - 7 W GPx.7PUDIS : GPx.7 Pull-up disable bit - 6 W GPx.6PUDIS : GPx.6 Pull-up disable bit - 5 W GPx.5PUDIS : GPx.5 Pull-up disable bit - 4 W GPx.4PUDIS : GPx.4 Pull-up disable bit - 3 W GPx.3PUDIS : GPx.3 Pull-up disable bit - 2 W GPx.2PUDIS : GPx.2 Pull-up disable bit - 1 W GPx.1PUDIS : GPx.1 Pull-up disable bit - W GPx.PUDIS : GPx. Pull-up disable bit - * Port Pull-up disable bit : No effect. 1 : 해당하는비트의 pull_up 을 Disable 한다 GPIO (General Purpose I/O) 6.4 Register Description Copyright 215, Advanced Digital Chips, Inc.

73 Port Rising Edge Detect Registers ( GPxRED ) Address: xffff_32 / xffff_36 / xffff_3a / xffff_3e / xffff_312 / xffff_316 / xffff_31a 31 : 8 R Reserved - 7 R/W GPx.7RED : GPx.7 Rising Edge Detect bit : Disable 1 : Enable 6 R/W GPx.6RED : GPx.6 Rising Edge Detect bit : Disable 1 : Enable 5 R/W GPx.5RED : GPx.5 Rising Edge Detect bit : Disable 1 : Enable 4 R/W GPx.4RED : GPx.4 Rising Edge Detect bit : Disable 1 : Enable 3 R/W GPx.3RED : GPx.3 Rising Edge Detect bit : Disable 1 : Enable 2 R/W GPx.2RED : GPx.2 Rising Edge Detect bit : Disable 1 : Enable 1 R/W GPx.1RED : GPx.1 Rising Edge Detect bit : Disable 1 : Enable R/W GPx.RED : GPx. Rising Edge Detect bit : Disable 1 : Enable * Rising Edge 와 Falling Edge 가동시에설정되었을때는 Any Edge mode 가된다 Port Falling Edge Detect Registers ( GPxFED ) Address: xffff_324 / xffff_364 / xffff_3a4 / xffff_3e4 / xffff_3124 / xffff_3164 / xffff_31a4 31 : 8 R Reserved - 7 R/W GPx.7FED : GPx.7 Falling Edge Detect bit : Disable 1 : Enable 6 R/W GPx.6FED : GPx.6 Falling Edge Detect bit : Disable 1 : Enable 5 R/W GPx.5FED : GPx.5 Falling Edge Detect bit : Disable 1 : Enable 4 R/W GPx.4FED : GPx.4 Falling Edge Detect bit : Disable 1 : Enable 3 R/W GPx.3FED : GPx.3 Falling Edge Detect bit : Disable 1 : Enable 2 R/W GPx.2FED : GPx.2 Falling Edge Detect bit : Disable 1 : Enable 1 R/W GPx.1FED : GPx.1 Falling Edge Detect bit : Disable 1 : Enable R/W GPx.FED : GPx. Falling Edge Detect bit : Disable 1 : Enable * Rising Edge 와 Falling Edge 가동시에설정되었을때는 Any Edge mode 가된다 Port Edge Detect Status Registers ( GPxEDS ) Address: xffff_328 / xffff_368 / xffff_3a8 / xffff_3e8 / xffff_3128 / xffff_3168 / xffff_31a8 31 : 8 R Reserved - 7 R/W GPx.7EDS : GPx.7 Edge Detect Status bit 6 R/W GPx.6EDS : GPx.6 Edge Detect Status bit 5 R/W GPx.5EDS : GPx.5 Edge Detect Status bit 4 R/W GPx.4EDS : GPx.4 Edge Detect Status bit 3 R/W GPx.3EDS : GPx.3 Edge Detect Status bit 2 R/W GPx.2EDS : GPx.2 Edge Detect Status bit 1 R/W GPx.1EDS : GPx.1 Edge Detect Status bit R/W GPx.EDS : GPx. Edge Detect Status bit * Port Edge Detect Status bit : No edge detect has occurred on port 1 : Edge detect has occurred on port * 상태비트는 write 하여 clear 됩니다., * 을 write 하면효과없음 Register Description 6 GPIO (General Purpose I/O) Copyright 215, Advanced Digital Chips, Inc.

74 Port Open Drain Mode Control Registers ( GPxODM ) Address: xffff_32c / xffff_36c / xffff_3ac / xffff_3ec / xffff_312c / xffff_316c / xffff_31ac 31 : 8 R Reserved - 7 : R/W GPx.yOD : GPx.y Open Drain Mode Setting bit : Normal 1 : Open Drain Port Schmitt Input Enable Registers ( GPxSHMT ) Address: xffff_334 / xffff_374 / xffff_3b4 / xffff_3f4 / xffff_3134 / xffff_3174 / xffff_31b4 31 : 8 R Reserved - 7 W GPx.7SHMT : GPx.7 Schmitt input enable bit 6 W GPx.6SHMT : GPx.6 Schmitt input enable bit 5 W GPx.5SHMT : GPx.5 Schmitt input enable bit 4 W GPx.4SHMT : GPx.4 Schmitt input enable bit 3 W GPx.3SHMT : GPx.3 Schmitt input enable bit 2 W GPx.2SHMT : GPx.2 Schmitt input enable bit 1 W GPx.1SHMT : GPx.1 Schmitt input enable bit W GPx.SHMT : GPx. Schmitt input enable bit * Port Schmitt input enable bit : CMOS input mode 1 : Schmitt input mode Port Pull-down Status Registers ( GPxPDS ) Address: xffff_33 / xffff_37 / xffff_3b / xffff_3f / xffff_313 / xffff_317 / xffff_31b 31 : 8 R Reserved - 7 : R GPx.yDN : GPx.y Pull-down Status bit x : Pull-down Disable 1 : Pull-down Enable Port Pull-down Enable Registers ( GPxPDEN ) Address: xffff_33 / xffff_37 / xffff_3b / xffff_3f / xffff_313 / xffff_317 / xffff_31b 31 : 8 R Reserved - 7 W GPx.7PDEN : GPx.7 Pull-down enable bit - 6 W GPx.6PDEN : GPx.6 Pull-down enable bit - 5 W GPx.5PDEN : GPx.5 Pull-down enable bit - 4 W GPx.4PDEN : GPx.4 Pull-down enable bit - 3 W GPx.3PDEN : GPx.3 Pull-down enable bit - 2 W GPx.2PDEN : GPx.2 Pull-down enable bit - 1 W GPx.1PDEN : GPx.1 Pull-down enable bit - W GPx.PDEN : GPx. Pull-down enable bit - * Port Pull-down enable bit : No effect 1 : 해당하는비트의 Pull-down 을 Enable 한다 GPIO (General Purpose I/O) 6.4 Register Description Copyright 215, Advanced Digital Chips, Inc.

75 Port Pull-down Disable Registers ( GPxPDDIS ) Address: xffff_31c / xffff_35c / xffff_39c / xffff_3dc / xffff_311c / xffff_315c / xffff_319c 31 : 8 R Reserved - 7 W GPx.7PDDIS : GPx.7 Pull-down disable bit - 6 W GPx.6PDDIS : GPx.6 Pull-down disable bit - 5 W GPx.5PDDIS : GPx.5 Pull-down disable bit - 4 W GPx.4PDDIS : GPx.4 Pull-down disable bit - 3 W GPx.3PDDIS : GPx.3 Pull-down disable bit - 2 W GPx.2PDDIS : GPx.2 Pull-down disable bit - 1 W GPx.1PDDIS : GPx.1 Pull-down disable bit - W GPx.PDDIS : GPx. Pull-down disable bit - * Port Pull-down disable bit : No effect 1 : 해당하는비트의 Pull-down 을 Disable 한다 Register Description 6 GPIO (General Purpose I/O) Copyright 215, Advanced Digital Chips, Inc.

76 7 PIN MUX 일반입력 / 출력 (GPIO) 기능과함께핀당최대세가지 peripheral function 을사용할수있다. 7.1 Pin Mux register Register GP Mux x8234 GP1 Mux x82344 GP2 Mux x82348 GP3 Mux x8234c GP4 Mux x82341 GP5 Mux x GP6 Mux x bit 1st 2nd 3rd 4th Default value 1: uart_tx[1] cap_in[] PG. 3:2 uart_rx[1] cap_in[1] PG.1 5:4 Spi_lcd_cs PG.2 7:6 Spi_lcd_sdi nand_d[7] PG.3 9:8 Spi_lcd_sdo nand_d[6] PG.4 11:1 Spi_lcd_scl nand_d[5] PG.5 13:12 nand_d[4] sd_clk PG.6 15:14 spi_sdo nand_d[3] sd_d[3] PG.7 1: spi_sdi nand_d[2] sd_d[2] PG1. 3:2 spi_cs nand_d[1] sd_d[1] PG1.1 5:4 spi_scl nand_d[] sd_d[] PG1.2 7:6 sf_hold (d3) nand_wrx PG1.3 9:8 sf_clk nand_ale PG1.4 11:1 sf_di (d) nand_cle PG1.5 13:12 sf_cs1 nand_cs PG1.6 15:14 sf_wp (d2) nand_rdx PG1.7 1: sf_do (d1) nand_busy PG2. 3:2 sf_cs sd_cmd PG2.1 5:4 twi_sda usb_host_in PG2.2 7:6 twi_scl usb_host_out PG2.3 9:8 uart_tx[] PG2.4 11:1 uart_rx[] PG2.5 13:12 lcd_r[] PG2.6 15:14 lcd_r[1] PG2.7 1: lcd_r[2] PG3. 3:2 lcd_r[3] PG3.1 5:4 lcd_r[4] PG3.2 7:6 lcd_r[5] PG3.3 x5fff 9:8 lcd_r[6] PG3.4 11:1 lcd_r[7] PG3.5 13:12 lcd_g[] dbg_sck PG3.6 15:14 lcd_g[1] dbg_sda PG3.7 1: lcd_g[2] PG4. 3:2 lcd_g[3] PG4.1 5:4 lcd_g[4] PG4.2 7:6 lcd_g[5] PG4.3 xffff 9:8 lcd_g[6] PG4.4 11:1 lcd_g[7] PG4.5 13:12 lcd_b[] ext_irq[] PG4.6 15:14 lcd_b[1] ext_irq[1] PG4.7 1: lcd_b[2] PG5. 3:2 lcd_b[3] PG5.1 5:4 lcd_b[4] PG5.2 7:6 lcd_b[5] PG5.3 xffff 9:8 lcd_b[6] PG5.4 11:1 lcd_b[7] PG5.5 13:12 dotclk PG5.6 15:14 disp_en PG5.7 xffff or x557f (nand boot) x3f or x5555 (nand boot) xfff or xfffd (nand boot) 1: hsync PG6. 3:2 vsync tm_out[] PG6.1 5:4 lcd_clk_in tm_out[1] PG6.2 xffff 7:6 pwm_p PG6.3 9:8 pwm_n PG6.4 11:1 pwm_p1 PG6.5 13:12 pwm_n1 PG Pin Mux 7.1 Pin Mux register Copyright 215, Advanced Digital Chips, Inc.

77 8 INTERRUPT CONTROLLER adstar-l 는 32 개채널의인터럽트입력을가지며, 이입력들은 Timer, SPI, TWI, UART 등과같은내부 장치에서발생하는 3 개의인터럽트와외부 2 개의인터럽트로구성된다. 8.1 Features - 32 채널의인터럽트 (2 채널의외부인터럽트와 3채널의내부인터럽트 ) - 외부인터럽트에대한동작조건설정 (5가지) - 내부인터럽트에대한동작조건설정 (2가지) - 채널별인터럽트 Enable 기능 - 채널별인터럽트 Mask 기능 - 개별적으로프로그램가능한인터럽트우선순위 8.2 Functional Description 인터럽트의순차처리는다음과같은과정을통하여이루어진다. 1. 각인터럽트소스들은인터럽트제어기에인터럽트를요청한다. 2. Interrupt Enable Register에의해선별된후, Interrupt Pending Register에저장한다. 3. 인터럽트우선순위를판단한후, CPU에인터럽트를요청한다. 4. 인터럽트를요청받으면 CPU의인터럽트가비활성화되며인터럽트벡터주소를읽어서해당 Interrupt Service Routine(ISR) 으로진입한다. 5. ISR 을수행한다. 6. ISR 수행이끝나면 Interrupt Pending Clear Register에해당 Vector값을씀으로써 Interrupt Pending Register에저장된인터럽트값을지운다. 7. ISR을빠져나오면서 CPU의인터럽트가활성화된다. 인터럽트의중첩처리는다음과같은과정을통하여이루어진다. 1. 각인터럽트소스들은인터럽트제어기에인터럽트를요청한다. 2. Interrupt Enable Register에의해선별된후, Interrupt Pending Register에저장한다. 3. 인터럽트우선순위를판단한후, CPU에인터럽트를요청한다. 4. 인터럽트를요청받으면 CPU의인터럽트가비활성화되며인터럽트벡터주소를읽어서해당 Interrupt Service Routine(ISR) 으로진입한다. 5. 인터럽트의중첩을허용하기위해 Interrupt Pending Clear Register에해당 Vector값을씀으로써 Interrupt Pending Register에저장된인터럽트값을지우고 asm( set 13 ) 을통해 CPU의인터럽트를 활성화시킨다. 6. ISR을수행한다. 7. 만약, 현재 ISR의수행도중다시인터럽트가발생하면중첩처리가허용되어해당 ISR로진입한 다. 8. 새롭게진입한 ISR의수행이끝나면이전 ISR로복귀하여나머지수행을진행한다. 9. ISR 수행이끝나면완전히빠져나온다 Features 8 Interrupt Controller Copyright 215, Advanced Digital Chips, Inc.

78 Interrupt Vector and Priority 인터럽트우선순위는 EIRQ 가가장높다. 인터럽트벡터주소는 CPU 가 32bit Addressing 을하기때문에 각각 4bytes 의크기를가진다. Table 8-1 Interrupt Vector & Priority Index Vector No. Description Vector Address 31 x3f SWD Interrupt xfc Use edge method Clock_ctrl_r[] 3 x3e MJPEG 1 Interrupt xf8 29 x3d Capture Over Interrupt xf4 28 x3c SPI LCD Interrupt xf 27 x3b RTC Alarm Interrupt xec 26 x3a RTC Interrupt xe8 25 x39 TWI Interrupt xe4 24 x38 NAND Interupt xe 23 x37 WDT Interrupt xdc 22 x36 DMA CH5 Interrupt, xd8 GPIO 3 interrupt, GPIO 6 interrupt 21 x35 SDCard Interrupt xd4 2 x34 DMA CH4 Interrupt, xd GPIO 2 Interrupt, GPIO 5 Interrupt 19 x33 MJPEG Interrupt xcc 18 x32 SPI Interrupt xc8 17 x31 DMA CH3 Interrupt xc4 16 x3 UART 1 Interrupt xc 15 x2f GPIO 1 Interrupt, xbc GPIO 4 Interrupt 14 x2e USB host interrupt, xb8 Device Interupt 13 x2d ADC Interrupt xb4 12 x2c DMA CH2 Interrupt xb 11 x2b PMC interrupt xac 1 x2a Timer 1 Interrupt xa8 9 x29 DMA CH1 Interrupt xa4 8 x28 UART Interrupt xa 7 x27 GPIO Interrupt x9c 6 x26 DMA CH Interrupt x98 5 x25 LCD Frame sync Interrupt x94 4 x24 EIRQ1 Interrupt x9 3 x23 Sound Mixer Interrupt x8c 2 x22 Timer Interrupt x88 1 x21 Core timer Interrupt x84 x2 EIRQ Interrupt (Highest Priority) x Interrupt Controller 8.2 Functional Description Copyright 215, Advanced Digital Chips, Inc.

79 External Interrupt (EIRQx) External Interrupt 는 EINTMOD 레지스터의설정에의해 5 가지형태의외부인터럽트를받아들인다. - Low Level Mode에서는 External Interrupt 신호가 Low 를유지하는동안에매 System Cycle 마다인터럽트발생시킨다. - High Level Mode에서는 External Interrupt 신호가 High 를유지하는동안에매 System Cycle 마다인터럽트를발생시킨다. - Falling Edge Mode에서는 External Interrupt 신호가 High->Low 로바뀔때인터럽트를발생시킨다. - Rising Edge Mode에서는 External Interrupt 신호가 Low->High 로바뀔때인터럽트를발생시킨다. - Any Edge Mode에서는 External Interrupt 신호가 High->Low 또는 Low-> High 로바뀔때인터럽트를발생시킨다. External Interrupt Low Level Interrupt Event High Level Interrupt Event Falling Edge Interrupt Event Rising Edge Interrupt Event Any Edge Interrupt Event Figure 8-1 External Interrupt Mode Internal Interrupt Mode 내부인터럽트는모두 Rising Edge 로동작한다. 그러나사용자가 High Level 로인터럽트를처리를원할 경우에 Internal Interrupt Mode Registers 를통해설정할수있다 Functional Description 8 Interrupt Controller Copyright 215, Advanced Digital Chips, Inc.

80 Interrupt Pending and Interrupt Pending Clear 각인터럽트의발생상태는 Interrupt Pending Registers 를통해확인할수있다. 일단한번발생한인터럽트는 Interrupt Pending Clear Register 에의해 Clear 되기전까지는계속 Interrupt Pending Register 에저장된다. 또한현재발생한인터럽트보다높은우선순위의인터럽트가 Masking 되지않은상태로 Interrupt Pending Registers 에저장되어있을경우에는높은우선순위의인터럽트가모두 Clear 될때까지 Interrupt Pending Registers 에저장되어자신의우선순위가되기를기다린다. Interrupt Pending Registers 에저장된인터럽트들을 Clear 하기위해서는 Interrupt Pending Clear Register 를통해해당인터럽트벡터번호값을 Write 하면된다 Interrupt Enable Interrupt Mask Registers 에의해 Mask 되어있는인터럽트는 Interrupt Pending Registers 에계속저장되는데비해, Interrupt Enable Registers(IENR) 에의해 Disable 된인터럽트는 Interrupt Pending Registers 에저장되지않는다. 따라서이레지스터는전혀받아들이고싶지않은인터럽트에대해 Disable 하는데사용한다 Interrupt Mask Set/Clear Register Set 이면 Request 가 Enable 되고, Clear 이면 Request 가 Disable 된다. 각인터럽트는 Interrupt Mask Registers 에의해해당인터럽트에대한 Request 를수행할수있다. Interrupt Mask Set bit 가 1 일경우에는 Interrupt Pending Register 에저장된 Interrupt 를 CPU 로요청하고, Interrupt Mask Clear bit 가 1 일경우에는 Interrupt Pending Register 에저장되어있는 Interrupt 를 CPU 로요청하지못한다. 설정되지않은나머지 Interrupt 들은요청될수있다. Mask bit 가 으로설정된인터럽트라도 Interrupt Pending Registers(IPR) 에는저장되기때문에 Mask bit 을 1 로재설정하면 Interrupt Pending Registers 에저장되어있는인터럽트가우선순위에의해 인터럽트를다시요청한다. 8 8 Interrupt Controller 8.2 Functional Description Copyright 215, Advanced Digital Chips, Inc.

81 8.3 Register Description Interrupt Pending Clear Register (INTPENDCLR) Address : xffff_ 31 : 8 R Reserved - 7 : W Interrupt Pending Register Clear Value (x2 ~ x3f) xff * Interrupt Pending Register 를 Clear 하기위해서는 Interrupt Vector No. 값으로 clear 해야한다. (Interrupt Vector No. 참고 ) External Interrupt Mode and External PIN Level Register (EINTMOD) Address : xffff_4 31:8 R Reserved - 7 R EIRQ1ST : EIRQ1 PIN Level - 6 : 4 R/W EIRQ1MOD : EIRQ1 Active State 1 : Low Level 1 : High Level 1 : Falling Edge 11 : Rising Edge 1xx : Any Edge 3 R EIRQST : EIRQ PIN Level - 2 : R/W EIRQMOD : EIRQ Active State 1 : Low Level 1 : High Level 1 : Falling Edge 11 : Rising Edge 1xx : Any Edge Register Description 8 Interrupt Controller Copyright 215, Advanced Digital Chips, Inc.

82 Internal Interrupt Mode Register (IINTMODn) Address : xffff_8 31 R/W Vector No. x3f Interrupt Mode bit 3 R/W Vector No. x3e Interrupt Mode bit 29 R/W Vector No. x3d Interrupt Mode bit 28 R/W Vector No. x3c Interrupt Mode bit - 27 R/W Vector No. x3b Interrupt Mode bit 26 R/W Vector No. x3a Interrupt Mode bit 25 R/W Vector No. x39 Interrupt Mode bit 24 - Reserved - 23 R/W Vector No. x37 Interrupt Mode bit 22 R/W Vector No. x36 Interrupt Mode bit 21 R/W Vector No. x35 Interrupt Mode bit 2 R/W Vector No. x34 Interrupt Mode bit - 19 R/W Vector No. x33 Interrupt Mode bit 18 R/W Vector No. x32 Interrupt Mode bit 17 R/W Vector No. x31 Interrupt Mode bit 16 - Reserved - 15 R/W Vector No. x2f Interrupt Mode bit 14 R/W Vector No. x2e Interrupt Mode bit 13 R/W Vector No. x2d Interrupt Mode bit 12 R/W Vector No. x2c Interrupt Mode bit - 11 R/W Vector No. x2b Interrupt Mode bit 1 R/W Vector No. x2a Interrupt Mode bit 9 R/W Vector No. x29 Interrupt Mode bit 8 - Reserved - 7 R/W Vector No. x27 Interrupt Mode bit 6 R/W Vector No. x26 Interrupt Mode bit 5 R/W Vector No. x25 Interrupt Mode bit 4 R/W Vector No. x24 Interrupt Mode bit - 3 R/W Vector No. x23 Interrupt Mode bit 2 R/W Vector No. x22 Interrupt Mode bit 1 R/W Vector No. x21 Interrupt Mode bit - Reserved - * Internal Interrupt Mode bit : High Level Mode 1 : Rising Edge Mode 82 8 Interrupt Controller 8.3 Register Description Copyright 215, Advanced Digital Chips, Inc.

83 Interrupt Pending Register (INTPENDn) Address : xffff_c 31 R Vector No. x3f Interrupt Pending bit - 3 R Vector No. x3e Interrupt Pending bit - 29 R Vector No. x3d Interrupt Pending bit - 28 R Vector No. x3c Interrupt Pending bit - 27 R Vector No. x3b Interrupt Pending bit - 26 R Vector No. x3a Interrupt Pending bit - 25 R Vector No. x39 Interrupt Pending bit - 24 R Vector No. x38 Interrupt Pending bit - 23 R Vector No. x37 Interrupt Pending bit - 22 R Vector No. x36 Interrupt Pending bit - 21 R Vector No. x35 Interrupt Pending bit - 2 R Vector No. x34 Interrupt Pending bit - 19 R Vector No. x33 Interrupt Pending bit - 18 R Vector No. x32 Interrupt Pending bit - 17 R Vector No. x31 Interrupt Pending bit - 16 R Vector No. x3 Interrupt Pending bit - 15 R Vector No. x2f Interrupt Pending bit - 14 R Vector No. x2e Interrupt Pending bit - 13 R Vector No. x2d Interrupt Pending bit - 12 R Vector No. x2c Interrupt Pending bit - 11 R Vector No. x2b Interrupt Pending bit - 1 R Vector No. x2a Interrupt Pending bit - 9 R Vector No. x29 Interrupt Pending bit - 8 R Vector No. x28 Interrupt Pending bit - 7 R Vector No. x27 Interrupt Pending bit - 6 R Vector No. x26 Interrupt Pending bit - 5 R Vector No. x25 Interrupt Pending bit - 4 R Vector No. x24 Interrupt Pending bit - 3 R Vector No. x23 Interrupt Pending bit - 2 R Vector No. x22 Interrupt Pending bit - 1 R Vector No. x21 Interrupt Pending bit - R Vector No. x2 Interrupt Pending bit - * Interrupt Pending Register 의각비트의값은해당인터럽트가발생하였음을나타낸다. Interrupt Pending Register 의 값은 Interrupt Pending Clear 레지스터에의해 Clear 된다. 일반적으로해당 Interrupt 가끝날때 Clear 한다 Register Description 8 Interrupt Controller Copyright 215, Advanced Digital Chips, Inc.

84 Interrupt Enable Register (INTENn) Address : xffff_1 31 R/W Vector No. x3f Interrupt Enable bit 3 R/W Vector No. x3e Interrupt Enable bit 29 R/W Vector No. x3d Interrupt Enable bit 28 R/W Vector No. x3c Interrupt Enable bit 27 R/W Vector No. x3b Interrupt Enable bit 26 R/W Vector No. x3a Interrupt Enable bit 25 R/W Vector No. x39 Interrupt Enable bit 24 R/W Vector No. x38 Interrupt Enable bit 23 R/W Vector No. x37 Interrupt Enable bit 22 R/W Vector No. x36 Interrupt Enable bit 21 R/W Vector No. x35 Interrupt Enable bit 2 R/W Vector No. x34 Interrupt Enable bit 19 R/W Vector No. x33 Interrupt Enable bit 18 R/W Vector No. x32 Interrupt Enable bit 17 R/W Vector No. x31 Interrupt Enable bit 16 R/W Vector No. x3 Interrupt Enable bit 15 R/W Vector No. x2f Interrupt Enable bit 14 R/W Vector No. x2e Interrupt Enable bit 13 R/W Vector No. x2d Interrupt Enable bit 12 R/W Vector No. x2c Interrupt Enable bit 11 R/W Vector No. x2b Interrupt Enable bit 1 R/W Vector No. x2a Interrupt Enable bit 9 R/W Vector No. x29 Interrupt Enable bit 8 R/W Vector No. x28 Interrupt Enable bit 7 R/W Vector No. x27 Interrupt Enable bit 6 R/W Vector No. x26 Interrupt Enable bit 5 R/W Vector No. x25 Interrupt Enable bit 4 R/W Vector No. x24 Interrupt Enable bit 3 R/W Vector No. x23 Interrupt Enable bit 2 R/W Vector No. x22 Interrupt Enable bit 1 R/W Vector No. x21 Interrupt Enable bit R/W Vector No. x2 Interrupt Enable bit * Interrupt Enable bit : Interrupt Disable and Pending Clear 1 : Interrupt Enable 84 8 Interrupt Controller 8.3 Register Description Copyright 215, Advanced Digital Chips, Inc.

85 Interrupt Mask Status Register (INTMASKn) Address : xffff_14 31 : R Interrupt Mask Status Register x_ * 모든 Mask bit 의상태를확인할수있다 Interrupt Mask Set Register (INTMASKSETn) Address : xffff_14h 31 W Vector No. x3f Interrupt Request Set bit 3 W Vector No. x3e Interrupt Request Set bit 29 W Vector No. x3d Interrupt Request Set bit 28 W Vector No. x3c Interrupt Request Set bit 27 W Vector No. x3b Interrupt Request Set bit 26 W Vector No. x3a Interrupt Request Set bit 25 W Vector No. x39 Interrupt Request Set bit 24 W Vector No. x38 Interrupt Request Set bit 23 W Vector No. x37 Interrupt Request Set bit 22 W Vector No. x36 Interrupt Request Set bit 21 W Vector No. x35 Interrupt Request Set bit 2 W Vector No. x34 Interrupt Request Set bit 19 W Vector No. x33 Interrupt Request Set bit 18 W Vector No. x32 Interrupt Request Set bit 17 W Vector No. x31 Interrupt Request Set bit 16 W Vector No. x3 Interrupt Request Set bit 15 W Vector No. x2f Interrupt Request Set bit 14 W Vector No. x2e Interrupt Request Set bit 13 W Vector No. x2d Interrupt Request Set bit 12 W Vector No. x2c Interrupt Request Set bit 11 W Vector No. x2b Interrupt Request Set bit 1 W Vector No. x2a Interrupt Request Set bit 9 W Vector No. x29 Interrupt Request Set bit 8 W Vector No. x28 Interrupt Request Set bit 7 W Vector No. x27 Interrupt Request Set bit 6 W Vector No. x26 Interrupt Request Set bit 5 W Vector No. x25 Interrupt Request Set bit 4 W Vector No. x24 Interrupt Request Set bit 3 W Vector No. x23 Interrupt Request Set bit 2 W Vector No. x22 Interrupt Request Set bit 1 W Vector No. x21 Interrupt Request Set bit W Vector No. x2 Interrupt Request Set bit * Interrupt Request Set bit : No Effect interrupt Mask. 1 : pending 인터럽트가활성화되도록허용 (interrupts sent to CPU) Register Description 8 Interrupt Controller Copyright 215, Advanced Digital Chips, Inc.

86 Interrupt Mask Clear Register (INTMASKCLRn) Address : xffff_18 31 W Vector No. x3f Interrupt Req. Clear bit 3 W Vector No. x3e Interrupt Req. Clear bit 29 W Vector No. x3d Interrupt Req. Clear bit 28 W Vector No. x3c Interrupt Req. Clear bit 27 W Vector No. x3b Interrupt Req. Clear bit 26 W Vector No. x3a Interrupt Req. Clear bit 25 W Vector No. x39 Interrupt Req. Clear bit 24 W Vector No. x38 Interrupt Req. Clear bit 23 W Vector No. x37 Interrupt Req. Clear bit 22 W Vector No. x36 Interrupt Req. Clear bit 21 W Vector No. x35 Interrupt Req. Clear bit 2 W Vector No. x34 Interrupt Req. Clear bit 19 W Vector No. x33 Interrupt Req. Clear bit 18 W Vector No. x32 Interrupt Req. Clear bit 17 W Vector No. x31 Interrupt Req. Clear bit 16 W Vector No. x3 Interrupt Req. Clear bit 15 W Vector No. x2f Interrupt Req. Clear bit 14 W Vector No. x2e Interrupt Req. Clear bit 13 W Vector No. x2d Interrupt Req. Clear bit 12 W Vector No. x2c Interrupt Req. Clear bit 11 W Vector No. x2b Interrupt Req. Clear bit 1 W Vector No. x2a Interrupt Req. Clear bit 9 W Vector No. x29 Interrupt Req. Clear bit 8 W Vector No. x28 Interrupt Req. Clear bit 7 W Vector No. x27 Interrupt Req. Clear bit 6 W Vector No. x26 Interrupt Req. Clear bit 5 W Vector No. x25 Interrupt Req. Clear bit 4 W Vector No. x24 Interrupt Req. Clear bit 3 W Vector No. x23 Interrupt Req. Clear bit 2 W Vector No. x22 Interrupt Req. Clear bit 1 W Vector No. x21 Interrupt Req. Clear bit W Vector No. x2 Interrupt Req. Clear bit * Interrupt Request Clear bit : No Effect Interrupt Mask. 1 : Pending 인터럽트가활성화되는것을마스킹 (interrupts not sent to CPU) Interrupt Controller 8.3 Register Description Copyright 215, Advanced Digital Chips, Inc.

87 9 CORE TIMER adstar_l 은 MCU 에밀접하게붙은 32-bit Core_Timer 가내장되어있다. 9.1 Features 15-bit Pre-scaler 32-bit Timer/Counter Core timer 는 CPU halt(halt3) 되면, counter 또한동작을멈춘다. CPU resume 되면 counter resume 된다 bit Pre-scaler with clock source selection Pre-scaler 는 15-bit Pre-scaler 를통해 1/2 ~ 1/32768 배분주된클럭을생성하여 Timer/Counter 로 전달한다. Timer/Counter 는 Pre-scaler 를통해분주된클럭을선택하여 32-bit Counter 를구동한다. Pre-scaler 에서분주되는클럭의정확한위상이필요할경우에는 TPCON 레지스터의 CNTCLR 비트를 통하여 Pre-scaler counter 를초기화한후사용한다. Figure 9-1 Pre-scaler Block Diagram Features 9 Core Timer Copyright 215, Advanced Digital Chips, Inc.

88 9.3 Timer/Counter Pre-scaler 에의해분주된 Clock 을사용하여설정된 Timer Counter register value 에서매 clock 마다 counter value 을 1 씩감소하여 x 에도달하면 interrupt 를발생하고, 다시사용자가설정한 Timer Counter register value 부터 1 씩감소하기시작한다. (Down Counter) (TMCNT : 사용자가설정한 timer counter register value) Figure 9-2 Timer Operation Timer 주기는선택된클럭, Pre-scaler 그리고 Timer Counter 에의해결정된다. 1 1 Timer Period TMCNT sec Clock Source Frequency Pr e scaler Factor 1 1 Timer Period TMCNT 1 sec Clock Source Frequency Pr e scaler Factor Pr e scaler Factor 3 Pr e scaler Factor 3 Timer Period Example : - Clock Source Frequency : 12MHz System Clock - Pre-scaler Factor : 1 / Timer Counter Value (TMCNT) : 1 => 1/12MHz X 124 X 1 = msec = Hz Timer Counter 로동작시키기위하여설정되어야하는레지스터는다음과같다. - TMRST : 필요에따라 Pre-scaler를 clear 한다. - TMCON s PFSEL : Timer Counter에서사용할 Clock을결정한다. - TMCON s TMEN : Timer Counter를 Enable 한다. - TMCNT : Timer Counter의시작 Counter 값을결정한다. Timer Counter 는다음순서로설정하여동작시킨다. - TMCNT 설정 - TMCTRL 설정 - 필요에따라 TMRST s CNTCLR 비트설정 88 9 Core Timer 9.3 Timer/Counter Copyright 215, Advanced Digital Chips, Inc.

89 9.4 Timer Control Registers Timer Reset Control Register (TMRST) Address : xffff_1 31 : 2 R Reserved - 1 R/W CNTCLR : 1 일경우 Pre-scale Counter, Timer Counter를 Reset 한 다 R Reserved Timer Control Registers (TMCON) Address : xffff_14 31 : 4 R Reserved - 3 : 1 R/W PFSEL : Pre-scale Factor Selection 111 : clock / 1 1 : clock / 2 1 : clock / 8 11 : clock / 32 1 : clock / : clock / : clock / : clock / R/W TMEN : Timer Enable bit : Disable 1 : Enable Core break (Core debug) 일때, core timer 의 counting 동작도같이멈춘다. CPU resume 되면, 다시 core timer counting 을재개한다. Core halt(halt3) 일때, core timer 의 counting 동작도같이멈춘다. CPU resume 되면, 다시 core timer counting 을재개한다 Timer Counter Registers (TMCNT ) Address : xffff_18 31 : R/W - Write : Timer Counter 값설정레지스터. xffffffffh - Read : 현재카운터값을출력한다 Timer Interrupt waveform counter TMCNT -1 x TMCNT clk timer_tick interrupt Figure 9-3 core timer interrupt waveform * Core timer 는다운카운터이다. 설정된값에서부터 down counting 을시작하고 이되면, interrupt 가발생한다. Figure 9-3. 에도시된바와같이, interrupt 가발생한다음 counter 값은설정된값에서부터다시 counting 을시작한다 Timer Control Registers 9 Core Timer Copyright 215, Advanced Digital Chips, Inc.

90 1 WATCHDOG TIMER Watchdog Timer 는시스템에러, 정상적으로응답하지않는장치또는 noise 와같은이유로 CPU 가 정상적인동작을하지않을때, 정상상태로복귀시키는역할을한다. Watchdog Timer 가 Enable 되면 WDTCNT 에설정된값에서 1 씩감소하여 WDTCNT 값이 이되면 Watchdog Reset 이발생한다. Watchdog Reset 이발생하면 WDTST bit 에 Watchdog Reset 이발생한상태가저장된다. 일단 Watchdog Timer 가설정되면 Time-out 이되지않게하기위해서는 32 비트의 Watchdog Counter 값이 이되지않도록주기적으로 WDTCNT 을재설정하여 Watchdog Reset 이발생하지않도록해야한다. WDTMOD bit 를 Interrupt mode 로설정하면, Watchdog Reset 은발생하지않고 Interrupt 를발생시켜 WDTCNT 에설정된값이 이되었음을알려준다. Watchdog timer 는 Lock 기능이있다. lock 일때는설정 (WDCON) 값이변경되지않고, 기록된값을 유지한다. Unlock 일경우, 변경된값 (WDCON) 이적용된다. (UnLock : x1acce551 write.) 9 1 Watchdog Timer 9.4 Timer Control Registers Copyright 215, Advanced Digital Chips, Inc.

91 1.1 Register Description Watchdog Timer Control Register (WDTCTRL) Address : x82_ 31 : 8 R Reserved - 7 R/W HALTEN : Watchdog timer halt enable bit : Disable 1: Enable 이 bit 를 set 하면 Halt3 에의해 core 가정지할경우, counting 도정지 한다. Wakeup에의해 core가다시동작하면재개된다. 6 R/W BRKEN : Watchdog timer core break enable bit : Disable 1: Enable 이 bit 를 set 하면 Debugger 를통해 core break 한경우, counting 도정 지한다. Resume 에의해 core 가다시동작하면재개된다. 5 R WDTLOCK : Watchdog timer 잠금상태를나타낸다. : Lock 상태. 1 : Unlock 상태. 4 R WDTST : Watchdog timer 상태비트. watchdog timer 가 reset mode, 일경우 : No watchdog reset 1 : Watchdog reset 상태비트는 read 동작에의해 clear된다. 3 : 2 R Reserved - 1 R/W WDTMOD : Watchdog timer의 mode를결정한다. : Reset mode 1 : Interrupt mode R/W WDTEN : Watchdog timer enable bit : Disable 1 : Enable * unlock 일경우에만, 설정값을 write 할수있다 Watchdog Timer Counter Value Register (WDTCNT) Address : x82_4 31 : R/W Watchdog timer counter 32-bit value. Down-counter xffff_ffff * unlock 일경우에만, 설정값을 write 할수있다 Watchdog Timer Lock Value Register (WDTLOCK) Address : x82_8h 31 : RW Watchdog Timer Lock 32-bit Value. (Unlock = x1acce551) x1h Read시, Lock : x1 Unlock :x Register Description 1 Watchdog Timer Copyright 215, Advanced Digital Chips, Inc.

92 Operational Flow Diagrams * Watch dog timer에대한 Flow chart이다. Lock register에 x1acce551 value를 write해줘야만 watch dog timer setting이가능하다. (Unlock 상태에서만 counter value와 control register setting이가능 ) * Control register의 [1] bit가 or 1에따라 reset mode, interrupt mode 선택이가능하다. * Watch dog timer는 down counter로써 counter값이 이됐을시, reset or interrupt를발생시킨다. interrupt 발생후, watch dog timer 는상태를유지한다. ( 주기적인동작은지원하지않는다. ) * interrupt 발생후, watch dog timer interrupt service routine에서 watch dog timer disable후, enable(control write) 동작에의해, 재개한다. BEGIN Lock value write Unlock No Yes Control value write WDT enable No *** Time-Out 이발생되지않게하기위해서는 32bit counter 값을주기적으로 write 해줘야한다. Yes Counter value write Counter value = Yes No *** interrupt 발생했을경우 interrupt 상태를유지하며, ( 주기적인동작을지원하지않음 ) Interrupt *** wdt 재개를위해서는 interrupt service routine 에서 wdt disable 후, enable 해줘야한다. Interrupt reset End Figure 1-1 Operational flow 92 1 Watchdog Timer 1.1 Register Description Copyright 215, Advanced Digital Chips, Inc.

93 Sel Clock / Sel Clock / 8192 Sel Clock / 248 Sel Clock / 128 Sel Clock / 32 Sel Clock / 8 Sel Clock / 2 adstar-l 11 TIMERS adstar_l 은 Timer/Counter, Capture, PWM 기능을가진 32-bit Timer/Counter 를 2 채널내장하였다 Features - 15-bit Pre-scale - 32-bit Timer/Counter - 32-bit Capture - 32-bit PWM - 32-bit Timer Counter Wave-Out 11.2 Functional Description bit Pre-scaler with clock source selection Pre-scaler 는 System Clock 과 External Clock 핀을통해외부로부터받아들인입력을 CLKSEL 비트를 통해선택한후, 15-bit Pre-scaler 를통해 1/2 ~ 1/32768 배분주된클럭을생성하여 Timer/Counter 로 전달한다. Timer/Counter 는 Pre-scaler 를통해분주된클럭을선택하여 32-bit Counter 를구동한다. Pre-scaler 에서분주되는클럭의정확한위상이필요할경우에는 TPxCTRL 레지스터의 CNTCLR 비트를 통하여 Pre-scaler counter 를초기화한후사용한다. apb clock capture clock 15-bit Timer/Counter pre-scaler Timer/Counter Clock Select 3 Timer/Counter Clock Figure 11-1 Pre-scaler Block Diagram Features 11 Timers Copyright 215, Advanced Digital Chips, Inc.

94 Timer/Counter Pre-scaler 에의해분주된 Clock 을사용하여 x 의초기값에서매클럭마다카운터값을 1 씩 증가하여사용자가설정한 Timer Counter 레지스터값에도달하면다시 x 이되면서인터럽트를발생한다. TCNTR TCNTR TCNTR Timer Counter Timer Interrupt *** TCNTR = Timer Counter Read. Figure 11-2 Timer Operation Timer 주기는선택된클럭, Pre-scaler 그리고 Timer Counter 에의해결정된다. Timer Period Clock Timer Period Clock 1 1 Source Frequency Pr e scaler 1 1 Source Frequency Pr e scaler Factor Factor Timer Period Example : - Clock Source Frequency : 12MHz System Clock - Pre-scaler Factor : 1 / Timer Counter Value (TMCNT) : 1 => 1/12MHz X 124 X 1 = msec = Hz Timer Counter 로동작시키기위하여설정되어야하는레지스터는다음과같다. TMCNT sec Pr e scaler Factor 3 TMCNT 1 sec Pr e scaler Factor 3 - TPxCTRL : Pre-scaler 의클럭입력을결정하고, 필요에따라 Pre-scaler 를 clear 한다. - TMxCTRL s TMOD : Timer Counter 모드를설정한다. - TMxCTRL s WAVE : Timer Counter 의주기로생성된클럭을출력유무를결정한다. - TMxCTRL s PFSEL : Timer Counter 에서사용할 Clock 을결정한다. - TMxCTRL s TMEN : Timer Counter 를 Enable 한다. - TMxCNT : Timer Counter 의최대 Counter 값을결정한다. Timer Counter 는다음순서로설정하여동작시킨다. - TPxCTRL 설정 - TMxCNT 설정 - TMxCTRL 설정 - 필요에따라 TPxCTRL s CNTCLR 비트설정 Timers 11.2 Functional Description Copyright 215, Advanced Digital Chips, Inc.

95 Pulse Width Modulation (PWM) PWM 은 programmable 한 duty 와주기의펄스신호를출력하기위한제어기이다. Pre-scaler 에서설정한 Clock 을통해동작하며 PWM Period 레지스터값의주기로카운트를반복하면서 사용자가설정한형태의파형을출력한다. PWM 의출력펄스는 32 비트카운터의값이 PWM Duty, PWM Period 레지스터값에이를때마다레벨이반전되어출력파형이만들어진다. PWM 의출력횟수는 PWM Pulse Number 레지스터에의해결정되며펄스의출력횟수에다다르면 PWM Interrupt 를발생한다. 그러나 PWM Interrupt 가발생하더라도별도의설정이없을경우에는 PWM 출력이계속생성된다. 따라서 PWM Pulse 를멈추기위해서는 Timer Interrupt 에서 PWM 을 Disable 해야한다. PWM Pulse Period Clock 1 Source 1 Frequency Pr e scaler Factor TMCNT sec Pr e scaler Factor 3 PWM Pulse Period Clock 1 Source 1 Frequency Pr e scaler Factor TMCNT 1 sec Pr e scaler Factor 3 PWM Period Example : - Clock Source Frequency : 12MHz System Clock - Pre-scaler Factor : 1 / PWM Period Value(TMxCNT) : 1 - PWM Duty Value : 6 => 1/12MHz X 124 X 1 =.853msec = 1.171KHz PWM 으로동작시키기위하여설정되어야하는레지스터는다음과같다. - TPxCTRL : Pre-scaler의클럭입력을결정하고, 필요에따라 Pre-scaler를 clear 한다. - TMxCTRL s TMOD : PWM 모드로설정한다. - TMxCTRL s PWML : PWM 출력의시작레벨을결정한다. - TMxCTRL s PFSEL : PWM에서사용할 Clock을결정한다. - TMxCTRL s TMEN : PWM을 Enable 한다. - TMxCNT : PWM의주기를결정한다. - TMxDUT : PWM의 Duty를결정한다. - TMxPUL : PWM의 Pulse 횟수를결정한다. PWM Pulse의횟수가이레지스터값에도달하면 Timer Interrupt가발생시킨다. 그러나 PWM Pulse는중지되지않고계속생성된다. PWM 은다음순서로설정하여동작시킨다. - TPxCTRL 설정 - TMxCNT 설정 - TMxDUT 설정 - TMxPUL 설정 - 필요에따라 TPxCTRL s CNTCLR 설정 Functional Description 11 Timers Copyright 215, Advanced Digital Chips, Inc.

96 PWM Period Value PWM Duty Value PWM Pulse Number Value = x9h = x6h = x1h Internal Counter PWM Output Period Duty PWM Interrupt Pulse Number Figure 11-3 PWM Operation ** Special Case Duty 1% 와 % 설정인경우의 PWM wave 출력은다음과같다. * period 1%,Duty 1%,start level = low PWM period value = x1h PWM Duty Value = x1h PWM start level = LOW Internal counter PWM Output PWM start level * period 1%,Duty %,start level = low PWM period value = x1h PWM Duty Value = xh PWM start level = LOW Internal counter PWM Output PWM start level * period 1%,Duty 1%,start level = high PWM period value = x1h PWM Duty Value = x1h PWM start level = HIGH Internal counter PWM Output PWM start level * period 1%,Duty %,start level = high PWM period value = x1h PWM Duty Value = xh PWM start level = HIGH Internal counter PWM Output PWM start level Timers 11.2 Functional Description Copyright 215, Advanced Digital Chips, Inc.

97 Capture Capture 기능은 Pre-scale 에서설정한 Clock 을기준으로하여외부입력을측정한다. 외부입력은 Low/High Pulse, Only Low Pulse, Only High Pulse, Falling to Falling Period, Rising to Rising Period 의 5 가지형태의펄스주기를측정할수있다. Capture mode 로 Timer 를 Enable 할때는첫번째로 Capture 하는값은신호가변하는중간의값이기 때문에무시하여야한다. Low/High Pulse Capture Mode Capture Input Capture Counter Capture Interrupt Capture Value High Pulse Capture Mode Low Pulse Capture Mode Capture Input Capture Input Capture Counter Capture Counter Capture Interrupt Capture Interrupt Capture Value Capture Value Falling to Falling Capture Mode Rising to Rising Capture Mode Capture Input Capture Input Capture Counter Capture Counter Capture Interrupt Capture Interrupt Capture Value Capture Value Figure 11-4 Capture Mode Operation Capture 주기는다음과같이측정된다. Capture Signal Width Time Clock 1 Source 1 Frequency Pr e scaler Factor OCA 1 sec Capture Time Example : - Clock Source Frequency : 12MHz System Clock - Pre-scaler Factor : 1 / Capture Value : 9 => 1/12MHz X 124 X 1 =.853msec Functional Description 11 Timers Copyright 215, Advanced Digital Chips, Inc.

98 Capture 모드로동작시키기위하여설정되어야하는레지스터는다음과같다. - TPxCTRL : Pre-scaler의클럭입력을결정하고, 필요에따라 Pre-scaler를 clear 한다. - TMxCTRL s TMOD : Capture 모드로설정한다. - TMxCTRL s CAPMOD : Capture Pulse 형태를결정한다. - TMxCTRL s PFSEL : Capture에서사용할 Clock을결정한다. - TMxCTRL s TMEN : Capture를 Enable 한다. Capture 는다음순서로설정하여동작시킨다. - TPxCTRL 설정 - TMxCTRL 설정 - 필요에따라 TPxCTRL s CNTCLR 설정 - TMxDUT를읽어서 Capture 주기확인 - TMxCTRL s OVST를읽어서 Overflow 유무확인 Timers 11.2 Functional Description Copyright 215, Advanced Digital Chips, Inc.

99 Register Description Timer Pre-scale Control Registers ( TPxCTRL ) Address : x82_4 / x82_42 31 : 2 R Reserved - 1 R/W CNTCLR : Pre-scale Counter and Timer Counter Reset When this bit is 1, the Timer Pre-scale and Counter will be reset. R/W CLKSEL : Pre-scale Clock Selection : apb clock 1 : CAPx * CAPx 는 Timer 채널별로할당되어있다 Timer Control Registers ( TMxCTRL) Address : x82_44 / x82_ : 19 R Reserved - 18 R/W HALTEN : Core Halt Enable bit : Disable 1: Enable 이 bit 를 set 하면 Halt3 에의해 core 가정지할경우, counting 도정지 한다. Wakeup에의해 core가다시동작하면재개된다.. 17 R/W BRKEN : Core Break Enable bit : Disable 1: Enable 이 bit 를 set 하면 Debugger 를통해 core break 한경우, counting 도정 지한다. Resume에의해 core가다시동작하면재개된다. 16 R/W DMAREQEN : Timer request(dma) Enable bit : Timer 는설정된주기마다 interrupt 만요청한다. 1: Timer 의설정된주기마다 interrupt 가일어나면, DMA 에 request 신 호를요청하게된다. 15 : 14 R/W TMOD : Timer/Counter Mode : Timer 1 : PWM 1x : Capture 13 R Reserved - 12 R OVST : Capture Overflow Status bit Read시 Overflow status bit가 clear된다. 11 R Reserved 1 : 8 R/W CAPMOD : Capture Mode Selection x : Low/High Pulse Capture mode 1 : Low Pulse Capture mode 11 : High Pulse Capture mode 1x : Failing to Failing Period Capture mode 11x : Rising to Rising Period Capture mode 7 R/W IUE : Immediately Update Enable 1 : Counter Register 에 Write 한값이이전에설정된 Period 가완료된 후적용된다. 1: Counter Register에 write하는즉시, Period나 duty가적용된다. 6 R/W PWMO : PWM Output One Period Generation : Disable 1 : Enable 5 R/W PWML : PWM Output Start Level : Start Level is Low 1 : Start Level is High 4 R/W TMOUT : Timer Wave Output Generation : Disable 1 : Enable 3 : 1 R/W PFSEL : Pre-scale Factor Selection : 1/2 1 : 1/8 1 : 1/32 11 : 1/128 1 : 1/ : 1/ : 1/ : 1/32768 R/W TMEN : Timer/Counter or PWM Enable : Disable 1 : Enable * PWM Output One Period Generation : PWM 모드로동작할때, 주기를설정한개수만큼발생시키는 bit 이다 Register Description 11 Timers Copyright 215, Advanced Digital Chips, Inc.

100 펄스가발생한이후에는자동으로 PWM 은 Disable 된다. * Timer Wave Output Generation : Timer 모드에서한주기마다 toggle 되는파형의출력여부를결정한다. * Immediately Update : 최초 Timer 의 Counter 값을설정할때는 IUE bit 가 1 인상태이어야한다 Timer Counter / PWM Period Registers ( TMxCNT ) Address : x82_48 / x82_ : R/W (Timer mode) - Write : Timer Counter Value - Read : Current Up-counter Value xffffffff (PWM mode) - Read/Write : PWM Period Value Capture Counter Registers / PWM Duty Registers ( TMxDUT ) Address : x82_4c / x82_42c 31 : R/W (Capture mode) - Read : Result value of counting at the sampling period xffffffff (PWM mode) - Read/Write : PWM Duty Value * PWM Duty : First Halt Duty of PWM Pulse PWM Pulse Count Registers ( TMxPUL ) Address : x82_41 / x82_43 31 : R/W (PWM mode) - Read/Write : PWM Pulse Number Value xffffffff 1 11 Timers 11.3 Register Description Copyright 215, Advanced Digital Chips, Inc.

101 12 REAL TIMER CLOCK adstar-l 은전원이분리된 RTC 를가진다 kHz 의 Clock 을사용하여동작하며년, 월, 일, 시간, 분, 초의레지스터를설정하고현재진행중인시간을읽어볼수있다. RTC 의인터럽트를 1/4 초, 1/2 초, 1 초, 2 초, 4 초, 1 분, 2 분, 4 분, 1 시간, 2 시간, 4 시간, 24 시간, 단위로설정할수있다. RTC 의 Alarm 은초, 분, 시, 일, 월단위로설정할수있다 RTC Features - 전원독립 - 윤년지원 - 주기적인인터럽트발생 : 1/4초 ~ 24시간 - alarm 지원 ( 초, 분, 시, 일, 월 ) - Crystal 오류에대한보상가능. (calibration mode 지원 ) RTC_VDD 에 3V 입력과 RTC_XIN 에 kHz Clock 을인가하면 RTC 는 4 년 1 월 1 일에서부터동작하게된다. RTC calibration RTC 에는 calibration mode 가존재한다. Crystal 에대한오차를최대 1day 마다 ±1sec 보상할수있다. - 다른타이머의자원을사용하여, 사용자는 kHz 의 Crystal 오류를찾아야합니다. 오류를알고나 면, calibration mode 를 enable 한상태에서 sub_mode, pul_mode 를선택하여설정하여야합니다. Calibration compare value 는 calibration mode 에서만유효하다 RTC Features 12 Real Timer Clock Copyright 215, Advanced Digital Chips, Inc.

102 RTC diagram Figure 12-1 RTC Block Diagram 12.3 RTC Calibration (function diagram) Figure 12-2 Calibration Function Diagram Real Timer Clock 12.2 RTC diagram Copyright 215, Advanced Digital Chips, Inc.

103 Real Time Counter Control Register Real Time Counter Control Register (RTCCON_1) Address : 82_38h 7 RW RTC Calibration Subtraction. : Disable 1 : Calibration Plus Crystal 이기존시간보다빨라졌을경우, (1day 동안총 -1sec를보상해준다.) 6 RW RTC Calibration Puls. : Disable 1 :Calibration Subtraction Crystal 이기존시간보다느려졌을경우, (1day 동안총 +1sec를보상해준다.) 5 RW RTC Calibration Mode. : Disable 1 : Calibration Mode Calibration mode 일때, Crystal 오차에대한보상이가능하다. 4 RW Test Mode : Normal Mode 1 : RTC Test Mode(Fast) 3 : RW RTC Interrupt Select : No Interrupt 1 : Alarm Interrupt 1 : 1/4 Sec Period 11 : 1/2 Sec Period 1 : 1 Sec Period 11 : 2 Sec Period 11 : 4 Sec Period 111 : Reserved 1 : 1 Min Period 11 : 2 Min Period 11 : 4 Min Period 111 : Reserved 11 : 1 Hour Period 111 : 2 Hour Period 111 : 4 Hour Period 1111 : 24 Hour Period * Calibration Mode Bit 를 Enable 해야 Crystal 오차에대한보상이가능하다 Real Time Counter Control Register (RTCCON_2) Address : 82_384h 7:6 R Reserved - 5 R RTC alarm interrupt state bit This bit is cleared by PMUCON read. : no interrupt 1 : alarm interrupt Occurs. 4 R RTC interrupt state bit. This bit is cleared by PMUCON read. : no interrupt 1 : interrupt Occurs. 3: RW RTC Calibration compare value(base 1 day) 1 1 : 1sec, 1 :.5sec, 11 :.33sec, (1 day 1 :.25sec, 11 :.2sec, 11 :.16sec, 111 :.14sec, 1 :.12sec, 11 :.11sec, 1sec Correction) 11 :.1sec, 111 :..9sec, 11 :.8sec, 111 :.76sec, 111 :.71sec, 1111 :.6sec, Crystal 오류 Correction value 선택할수있다. 1day 동안, 최소.6sec, 최대 1 sec Correction. * Calibration Mode 상태에서얼마만큼보상해줄지결정하는 register 이다 (default value 는 1day 기준으로 1sec 보상이다 ) Real Time Counter Control Register 12 Real Timer Clock Copyright 215, Advanced Digital Chips, Inc.

104 Real Time Counter Register Real Time Counter Sec Register (RSEC) Address : 82_388h 7 : 6 R Reserved - 5 : RW Sec (~59) Real Time Counter Min Register (RMIN) Address : 82_38Ch 7 : 6 R Reserved - 5 : RW Min (~59) Real Time Counter Hour Register (RHOUR) Address : 82_381h 7 : 5 R Reserved - 4 : RW Hour (~23) Real Time Counter Day Register (RDAY) Address : 82_3814h 7 : 5 R Reserved - 4 : RW Day (1~31) Real Time Counter Week Register (RWEEK) Address : 82_3818h 7 : 3 R Reserved - 2 : RW Week (~6) Real Time Counter Month Register (RMONTH) Address : 82_381Ch 7 : 4 R Reserved - 3 : RW Month (~11) Real Time Counter Year Register (RYEAR) Address : 82_382h 7 R Reserved - 6 : RW Year (~99) Real Timer Clock 12.5 Real Time Counter Register Copyright 215, Advanced Digital Chips, Inc.

105 Real Time Alarm Register Real Time Alarm Register (RALM_S) Address : 82_3824h 7 : 6 R Reserved - 5 : RW Sec(~59) Real Time Alarm Register (RALM_M) Address : 82_3828h 7 : 6 R Reserved - 5 : RW Min(~59) Real Time Alarm Register (RALM_H) Address : 82_382Ch 7 : 5 R Reserved - 4 : RW Hour(~23) Real Time Alarm Register (RALM_D) Address : 82_383h 7 : 5 R Reserved - 4 : RW Day(1~31) Real Time Alarm Register (RALM_MO) Address : 82_3834h 7 : 4 R Reserved - 3 : RW Month(~11) * RTC alarm 은 month, day, hour, minute, second 모두설정을해줘야 alarm interrupt 가발생한다 Real Time Alarm Register 12 Real Timer Clock Copyright 215, Advanced Digital Chips, Inc.

106 Real Time Back up Register Real Time Back up Register (BACKUP_) Address : 82_384h 7 : RW Back up data_ Real Time Back up Register (BACKUP_1) Address : 82_3844h 7 : RW Back up data_ Real Time Back up Register (BACKUP_2) Address : 82_3848h 7 : RW Back up data_ Real Time Back up Register (BACKUP_3) Address : 82_384Ch 7 : RW Back up data_ Real Timer Clock 12.7 Real Time Back up Register Copyright 215, Advanced Digital Chips, Inc.

107 Real Time Back up Register (BACKUP1_) Address : 82_385h 7 : RW Back up data1_ Real Time Back up Register (BACKUP1_1) Address : 82_3854h 7 : RW Back up data1_ Real Time Back up Register (BACKUP1_2) Address : 82_3858h 7 : RW Back up data1_ Real Time Back up Register (BACKUP1_3) Address : 82_385Ch 7 : RW Back up data1_ Real Time Back up Register 12 Real Timer Clock Copyright 215, Advanced Digital Chips, Inc.

108 Real Time Back up Register (BACKUP2_) Address : 82_386h 7 : RW Back up data2_ Real Time Back up Register (BACKUP2_1) Address : 82_3864h 7 : RW Back up data2_ Real Time Back up Register (BACKUP2_2) Address : 82_3868h 7 : RW Back up data2_ Real Time Back up Register (BACKUP2_3) Address : 82_386Ch 7 : RW Back up data2_ Real Timer Clock 12.7 Real Time Back up Register Copyright 215, Advanced Digital Chips, Inc.

109 Real Time Back up Register (BACKUP3_) Address : 82_387h 7 : RW Back up data3_ Real Time Back up Register (BACKUP3_1) Address : 82_3874h 7 : RW Back up data3_ Real Time Back up Register (BACKUP3_2) Address : 82_3878h 7 : RW Back up data3_ Real Time Back up Register (BACKUP3_3) Address : 82_387Ch 7 : RW Back up data3_ Real Time Back up Register 12 Real Timer Clock Copyright 215, Advanced Digital Chips, Inc.

110 Real Time PMU Controller Register (PMUCON) Address : 82_388h 7:4 R Reserved - 3 R/W Halt1 state bit 1 : power down signal occur Clear Halt1 state bit 1을 write 하면 clear 한다. 그리고 으로자동으로된다. 2 R/W Halt state bit 1 : osc disable signal occur Clear Halt state bit 1을 write 하면 clear 한다. 그리고 으로는자동으로된다. 1 R/W Wakeup latch output signal select : f/f output 1 : latch output R/W RTC wakeup state bit state clear : release 1: clear * RTC은 32K를사용하는 RTC macro block과 CPU clock을사용하는 RTC interface block이따로존재한다. RTC clock에맞춰서 data 전송을위해 update bit를확인후, data W/R 해야한다. Ex) RTCCON = x77; // First data (w/r) while (RTCCON & x1); // Update bit occur RTCCON_1 = x1; // Second data (w/r) while (RTCCON & x1); // Update bit occur Real Timer Clock 12.8 Real Time PMU Controller Register (PMUCON) Copyright 215, Advanced Digital Chips, Inc.

111 RTC interrupt timing diagram * RTC 는시간설정에의한 alarm interrupt 와주기적으로발생하는 interrupt 두가지가존재한다. * Control register [3:] 에 alarm int 설정후, alarm register write을하면, 원하는시간interrupt를발생시킬수있다. Alarm interrupt는 1sec동안 high level을유지한다. (Refer to Figure 12-3) * 주기적인 interrupt 는발생은 1/4, 1/2 interrupt 를제외하고, 1cycle interrupt 를발생시킨다 (Refer to Figure 12-4, Figure 12-5, Figure 12-6) SEC_reg Alarm interrupt operation sec -1 sec sec +1 RTC_CLK Alarm_int 1 clock = 3, n/s 1sec = 1,,.716 n/s Figure 12-3 Alarm Interrupt Operation sec interrupt operation SEC_reg sec -1 sec sec +1 RTC_CLK 1sec_int 3 clock = 91, n/s Figure sec Interrupt Operation 3 clock RTC interrupt timing diagram 12 Real Timer Clock Copyright 215, Advanced Digital Chips, Inc.

112 /2 interrupt operation SEC_reg sec -1 sec sec +1 RTC_CLK 1/2_int 8192 cycle 8192 cycle 8192 cycle 8192 cycle 25,,172.2 n/s Figure /2 Interrupt Operation /4 interrupt operation SEC_reg sec -1 sec RTC_CLK 1/4_int 496 cycle 125,,89.6 n/s 496 cycle 496 cycle 496 cycle SEC_reg sec sec +1 RTC_CLK 1/4_int 1 clock = 3, n/s 496 cycle 496 cycle 496 cycle Figure /4 Interrupt Operation Real Timer Clock 12.9 RTC interrupt timing diagram Copyright 215, Advanced Digital Chips, Inc.

113 13 COPROCESSOR adstar-l 의 Coprocessor 는메모리관리를위한 Memory Management Unit(MMU) 과 I-Cache, D-Cache 기능블록을포함하며, 이들기능블록들과기타부가기능블록에대한제어를담당한다 Features - Memory Management Unit - Real Memory mode - 2 Way Set Associative Harvard Cache - 8KBytes I-Cache - 8KBytes D-Cache - Write Through - 16 Bytes / Line - LRU Replacement - Cache Invalidation by Software - 4 Words Deep Write Buffer (FIFO) Real Memory mode 는 CPU 가 4GB 크기의선형메모리영역을위해예약된일부메모리영역만접근할 수있으며, CPU 의주소는실제메모리주소와일치한다. Table 13-1 Real Memory map Address Range Sector Number Size x_ xf_ffff Flash 512KBytes (Memory Bank) x1_ x1_7ff Internal SRAM for Instruction 2KBytes (Memory Bank) x18_ x18_77ff Internal SRAM for Data 3KBytes (Memory Bank1) x2_ ~ x2fff_ffff SDRAM 8 or 16Mbytes x5_ ~ x5fff_ffff External SRAM Coprocessor Description Table 13-2 Coprocessor Register Description Register R/W Description SCPR15 R System Coprocessor Status Register W Master Command Register SCPR14 R/W Supervisor Stack Point Register SCPR13 R/W User Stack Pointer SCPR12 R/W Vector Base Register SCPR11 W Invalidate Cache Line and Lock Register SCPR1 - Reserved SCPR9 R/W Memory Bank Configuration Register SCPR8 R/W Sub-Bank Configuration Register SCPR7 R/W Reserved SCPR6 R/W Reserved SCPR5 R/W Sub-Bank Address Register SCPR4 R/W General Access Point Data Register SCPR3 R/W General Access Point Index Register SCPR2 R/W Reserved SCPR1 R/W Reserved SCPR R/W Reserved Features 13 Coprocessor Copyright 215, Advanced Digital Chips, Inc.

114 Coprocessor Control Registers System Coprocessor Status Register (SCPR15) 31 R System Co-Processor Access Right (Privileged) Coprocessor이접근권한을나타낸다. : Supervisor/User Accessible 1 : Supervisor Access only 3 : 28 R Coprocessor Type 1 27 : 25 R Coprocessor Subtype 24 : 19 R Reserved - 18 R L1 Cache Presented : Presented 1 : Not Presented 17 R L1 Cache Snooping Capability 1 : Support Snooping 1 : Not support Snooping 16 : 7 R Reserved - 6 R Misalign Correction Support for Data Access : Not support Misalign Correction 1 : Support Misalign Correction 5 : 2 R SCP Rending Exception Number 1111 : Inst. Fetch - Access Violation 1 : Privilege Violation Exception 11 : Data Access - Address Misalignment 1 : Data Access Access Violation 1 : Inst. Fetch - Address Misalignment 1111 : N/A 1 R SCP Pending Exception status : No Pending Exception 1 : Pending Exception Exist R Reserved Master Command Register (SCPR15) 31 : 6 W Reserved - 5 : 2 W End of Exception 1111 : Inst. Fetch - Access Violation 1 : Privilege Violation Exception 11 : Data Access - Address Misalignment 1 : Data Access Access Violation 1 : Inst. Fetch - Address Misalignment 1111 : Privilege Violation Exception 1 : W Reserved Supervisor Stack Point Register (SCPR14) 31 : 2 R/W Supervisor Stack Pointer x_ 1 : R/W Always User Stack Point Register (SCPR13) 31 : 2 R/W User Stack Pointer x_ 1 : R/W Always Vector Base Register (SCPR12) 31 : 2 R/W Vector Base for Exception x_ 1 : R/W Always Coprocessor 13.3 Coprocessor Control Registers Copyright 215, Advanced Digital Chips, Inc.

115 Invalidate Cache Line and Lock Register (SCPR11) 31 : 7 W Invalidation Target Address/Way - 6 : 4 W Invalidation Target Address/Way - 3 W Invalidation Mode - : Address Based Invalidation 1 : Way Based Invalidation 2 W Copy-back Selection in Invalidation - : Invalidation without Copy-back 1 : Invalidation with Copy-back if need 1 W Cache Line Locking in Invalidation - : Invalidation without Locking 1 : Invalidation with Locking W Cache Type in Invalidation - : I-Cache 1 : D-Cache Memory Bank Configuration Register (SCPR9) 31 : 16 R Reserved 15 R/W Always 14 R/W Memory Bank 3 Access Right : Supervisor only Accessible 1 : Supervisor/User Accessible 13 : 12 R/W Memory Bank 3 Cache Configuration : Disable Cache 1 : Reserved 1 : Enable Cache with Write-through 11 : N/A 11 R/W Always 1 R/W Memory Bank 2 Access Right : Supervisor only Accessible 1 : Supervisor/User Accessible 9 : 8 R/W Memory Bank 2 Cache Configuration : Disable Cache 1 : Reserved 1 : Enable Cache with Write-through 11 : N/A 7 R/W Always 6 R/W Memory Bank 1 Access Right : Supervisor only Accessible 1 : Supervisor/User Accessible 5 : 4 R/W Memory Bank 1 Cache Configuration : Disable Cache 1 : Reserved 1 : Enable Cache with Write-through 11 : N/A 3 R/W Always 2 R/W Memory Bank Access Right : Supervisor only Accessible 1 : Supervisor/User Accessible 1 : R/W Memory Bank Cache Configuration : Disable Cache 1 : Reserved 1 : Enable Cache with Write-through 11 : N/A Coprocessor Control Registers 13 Coprocessor Copyright 215, Advanced Digital Chips, Inc.

116 General Access Point Data Register (SCPR4) 31 : R/W General Access Point Data Register value that is configured at SCPR3 x_ General Access Point Index Register (SCPR3) 31 : R/W General Access Point Index - Core Debugging Information x_ : Backup IR x_1 : Backup ER x_2 : Backup PC x_1 : Backup EAD - System Coprocessor Debugging Information x_33 : Inst. Bus Error Address x_34 : Data Bus Error Address - Cache Lock Information x_5 : Inst. Lock Condition x_51 : Data Lock Condition - Memory Bank Management Information x_6 : Inst. MBMB Violation Address x_61 : Data MBMB Violation Address - Internal SRAM Configuration Information x_7 : Global Control Reg. Address Local Control Registers x_71 : Local I-Control Reg. Address x_711 : Local I-Control Reg.1 Address x_721 : Local I-Control Reg.2 Address x_731 : Local I-Control Reg.3 Address x_74 : Local D-Control Reg. Address x_714 : Local D-Control Reg.1 Address x_724 : Local D-Control Reg.2 Address x_734 : Local D-Control Reg.3 Address Local Start Address Registers x_72 : Local I-Start Reg. Address x_712 : Local I-Start Reg.1 Address x_722 : Local I-Start Reg.2 Address x_732 : Local I-Start Reg.3 Address x_75 : Local D-Start Reg. Address x_715 : Local D-Start Reg.1 Address x_725 : Local D-Start Reg.2 Address x_735 : Local D-Start Reg.3 Address Local End Address Registers x_73 : Local I-End Reg. Address x_713 : Local I-End Reg.1 Address x_723 : Local I-End Reg.2 Address x_733 : Local I-End Reg.3 Address x_76 : Local D-End Reg. Address x_716 : Local D-End Reg.1 Address x_726 : Local D-End Reg.2 Address x_736 : Local D-End Reg.3 Address x_ Coprocessor 13.3 Coprocessor Control Registers Copyright 215, Advanced Digital Chips, Inc.

117 14 UART adstar_l 의 UART 는 RS-232C 인터페이스의기능을보유한일반적인 PC 및 I/O device 와직렬비동기통신을위한다양한제어기능을가진 2 채널 UART(Universal Asynchronous Receiver/ Transmitter) Controller 가내장되어있다 Features - Compatible with standard 1645/1655 UARTs - Fully programmable serial-interface protocols 5,6,7,8-bit characters Even, odd or no-parity, stick parity generation and detection 1, 1.5, 2 stop bit generation Baud rate generator - Line break generation and detection - False start bit detection - Prioritized transmit, receive and line status control interrupts - Independent 16 characters transmit and receive 16Bytes FIFOs - 2 Ch. UARTs 14.2 Block Diagram S E L E C T Receiver Buffer Register Receiver FIFO Receiver Shift Register Serial Input Transmitter Holding Tr Register Transmitter FIFO S E L E C T Transmitter Shift Register Serial Output APB BUS FIFO Control Register Divisor Latch(MS,LS) Baud Generator Line Control Register Line Status Register Interrupt Enable Register Interrupt ID Register Interrupt Control Logic UART Interrupt Figure 14-1 UART Block Diagram Features 14 UART Copyright 215, Advanced Digital Chips, Inc.

118 Functional Description Serial Data Format adstar_l 의 UART 에서는 ULCRn[4:] 비트의레지스터설정으로 UART 통신 Serial Data Format 에대한 변경이가능하다. 다음표는 ULCRn[4:] bit 의 Register 설정으로변경가능한데이터포맷에대한설명이다. ULCRn[4:] Description 1 No Parity / 1 Stop bit / 7 Data bit 11 No Parity / 1 Stop bit / 8 Data bit 11 No Parity / 2 Stop bit / 7 Data bit 111 No Parity / 2 Stop bit / 8 Data bit 111 Even Parity / 1 Stop bit / 7 Data bit 1111 Even Parity / 1 Stop bit / 8 Data bit UART 14.3 Functional Description Copyright 215, Advanced Digital Chips, Inc.

119 Even Parity / 2 Stop bit / 7 Data bit Even Parity / 2 Stop bit / 8 Data bit 11 Odd Parity/ 1 Stop bit / 7 Data bit 111 Odd Parity/ 1 Stop bit / 8 Data bit 111 Odd Parity/ 2 Stop bit / 7 Data bit 1111 Odd Parity/ 2 Stop bit / 8 Data bit Figure 14-2 UART LCR Register Setting and Serial Data Format Functional Description 14 UART Copyright 215, Advanced Digital Chips, Inc.

120 UART Baud Rate TX/RX Baud Rate 은아래식으로계산된다. UART Baud Rate 16 f PCLK UDL UART Divisor Latch Value (UDL) = UDLM[7:] << 8 + UDLL[7:] Table 14-1 UART Baud Rate f PCLK 1.24 (MHz) bps UDL ERR(%) bps UDL ERR(%) bps UDL ERR(%) bps UDL ERR(%) bps UDL ERR(%) bps UDL ERR(%) bps UDL ERR(%) bps UDL ERR(%) *ERR 이 2.2% 이상에서는 UART 동작의안정성을보장받을수없다. UART Fractional Divider Latch Value (FDL) = {(float(pclk/16*bps)) (int(pclk/16*bps))}* Table 14-2 UART Fractional Baud Rate f PCLK 1.24 (MHz) bps FDL ERR(%) bps FDL ERR(%) bps FDL ERR(%) bps FDL ERR(%) bps FDL ERR(%) bps FDL ERR(%) bps FDL ERR(%) bps FDL ERR(%) UART 14.3 Functional Description Copyright 215, Advanced Digital Chips, Inc.

121 Register Summery Bit No. Table 14-3 UART Register Summery DLAB = x DLAB = x DLAB = x4 DLAB = x8 DLAB = X x8 DLAB = X xc DLAB = X x14 DLAB = 1 x DLAB = 1 x4 Transmitt Receiver Interrupt Interrupt FIFO Line Line Divisor Divisor er Buffer Enable Ident. Control Control Status Latch Latch Holding Register Register Register Register Register Register (LSB) (MSB) Register RBR THR IER IIR FCR LCR LSR DLL DLM R R/W R/W R R/W R/W R R/W R/W Bit Bit Data Bit Data Bit Enable Received Data Available Interrupt 1 Data Bit 1 Data Bit 1 Enable Transmitt er Holding Register Empty Interrupt 2 Data Bit 2 Data Bit 2 Enable Receiver Line Status Interrupt if Interrupt Pending Interrupt ID Bit Interrupt ID Bit 1 FIFO Enable RCVR FIFO Reset XMIT FIFO Reset Word Length Select Bit Word Length Select Bit 1 Number of Stop Bits 3 Data Bit 3 Data Bit 3 Interrupt ID Bit 2 Parity Enable 4 Data Bit 4 Data Bit 4 Reserved Even Parity Select 5 Data Bit 5 Data Bit 5 Reserved Stick Parity 6 Data Bit 6 Data Bit 6 FIFOs Enabled 7 Data Bit 7 Data Bit 7 FIFOs Enabled RCVR Trigger(L SB) RCVR Trigger(M SB) Set Break Divisor Latch Access Bit (DLAB) Data Ready Overrun Error Parity Error Framing Error Break Interrupt Transmitt er Holding Register Transmitt er Empty Error in RCVR FIFO * DLAB = LCR[7](Divisor Latch Access Bit) * FIFO Control Register : - DLAB = : Register Write - DLAB = 1 : Register Read * Address x1(x3), x18(x38), x1c(x3c) 는 1655 UART 표준과의호환성을위해 Reserved 되었다 Bit 1 Bit 1 Bit 2 Bit 2 Bit 3 Bit 3 Bit 4 Bit 4 Bit 5 Bit 5 Bit 6 Bit 6 Bit 7 Bit Register Summery 14 UART Copyright 215, Advanced Digital Chips, Inc.

122 Register Description UART Channel Receiver Buffer Registers ( UxRB ) Address : x82_8 / x82_82 31: 8 R Reserved. - 7 : R Receive Buffer Data - * DLAB가 일때 Access 가능하다 UART Channel Transmitter Holding Registers ( UxTH ) Address : x82_8 / x82_82 31: 8 W Reserved. - 7 : W Transmit Holding Data - * DLAB가 일때 Access 가능하다 UART Channel Interrupt Enable Registers ( UxIE ) Address : x82_84 / x82_824 31: 3 R Reserved. - 2 RW RLSIEN : Receiver Line Status Interrupt Enable bit : Disable 1 : Enable 1 RW THEIEN : Transmitter Holding Empty Interrupt Enable bit : Disable 1 : Enable RW RDAIEN : Received Data Available Interrupt Enable bit : Disable 1 : Enable * DLAB가 일때 Access 가능하다 UART Channel Interrupt Identification Register ( UxII ) Address : x82_88 / x82_ : 8 R Reserved. - 7 : 6 R FIFOST : FIFOs Enabled Status bit. : not in FIFO mode 11 : FIFO mode 5 : 4 R Reserved 3 : R INTID : UART Interrupt ID ( Note, UART Interrupt Control Function) 1 * DLAB가 일때만 Read Mode로 Access 가능하다 UART 14.5 Register Description Copyright 215, Advanced Digital Chips, Inc.

123 Table 14-4 UART Interrupt Control Function Interrupt Identification Register Priority Interrupt Interrupt Reset Interrupt Source Level Type Condition Bit 3 Bit 2 Bit 1 Bit 1 - None None Highest Receiver Line Status Overrun Error or Parity Error Framing Error or Break Interrupt Reading the Line Status Register 1 Second Received Data Available Receiver Data Available or Trigger Level Reached Reading the Receiver Buffer Register or the FIFO Drops Below the Trigger Level 1 1 Second Character Timeout Indication 1 Third Transmitter Holding Register Empty No Characters have been removed from or input to the RCVR FIFO during the last 4 Char. times, and there is at least 1 Char. in it during this Time Transmitter Holding Register Empty Reading the Receiver Buffer Register Reading the IIR Register (if source of interrupt) or Writing into the Transmitter Holding Register UART Channel FIFO Control Register ( UxFC ) Address : x82_88 / x82_ : 8 R Reserved. - 7 : 6 RW RFTL : Receiver FIFO Trigger Level : 1 Byte 1 : 4 Byte 1: 8 Byte 11 : 14 Byte 5 : 3 R Reserved - 2 RW XFR : XMIT FIFO Reset XFR 가 1 일때, XMIT FIFO 내의모든데이터는 Reset 된다. 그러나 Shift Register 내의데이터는 Reset 되지않는다. 1 RW RFR : RCVR FIFO Reset RFR 가 1 일때, RCVR FIFO 내의모든데이터는 Reset 된다, 그러 나 Shift Register 내의데이터는 Reset 되지않는다. RW FIFOEN : FIFO Enable Bit : 1645 UART Mode 1 : Enables FIFO * DLAB가 일때는 Write Mode 이고, DLAB가 1 일때는 Read Mode 이다 Register Description 14 UART Copyright 215, Advanced Digital Chips, Inc.

124 UART Channel Line Control Register ( UxLC ) Address : x82_8c / x82_82c 31 : 8 R Reserved. - 7 RW DLAB : Divisor Latch Access Bit DLAB이 1 일때, Divisor Latch Registers의 Read/Write와 FIFO Control Register의 Read가가능하다. 6 RW SB : Set Break SB가 1 일때, Serial Data Output에 Logic 이출력된다. SB는내부 Transmitter Logic에는영향을미치지않으며, 단지 Serial Output에만영향을미친다. 5 RW SP : Stick Parity : Disables Stick Parity 1 : PEN, EPS, SP가 1 일때, Parity Bit PEN, SP가 1 이고, EPS가 일때, Parity Bit 1 4 RW EPS : Even Parity Select : Select Odd Parity 1 : Select Even Parity 3 RW PEN : Parity Enable Bit : Disables Parity 1 : Enables Parity 2 RW STB : Number of Stop Bit : 1 Stop bit 1 : 2 Stop bits( 만약, WLS Bit에서 5 Bits/Character를선택했다면, 1.5 Stop bits 을갖는다.) 1 : RW WLS : Word Length Select : 5 Bits/Character 1 : 6 Bits/Character 1 : 7 Bits/Character 11 : 8 Bits/Character UART 14.5 Register Description Copyright 215, Advanced Digital Chips, Inc.

125 UART Channel Line Status Register ( UxLS ) Address : x82_814 / x82_ : 8 R Reserved. - 7 R EIRF : Error in RCVR FIFO FIFO 모드가아닌경우 EIRF 는항상 이다. FIFO 모드에서 EIRF 는 RCVR FIFO 내에서 OE, PE, FE, BI 중어느하나라도 1 이설정되면, 1 이된다. EIRF 는만약 FIFO 내에연속적인에러가없다면, LSR 레 지스터를읽었을때 Clear( ) 된다. 6 R TEMP : Transmitter Empty FIFO 모드가아닌경우 TEMT 는 Transmitter Holding Register (THR) 와 Transmitter Shift Register(TSR) 이모두 Empty 일때 1 이된다. THR 또는 TSR 에데이터가있으면 Clear 된다. FIFO 모드에서는, TEMT 는 Transmitter FIFO와 TSR이모두 Empty일때 1 이된다. 5 R THRE : Transmitter Holding Register Empty Interrupt가발생한다. 4 R BINT : Break Interrupt FIFO 모드가아닌경우 THRE 는 THR 의데이터가 TSR 로전송되어 Empty 가되었을때 1 이되며, THR 에전송을위한새로운데이터를 쓸수있다. FIFO 모드에서는 Transmit FIFO 가 Empty 일때 THRE 가 1 이되며, 적어도하나의 Byte 라도 Transmit FIFO 에써지면 Clear 된 다. 만약 THRE interrupt(ethrei) 가 1 이고 THRE 가 1 이라면 : 수신되는입력데이터가 Full-word 전송시간동안 일때 BI 는 1 이된다. Full-word 전송시간은 Start, Data, Parity 그리고 Stop 비트전 송을위한전체시간을의미한다. FIFO 모드에서이에러는 FIFO 내의 각각의 Byte 에적용되며, BI 가발생했을때 FIFO 에는 이써진다. CPU가 LSR을읽어을때 Clear 된다. 3 R FERR : Framing Error FE 는수신되는입력데이터가유효한 Stop 비트를가지지않았을때 1 이된다. FIFO 모드에서이에러는 FIFO 내의각각의 Byte 에적용 된다. CPU가 LSR을읽어을때 Clear 된다. 2 R PERR : Parity Error PE 는수신되는입력데이터가 LCR 레지스터에의해선택된 Parity 비트와같지않을때 1 이된다. FIFO 모드에서이에러는 FIFO 내의 각각의 Byte에적용된다. CPU가 LSR을읽어을때 Clear 된다. 1 R OERR : Overrun Error 다 R DRDY : Data Ready OE 는, FIFO 모드가아닌경우, RBR 내의데이터를읽어가기전 에새로운데이터가써진경우 1 이된다. FIFO 모드에서는 FIFO 가 Full 상태에서 Receiver Shift Register(RSR) 에새로운 Full-word 가들어 왔을때 1 이된다. 이경우 RSR 은새로운데이터로계속갱신이되 지만, FIFO 로전송은되지않는다. CPU 가 LSR 을읽어을때 Clear 된 DR 은수신된데이터가 RBR 또는 FIFO 에써졌을때 1 이된다. RBR 또는 FIFO 내의모든데이터가 CPU 에의해읽혀졌을때 Clear 된다 Register Description 14 UART Copyright 215, Advanced Digital Chips, Inc.

126 UART Channel Divisor Latch LSB Register ( UxDLL ) Address : x82_8 / x82_82 31: 8 R Reserved. - 7 : RW Divisor Latch Least Significant Byte x * DLAB가 1 일때 Access 가능하다 UART Channel Divisor Latch MSB Register ( UxDLM ) Address : x82_84 / x82_824 31: 8 R Reserved. - 7 : RW Divisor Latch Most Significant Byte x * DLAB 가 1 일때 Access 가능하다 UART Channel Fractional Divider Register ( UxFDR ) Address : x82_81c / x82_82c 7 RW : Normal divider baud rate mode 1: Fractional divider baud rate mode 6 R Reserved - 5: RW Fractional Divider Bit UART 14.5 Register Description Copyright 215, Advanced Digital Chips, Inc.

127 15 DMA 15.1 Features - AMBA AHB Specificaiton 과호환. - 6 채널지원. 각채널별로 DMA 전송이가능하다 - 16 포트 DMA Request 지원. DMAC 는 Peripheral 을위한 16 포트의 DMA Request 신호를제공하고있다. - Single Request 와 Burst Request 신호를제공. Peripheral 에게제공되는 DMA Request 신호는 Single Request 와 Burst Request 신호두종류를제공하며두가지모두사용할수있다. - 4 가지 DMA 전송지원. memory-to-memory, Memory-to-peripheral, peripheral-to-memory peripheral-to-peripheral 전송을지원한다. - Auto Reload 기능을이용한 Scatter 와 Gather 기능을지원한다. - Linked list 를이용한 Scatter 와 Gather 기능을지원한다. - 채널별 Priority 는하드웨어로고정되어있다. 채널 가가장높은 Priority 를갖고채널 7 이가장낮은 Priority 를갖게된다. - 2 개의 AHB Master 를내장하여 Multi Layer AHB Bus 를지원하고있다. - Programmable Burst Size 를제공하고있다. 사용자는 DMA 전송의효율성을높이기위하여 Burst Size 를설 정한다. Burst Size 는 Peripheral 안에있는 FIFO 크기의절반으로설정하는것이일반적이다. - 각채널별로 4 Word FIFO 를내장하고있다. - 각채널별로분리된 DMA Error Interrupt 와 DMA Terminal Count Interrupt( 전송종료인터럽트 ) 를가지고있 다. - Interrupt Enable 비트지원. DMA Error Interrupt 와 DMA Terminal Count Interrupt( 전송종료인터럽트 ) 에대한 Enable 비트를가지고 있다 Features 15 DMA Copyright 215, Advanced Digital Chips, Inc.

128 Block Description DMA Controller AHB Bus Signals AHB Slave Interface Channel N AHB Master Interface AHB Bus Signals DMA_INT Arbiter DMABREQ[15:] DMASREQ[15:] DMALBREQ[15:] DMALSREQ[15:] DMACLR[15:] DMATC[15:] Peripheral Interface 4 Word FIFO AHB Master Interface 1 AHB Bus 1 Signals Figure 15-1 DMA Block Diagram DMA 는 6 개의채널을가지고있다. 각채널은 Source Peripheral 에서 Destination Peripheral 로전송되는 단방향의데이터흐름을제어하며내부에 4x4 byte FIFO 를내장하고있다. AHB Master Interface 는채널로부터들어오는데이터의전송요청을받아서 AHB Bus 에서데이터전송을수행하는역할을한다. 내부에 2 개의 AHB Master Interface 가내장되어있어서로다른버스에연결할수있다. 그래서 Source Peripheral 과 Destination Peripheral 이다른버스에연결되어있더라도둘사이의데이터전송이가능하다. Arbiter 는각채널에서발생하는데이터전송요청을우선순위에따라 AHB Master Interface 또는 AHB Master Interface1 에전달하며어느 AHB Master Interface 를사용할지는요청되는데이터의 Address 에 의해결정된다. AHB Slave Interface 는채널마다할당되어있는레지스터등을설정하고인터럽트를요청하는역할을 한다. Peripheral Interface 는 Peripheral 들이요청하는 DMA Request 신호를받아서각채널의 Peripheral Selection 비트에의해선택된신호를해당채널로전달하게된다. 최대 16 개의 DMA Request 신호를받을수있으며채널입장에서는 Source DMA Request 신호와 Destination DMA Request 신호로구분하여 2 개의 DMA Request 신호를받을수있다 DMA 15.2 Block Description Copyright 215, Advanced Digital Chips, Inc.

129 Functional Description DMA Operation - Transfer Hierarchy DMA 전송은그림 2 와같은 3 단계의계층구조를갖는다. 최상위단계의전송을 DMA Transfer 라정의한다. DMA Transfer 전송은 DMA 가전송하는전체데이터의 양을의미하며 Control 레지스터에있는 Transfer Size 로전송량을결정하게된다. 차상위단계전송을 Burst Transaction 으로정의한다. Burst Transaction 에서전송하는데이터의양은 Control 레지스터에있는 Burst Size 로설정하게되며보통 Peripheral 들의 FIFO 크기에맞추어설정한다. 일반적인 Peripheral 들은메모리처럼필요한모든데이터를한번에전송하지못하므로 Peripheral 내부의 FIFO 단위로쪼개서전송하게된다. 한가지주의할사항은여기서설정하는 Burst size 가 AMBA Burst transfer 의 burst size 가아니라는점이다. 최하위단계전송은 AMBA Burst Transfer 이다. Burst Transaction 은 AMBA Burst Transfer 단위로 나뉘어진다. 이단계의전송에서사용자가설정하는부분은없으며하드웨어적으로관리된다. 사용자는 Burst Size 보다적은 Transfer Size Transaction 은설정된 Transfer size 양만전송되며 DMA 전송이종료된다. 값을설정하는것이가능하다. 이러한경우 Burst The amount of transfer is adjusted by Transfer Size DMA Transfer The amount of transfer is adjusted by Burst Size Burst Transaction Burst Transaction Burst Transaction Single Transaction AMBA Burst Transfer AMBA Burst Transfer AMBA Burst Transfer AMBA Single Transfer Figure 15-2 DMA Transfer hierarchy - Transfer type 사용자는 DMA 설정에서데이터전송의종류 (Transfer type) 를지정해야한다. Transfer Type 은아래의 4 가지중에하나가된다. 1. Memory to Memory 2. Memory to Peripheral 3. Peripheral to Memory 4. Source Peripheral to Destination Peripheral Memory to Memory 의의미는 Source Address 가 Memory 이고 Destination Address 도 Memory 로지정한 경우를말한다 Functional Description 15 DMA Copyright 215, Advanced Digital Chips, Inc.

130 Memory to Peripheral 의의미는 Source Address 는 Memory 이고 Destination Address 는 Peripheral 로 지정한경우이다. 즉메모리에있는데이터를 Peripheral 의버퍼등으로옮기는것을뜻한다. 이렇게사용자가 Transfer Type 을지정하는이유는 handshake 과정이필요한지아닌지를 DMA 에게알려주기위함이다. DMA 는메모리가아닌 Peripheral 과의데이터전송을수행할때에는 Handshake 방식으로진행한다. 메모리가아닌 Peripheral 들은데이터전송을위한준비과정과시간이필요하며데이터전송량도한정되어있다. Handshake 방식은 Peripheral 이데이터가준비되었을때만 DMAC 가데이터를전송하도록유도하므로필요한방식이다. 하지만 Peripheral 이메모리인경우는언제든 Access 가가능하므로이러한 handshake 과정은필요하지않다. 따라서사용자는 Transfer type 을지정하여 Peripheral 과의데이터전송에서 handshake 방식이필요한지아닌지를알려주어야한다. - Flow Controller Flow controller 란 DMA 전송량을결정하는모듈을말한다. Flow Controller 는 DMAC 또는 Peripheral 중에하나로정해진다. 만약 DMAC 가 Flow controller 가되면 DMA 전송량은 Transfer Size 에설정된값으로결정된다. 또한 Peripheral 이 Flow Controller 역할을할수있다. 이러한경우 DMAC 는 Peripheral 의 Request 신호에맞추어데이터를전송하게하게되며 Transfer size 에설정된값들은무시된다. DMA 전송을종료하기위해서는마지막데이터를요구할때 Last Request 신호를보내면된다. DMAC 가 Last Request 신호를받게되면마지막요청에대한데이터전송을수행한후에 DMA 전송이종료된다 Linked List Operation - LLI LLI(Linked List Item) 는 DMA 전송을위해필요한기본적인정보들을담고있는배열이다. LLI 가담고있는내용은 Source Address, Destination Address, Next LLI Address, Control 정보이렇게 4 가지이다. Linked List Operation 은 DMAC 가첫번째 LLI 를읽어서내부레지스터들을갱신한후 DMA 전송을수행하고종료되면 Next LLI 주소를통해다음번 LLI 를읽어들이는방식으로동작한다. 아래의그림은 LLI 의구조를설명하는그림이다. x1 x14 x18 x1c Source Address Destination Address Next LLI Address (x2) Control 1st LLI x2 x24 x28 x2c Source Address Destination Address Next LLI Address(x3) Control 2nd LLI x3 x34 x38 x3c Source Address Destination Address Next LLI Address (x) Control Figure 15-3 Linked list Last LLI DMA 15.3 Functional Description Copyright 215, Advanced Digital Chips, Inc.

131 마지막 LLI 는항상 Next LLI Address 에 x 을쓰도록약속되어있다. DMAC 는 Next LLI Address 가 x 임을확인하면현재읽은 LLI 가마지막임을알게된다. 그러므로 LLI 가실제주소 x 에놓이면 수행되지않으므로주의해야한다. - Multi Block Transfer LLI 로기술되어있는데이터를전송하는경우를 Multi Block Transfer 라고부르기도한다. 즉하나의 LLI 가전송하는데이터를 Block 이라고정의하며 LLI 의개수는 Block 의개수가된다. 또한 Block 사이즈는각각의 LLI 에포함된 Control 레지스터의 Transfer Size 로정의된다. 아래의그림은 Multi Block Transfer 에대한계층구조를보여주고있다. The amount of transfer is adjusted by Transfer Size DMA Transfer Block Block Block The amount of transfer is adjusted by Burst Size Burst Transaction Burst Transaction Burst Transaction Single Transaction AMBA Burst Transfer AMBA Burst Transfer AMBA Burst Transfer AMBA Burst Transfer AMBA Single Transfer Figure 15-4 Multi Block Transfer Functional Description 15 DMA Copyright 215, Advanced Digital Chips, Inc.

132 - Scatter & Gather with Liked list Scatter 는한덩어리로모여있는데이터를 DMA 전송을통하여분산시키는것을의미하며 Gather 는그반대의의미로써흩어져있는데이터를한군데로모으는것을말한다. LLI 를이용하면 Scatter 와 Gather 기능을수행할수있다. 아래의그림은 LLI 를사용하여 Gather 기능을수행하는예를보여준다. 예제의 LLI 의내용은그림처럼 사각형형태로저장된데이터를 Peripheral 로옮기는 Gather 작업을수행하고있다. Figure 15-5 Gathering by using LLI LLI 의위치는 x2 에서시작한다. 첫번째 LLI 내용 Source Address: xa2 Destination Address: Peripheral Address Source and Destination transfer width: 8bit Source and Destination burst Size: 16 burst Transfer Size: 372 byte, xc Next LLI Address: x21 두번째 LLI 내용 Source Address: xb2 Destination Address : Peripheral Address Source and Destination transfer width: 8bit Source and Destination burst Size: 16 burst Transfer Size: 372 byte, xc Next LLI Address: x22... 마지막 LLI 내용 Source Address: x112 Destination Address: Peripheral Address Source and Destination transfer width: 8bit Source and Destination burst Size: 16 burst Transfer Size: 372 byte, xc Next LLI Address: x DMA 15.3 Functional Description Copyright 215, Advanced Digital Chips, Inc.

133 Auto Reload Operation Auto Reload Operation 의기본동작은 DMA 전송이완료되었을때 Control 레지스터를다시 Reload 하여 DMA 전송을반복하는것이다. 반복회수는 Auto Reload count 레지스터값으로정하게된다. Auto Reload 가 1 회발생할때 Auto Reload Count 값이 1 씩감소하며 이되면 Auto Reload 는발생하지않는다. Auto Reload Operation 은별도의모드설정이없으며 DMA 전송이완료되었을때 Auto Reload Count 레지스터가 이아니면 Auto Reload 를수행하는방식이다. - Transfer Hierarchy Auto Reload Operation 은 Linked List Operation 처럼 Multi Block Transfer 로분류된다. Block 의개수는 Auto Reload count + 1 이되고 Block 의데이터전송량은 Transfer size 로설정된다. The amount of transfer is adjusted by Transfer Size DMA Transfer Block Block Block The amount of transfer is adjusted by Burst Size Burst Transaction Burst Transaction Burst Transaction Single Transaction AMBA Burst Transfer AMBA Burst Transfer AMBA Burst Transfer AMBA Burst Transfer AMBA Single Transfer Figure 15-6 Auto Reload Operation Transfer Hierarchy Functional Description 15 DMA Copyright 215, Advanced Digital Chips, Inc.

134 - Scatter with Auto reload 아래의그림은 Auto Reload Operation 을통하여 Scatter 기능을보여주는예제이다. Destination Scatter Address 는 Block 전송이완료될때마다 Destination Block 의시작주소를일정간격으로띄우는역할을한다. 사용자는이레지스터를통하여 Destination Block 간의간격을둠으로써 Scatter 기능을구현하게된다. xa Source Data xb Destination Data Block Block xa1 Block 1 xb12 Dest Scatter Addr = x2 xa2 Block 1 Block 2 Dest Scatter Addr = x2 xb24 Block 2 Figure 15-7 Scatter with Auto Reload Operation 레지스터설정 Source Address: xa Destination Address: xb Source and Destination transfer width: 32bit Source and Destination burst Size: 4 burst Transfer Size: x4 Auto Reload Count: 2 Destination scatter Address: x DMA 15.3 Functional Description Copyright 215, Advanced Digital Chips, Inc.

135 - Gather with Auto reload 아래의그림은 Auto Reload Operation 을사용한 Gather 기능을보여주는예제이다. Source Gather Address 는블록전송이완료될때마다 Source 블록의시작주소를일정간격으로띄우는역할을한다. 사용자는이레지스터를통하여 Source Block 간의간격을둠으로써 Gather 기능을구현하게된다. xa Source Data Destination Data xb Block Block Source Gather Addr = x5 xb1 xa15 Block 1 Block 1 xb2 xa3 Source Gather Addr = x5 Block 2 Block 2 Figure 15-8 Gather with Auto Reload Operation Register 설정 Source Address: xa Destination Address: xb Source and Destination transfer width: 32bit Source and Destination burst Size: 4 burst Transfer Size: x4 Auto Reload Count: 2 Source gather Address: x Functional Description 15 DMA Copyright 215, Advanced Digital Chips, Inc.

136 Peripheral Interface - Hand Shake Signals DMA Request 신호와 DMA Clear 신호는 DMA 가메모리가아닌 Peripheral 과의데이터전송에서 Handshake 방식으로데이터를전송하는데사용하는신호이다. DMA Request 신호는 Peripheral 이 DMAC 에게데이터전송을요청할때사용하는신호이며 4 가지가 있다. ( 아래의그림참조 ) Peripheral 은이중하나를선택하여 Request 를하며동시에여러개를 Request 하는것은허용하지않는다. DMA Clear 신호는 DMA Request 신호에대한응답으로 DMAC 가 Peripheral 에보내는신호이다. Figure 15-9 DMA Handshake Signals - DMABREQ Burst Request 신호. 이신호가 Active 되면 DMAC 에의해 Burst Transaction 이발생하며전송되는 데이터의양은 Burst Size 에서정해진다. - DMASREQ Single Request 신호. 이신호는 Active 되면 DMAC 에의해 Single Transaction 이발생한다. - DMALBREQ Last Burst Request 신호. Peripheral 이 Flow Control 을역할을하도록설정하였을때마지막 DMA Burst Request 신호임을알리는신호이다. DMALBREQ 신호가 Active 되면마지막 Burst Transaction 이발생하고 DMA 전송이종료된다. - DMALSREQ Last Single Request 신호. Peripheral 이 Flow Control 을역할을하도록설정하였을때마지막 DMA Single Request 신호임을알리는신호이다. DMALSREQ 신호가 Active 되면마지막 Single Transaction 이 발생하고 DMA 전송이종료된다. - DMACLR DMA Clear 신호. Peripheral 이요청하는 4 가지 Request 신호를 inactive 시키는신호이다 DMA 15.3 Functional Description Copyright 215, Advanced Digital Chips, Inc.

137 - Time diagram of DMA Request Peripheral 이 Request 를보내면 DMAC 는 Program 된 Burst Size 만큼데이터를전송한후에 DMA Clear 신호를보내게된다. 이때모든전송이종료된경우에는 DMATC(DMA Terminal Count: DMA 전송종료 ) 신호도동시에 Active 된다. 이신호를통하여 Peripheral 은 DMA 전송이종료되었는지체크할수있다. Peripheral 이 DMA Clear (DMACLR) 신호를받게되면 DMA Request 신호를 Inactive 상태로만들게된다. 만약 DMA Clear 신호가오기전에 Peripheral 스스로 DMA Request 신호를 Inactive 상태로만들면문제가발생하게된다. 또한 Next DMA Request 신호를보낼때에는현재 DMA Clear 신호가 Inactive 상태일때만가능하다. Figure 15-1 Time Diagram of DMA Request Functional Description 15 DMA Copyright 215, Advanced Digital Chips, Inc.

138 Register Description DMA Interrupt Status ( DMAIntStatus ) Address: 8_14 31 : 8 R Reserved 7 : R Interrupt Status of Channel 각채널에서발생할수있는 Interrupt 의발생유무를알려준다. ex) 번비트가 set 인경우 번채널인터럽트발생 1 번비트가 set 인경우 1 번채널인터럽트발생 인터럽트는 2 종류가있으므로 DMATCIS 와 DMATCIC 를읽어서인터럽 트의종류를확인해야한다 DMA Terminal Count Interrupt Status ( DMATCIntStatus ) Address: 8_ : 8 R Reserved 7 : R Terminal Count Interrupt Status of Channel 각채널의 Terminal Count 인터럽트발생유무를알려준다 DMA Terminal Count Interrupt Clear ( DMATCIntClr ) Address: 8_ : 8 R Reserved 7 : W Terminal Count Interrupt Clear 각비트는해당채널의 Terminal count 인터럽트를 Clear 하는역할을 한다. Set 하게되면해당채널의인터럽트가 Clear 된다 DMA Error Interrupt Status ( DMAErrorIntStatus ) Address: 8_14C 31 : 8 R Reserved 7 : R Error Interrupt Status of Channel 각채널의 DMA 전송에러인터럽트에대한발생유무를알려준다 DMA Error Interrupt Clear ( DMAErrorIntClr ) Address: 8_ : 8 R Reserved 7 : W Error Interrupt Clear 각비트는해당채널의 DMA 전송에러인터럽트를 Clear 하는역할을 한다. Set 하게되면해당채널의인터럽트가 Clear 된다 DMA 15.4 Register Description Copyright 215, Advanced Digital Chips, Inc.

139 DMA Block Interrupt Status ( DMABlockIntStatus ) Address: 8_ : 8 R Reserved 7 : R Block Interrupt Status of Channel 각채널의 DMA Block 인터럽트에대한발생유무를알려준다 DMA Block Interrupt Clear ( DMABlockIntClr ) Address: 8_ : 8 R Reserved 7 : W Block Interrupt Clear 각비트는해당채널의 DMA Block 인터럽트를 Clear 하는역할을한다. Set 하게되면해당채널의인터럽트가 Clear 된다 DMA Raw Terminal Count Interrupt Status ( DMARawTCIntStatus ) Address: 8_141C 31 : 8 R Reserved 7 : R Raw Terminal Count Interrupt Status of Channel Interrupt Enable 비트로 Disable 된각채널의 Terminal Count 인터럽트 가발생되었는지를알려준다 DMA Raw Error Interrupt Status ( DMARawErrorIntStatus ) Address: 8_ : 8 R Reserved 7 : R Error Interrupt Status of Channel Interrupt Enable 비트로 Disable 된각채널의에러인터럽트에대한발 생유무를알려준다 DMA Enabled Channel Status ( DMAEnbldChn ) Address: 8_ : 8 R Reserved 7 : R Enabled Channel Status 각비트는해당채널의 DMA 가 Enable 되어있는지를알려준다 DMA Software Burst Request ( DMASoftBReq ) Address: 8_ : 16 R Reserved 15 : RW Software Burst Request 소프트웨어적으로 DMA Burst Request 신호를생성하는레지스터이다. 해당비트에 1 을쓰게되면 DMA Burst Request 신호가생성되면 Clear 는자동으로이루어진다 Register Description 15 DMA Copyright 215, Advanced Digital Chips, Inc.

140 DMA Software Single Request ( DMASoftSReq ) Address: 8_142C 31 : 16 R Reserved 15 : RW Software Single Request 소프트웨어적으로 DMA Single Request 신호를생성하는레지스터이다. 해당비트에 1 을쓰게되면 DMA Burst Request 신호가생성되면 Clear 는자동으로이루어진다 DMA Software Last Burst Request ( DMASoftLBReq ) Address: 8_ : 16 R Reserved 15 : RW Software Last Burst Request 소프트웨어적으로 DMA Single Request 신호를생성하는레지스터이다. 해당비트에 1 을쓰게되면 DMA Burst Request 신호가생성되면 Clear 는자동으로이루어진다 DMA Software Last Single Request ( DMASoftLSReq ) Address: 8_ : 16 R Reserved 15 : RW Software Last Single Request 소프트웨어적으로 DMA Last Single Request 신호를생성하는레지스터 이다. 해당비트에 1 을쓰게되면 DMA Last Single Request 신호가생성 되면 Clear 는자동으로이루어진다 Channel Source Address Register ( ChnSrcAddr ) Address: 8_15 / 8_152 / 8_154 / 8_156 8_158 / 8_15A 31 : RW Source Address 각채널의 Source Address 를설정하는레지스터이다. 또한설정된값은 Source transfer Width 에따라 Align 이맞아야한다. Source Address 는채널에서데이터전송이진행됨에따라자동으로증 가한다. 그래서이레지스터는언제나앞으로전송해야할데이터의 Address 를지시하고있게된다. 하지만해당채널이동작중인상태에서이값을읽는것은의미가없다. 왜냐하면프로그램이 Read 하는순간에도채널은계속진행하고있기 때문이다. 다만해당채널이종료된후이레지스터를체크하면읽어야 할데이터가모두읽었는지는확인해볼수있다 DMA 15.4 Register Description Copyright 215, Advanced Digital Chips, Inc.

141 Channel Destination Address Register ( ChnDstAddr ) Address: 8_154 / 8_1524 / 8_1544 / 8_1564 8_1584 / 8_15A4 31 : RW Destination Address 각 DMA 채널의 Destination Address 를설정하는레지스터이다. 설정된값은 Destination transfer Width 에따라 Align 이맞아야한다. 또한 Destination Address 는채널에서데이터전송이진행됨에따라자동으로 증가한다. 그래서이레지스터는언제나앞으로전송되는데이터가저 장되는주소를지시하고있게된다. 하지만채널이동작중인상태에서이값을읽는것은의미가없다. 왜 냐하면프로그램이 Read 하는순간해당채널은계속진행되고있기 때문이다. 다만채널이종료된후이레지스터를체크하면읽어야할 데이터가모두읽었는지는확인해볼수있다 Channel Linked List Item Register ( ChnLLI ) Address: 8_158 / 8_1528 / 8_1548 / 8_1568 8_1588 / 8_15A8 31 : 2 RW Linked List Item Address 각 DMA 채널의첫번째 Linked List Item 이위치한곳의시작주소를 지정하는레지스터이다. 이레지스터가 x 이아닌값으로설정되고채 널이 Enable 되면 DMAC 는이주소에위치한첫번째 Linked List Item 을 Load 하여내부레지스터들을갱신하고 Linked List Operation 을수행 한다. Default Value는 Linked List Operation이수행하지않는다. 1 : R Reserved Channel Control Register ( ChnCntl ) Address: 8_15C / 8_152C / 8_154C / 8_156C 8_158C / 8_15AC 31 : 3 R Reserved - 29 RW Destination Increment 설정되면 Destination 어드레스가데이터전송에따라자동으로증가한다 28 RW Source Increment 설정하게되면 Source 어드레스가데이터전송에따라자동으로증가한 다 26 : 24 RW Destination transfer width : 8bit 1 : Reserved 1 : 16bit 11 : Reserved 1 : 32bit 11 : Reserved 11 : Reserved 111 : Reserved Destination 측 data width 를설정하는비트이다. Source transfer width 와 다르게설정하는것이가능하다. 만약 Destination transfer width < Source tranfer width 인경우 Transfer size 설정에주의한다. (Program Consideration 참조 ) 23 R Reserved 22 : 2 RW Source transfer width : 8bit 1 : Reserved 1 : 16bit 11 : Reserved Register Description 15 DMA Copyright 215, Advanced Digital Chips, Inc.

142 1 : 32bit 11 : Reserved 11 : Reserved 111 : Reserved Source 에서전송하는 data width를설정하는비트이다. 19 R Reserved 18 : 16 RW Destination burst size : 1 1 : 32 1 : 4 11 : 64 1 : 8 11 : : : 256 Destination 측 Peripheral 에서수행하는 Burst Transaction 의크기를지정한다. AHB Burst Size와유사하나그것을포함하는상위레벨의 Transaction 이다. (Transfer Hierarchy 참조 ) Destination이 Memory인경우에도동일한 Burst size로접근한다. 15 R Reserved 14 : 12 RW Source burst size : 1 1 : 32 1 : 4 11 : 64 1 : 8 11 : : : 256 Source 측 Peripheral 에서수행하는 Burst Transaction 의크기를지정한다 AHB Burst Size 와유사하나그것을포함하는상위레벨의 Transaction 이다. (Transfer Hierarchy 참조 ) Source가 Memory인경우에도동일한 Burst Size로접근한다. 11 : RW Transfer Size DMAC 가 Flow Control 역할을할때 DMA 채널이전송하는데이터의전 체양을의미한다. 전송단위는 Byte 가아니고 Source Transfer Width 가 된다. 즉전체전송량을계산식은다음과같다 (Transfer size) x (source transfer width) 이값은사용자가설정한값에서데이터전송이수행될때마다 1씩줄어들게되고 이되면 DMA 전송이종료된다. 따라서 DMA 전송중에이값을읽게되면앞으로전송종료까지남은데이터의양을확인할수있다. DMAC 가 Flow Controller 가아닌경우이값은무시되지만 Program 에 서는이값을 으로설정해야한다 DMA 15.4 Register Description Copyright 215, Advanced Digital Chips, Inc.

143 Channel Configuration Register ( ChnCfg ) Address: 8_151 / 8_153 / 8_155 / 8_157 8_159 / 8_15B 31 : 22 R Reserved 21 RO FIFO Active - : 해당채널의 FIFO 내에데이터가비어있음 1 : 해당채널의 FIFO 내에데이터가남아있음 2 RW Halt : enable DMA request 1 : ignore DMA request. 사용자는이비트를사용하여 FIFO 에아무런데이터도남기지않고깨끗 하게 DMA 채널을 Disable 할수있다. 19 RW Lock 이비트를설정하면 Locked transfer를수행하게된다 18 RW Block Interrupt Enable Multi Block Transfer 전송에서 Block 전송을끝냈을때발생하는인터럽트 에대한 Enable 비트이다. Block Interrupt 가발생하면 DMA 는 Block Interrupt가 Clear 될때까지 Next Block 전송을진행하지않는다. 17 RW Terminal count interrupt Enable DMA 전송종료인터럽트에대한 Enable 비트이다.. 16 RW Interrupt error Enable DMA Error 인터럽트에대한 Enable 비트이다. 15 R Reserved 14 : 12 RW Flow Control Value Transfer type Flow controller Memory-to-Memory (Default) DMA 1 Memory-to-Peripheral DMA 1 Peripheral-to-Memory DMA 11 Source peripheral-to-destination peripheral DMA 1 Source peripheral-to-destination peripheral Dst. Peri. 11 Memory-to-Peripheral Peripheral 11 Peripheral-to-Memory Peripheral 111 Source peripheral-to-destination peripheral Src. Peri. This bit determines both Transfer type and Flow Controller. 11 : 8 RW Destination Peripheral 16 개의 DMA Request 중하나를선택하는비트이다. : NAND Flash TX 1: SDHC 1: Reserved 11: Reserved 1: USB Device Bulk In 11: Mixer Play CH 11: Mixer Play CH1 111: Mixer Play CH2 1: Mixer Play CH3 11: Reserved 11: ADC 111: TIMER REQ[] 11: TIMER REQ[1] 111: LCD 111: Reserved 1111: Reserved 7 : 4 RW Source Peripheral 16 개의 DMA Request 중하나를선택하는비트이다. : Reserved 1: SDHC 1: NAND Flash RX 11: USB Device Bulk out 1: Reserved 11: Mixer Play CH 11: Mixer Play CH1 111: Mixer Play CH2 1: Mixer Play CH3 11: Reserved 11: ADC 111: TIMER REQ[] 11: TIMER REQ[1] 111: LCD 111: Reserved 1111: Reserved 3 : 1 R Reserved RW Channel Enable 채널을활성화시키는비트이다. 사용자가 DMA 전송을시작하기위해 이비트를 Set 하게되면설정한대로데이터전송이시작되고모든전 Register Description 15 DMA Copyright 215, Advanced Digital Chips, Inc.

144 송이완료되면자동으로 Clear 된다. Auto Clear 조건은다음과같다. - 일반 DMA 전송의완료 - Linked List Operation 완료 - Auto Reload Operation 완료 - Error 발생에의한종료 사용자는활성화되어있는채널을강제로종료할수도있다. 강제종료 는 Enable 비트를 clear 하면된다. 하지만채널 FIFO 에남아있는데이터 는사라지게된다 Channel Source Gather Address Register ( ChnSrcGaAddr ) Address: 8_1514 / 8_1534 / 8_1554 / 8_1574 8_1594 / 8_15B4 31 : 17 R Reserved - 16 RW Auto Reload Source Address 이비트가설정되면 Auto Reload 발생시 Source Address 가초기설 정했던 Source Address로 Reload 된다. 15 : RW Source Gather Address Auto Reload 가수행될때 Source Address 에 Source Gather Address 가더해진다 Channel Destination Scatter Address Register ( ChnDstScaAddr ) Address: 8_1518 / 8_1538 / 8_1558 / 8_1578 8_1598 / 8_15B8 31 : 17 R Reserved - 16 RW Auto Reload Destination Address Auto Reload 가수행될때 Destination Address 가초기설정했던값 으로 Reload 된다. 15 : RW Destination Scatter Address Auto Reload 가수행될때 Destination Address 에 Destination Scatter Address 가더해진다 Channel Auto Reload Count Register ( ChnAutoReloadCnt ) Address: 8_151C / 8_153C / 8_155C / 8_157C 8_159C / 8_15BC 31 : 22 R Reserved - 21 RW Uncountable Auto Reload 무제한이루어진다. 2 : RW Auto Reload Count 설정하게되면 Auto Reload Count 의값과상관없이 Auto Reload 가 사용자는이곳에 Auto Reload 회수를설정하여 DMA 전송을반복한다. Auto Reload count는설정된값에서 Block 전송이완료되었을때 (Transfer Size가 이되었을때 ) 1씩줄어들며 Auto reload count가 이되면 Auto Reload Operation이종료된다 DMA 15.4 Register Description Copyright 215, Advanced Digital Chips, Inc.

145 Program Guide Sumary of Register Name Address Type Description DMAIntStatus x R DMA Interrupt Status DMATCIntStatus x4 R DMA Terminal Count Interrupt Status DMATCIntClr x8 W DMA Terminal Count Interrupt Clear DMAErrorIntStatus xc R DMA Error Interrupt Status DMAErrorIntClr x1 W DMA Error Interrupt Clear DMABlockIntStatus x14 R DMA Block Interrupt Status DMABlockIntClr x18 W DMA Block Interrupt Clear DMARawTCIntStatus x1c R DMA Raw Terminal Count Interrupt Status DMARawErrorIntStatus x2 W DMA Raw Error Interrupt Status DMAEnbldChns x24 R DMA Enabled Channels DMASoftBReq x28 RW DMA Software Burst Request DMASoftSReq x2c RW DMA Software Single Request DMASoftLBReq x3 RW DMA Software Last Burst Request DMASoftLSReq x34 RW DMA Software Last Single Request ChnSrcAddr x1 RW Channel Source Address ChnDestAddr x14 RW Channel Destination Address ChnLLI x18 RW Channel Linked List Item ChnCntl x1c RW Channel Control ChnCfg x11 RW Channel Configuration ChnSrcGaAddr x114 RW Channel Source Gather Address ChnDestScatAddr x118 RW Channel Destination Scatter Address ChnAutoReloadCnt x11c RW Channel Auto Reload Count Programming Sequence - DMA Operation (Memory to Memory) - 사용할채널을선택 - 해당채널의 Source Address 설정 (ChnSrcAddr 레지스터 ) - 해당채널의 Destination Address 설정 (ChnDstAddr 레지스터 ) - 해당채널의 Source 와 Destination의 Transfer Width 설정 (ChnCntl 레지스터 ) - 해당채널의 Source 와 Destination의 Burst Size 설정 (ChnCntl 레지스터 ) - 해당채널의 Transfer size(dma 전송량 ) 를설정 (ChnCntl 레지스터 ) - 해당채널을 Enable 함 (ChnCfg 레지스터 ) - 전송완료를확인 (DMAEnbldChns 레지스터 ) - 종료 - DMA Operation (Memory to Peripheral) - 사용할채널을선택 - 해당채널의 Source Address 설정 (ChnSrcAddr 레지스터 ) - 해당채널의 Destination Address 설정, Peri의주소 (ChnDstAddr 레지스터 ) - 해당채널의 Source 와 Destination의 Transfer Width 설정 (ChnCntl 레지스터 ) - 해당채널의 Source 와 Destination의 Burst Size 설정 (ChnCntl 레지스터 ) - 해당채널의 Transfer size(dma 전송량 ) 를설정 (ChnCntl 레지스터 ) - 해당채널의 Transfer Type 지정 (ChnCfg 레지스터 ) - 해당채널을 Enable 함 (ChnCfg 레지스터 ) - 전송완료를확인 (DMAEnbldChns 레지스터 ) - 종료 Program Guide 15 DMA Copyright 215, Advanced Digital Chips, Inc.

146 - Linked List Operation (Memory to Memory) Linked List Item은미리준비되어있다고가정한다. 1. 사용할채널을선택 2. 첫번째 LLI 의주소를지정 (ChnLLI 레지스터 ) 3. 해당채널을 Enable 함 (ChnCfg 레지스터 ) 4. 전송완료를확인 (DMAEnbldChns 레지스터 ) 5. 종료 - Auto Reload Operation Program (Memory to Memory) - 사용할채널을선택 - 해당채널의 Source Address 설정 (ChnSrcAddr 레지스터 ) - 해당채널의 Destination Address 설정 (ChnDstAddr 레지스터 ) - 해당채널의 Source 와 Destination의 Transfer Width 설정 (ChnCntl 레지스터 ) - 해당채널의 Source 와 Destination의 Burst Size 설정 (ChnCntl 레지스터 ) - 해당채널의 DMA 전송량을지정 (ChnCntl 레지스터 ) - 해당채널의 Auto Reload Count 설정 (ChnAutoReloadCnt 레지스터 ) - 해당채널을 Enable 함 (ChnCfg 레지스터 ) - 전송완료를확인 (DMAEnbldChns 레지스터 ) - 종료 Program Consideration 사용자프로그램은다음과같은고려사항을반영되어야한다. 1. 채널이 Enable 된후에는채널의레지스터들을변경하지말아야한다. 채널이 Enable 되면 DMA 전송이 진행중이므로전송도중레지스터값변경은문제를발생시킬수있다. 따라서사용자가채널의 레지스터들을변경하기위해서는채널이 Disable 상태인지확인한후에설정해야한다. 2. Source transfer width 가 Destination transfer width 보다작은경우 DMA 전송량은 Destination transfer width 의배수가되도록설정해야한다. 왜냐하면 DMA 전송량은 Source측에서 Read하는데이터의양 (Source width x Transfer size) 으로계산되는데 DMA 전송량이 Destination width x N으로되지못하면 Destination으로 Write하는데이터양이부족하거나남을수있기때문이다. 3. Linked List Item 은 x 번지에위치할수없다 DMA 15.5 Program Guide Copyright 215, Advanced Digital Chips, Inc.

147 16 LOCAL MEMORY CONTROLLER 16.1 Register Description SDRAM Control Register (MEMCON) Address : x8_4 31 : 16 R Reserved - 15 : 8 R Reserved - 7 : 6 R/W Row Address Line Number 11b : 11 bit 1 : 12 bit 1 : 13 bit 11 : 14 bit 5 : 4 R/W Column Address Line Number 11b : 8 bit 1 : 9 bit 1 : 1 bit 11 : 11 bit 3 R/W Timing Constraint Select b ( : Upper 1MHz, 1 : Under 1 MHz) : trcd = 3 Clock, trp = 3 Clock, tras = 7 Clock, trc = 1 Clock 1 : trcd = 2 Clock, trp = 2 Clock, tras = 5 Clock, trc = 7 Clock 2 R/W CAS Latency b : 2 Clock 1 : 3 Clock 1 : R/W This bit determine data bus width : 8 bit 1 : 16 bit 1 : 32 bit 11 : Reserved 1b < Register 설명 > - Bit [7:6] : SDRAM 의 Row Address 수를선택한다. - Bit [5:4] : SDRAM 의 Column Address 수를선택한다. - Bit [3] : SDRAM 동작에필요한 Timing 조건을결정한다. 1MHz 를기준으로 1MHz 이상인경우에는 을선택하여 Timing 을맞춰준다. - Bit [2] : SDRAM 동작에서 CAS Latency Cycle 을선택한다. - Bit [1:] : 해당 Bank 의 SDRAM 의 Data Bus 폭을결정한다 SDRAM Clock Delay Register (MEMCLKCON) Address : x8_44h 31 : 12 R Reserved - 11 : 8 R/W Local SDRAM Clock Generation (Clock delay) h : CLOCK 1 : Invert CLOCK 1 : CLOCK+1ns 11 : Invert CLOCK+1ns 1 : CLOCK+2ns 11 : Invert CLOCK+2ns 11 : CLOCK+3ns 111 : Invert CLOCK+3ns 1 : CLOCK+4ns 11 : Invert CLOCK+4ns 11 : CLOCK+5ns 111 : Invert CLOCK+5ns 11 : CLOCK+6ns 111 : Invert CLOCK+6ns 111 : CLOCK+7ns 1111 : Invert CLOCK+7ns 7 : R/W 1Mhz Clock generation Divider Value FFh < Register 설명 > - Bit [11:8] : SDRAM 의 Data 읽기시에사용되는 SDRAM Feedback Clock 의지연정도를결정한다. - Bit [7:] : SDRAM Refresh 동작을위하여 1MHz 주파수를생성하는데필요한값을설정한다. 사용되는 Main Clock 에따라서 Main Clock / (n+1) 로생성되므로 divider 값에는 n-1 값을설정한다 Register Description 16 Local Memory Controller Copyright 215, Advanced Digital Chips, Inc.

148 SDRAM Refresh Control Register (MEMREFCON) Address : x8_48h 31 : 1 R Reserved - 9 R/W Refresh Period < Refresh Source : 1Mhz > b : 15 usec 1 : 3 usec 8 R/W Number of Refresh Cycle / Period < Refresh Source : 1Mhz > b : 1 Cycle 1 : 2 Cycle 7 : 1 R Reserved - R/W : Auto Refresh 1: Self Refresh b < Register 설명 > - Bit [9] : 1MHz 를사용하는경우의 Refresh 주기에대한선택을한다. - Bit [8] : 한주기에의해서몇번의 Refresh 를할것인지선택한다. - Bit [] : Refresh Mode select Local Memory Controller 16.1 Register Description Copyright 215, Advanced Digital Chips, Inc.

149 17 NAND FLASH CONTROLLER NAND Flash 제어기는 8-bit I/O 타입의 NAND Flash memory 와의데이터전송을관리한다 Features - 8bit I/O support - 3-cycle/4-cycle/5-cycle Address support - 1bit for SLC and 4bit/24bit ECC for MLC - Auto ECC Decoding support NFCTRL_IRQ (To Interrupt Controller) SYS_RESETX (To All Blocks) adr_siz (From external pin) NFCFG NF_nCS NF_CLE NFCTRL Controller / Auto Boot logic NF_nWE NF_nRE AHB BUS NFSTAT NFCMD NFADD 1bit ECC 4-bit ECC 24-bit ECC NF_nBUSY NFDATA NF_IO[7:] 1Kbytes Buffer Figure 17-1 NAND Flash Controller Block Diagram Features 17 NAND Flash Controller Copyright 215, Advanced Digital Chips, Inc.

150 Functional Description Data Read/Write 1. 데이터전송을위한타이밍을 NFCFG 레지스터에설정한다. 2. NAND Flash Memory Command를 NFCMD 레지스터에설정한다. 3. 접근할 NAND Flash Memory의주소를 NFADR 레지스터를통해설정한다. 이때 NAND Flash에 접근에필요한 Address cycle 만큼반복하여설정하여야한다. 4. NFCPUDATA 레지스터를통해 Read/Write 동작을수행한다. 데이터를읽기전또는데이터를 쓰고난뒤에는반드시 NDFL_nBUSY핀을확인하여야한다. HCLK NAND_ALE NAND_CLE NAND_nWE NAND_nRE T s Twp / Trp T h Figure 17-2 Read/Write Timing Diagram of NAND Flash Memory DMA Operation NAND Flash 제어기는 DMA 전송을지원한다. 먼저 DMA 제어기를설정한후, NAND Flash 제어기를설정을한다. NFCTRL 레지스터에서 DMA 동작을설정하게되면 NAND Flash Memory 와 DMA 전송을시작한다. NAND Flash Memory 가 Large type(2 세대 ) 일경우, 최대 2KBytes 까지전송단위의설정이가능하며, Small type(1 세대 ) 인경우는 512Bytes 까지만설정할수있다 ECC Operation adstar-l 는 SLC 타입의 NAND Flash 뿐만아니라 MLC 타입의 NAND Flash 도지원한다. MLC 타입의 NAND Flash 는 SLC 에비해에러발생률이높기때문에이에러를보정해주어야사용할수있다. adstar_l 의 NAND Flash Controller 는 BCH 알고리즘을이용하여 Parity bit 를생성하며, 이를이용하여 데이터에러를복구할수있는기능을제공한다. 512Bytes 의데이터에대하여 4bit 에러, 1Kbytes 의 데이터에 24bit 에러까지검출및복원을지원한다 NAND Flash Controller 17.2 Functional Description Copyright 215, Advanced Digital Chips, Inc.

151 ECC Encoding 1. NAND Flash 를사용하기위해 NFCFG 레지스터를설정한후, Command 와 Address 를전송한다. 2. NFECC1 레지스터를 read 하여 ECC 상태와 ECC 관련레지스터를 clear 한다. 3. NFCTRL 레지스터의 ECC GEN bit 를 1 로설정한다. (ECC Generation enable) Bytes 혹은 124Bytes 의데이터를전송한다. 데이터를전송할때마다 52-bit 또는 336-bit 크기 의 Parity bits 가생성되어 NFECCn 들에저장된다 Bytes 혹은 124Bytes 의전송이완료되면, NFECC, NFECC1 레지스터순서로 read 하여메모리 상에저장해둔다. 6. 다시 512Bytes 혹은 124Bytes 단위로전송하기위하여 2-5 과정을반복한다. 7. 한페이지크기의전송이완료되면, NFCTRL 레지스터의 ECC GEN bit 를 으로설정한다. (ECC Generation disable) 8. 메모리에저장해두었던각 512Bytes 혹은 124Bytes 에대한 Parity bits 를 NAND Flash 의 spare 영 역에저장한다 ECC Decoding by S/W 1. NAND Flash 를사용하기위해 NFCFG 레지스터를설정한후, Command 와 Address 를전송한다. 2. NFECC1 레지스터를 read 하여 ECC 상태와 ECC 관련레지스터를 clear 한다. 3. NFCTRL 레지스터에서 4-bit 혹은 24-bit ECC Mode 를선택하고, ECC GEN bit 를 1 로설정한다. (ECC Decoding enable) Bytes 혹은 124Bytes 의데이터를 read 한다 Bytes 혹은 124Bytes read 가완료되면, spare 영역에접근하여해당하는 Parity bits 를 read 한다. 6. Parity bits 의 read 가완료되면, 자동적으로 decoding 작업을시작하며, 사용자는 NFSTAT 레지스터 에서 decoding 완료여부와성공여부를확인할수있다. 7. Decoding 이완료되면, NFERRLOC~3 혹은 ~23 레지스터에에러가발생한위치와 NFERRPTN~3 혹은 ~23 레지스터에 8bit 에러패턴이저장된다. 8. NFERRLOCn 위치의 8bit 데이터와 NFERRPTNn 값을 Exclusive-OR 하여손상된데이터를복원한 다. 9. 한페이지를 read 할때까지 2-8 과정을반복한다 ECC Decoding by H/W (Auto ECC Decoding) 1. NAND Flash를사용하기위해 NFCFG레지스터를설정한후, Command와 Address를전송한다. 2. NFECC1 레지스터를 read하여 ECC상태와 ECC관련레지스터를 clear한다. 3. NFCTRL 레지스터에서 4-bit 혹은 24-bit ECC Mode를선택하고 Auto ECC Decoding bit를 1로설 정하면, 자동으로 NAND Flash에서데이터와 parity를읽어들인다. 4. NFSTAT에서 Auto ECC Done bit가 1이되는것을확인한다. 5. NFECD 레지스터를통해복구된데이터를읽는다. 6. 한페이지를 read할때까지 2-5 과정을반복한다 ECC Operation 17 NAND Flash Controller Copyright 215, Advanced Digital Chips, Inc.

152 Register Description NAND Flash Memory Control Register (NFCTRL) Address: xa_c 31:17 R Reserved - 16 R/W Auto ECC Enable bit : Auto ECC done 1: Auto ECC Start 이 bit를 set하면 Auto ECC를시작하며, 완료되면자동으로 clear된다.. 15 R/W 4-bit ECC Mode Set bit 1 : 24-bit ECC Mode 1: 4-bit ECC Mode 14:13 R Reserved - 12 R/W ECC Generation Enable bit : Disable 1 : Enable 11 R/W Endian Select bit : Little Endian 1 : Big Endian 1 R/W Data Swap Size : 8bit 1 : 16bit 9 R/W DMA Write Request bit : DMA Write Request Clear 1 : DMA Write Request 이 bit 를 set 하면 DMA 전송을시작하게되며, 완료되면자동으로 clear된다. 8 R/W DMA Read Request bit : DMA Read Request Clear 1 : DMA Read Request 이 bit 를 set 하면 DMA 전송을시작하게되며, 완료되면자동으로 clear된다. 7 R/W Busy End Interrupt Enable bit : Interrupt Disable 1 : Interrupt Enable 6 R/W DMA Clear Interrupt Enable bit : Interrupt Disable 1 : Interrupt Enable 5 R/W BCH ECC Decoding Done Interrupt Enable bit : Interrupt Disable 1 : Interrupt Enable 4 R/W Auto ECC Done Interrupt Enable bit : Interrupt Disable 1 : Interrupt Enable 3: R/W Reserved NAND Flash Memory Command Set Register (NFCMD) Address: xa_c4 31 : 8 R Reserved - 7 : R/W NAND Flash Memory Command h NAND Flash Memory Address Register (NFADR) Address: xa_c8 31 : 8 R Reserved - 7 : R/W NAND Flash Memory Address h NAND Flash Controller 17.4 Register Description Copyright 215, Advanced Digital Chips, Inc.

153 NAND Flash Memory Data Register (NFDATA) Address: xa_cc 31 : R/W NAND Flash Memory Read/Program Data 32/16/8-bit accessible _h NAND Flash Memory Operation Status Register (NFSTAT) Address: xa_c14 31 : 17 R Reserved - 16:12 R Error bit count ECC가완료된후, 검출된 Error bit의개수 11 R Read data not FF Flag Erase 후, NAND Flash 의 data 가전부 FF 인지확인하는용도로사용된 다. 읽은 data 가 FF 가아닌경우 1 로 set 되며, 이레지스터를읽으면 clear된다. 1 R Reserved - 9 R DMA Write Done DMA Write가완료되면 set된다. 이 register를읽으면 clear된다. 8 R DMA Read Done DMA Read가완료되면 set된다. 이 register를읽으면 clear된다. 7 R BCH Decoding Done Status ECC의 Decoding이완료되면 set된다. 이 register를읽으면 clear된다 6 : 4 R Reserved - 3 R BCH Decoding Result : Decoding Fail 1 : Decoding Success 2 R Auto ECC Done bit 이 bit 가 1 이면 Auto ECC 가완료되었음을나타낸다. 이 register 를읽 으면 clear된다. 1 R NAND Flash Memory nbusy Level : Busy 1 : Ready R NAND Flash Memory Busyx Rising Edge Status Ready/Busyx 신호가 low 에서 high 로변하면 1 로설정된다. 이 register 를읽으면 clear 가된다. nbusy Level NAND Flash Memory ECC(Error Correction Code) Register (NFECC) Address: xa_c18 31 : 24 R Reserved - 23 : 16 R/Clear ECC2 FFh (~P4, ~P4, ~P2, ~P2, ~P1, ~P1, ~P248, ~P248 ) 15 : 8 R/Clear ECC1 FFh (~P124, ~P124, ~P512, ~P512, ~P256, ~P256, ~P128, ~P128 ) 7 : R/Clear ECC FFh (~P64, ~P64, ~P32, ~P32, ~P16, ~P16, ~P8, ~P8 ) * P1~P4 : Column Parity, P8~P248 : Row Parity * ~ : Logically inverse operation Register Description 17 NAND Flash Controller Copyright 215, Advanced Digital Chips, Inc.

154 NAND Flash Memory Configuration Register (NFCFG) Address: xa_c1c 31 : 21 R Reserved - 2 R/w Read data Latch timing Adjust bit. Configure as system clock. 1 : Minimum ~ 6Mhz 1 : 4Mhz ~ Maximum 19 : 17 R Reserved - 16 R/W NDFL_nCS Control 1 : Chip Enable 1 : Chip Disable 15 R Reserved - 14 : 12 R/W Ts : NDFL_ALE/NDFL_CLE Set-up Time 111 : 1 Clock 1 : 2 Clocks 1 : 3 Clocks 11 : 4 Clocks 1 : 5 Clocks 11 : 6 Clocks 11 : 7 Clocks 111 : 8 Clocks 11 R Reserved - 1 : 8 R/W Twp : NDFL_nWE Pulse Width 111 : 1 Clock 1 : 2 Clocks 1 : 3 Clocks 11 : 4 Clocks 1 : 5 Clocks 11 : 6 Clocks 11 : 7 Clocks 111 : 8 Clocks 7 R Reserved - 6 : 4 R/W Trp : NDFL_nRE Pulse Width 111 : 1 Clock 1 : 2 Clocks 1 : 3 Clocks 11 : 4 Clocks 1 : 5 Clocks 11 : 6 Clocks 11 : 7 Clocks 111 : 8 Clocks 3 R Reserved - 2 : R/W Th : NDFL_ALE/ NDFL_CLE/ NDFL_nCS Hold Time 111 : 1 Clock 1 : 2 Clocks 1 : 3 Clocks 11 : 4 Clocks 1 : 5 Clocks 11 : 6 Clocks 11 : 7 Clocks 111 : 8 Clocks NAND Flash Memory ECC Code for LSN data (NFECCL) Address: xa_c2 31 : 16 R Reserved - 15 : 8 R S_ECC1 FFh (1, 1, 1, 1, 1, 1, ~P4_s, ~P4 _s) 7 : R S_ECC FFh (~P2_s, ~P2 _s, ~P1_s, ~P1 _s, ~P16_s, ~P16 _s, ~P8_s, ~P8 _s) * P1_s~P4_s : Column Parity, P8_s~P16_s : Row Parity * ~ : Logically inverse operation NAND Flash Memory Error Corrected Data Register (NFECD) Address: xa_c24 31 : R Automatically Error Corrected Data NAND Flash Controller 17.4 Register Description Copyright 215, Advanced Digital Chips, Inc.

155 NAND Flash Memory Spare Address Register (NFSPADR) Address: xa_c28 31 : 16 R Reserved - 15 : R/W Spare address to access during Auto ECC h NAND Flash Memory MLC ECCn Register (NFECCn) Address: xa_c2c / xa_c3 / xa_c34 / xa_c38 / xa_c3c / xa_c4 / xa_c44 / xa_c48 / xa_c4c / xa_c5 / xa_c54 31 : R 4-bit ECC Parity Value 52-bit parity[31:] / 52-bit parity[52:32] 24-bit ECC Parity Value _h 336-bit parity[31:], 336-bit parity[63:32], 336-bit parity[95:64], 336-bit parity[127:96], 336-bit parity[159:128], 336-bit parity[191:16], 336-bit parity[223:192], 336-bit parity[255:224], 336-bit parity[287:256], 336-bit parity[319:288], 336-bit parity[335:32] NAND Flash Memory Error Location n Register (NFERRLOCn) Address: xa_c58 / xa_c5c / xa_c6 / xa_c64 / xa_c68 / xa_c6c / xa_c7 / xa_c74 / xa_c78 / xa_c7c / xa_c8 / xa_c84 / xa_c88 / xa_c8c / xa_c9 / xa_c94 / xa_c98 / xa_c9c / xa_ca / xa_ca4 / xa_ca8 / xa_cac / xa_cb / xa_cb4 31 : 11 R Reserved - 1 : R Error byte location 1st~24th h NAND Flash Memory Error Pattern n Register (NFERRPTNn) Address: xa_cb8 ~ xa_d14 31 : 8 R Reserved - 7 : R Error byte pattern 1st~24th h NAND Flash Memory ID Register (NFMID) Address: xa_d18 31 : R NAND Flash ID _h Register Description 17 NAND Flash Controller Copyright 215, Advanced Digital Chips, Inc.

156 18 SD HOST CONTROLLER 18.1 Features - SD (ver 2.) / MMC (ver 3.31) 카드지원 - High Speed (5MHz) 지원 - 1bit/4bit data bus 지원 - DMA 전송지원 - 64 byte FIFO 내장 - 4-bit Command Register bit Response Register 18.2 Block Diagram AMBA Bus (AHB) AMBA Interface CMD register (4 bit) Response register (136 bit) CLK control CMD control shift_register crc7 Tx cmd Rx resp CMD Line SDCLK FIFO (64 Byte) DATA control shift_register crc16 Tx data[3:] Rx data[3:] DATA Line Figure 18-1 SDHC Block Diagram 18.3 SD Card Protocol SD card 와 SD Host 사이의통신은 start bit 으로시작해서 stop bit 으로끝나는 command 와 response, data 를기반으로한다. Command : Command 는 Host(Controller) 가 Command line 을통해 SD 카드로전송되는명령어이다. Command 는여러개의 SD 카드를향해동시에전송되는 broadcast command 와 Address 로 선택된하나의 SD 카드에만전송되는 addressed command 로분류된다. Response : Host 가전송한 Command 에대한응답으로써선택된카드가 Command line 을통해전송한다. Data : Host 에서 SD 카드로또는 SD 카드에서 Host 로 Data line 을통하여블록단위로전송되며일반적 SD Host controller 18.1 Features Copyright 215, Advanced Digital Chips, Inc.

157 으로 1 block 의크기는 512byte 또는 124 byte 이다. SD Card protocol 에서는데이터전송의신뢰성을위해 Command 와 Response 그리고 Data 를 CRC7 과 CRC16 로체크하며 CRC 코드생성과오류검출은하드웨어내부에서스스로이루어진다 Register Description SDHC Control Register (SDHCCON) Address : xa_1h 31 : 6 R Reserved - 5 R/W MMC/SD HC Enable : Disable (Controller is initialized) 1 : Enable MMC/SD HC Enable b Host 에대한 Enable 비트이다. 이비트가 Disable 상태가되면컨트롤 러의상태는초기화되고내부버퍼들은모두 clear된다. 4 : 3 R/W Memory access type : byte align 1 : short align 1 : word align 11 : not use 비트는 SD 메모리카드에 Data 를저장할때데이터정렬방식을 정하게된다. 2 R/W DMA mode selection : Normal mode (data transfer by CPU) 1 : DMA mode (data transfer by DMA) DMA를사용하여빠르게데이터를전송할수있는모드를제공한다. 1 R/W Bus width Selection : 1bit data bus 1 : 4bit data bus R/W MMC/SD clock enable : Disable 1 : Enable b b b b Register Description 18 SD Host controller Copyright 215, Advanced Digital Chips, Inc.

158 SDHC Status Register (SDHCSTAT) Address: xa_14h 31 : 16 R Reserved - 15 R Card_Insertion b Data line[3] 을통하여 SD 카드가슬롯에삽입되었는지를알려주는비트 이다. 달아야한다. : No card insertion detection 1 : card insert detected 14 R Card_Removal 이를사용하기위해서는 data line[3] 은 weak Pull down 저항을 Data line[3] 을통하여 SD 카드가슬롯에서제거되었는지를알려주는비 트이다. : No card removal detection 1 : card remove detected 13 R FIFO full 64바이트데이터 FIFO 가가득찼음을나타내는비트이다. 12 R FIFO half full 64바이트데이터 FIFO 가절반이상찼음을나타내는비트이다. 11 R FIFO empty 64바이트데이터 FIFO가비워졌음을나타내는비트이다. 1 R/C Command & response transaction done Host 가 Command 를보내었을때그에대한 response 를받았음을 려주는비트이다. 만약 Response 가도착하지않는비정상적인경우에 도 Time out error를발생시키며이비트가 1이된다. : Command and response transaction is in progress 1 : Command and response transaction is done 9 R/C Data Write operation done Data write operation 이완료되었음을알려주는비트이다. Data CRC error 가발생한경우에도 write operation 이종료되면서이비트가 1 이 된다. : Write operation is in progress or incomplete 1 : Write operation complete 8 R/C Read operation done Data read operation 이완료되었음을알려주는비트이다. 알 Read data CRC error 가발생한경우에도 read operation 이종료되면서이비트가 1이된다. : Read operation is in progress or incomplete 1 : Read operation complete. 7 :6 R/C Write CRC error code Write operation 진행중에 SD 카드로부터받은 CRC 검사결과를나타 내는코드이다. SD 카드는 Host 가한블록씩데이터를보낼때마다 각블록에대한 CRC 를검사하여그결과값을 Host 에게전송한다. : No CRC Error 1 : CRC Error ( 데이터블록에서 CRC 에러발생 ) 1 : No CRC response ( 데이터블록이 SD 카드에서무시되었음 ) 11 : Reserved 5 R/C Response CRC error Response 에 CRC 에러가발생했음을알려주는비트이다. : No error 1 : Response CRC error occurred 4 R/C Read data CRC error SD 카드로부터 Read 한데이터에 CRC 에러가발생했음을알려주는 비트이다. : No error 1 : Read data CRC error occurred 3 R/C Write data CRC error SD 카드로전송한데이터에 CRC 에러가발생했음을알려주는비트이 b b b 1b b b b b b b b SD Host controller 18.4 Register Description Copyright 215, Advanced Digital Chips, Inc.

159 다. : No error 1 : Write data CRC error occurred 2 R/C Response time out error Response가설정된시간안에오직않았음을알려주는비트이다. : No error 1 : Command response was not received in time Specified. 1 R/C Read data time out error Read 데이터가지정된시간안에오지않았음을알려주는비트이다. : No error 1 : The expected data from card was not received in time Specified R Memory busy state SD 카드의 busy 상태를나타내는비트이다. : Memory is ready 1 : Memory is busy. b b b R/C 는 Read/Clear 를의미한다. Status 의특정비트를 Clear 하는방법은해당비트에 1 을쓰면 clear 된다. Status[15:8] 는인터럽트를발생하는인터럽트소스이기도한다. 이중에한비트가 1 이되면인터럽트가발생하고해당비트가 clear 되기전까지계속인터럽트를요청하게된다 SDHC Clock Divide Register (SDHCCD) Address : xa_18h 31 : 1 R Reserved. - 9 : R/W MMC/SD clock Divide Register 2h f SDCLK f AHB_ Clock 2 Divide [9 : ] SDHC Response Time Out Register (SDHCRTO) Address: xa_1ch 31 : 8 R Reserved - 7 : R/W Response time out. FFh Command 를보낸후 response 를기다리는최대시간을설정한다. 지정된시간안에 response 가도착하지않을경우 response time out error 가발생된다. 시간단위는 SD 카드에전송되는클럭을기준으로 하며 Command 의마지막비트가전송되면클럭카운트가시작된다. 1h : 1 clock count 2h : 2 clock counts... FFh : 255 clock counts Register Description 18 SD Host controller Copyright 215, Advanced Digital Chips, Inc.

160 SDHC Read Data Time Out Register (SDHCRDTO) Address: xa_11h 31 : 16 R Reserved - 15 : 8 R/W Data read time out. FFh Read command 를보낸후 read 데이터를받기까지기다리는최대시 간을설정한다. 사용자는상위 8 비트만설정할수있고하위 8 비트는 h로고정되어있다. 일반적으로 FFh로설정할것을권장한다. 7 : R Reserved. h SDHC Block Length Register (SDHCBL) Address: xa_114h 31 : 12 R Reserved - 11 : R/W Block length. 2h 데이터전송의최소단위인블록의 byte 크기를정하는레지스터임 SDHC Number of Block Register (SDHCNOB) Address: xa_118h 31 : 16 R Reserved - 15 : R/W Multi-block command를사용하여다수의 data block을전송하는경우블 h 록의개수를지정하는레지스터이다. 한블록씩전송될때마다 1 씩감 소하며전송완료되면 이된다 SD Host controller 18.4 Register Description Copyright 215, Advanced Digital Chips, Inc.

161 SDHC Interrupt Enable Register (SDHCIE) Address : xa_11ch 31 : 8 Reserved - 7 R/W Card insert detection Interrupt enable b : disable 1 : enable 6 R/W Card remove detection Interrupt enable b : disable 1 : enable 5 R/W FIFO full Interrupt enable b : disable 1 : enable 4 R/W FIFO half full Interrupt enable b : disable 1 : enable 3 R/W FIFO empty Interrupt enable b : disable 1 : enable 2 R/W End command response Interrupt enable b : disable 1 : enable 1 R/W Write operation done Interrupt enable b : disable 1 : enable R/W Read operation done Interrupt enable : disable 1 : enable b SDHCSTAT[15:8] 이인터럽트소스이고 SDHCIE 레지스터는이에대한인터럽트 Enable 신호이다. 인터럽트가발생하면인터럽트서비스루틴에서필요한작업을수행하고 SDHCSTAT[15:8] 중에인터럽트를 발생시킨비트를 으로만든다. 그러나 card insert detection 인터럽트와 card remove detection 인터럽트는 SDHCSTAT[15] 와 SDHCSTAT[14] 는해당비트가 clear 되지않기때문에인터럽트서비스루틴안에서 인터럽트 Enable 비트를 으로만들어인터럽트신호를 Disable 시킨다 Register Description 18 SD Host controller Copyright 215, Advanced Digital Chips, Inc.

162 SDHC Command Control Register (SDHCCMDCON) SDHCCMDCON 레지스터는사용자가 command 를보내기위해구성하는레지스터이다. 사용자가 SDHCCMDCON 레지스터에 write 하게되면레지스터에쓰여진설정대로 command 가 SD 카드로전송된다. Address: xa_12h 31 : 11 R Reserved - 1 R/W Response 가필요한 command type인지아닌지를결정하는비트이다. b No response 를설정하는경우 response 가 response buffer 에저장되지 않는다. : no response 1 : wait response 9 : 8 R/W Response type을결정하는비트이다. Response type은 command 에 따라달라지므로 command 에맞는 response type 을잘선택해야한 다. : short response (response size : 48bit ) 1 : short response with busy (response size : 48bit, ) 1 : long response (response size : 136bit) 7 R/W Data stream이사용되는 command 인지아닌지를결정하는비트이다. Read command 또는 Write command 인경우이비트를 1 로해야한 다 : without data 1 : with data 6 R/W 데이터 FIFO의입출력방향을결정하는비트이다. Read command 인경우 로설정하고 write command인경우 1로설정한다. : read data 1 : write data 5 : R/W command number를지정하는비트이다. Command number의의미는 b b b h MMC 와 SD card 가조금씩다르므로각각의 spec 을참고하기바람. h = CMD 1h = CMD1... 3Fh = CMD SDHC Command Argument Register (SDHCCMDA) Address: xa_124h 31 : R/W Command argument. h Command token을구성하는항목중에 argument를설정하는레지스터이다 SDHC Response FIFO Access Register (SDHCRFA) Address: xa_128h 31 : 16 R Reserved - 15 : R/W Response를저장하는 FIFO이다. 크기는 8x16 bit. h SDHC Data FIFO Access Register (SDHCDFA) Address: xa_12ch 31 : R/W 데이터를저장하는 FIFO 이다. 크기는 16x32 bit SD Host controller 18.4 Register Description Copyright 215, Advanced Digital Chips, Inc.

163 19 SPI LCD CONTROLLER 19.1 Features - Support Normal SPI transfer with 9bit (Not support falling SCK data sampling) - Support bidirectional SDO mode for 3 wire transaction - Support 24 bit format color and 32bit reserved format color - External clock for SCK - 16byte FIFO for Tx, Rx data 19.2 Register Description SPI LCD control Register (CTRL) Address : xa_8 31 : 8 R Reserved - 7 R/W Enable : Operation Enable : Operation is disabled. 1 : Operation is enabled 6 R/W SDO Direction : Output 1 : Input 5 R/W Lower Byte First 설정되면 Data size 가 16bit, 24bit, 32bit 일때하위바이트의데이터 가먼저전송된다. 4 R/W SCK Polarity 3 R/W Level of D/C bit 2 R/W Add D/C bit : 8bit 전송 1 : 9 bit 전송 (MSB에 D/C bit가추가됨 ) 1 : R/W Data Size : 8 bit data transfer. 1 : 16 bit data transfer. 2 : 24 bit data transfer, 3 : 32 bit data transfer, 24 bit data transfer 의경우메모리에서 32bit 데이터를읽어서상위 8bit 가제거된 24bit 만전송한다 SPI LCD Baud Rate Register (BAUD) Address : xa_84 31 : 8 R Reserved. - 7 : R/W Serial Clock Baud Rate fdotclk SCK 2 ( SPIBR 1) xff SPI LCD DMA Configuration Register (SPI_LCD_DMA) Address : xa_88 31 : 1 R Reserved - RW DMA Enable DMA 의전송량은 DMA 블록의 Trans count 로설정한다 Features 19 SPI LCD Controller Copyright 215, Advanced Digital Chips, Inc.

164 SPI LCD ChipSelect Register (CSx) Address : xa_81 31 : 1 R Reserved - RW CSx : CSx Output Level SPI LCD Status Register (SPI_LCD_STAT) Address : xa_ : 8 R Reserved - 7 R SPIF : SPI Finished Flag : Transfer is not finished. 1 : Transfer is finished. 6 R STXHF : Tx FIFO Is Half Empty : The Empty space is less than Half 1 : The Empty space is more than Half 5 R STXF : TX FIFO Full Status bit : TX FIFO is not full 1 : TX FIFO is full 4 R STXE : TX FIFO Empty Status bit : TX FIFO is not empty 1 : TX FIFO is empty 3 R Reserved 2 R SRXHF : RX FIFO Half Full Status bit : The Remain Data in Rx FIFO is less than Half 1 : The Remain Data in Rx FIFO is more than Half 1 R SRXF : RX FIFO Full Status bit : FIFO_RX is not full 1 : FIFO_RX is full R SRXE : RX FIFO Empty Status bit : FIFO_RX is not empty 1 : FIFO_RX is empty LCD Data Register (SPI_LCD_DATA) Address : xa_ : R/W 16 byte FIFO x_ It is possible to access with 8, 16, 32 bit LCD Interrupt Mask Register (SPI_LCD_INT) Address : xa_81c 31 : 8 R/W Reserved - 7 R/W SPIF : SPI finished Interrupt enable 6 R/W STXHF : Tx fifo half empty interrupt enable 5 R/W STXF : Tx fifo full status interrupt enable 4 R/W STXE : Tx fifo empty status Interrupt enable 3 R/W Reserved 2 R/W STXHF : Rx fifo half full interrupt enable 1 R/W SRXF : Rx fifo Full interrupt enable R/W SRXE : Rx fifo empty interrupt enable SPI LCD Controller 19.2 Register Description Copyright 215, Advanced Digital Chips, Inc.

165 2 SPI (SERIAL PERIPHERAL INTERFACE) adstar_l 에내장된 SPI 는동기직렬버스를통해외부의장치나다른 CPU 와데이터교환을한다. 이 SPI 는모토로라 M68HC11, M68HC5 와 MC68HC16 계열의 SPI 와호환을이루어, Full duplex 3-wire 전송이나 Half duplex 2-wire 를수행할수있다. 고속 SPI 전송을위해 8Bytes 의 FIFO 를내장하여 Mbps 속도의전송에서도 CPU 에부담을주지않고 수행할수있다. adstar_l 의 SPI 는 Master Mode 와 Slave Mode 를모두지원한다 Features - Full duplex mode. Three-wired synchronous Transfer - Master or Slave Operation - Programmable clock polarity and phase - End of transmission interrupt flag - Write collision flag protection - Master-master mode fault protection capability - 8Bytes FIFO 2.2 Block Diagram SPIBR Counter SPICTRL sck_in Control Logic Clock Logic sck_out sck_oen SCK ssx_in APB BUS SPISTAT 32-BIT RX Shift Register 8/16/32-BIT TX Shift Register SPIDATA (8Bytes) CLK master input master output slave input slave output ssx_out ssx_oen mosi_in mosi_out mosi_oen miso_in miso_out miso_oen nss MOSI MISO nssctrl Ouput Control Logic SPIINT Figure 2-1 SPI Block Diagram Features 2 SPI (Serial Peripheral Interface) Copyright 215, Advanced Digital Chips, Inc.

166 2.3 Functional Description 클럭제어회로에서클럭의극성선택과두개의클럭프로토콜의선택을통해서대부분의동기직렬 주변장치와의호환이이루어진다. SPI 가 Master 로설정되면소프트웨어적으로 256 개의다양한시리얼 클럭을만들수있다. SPI 는데이터전송동작과데이터수신동작이동시에이루어진다. 두시리얼데이터라인에서정보의샘플링 (sampling) 과쉬프팅 (shifting) 은시리얼클럭라인에의해동기된다. Slave SPI 디바이스의개별적인선택은 Slave 선택라인을통해할수있다. 선택되지않은 Slave 디바이스는 SPI 버스의동작에영향을주지않는다. Master SPI 디바이스에서는 Slave 선택라인은다중 Master 버스충돌을나타내는데사용될수있다. 에러검출회로는프로세스끼리의연결을위해사용된다. 전송동작중에시리얼쉬프터레지스터에 데이터를쓰게되면쓰기충돌이발생한다. 다중 Master 모드실패검출은한개이상의 CPU 가동시에 버스 Master 가되려고시도할때출력드라이버를 disable 시킨다 SPI Pins SPI 에는 MISO, MOSI, SCK, nss, 네개의양방향핀이있다. SPI 컨트롤레지스터의 WOMP 비트가 각각의핀의출력동작에대해 Open Drain 출력이나 CMOS 출력을결정하게된다. SPI 컨트롤레지스터의 MSTR 비트에의해 Master 또는 Slave 동작이결정되고이에따라핀의동작이 결정된다 Table 2-1 SPI Pin Functions Pin Name Mode Function Master in, slave out(miso) Master Provides serial data input to the SPI Slave Provides serial data output from the SPI Master out, slave in (MOSI) Master Provides serial output from the SPI Slave Provides serial input to the SPI serial clock(sck) Master Provides clock output from the SPI Slave Provides clock input to the SPI Slave select(nss) Master Output : Selects slave devices Slave Input : chip select for SPI SPI (Serial Peripheral Interface) 2.3 Functional Description Copyright 215, Advanced Digital Chips, Inc.

167 SPI Operating Modes SPI 는 Master 나 Slave 모드에서동작한다. Master 모드는 CPU 가데이터전송을주관할경우에사용된다. Slave 모드는외부디바이스에의해 CPU 에시리얼전송이이루어지는경우에사용된다. 컨트롤레지스터의 MSTR 비트에의해 Master 나 Slave 동작이선택된다. Master Mode SPICTRL 의 MSTR 비트를설정하면 Master 모드동작이선택된다. Master 모드에서는시리얼전송을 초기화할수있고외부에서의초기화된전송에응답하지않는다. Master 모드에서는 MISO 핀이시리얼데이터입력으로사용되고 MOSI 핀은시리얼데이터출력으로 사용된다. 특정한응용분야에따라하나또는둘다필요할수있다. SPI 를 Master 모드에서사용하려면다음과정을거쳐야한다. 1. SPICTRL 레지스터에 BAUD, CPHA, CPOL, SIZE, MSBF, WOMP 의값을할당한다 2. Master 동작을위해 MSTR 비트설정한다. 3. Set SPIEN bit to enable SPI. 4. SPI 을 enable 하도록 SPIEN 비트을설정한다. 5. Slave 디바이스를 enable 한다. 6. 전송을시작하기위해적당한데이터를 SPIDATA 레지스터에쓰기를한다. 7. SPI 는전송이끝나면 SPISTAT 레지스터의 SPIF 플래그를 H/W 적으로설정한다. SPIF 가 인가되면인터럽트요청이발생된다. SPIF 가설정되어있는상태에서 SPISTAT 레지스터를읽고 SPIDATA 레지스터에쓰기나읽기동작이일어나면 SPIF 플래그는자동적으로클리어된다. 데이터전송은내부에서만든시리얼클럭 (SCK) 에동기된다. SPICTRL 레지스터의 CPHA 와 CPOL 비트들은클럭의위상과극성을제어한다. CPU 가 MOSI 핀에서데이터를보내는 SCK edge 와 MISO 핀을 통해들어오는데이터의 latch 하는 SCK edge 는 CPHA 와 CPOL 에의해결정된다. Slave Mode SPICTRL 레지스터의 MSTR 비트을 으로설정하면 Slave 모드로동작한다. Slave 모드에서는, SPI 는시리얼전송을초기화할수없다. 전송은외부버스 Master 에의해초기화된다. Slave 모드는특히다중 Master SPI 버스에서사용된다. 주어진시간에단하나의디바이스만이버스 Master 가될수있기때문이다. Slave 모드에서는시리얼데이터출력을위해 MISO 핀이사용되고, 시리얼데이터입력을위해 MOSI 핀이사용된다. 특정한응용분야에따라서둘다또는하나의핀만필요하다. SCK 는입력시리얼클럭 이다. nss 가인가되면 Slave 로선택된다. 데이터전송을위해데이터레지스터에쓰기를한다. Slave 모드에서는 SCK, MOSI, and nss 는입력이고 MISO 는출력이된다. CPHA, CPOL, SIZE, MSBF, WOMP 의설정을위해컨트롤레지스터에값을쓴다. MSTR 비트클리어함으로써 Slave 동작을선택한다. SPIEN 를설정하여 SPI 를 enable 시킨다. Slave 모드의디바이스에서는 BAUD 의값은 SPI 동작에영향을미치지않는다 Functional Description 2 SPI (Serial Peripheral Interface) Copyright 215, Advanced Digital Chips, Inc.

168 SPIEN 가설정되고 MSTR 이클리어되면, nss 핀입력의 Low 상태가 Slave 모드동작을초기화한다. nss 핀은오로지입력으로만사용된다. 데이터의바이트나워드전송후에 SPI 는 SPIF 플래그를설정한다. 컨트롤레지스터의 SPIE 비트가 설정되어있으면, SPIF 가인가되면인터럽트요청이발생한다. 전송은외부에서발생된 SCK 에동기된다. CPHA 와 CPOL 은 Slave CPU 가 MOSI 핀을통해들어오는 데이터를래치하거나 MISO 핀을통해나가는데이터의클럭의 Edge 를결정한다 Data Transfer Timing CPHA= 이고 MSB 시작인모드에서 1Byte 데이터전송타이밍도를보여준다. SCK 의두개의형태의파형을나타나있다. 하나는 CPOL 인 인경우이고다른하나는 CPOL 이 1 인경우이다. 이타이밍도는 Master 와 Slave 가 SCK, MISO 와 MOSI 핀으로직접연결되어있으므로 Master 타이밍도또는 Slave 타이밍도로볼수있다. MISO 신호는 Slave 에서의출력이고 MOSI 신호는 Master 의출력신호이다. nss 신호는 Slave 로의칩선택신호이다. Master 일때 SPDR 에데이터를쓰면전송이초기화된다. Slave 는 nss 가 falling edge 일때전송을초기화한다. SCK 신호는첫번째 SCK cycle 의반주기까지 inactive 상태로남아있다. 전송완료를나타내는 SPIF 비트는 8 번째 SCK cycle 의끝에서 set 된다. CPHA= 일때는 nss 가 low 였다가 1 바이트전송후짧은시간내에 Inactive (High) 된다. Slave 는 nss 가 low 일때 data register 에값을 write 하면 write collision error 가발생한다. SCK CYCLE SCK (CPOL=) SCK (CPOL=1) MOSI (Master Out) MSB LSB MISO (Master In) MSB LSB nss (To Slave) Figure 2-2 Transfer Timing when CPHA = CPHA= 1 인경우의전송타이밍도이다. SCK 는마지막 8 번째 cycle 의반주기에서 inactive 된다. SPIF 비트는 8 번째 SCK cycle 의종단에서 set 된다. 8 번째 SCK cycle 의중간주기에서마지막 edge 가생기기때문에 Slave 는 8 번째 SCK cycle 의중간에서마지막데이터를 sample 한후에수신완료한다. nss 는 1Byte 전송마치고어느정도시간동안충분히 low 를유지한다. 따라서 CPU 가전송상태를 Polling 하여연속으로전송하는경우에는계속 low 상태를유지하게된다 SPI (Serial Peripheral Interface) 2.3 Functional Description Copyright 215, Advanced Digital Chips, Inc.

169 SCK CYCLE SCK (CPOL=) SCK (CPOL=1) MOSI MSB LSB MISO MSB LSB nss Figure 2-3 Transfer Timing when CPHA = SCK Phase and Polarity Control 컨트롤레지스터의두개의비트가 SCK 의위상과극성을결정한다. 클럭극성 (CPOL) 비트는클럭의극성 (High or Low) 을선택한다. 클럭위상비트 CPHA 는전송타이밍에영향을주는두가지전송형태중하나를선택한다. 클럭의위상과극성은 Master 와 Slave 모두동일하여야한다. 어떤경우에는전송사이에위상과극성을바꾸어 Master 디바이스가 Slave 디바이스와다른조건으로데이터를주고받을수도있다. SPI 의이러한유연성은거의모든동기시리얼주변장치와의직접적인연결을가능하게한다. nss SCK SCK SCK SCK (CPOL=, CPHA=) (CPOL=, CPHA=1) (CPOL=1, CPHA=) (CPOL=1, CPHA=1) MSB LSB MSB if CPHA= Internal strobe for data capture (for all modes) Figure 2-4 SCK Phase and Polarity SPI Serial Clock Baud Rate SPI Baud rate 는 SPBR 레지스터에 1 에서 255 까지의값을저장하여설정할수있다. Slave Mode 에서의외부 SPI Master 가제공하는 SCK 를받아들이기때문에 SPIBRR 레지스터의값의설정에영향을받지않는다. 그러나 Slave Mode 에서동작할수있는최대속도는 System Clock 에영향을받는다 Functional Description 2 SPI (Serial Peripheral Interface) Copyright 215, Advanced Digital Chips, Inc.

170 f PCLK SCK Baud Rate 2 ( SPIBR 1) or f PCLK SPIBR 1 2 SCK Baud Rate Open-Drain Output for Wired-OR Multiple SPI Master 가아니면 SPI 버스출력이 Open-Drain 을지원할필요는없다. Open-Drain 출력이 필요할경우 SPICTRL 레지스터의 WOMP 비트를설정하여 Open-Drain 출력을제공하도록할수있다. Open-Drain 으로설정할경우각각의출력라인에반드시 pull-up 저항을달아야한다 Transfer Size and Direction SPICTRL 레지스터의 SPISIZE 비트은전송크기 8/16/32 비트를선택한다. SPICTRL 레지스터의 MSBF 비트는데이터전송의시작을 MSB(MSBF=1) 나 LSB 부터하도록한다 Write Collision 전송진행중에 SPIDATA 레지스터에쓰기를시도하면쓰기충돌이발생한다 MODE Fault SPI system 이 Master 로설정되고, nss signal input line 이 assert 되었을때, mode fault error 가발생하면, SPISTAT 의 MODF bit 이 set 된다. Master device 만 MODF 를발생시킬수있으며, 다른 SPI device 가 master 가되려고할때발생한다 SPI (Serial Peripheral Interface) 2.3 Functional Description Copyright 215, Advanced Digital Chips, Inc.

171 Interrupt SPIF Interrupt FIFO 에저장된데이터와 TX Shift 레지스터가모두비워지면발생하고, SPI 전송이완료되었음을의미한다. SPI 전송이완료되었음을확인할수있는 Interrupt 이다. MODF Interrupt Mode fault 가일어나면발생한다. Mode fault 란여러개의 Master 가존재하는경우둘이상의 Master 가 데이터를전송하는경우를말한다. nss Interrupt nss port 신호를감지하여변화가생기면발생한다. TX_FIFO_FULL, TX_FIFO_EMPTY, RX_FIFO_FULL, RX_FIFO_EMPTY - TX_FIFO_FULL: 8Byte의내부 FIFO 가모두채워졌음을의미한다. 이상태에서 TX FIFO에데이터를더채우게되면, 잘못된데이터전송이이루어진다. - TX_FIFO_EMPTY: TX FIFO에채워졌던데이터가모두전송되었음을의미한다. 그러나아직 TX Shift 레지스터가비워지지않았기때문에 SPI 전송이완료된것은아니다. - RX_FIFO_FULL: RX_FIFO가모두채워졌음을의미한다. - RX_FIFO_EMPTY: RX_FIFO 가모두비워졌음을의미한다. SSX SCK F E F E F E F MOSI 1Byte TX FIFO Write 1Byte TX FIFO Write 1Byte TX FIFO Write 1Byte TX FIFO Write Figure Byte Transfer vs. Status and Interrupt SSX SCK E F E F E F MOSI nbyte TX FIFO Write nbyte TX FIFO Write nbyte TX FIFO Write Figure 2-6 n-bytes Transfer vs. Status and Interrupt Functional Description 2 SPI (Serial Peripheral Interface) Copyright 215, Advanced Digital Chips, Inc.

172 2.4 Register Description SPI Control Register (SPICTRL) Address : xa2_1 31 : 8 R Reserved - 7 R/W SPIEN : SPI Enable : SPI is disabled. 1 : SPI is enabled 6 R/W WOMP : Wired-OR Mode for SPI Pins : Outputs have normal CMOS drivers. 1 : Open-drain drivers 5 R/W MSTR : Master/Slave Mode Select : Slave operation 1 : Master operation 4 R/W CPOL : Clock Polarity : The inactive state value of SCK is logic level zero 1 : The inactive state value of SCK is logic level one. 3 R/W CPHA : Clock Phase : Data captured on the leading edge of SCK and changed on the trailing edge of SCK. 1 : Data is changed on the leading edge of SCK and captured on the trailing edge of SCK. 2 R/W MSBF : Most Significant Bit First : Serial data transfer starts with LSB. 1 : Serial data transfer starts with MSB. 1 : R/W SPISIZE : Transfer Data Size : 8-bit data transfer. 1 : 16-bit data transfer. 1 : 32-bit data transfer SPI Baud Rate Register (SPIBR) Address : xa2_14 31 : 8 R Reserved. - 7 : R/W Serial Clock Baud Rate xff f PCLK SCK 2 ( SPIBR 1) Master Mode SCK APB Clock / 2 Slave Mode SCK APB Clock / SPI (Serial Peripheral Interface) 2.4 Register Description Copyright 215, Advanced Digital Chips, Inc.

173 SPI Status Register (SPISTAT) Address : xa2_18 31 : 8 R Reserved - 7 R SPIF : SPI Finished Flag : SPI is not finished. 1 : SPI is finished. 6 R WCOL : Write Collision : No attempt to write to the SPDR happened during the serial transfer. 1 : Write collision occurred. 5 R MODF : Mode Fault Flag : Normal operation 1 : Another SPI node requested to become the network SPI master while the SPI was enabled in master mode 4 R nss : Slave Select Flag : Current Value of nss port is low 1 : Current Value of nss port is high 3 R STXF : TX FIFO Full Status bit : FIFO_TX is not full 1 : FIFO_TX is full 2 R STXE : TX FIFO Empty Status bit : FIFO_TX is not empty 1 : FIFO_TX is empty 1 R SRXF : RX FIFO Full Status bit : FIFO_RX is not full 1 : FIFO_RX is full R SRXE : RX FIFO Empty Status bit : FIFO_RX is not empty 1 : FIFO_RX is empty SPI Data Register (SPIDATA) Address : xa2_1c 31 : R/W SPI Data At 32-bit transfer mode - MSB of Data is SPDR[31] At 16-bit transfer mode - MSB of Data is SPDR[15] At 8-bit transfer mode - MSB of Data is SPDR[7] x_ LSB of Data (received or transmit) is SPDR[] in any transfer mode Register Description 2 SPI (Serial Peripheral Interface) Copyright 215, Advanced Digital Chips, Inc.

174 SPI nss Control Register (nssctrl) Address : xa2_11 31 : 1 R Reserved - RW nsscon : nss Output Level SPI Interrupt Mask Register (SPIINT) Address : xa2_ : 8 R Reserved - 7 RW SPIFE : SPIF Interrupt en/disable SPIF Interrupt occurs when transfer has completed. : SPIF interrupt is disabled 1 : SPIF is enabled 6 RW MODFE : MODFI Interrupt en/disable MODFI Interrupt occurs when two more master use data line. : MODFI interrupt is disabled 1 : MODFI is enabled 5 R Reserved 4 RW nssen : nss Interrupt en/disable nss Interrupt occurs when nss signal has changed. : nss Interrupt is disabled 1 : nss Interrupt is enabled 3 RW STXFE : FIFO_TX_FULL Interrupt en/disable FIFO_TX_FULL Interrupt occurs when FIFO_TX is full : FIFO_TX_FULL Interrupt is disabled 1 : FIFO_TX_FULL Interrupt is enabled 2 RW STXEE : FIFO_TX_EMPTY Interrupt en/disable FIFO_TX_EMPTY Interrupt occurs when FIFO_TX is empty : FIFO_TX_EMPTY Interrupt is disabled 1 : FIFO_TX_EMPTY Interrupt is enabled 1 RW SRXFE : FIFO_RX_FULL Interrupt en/disable FIFO_RX_FULL Interrupt occurs when FIFO_RX is full : FIFO_RX_FULL Interrupt is disabled 1 : FIFO_RX_FULL Interrupt is enabled RW SRXEE : FIFO_RX_EMPTY Interrupt en/disable FIFO_RX_EMPTY Interrupt occurs when FIFO_RX is empty : FIFO_RX_EMPTY Interrupt is disabled 1 : FIFO_RX_EMPTY Interrupt is enabled SPI (Serial Peripheral Interface) 2.4 Register Description Copyright 215, Advanced Digital Chips, Inc.

175 21 TWI (TWO WIRED INTERFACE) adstar-l 은범용 TWI 버스와의인터페이스를위해 TWI 제어기를내장한다. TWI 는 SCL 과 SDA 신호를 가진다 Features - Master transmitter mode - Master receive mode - Slave transmitter mode - Slave receive mode - Software programmable clock frequency - Software programmable acknowledge bit - Interrupt driven data-transfers - Start/Stop/Repeated Start/Acknowledge generation - Multi master operation 21.2 Block Diagram SDA TWIBR/TWIBR1 START/STOP Condition Generaion SCL APB BUS TWICTRL TWISTAT Arbitration and START/STOP Detection Address Compare TWIADR 8-bit Address Shifter TWIDATA 8-bit Shifter Figure 21-1 TWI Block Diagram Features 21 TWI (Two Wired Interface) Copyright 215, Advanced Digital Chips, Inc.

176 Functional Description DATA TRANSFER FORMAT SDA 라인에는모든데이터길이는 8 비트다. 매전송마다전송될수있는바이트수는제한되어있지않다. Start condition 다음의첫바이트는주소필드이다. TWI-bus 가 Master 로모드로동작할때 Master 에의해주소필드가전송된다. 모든바이트는다음에는 ACK 비트가따라온다. 항상데이터와주소의 MSB 비트부터전송이시작된다. Write Mode Format with 7-bit Addresses S Slave Address 7bits R/W A DATA(1Byte) A P "" (Write) Data Transferred (Data + Acknowledge) Read Mode Format with 7-bit Addresses S Slave Address 7bits R/W A DATA(1Byte) A P "1" (Read) Data Transferred (Data + Acknowledge) NOTES: 1. S:Start, rs:repeat Start, P:Stop, A:Acknoledge 2. :From Master to Slave, from Slave to Master Figure 21-2 TWI-Bus Interface Data Format START AND STOP CONDITION Start condition 은 1 Byte 의 data 를전송할수있다. 그리고, Stop condition 은 data 전송을종료한다. Start condition 은 SCL 이 high 일때 SDA line 이 high to low 로 transition 한다. Stop condition 은 SCL 이 high 일때 SDA line 이 low-to-high 로 transition 한다. Start condition 이발생하면, TWI bus 는 busy 가된다. Stop condition 이발생한후, TWI bus 는자유롭게된다. SDA MSB Acknowledgement Signal from Receiver Acknowledgement Signal from Receiver SCL Start ACK Stop Byte Complete, Interrupt within Receiver Clock Line Held Low While Interrupts are Serviced Figure 21-3 Data Transfer on the TWI-Bus TWI (Two Wired Interface) 21.3 Functional Description Copyright 215, Advanced Digital Chips, Inc.

177 ACK SIGNAL TRANSMISSION 한바이트전송을완전히끝내기위해서는수신단은송신단에 ACK 비트를보내야한다. ACK 펄스는 SCL 라인의 9 번째클럭에서발생해야한다. 그래서한바이트데이터를전송을위해모두 9 개의클럭이 필요하다. Master 는 ACK 비트전송을위한클럭펄스를생성해야한다. 송신단은 ACK 클럭펄스를입력받을때 SDA 라인을 High 로만들기위해 SDA 라인을놓아줘야한다. 또한수신기는 ACK 펄스때 SDA 라인을 Low 로유지하여 SCL 의아홉번째의 High 구간에서 SDA 를 Low 로만든다. ACK 비트는소프트웨어적으로 control register 의 TXACK 비트를설정하여 ACK 나 NOACK 로선택할수 있다. Data Output by Transmitter Data Output by Receiver Clock to Output SCL from Master Start Start Condition Clock Pulse for Acknowledgement Figure 21-4 Acknowledgement of TWI READ-WRITE OPERATION 송신동작모드에서데이터전송후에 TWI-bus 인터페이스는데이터쉬프터레지스터에데이터가준비될때까지기다려야한다. 데이터쓰여질때까지 SCL 라인은 Low 로유지될것이다. 새로운데이터가데이터쉬프터레지스터에쓰여지고나서 SCL 은 release 된다. Interrupt 를사용할경우, TWI 는현재데이터전송후 interrupt 를요청한다. CPU 는 interrupt 요청을받은뒤에새로운데이터를버퍼에쓴다. 수신동작모드에서데이터를수신한후에, TWI bus 는 data 를읽어갈때까지기다린다. 수신된데이터가읽어갈때까지 SCL 을 LOW 로유지된다. 새로운 data 가읽혀지고난다음에 SCL 은 release 된다. Interrupt 를사용할경우, TWI 는데이터를수신한후 interrupt 를발생하고, interrupt request 를받은 CPU 는 data 를읽는다 Functional Description 21 TWI (Two Wired Interface) Copyright 215, Advanced Digital Chips, Inc.

178 BUS ARBITRATION PROCEDURES 여러개의 master 가 bus 를동시에제어하는것을방지한다. SDA line 에 high level 을내보낸 master 가 또다른 master 가내보낸 low level 의 SDA line 을인식하면, 현재 TWI bus 를자신이아닌다른 master 가 제어한다고인식하고, 데이터전송을더이상진행하지않도록한다. Device1 과 Device2 과동시에 master mode 로동작하는경우에 SCL 라인에서발생하는클럭의모양을 보면다음과같이동기화가이루어진다. wait state start counting HIGH period CLK1 CLK2 counter reset SCL Figure 21-5 Bus arbitration 1 of TWI 위상황에서 SDA 라인에나타나는 data 값에따라 Device1, Device2 중하나가우선권을갖는과정은 다음과같다 DATA1 master1 loses Arbitration DATA1 SDA DATA2 SDA SCL S Figure 21-6 Bus arbitration TWI (Two Wired Interface) 21.3 Functional Description Copyright 215, Advanced Digital Chips, Inc.

179 ABORT CONDITIONS arbitration 이발생하지않은경우 1. TWICTRL 레지스터의 MSTR 비트를클리어시키면 stop 조건이발생한다. 2. NO ACK 발생하여 stop 조건이발생한다. 즉 ACK 구간에서 SDA 신호가 Low 가아니면발생한다. Arbitration이발생한경우 Arbitration 발생에의해제어권을잃은경우 MSTR 비트는클리어되지만이에의한 stop condition 은발생하지않는다. 현재진행중인 SCL 클럭은한바이트전송끝까지진행되고데이터출력인 SDA 는 High 상태가된다 Operational Flow Diagrams TWI initialization TWI 는먼저초기화가이루어져야한다. BEGIN Enable TWI by setting TWIEN Register setting Enable TWI interrupt (Optional) END Figure 21-7 TWI Initialization Flow Char Functional Description 21 TWI (Two Wired Interface) Copyright 215, Advanced Digital Chips, Inc.

180 Master Transmit / Receive TWI 의데이터송신과데이터수신에대한 Flow chart 이다. 송신시와수신시에있어서가장큰차이점은수신시에는마지막데이터를수신하기전에 ACK 비트를 NOACK 로설정하는단계가더있다는점이다. 이것은 master 가 slave 에게마지막수신데이터임을알리기위한것이다. 또한, 실제데이터를수신하기위한 SCL 클럭을생성하기위해 TWIDATA 레지스터의 dummy read 단계가필요하다 BEGIN Bus Busy? YES NO Write Slave address (TWIDATA) Master (MSTR =1, START) Transfer Complete? NO YES RXACK = 1? NOACK ACK Write DATA (TWIDATA) YES Transfer Complete? NO YES RXACK = 1? YES Last Data? NO YES Clear Master Mode (TWIMOD=, STOP) END Figure 21-8 Master Transmit Flow Char TWI (Two Wired Interface) 21.3 Functional Description Copyright 215, Advanced Digital Chips, Inc.

181 BEGIN Bus Busy? YES NO Write Slave address (TWIDATA) Master (MSTR =1, START) Transfer Complete? NO YES Dummy Read (TWIDATA) NO Transfer Complete? RXACK YES NO Read Data (TWIDATA) YES last Data -1? NO YES TXACK =1 Seting(NOACK) YES Read data (TWIDATA) Transfer Complete? NO RXACK (don't care) END YES Figure 21-9 Master Receive Flow Char Functional Description 21 TWI (Two Wired Interface) Copyright 215, Advanced Digital Chips, Inc.

182 BEGIN Bus Busy? YES NO Write Slave address (TWIDATA) Master (MSTR =1, START) Transfer Complete? NO NO RXACK = 1? YES Set RS (repetes start) TWICTRL to Generate RESTART RS(Repeated Start) is occurred by other slave access or MSTR or tx/rx configuration. Write Slave address (TWIDATA) Transfer Complete? NO YES Dummy Read (TWIDATA) Transfer Complete? NO YES last Data -1? YES NO Read Data (TWIDATA) Set TXAK in TWICTRL to NOACK YES Read data (TWIDATA) Transfer Complete? NO END YES Figure 21-1 Master combined format Flow Char TWI (Two Wired Interface) 21.3 Functional Description Copyright 215, Advanced Digital Chips, Inc.

183 Slave Mode (Polling mode) BEGIN Slave address (TWIDT = 1?) Matching Slave address? NO(NOACK) Rx YES(ACK) Check SRW bit in TWISTAT for Tx/Rx Tx Read dummy data From TWIDATA (for tcie bit clear) Write Tx Data (TWIDATA) Matching Slave address? NO YES Read Rx Data (TWIDATA) Transfer Complete? NO YES YES YES Bus Busy? YES Bus Busy? NO NO END Figure Slave Mode Flow Chart (Polling) Functional Description 21 TWI (Two Wired Interface) Copyright 215, Advanced Digital Chips, Inc.

184 Slave Mode (Interrupt mode) BEGIN (tcf Interrupt occurred) Addressed as Slave? NO YES Check SRW bit in TWISTAT for Rcv/Xmit Read/Write TWIDATA END Figure Slave Mode Flow Chart (Interrupt) TWI (Two Wired Interface) 21.3 Functional Description Copyright 215, Advanced Digital Chips, Inc.

185 Register Description TWI Control Register (TWICTRL) Address : x82_18 31 : 8 R Reserved. - 7 RW TWIEN : TWI Controller Enable. TWI 송수신을위해서다른 register 의 setting 에앞서먼저이 bit 를 set시킨다. : Disable 1: Enable 6 R Reserved. - 5 RW TWIMOD : Master/Slave Mode Select. 에서 1 로바뀌면 Master mode 가선택되면서 START condition 이발 생한다. clear 되면 STOP condition 이발생하고, Slave mode 로전환한 다. clear 되더라도제어권한을잃은상태라면, STOP condition 은발생 하지않는다. : STOP condition 을발생시킨다. 1: START condition을발생시킨다. 4 RW TWITR : Transmit/Receive Mode Select. Master Mode 에서의전송동작을결정한다. : TWI Master 수신 1: TWI Master 송신 3 RW TWIAK : Transmit Acknowledge Enable. 이비트는 ACK 구간동안에 SDA line 의값을결정한다. Master Receive Mode 일때마지막바이트전송일때 NO ACK 는데 이터전송이마지막임을나타낸다. 마지막전송후 NO ACK 이면, STOP condition을발생시킨다. : ACK bit = ACK (acknowledge) 1: ACK bit = 1 NO ACK (no acknowledge) 2 RW REPST : Repeated Start. 이 bit 를 1 로 write 하면, TWI controller 가 Master 일때 Repeated START condition 을발생시킨다. Repeated START condition 이발생하 면 clear 된다. : N/A 1: Repeated START condition을발생시킨다. 1 R/W TCIE : Transfer complete Interrupt enable bit 1-byte 단위의데이터전송이완료되었을때, 인터럽트발생여부를 결정한다. : Disable 1: Enable R/W LSTIE : Lost arbitration Interrupt enable bit Master 로동작시, 전송권한을잃었을경우, 인터럽트발생여부를 결정한다. : Disable 1: Enable Register Description 21 TWI (Two Wired Interface) Copyright 215, Advanced Digital Chips, Inc.

186 TWI Status Register (TWISTAT) Address : x82_ : 1 R Reserved. - 9 RW TXEMPTY : TX Buffer Empty. 1 송신버퍼의상태를나타낸다. 일때, 원하는값으로 Write 할수있 다. : 송신버퍼에보낼데이터가있음 1: 송신버퍼가비었음 8 RW RXFULL : RX Buffer Full. 수신버퍼의상태를나타낸다. 1 일때, 원하는값으로 Write 할수있 다. : 수신버퍼가비었음 1: 수신버퍼에읽어갈데이터가있음 7 R TWIDT : Data Transferring Bit. 한바이트전송될때마다 set 되고, TWIDATA 레지스터를 read 나 write 할때 clear 된다. 또한, 이 bit 에 1 을 write 하면 clear 된다. : 바이트전송중 1: 한바이트전송완료 6 R TWIAS : Addressed as Slave Bit. 자신의 address 와전송받은 address 가일치할때 TWI controller 는 slave 로서동작하게된다. TWICON 레지스터가 write 되거나, STOP condition 발생시 clear 된다. : Address 가일치하지않음 1: Address가일치함 5 R TWIBUSY : Bus Busy Bit. TWI bus 상태를의미한다. START condition 에의해 set 되고, STOP condition 에의해 clear 된다. 이비트에 을 write 하여도 clear 된다. : Bus idle 상태 1: Bus busy 상태 4 RW TWILOST : Lost Arbitration Bit. TWI controller 가 master mode 일때, bus 의제어권한을잃었을경우 set 된다. 소프트웨어적으로 clear 해주어야한다. 1 을 write 하면 clear 된 다. : Lost arbitration 이발생하지않았음. 1: Lost arbitration이발생하였음. 3 R TWISRW : Slave Read/Write Bit. TWI controller 가 slave mode 일때송수신동작을나타낸다. : Slave 수신모드 1: Slave 송신모드 2 R Reserved. - 1 RW RSF : Repeated start flag Repeated START condition 이발생하였는지확인하는 flag bit 이다. Repeated START condition 이발생하면 set 되며, STOP condition 이발 생하거나, set 된상태에서이 bit 에 1 을 write 하면 clear 된다. : Repeated START condition 이발생하지않았거나 STOP condition 이 발생하였음. 1: Repeated START condition이발생하였음 R TWIRXAK : Received Acknowledge Bit. ACK 구간에들어온 SDA line 의값을의미한다. : Acknowledge 수신 1: No Acknowledge 수신 TWI (Two Wired Interface) 21.4 Register Description Copyright 215, Advanced Digital Chips, Inc.

187 TWI Address Register(TWIADR) Address : x82_ : 8 R Reserved. - 7: RW (At only slave mode) x 7-bit slave address. TWI controller 의 device address 를나타낸다. [7:1] = Slave Address [] = Not mapped TWI Data Register (TWIDATA) Address : x82_18c 31 : 8 R Reserved. - 7 : RW TWI data : TWI 데이터를나타낸다. x Write - 송신데이터혹은접근할 device 의주소. Read - 수신데이터 TWI Baud-Rate Register (TWIBR) Address : x82_ : 8 R Reserved. - 7 : RW Baud-rate Value. TWIBR 3 xf TWI Baud-Rate 1 Register (TWIBR1) Address : x82_ : 9 R Reserved. - 8 : RW Baud-rate 1 Value.. TWIBR1 xff * f = AMBA APB clock frequency PCLK *SCL = TWI transmission rate TWIBR f PCLK 7ns 3 f PCLK SCL (2TWIBR1 TWIBR 7) f PCLK TWIBR 7 TWIBR1 2SCL 2 ex) 만약 APB clock이 5MHz 이고, TWI transmission rate이 4Kbps이라면계산식은다음과같다. ( f = 5MHz, SCL = 4Kbps) PCLK 6 TWIBR 5MHz 7ns f PCLK 5MHz SCL 4Kbps 4 1 (2TWIBR 1 TWIBR 7) (2TWIBR ) TWIBR1 = 9 5 X 1 3 (TWIBR + 5) 4kbps 2-7ns: rise time, fall (fast mode, max) for the synchronization - 3cycle: low, high duty for the synchronization of ratio (2TWIBR 1 45) Register Description 21 TWI (Two Wired Interface) Copyright 215, Advanced Digital Chips, Inc.

188 f PCLK TWIBR <Baud-rate Register Setting Reference Table> TWIBR1 4Kbps 3Kbps 2Kbps 1Kbps 5Kbps 6Mhz 45(x2D) 5(x32) 75(x4B) 125(x7D) 275(x113) - 5Mhz 38(x26) 41(x29) 62(x3E) 14(x68) 228(xE4) - 48Mhz 37(x25) 39(x27) 59(x3B) 99(x63) 219(xDB) 459(x1CB) 33Mhz 26(x1A) 26(x1A) 4(x28) 67(x43) 15(x96) 315(x13B) 24Mhz 2(x14) 18(x12) 28(x1C) 48(x3) 18(x6C) 228(xE4) 12Mhz 12(xC) 7(x7) 12(xC) 22(x16) 52(x34) 112(x7) 6Mhz 7(x7) 2(x2) 4(x4) 9(x9) 24(x18) 54(x36) Mhz 11(xB) 6(x6) 11(xB) 2(x14) 48(x3) 15(x69) Mhz 7(x7) 1(x1) 3(x3) 8(x8) 22(x16) 5(x32) * Above table can bear some errors. TWI baud rate 설정은 data setup time, hold time을확보하기위해서 scl의 LOW 구간은 scl의 HIGH구간이상의값을설정해야한다. EX) 5 Mhz, 5kbps 에서 scl의 LOW은 TWIBR (38) + TWIBR1 (479) 이다. 이때, scl 의 LOW 구간은 517(x25) 가아닌 17(x11) 이된다. ( TWIBR + TWIBR1 은 5이넘어서는안된다.) 이같은경우, data setup time, hold time에대하여확보할수없기때문에정상적인동작이이루어지지않는다. data setup time, hold time을확보하기위해서는최소 TWIBR 설정이상의 LOW구간이필요하기때문이다. * TCF interrupt. tcf_irq interrupt 신호는데이터전송의끝에발생하는신호이다 (1-byte). 이신호는 SCL 라인의 9 번 toggle 후에나타난다.(TCIE(Confirm Transfer complete bit )). SDA SCL tcf_irq twi_irq Figure Tcf interrupt wave form 3cycle 1cycle 4cycle Clk SCL N+1 cycle 3cycle TWIBR + TWIBR1 High edge (N+4 cycle) TWIBR1 Low edge (1cycle) Low Figure SCL Hold wave form High * 최소 high edge 구간은 4cycle 이다. 최대 high edge 구간은 4-cycle + α. (TWI 가 master Mode 로동작할경우, slave 측에서 SCL 라인을 low 로 hold 하기때문이다 ) TWI (Two Wired Interface) 21.4 Register Description Copyright 215, Advanced Digital Chips, Inc.

189 22 SOUND MIXER 22.1 Features - 4-CH. Mixing - Re-Sampler - Gain Controller - 32-Depth Buffer for each channel - 1-CH PWM output for Stereo or 2-CH PWM output for mono (1-CH Digital Modulator) 22.2 Block Diagram Interpolation Nearest-neighbor Linear BUFFER (FIFO) RE- SAMPLER GAIN CONTROL GAIN CONTROL IN- OUT IN-1 BUS INTERFACE (APB) IN-2 IN-3 Figure 22-1 Mixer Block Diagram Features 22 Sound Mixer Copyright 215, Advanced Digital Chips, Inc.

190 Low Pass Filter for Digital Modulator 22pF.47uF/16V 2K 27K - + Figure 22-2 Low pass filter for digital modulator 22.4 Sound Mixer clock clk16_ clk16_1 clk15 clk25 clk45 clk5 clk256 main osc clk dm_clk_sel[2:] dm_clk_div_val[3:] 1/1~ 1/16 g MCLK Figure 22-3 Sound Mixer Pre-Scaler Sound Mixer Clock Figure 22-3 에나타낸바와같이, MCLK 에대한 8 개의가능한소스가있다. 선택된클럭은추가로음향 믹서모듈가기전에 1 ~ 1/16 까지모든비율로분할될수있다 ( 4.2 Clock control 참조 ) Sound Mixer 22.3 Low Pass Filter for Digital Modulator Copyright 215, Advanced Digital Chips, Inc.

191 Mixer Block Diagram Mixter_regif Mixter_IN- irq [] BUFFER (fifo) QUANTIZE RE-SAMPLE GAIN CONTROL Mixter_IN-1 irq [1] BUFFER (fifo) QUANTIZE RE-SAMPLE GAIN CONTROL Mixter out AMP_ctrl PWM_P [] APB BUS INTERFACE (regif) irq [2] Mixter_IN-2 BUFFER (fifo) QUANTIZE RE-SAMPLE GAIN CONTROL MIXER CORE GAIN CONTROL Digital modulator PWM PWM_P [] PWM_N [1] PWM_N [1] MONO MONO STEREO Mixter_IN-3 irq [3] BUFFER (fifo) QUANTIZE RE-SAMPLE GAIN CONTROL Figure 22-4 Sound Mixer output diagram * Sound mixer 는 4ch input(in~3) 이존재하고, 1ch output(out_2) 이존재한다. Figure 22-4 에도시된바와같이 IN~3 그리고 out 이존재하고 PWM_P, N 두개를사용하면 mono 출력이고 4 개를사용하면, stereo 출력이다 Mixer Block Diagram 22 Sound Mixer Copyright 215, Advanced Digital Chips, Inc.

192 Register Description Mixer Control Register (MIXER_ CON) Address: xa2_1c, xa2_1c1, xa2_1c2, xa2_1c3 (IN- ~ IN-3) 31 : 29 R Reserved - 28 R/W Method of interpolation x : Nearest-neighbor 1: Linear 27 : 25 R Reserved - 24 : 16 R/W Step for re-sampling xff N = (( InFs * 256 ) / OutFs ) 1, (N=~511) 15 : 1 R Reserved - 9 : 8 R/W Out selection x 1 : Out 7 : 4 R/W Mode x : Unsigned stereo 8-bit PCM 1: Unsigned mono 8-bit PCM 1: Signed stereo 8-bit PCM 11: Signed mono 8-bit PCM 1: Unsigned stereo 16-bit PCM 11: Unsigned mono 16-bit PCM 11: Signed stereo 16-bit PCM 111: Signed mono 16-bit PCM 1xxx: Reserved 3 R/W DMA request x : Disable 1: Enable 2 R/W Interrupt x : Disable 1: Enable 1 R/W L/R swap x : Disable 1: Enable R/W Active x : Disable 1: Enable Sound Mixer 22.6 Register Description Copyright 215, Advanced Digital Chips, Inc.

193 Address: xa2_1ca (OUT) 31 : 1 R Reserved - R/W Active x : Disable 1: Enable Mixer Volume Register (MIXER_VOL) Address: xa2_1c4, xa2_1c14, xa2_1c24, xa2_1c34, xa2_1ca4 (IN- ~ IN-3, OUT) 31 : 16 R Reserved - 15 : 8 R/W Right gain (±.5dB) xff xff(db) ~ x8(-63.5db), x7f~x(- db) 7 : R/W Left gain (±.5dB) xff(db) ~ x8(-63.5db), x7f~x(- db) xff Mixer Buffer Status Register (MIXER_BST) Address: xa2_1c8, xa2_1c18, xa2_1c28, xa2_1c38 (IN- ~ IN-3) 31 : 6 R Reserved - 5 : R Buffer count value (Empty) ~ 32(Full) x Mixer Data Register (MIXER_DAT) Address: xa2_1cc, xa2_1c1c, xa2_1c2c, xa2_1c3c (IN- ~ IN-3) 31 : R/W PCM data Mixer Out Register (MIXER_OUT) Address: xa2_1cac (OUT) 31 : 1 R/W Reserved - 9 : 8 R/W Step for over-sampling x : x1 1: x2 1: x4 11: x8 7 : 4 R/W Sine wave generation (For test) x : Disable otherwise: Enable 3 : 2 R/W PWM modulation x : Class-AD single side modulation 1: Class-AD double side modulation 1: Class-BD single side modulation 11: Class-BD double side modulation 1 : R/W Noise transfer function x : Disable 1: 4th-order FIR filter 1: 5th-order FIR filter 11: 5th-order optimal FIR filter Mixer Interrupt Status Register (MIX_IST) Address: xa2_1cc 31 : 7 R Reserved - 6 : 4 R Reserved - 3 R IN-3 interrupt x 2 R IN-2 interrupt x 1 R IN-1 interrupt x R IN- interrupt x Register Description 22 Sound Mixer Copyright 215, Advanced Digital Chips, Inc.

194 APB adstar-l 23 ADC CONTROLLER adstar-l 은 1KSPS 12-bit SAR ADC 를내장한다. 권장동작 frequency 는 1.2Mhz 이다. Conversion cycle 은 ADC input clock 으로 15cycle 이다. adc_irq Interrupt Interface APB Interface Trigger Control Logic ADC Controller 1 Trigger input 3 adc_dsel adc_clk adc_start adc_en adc_ad adc_eoc Trig Timer Trig Timer1 Trig GPIO A Trig GPIO B Trig GPIO C Trig GPIO D Trig GPIO E Trig GPIO F dma_clr dma_req dma_lreq DMA Interface FIFO Figure 23-1 ADC Block Diagram 23.1 Features - Various SOC source select - Continuous Mode support - 4-depth FIFO - DMA Mode (in FIFO Mode) - 4 channel input ADC Controller 23.1 Features Copyright 215, Advanced Digital Chips, Inc.

195 Register Description ADC Control Register (ADCCTRL) Address : xa2_38 31 : 16 R Reserved - 15 R/W External Trigger Enable 1: External Trigger enable : External Trigger disable 14 : 12 R/W External Trigger Source Select Choose trigger source for SOC : Timer 1: Timer 1 1: GPIOA[7] 11: GPIOB[] 1: GPIOC[7] 11: GPIOD[7] 11: GPIOE[7] 111: GPIOF[7] 11 R/W Periodic Mode Selection : Normal Operation Mode (1 pulse SOC Generation) 1: Periodic Mode (Continuous SOC Generation) 1 R/W DMA Last Transfer FIFO Mode 이고, DMA Mode 일때, 이 bit 를 1 로 set 하면, DMA Last Request 를수행. Request가발생하면 clear 9 R/W DMA Mode Enable FIFO Mode 일경우, 이 bit 를 1 로 set 하면, FIFO 가 full 이될때마다 DMA 전송을요청. DMA Last Request가발생하면 clear 8 R/W FIFO Mode 1: Using FIFO : NOT using FIFO 7 : 5 R/W ADC Channel Selection : ADCIN 1: ADCIN1 1: ADCIN2 11: ADCIN3 4 : 2 R/W ADC Source clock selection : APB Clock / 2 1: APB Clock / 4 1: APB Clock / 8 11: APB Clock / 16 1: APB Clock / 32 11: APB Clock / 64 11: APB Clock / : APB Clock / 256 * Sampling 주기는 ADC Source clock의주기의 12배가된다.. 1 R/W ADC Start Conversion(STC) 1로설정하면 SOC 발생. ADC Clock으로한주기가지나면 clear. R/W ADC Enable : ADC Disable 1: ADC Enable ADC Data Register (ADCDATA) Address: xa2_ : 12 R Reserved - 11 : R 12-bit ADC data x ADC FIFO Register (ADCFIFO) Address: xa2_ : 12 R Reserved - 11 : R In case of ADC FIFO Mode 12-bit ADC FIFO Data Register Description 23 ADC Controller Copyright 215, Advanced Digital Chips, Inc.

196 ADC Status Register (ADCSTAT) Address : xa2_38c 31 : 9 R Reserved - 8 R EOC status : EOC have not occurred. 1: an EOC has occurred. EOC가발생했을때, 1 의상태가되며, 이 bit를읽으면 Clear 된다. 7 R EOC Occur Check [START/EOC pair] ADC START and ADC EOC pair latch 를선택했을경우, 유효하며, ADC START 이후 ADC EOC 가발생하지않았을경우 1 의상태가된다. EOC가발생하거나, EOC Reset를 set 했을경우, 의상태가된다.. 6 R FIFO Overflow 1 이면 FIFO 가 Overflow 되었다는의미이며, Overflow 상태에서새로운데이 터가들어오면, 오래된데이터부터삭제되고, 새로운데이터가 FIFO 에쌓이 게된다. 5 R FIFO Full 1: FIFO is Full : FIFO is not Full 4 R FIFO Empty 1 1: FIFO is Empty : FIFO is not empty 3 : 1 R FIFO Level (~4) R ADC Data Ready 1: ADC Data is valid : ADC Data is not ready ADC Control Register2 (ADCCTRL2) Address: xa2_ : 5 R Reserved - 4 R/W EOC Reset : Disable 1: Enable ADC START and ADC EOC pair latch 를선택했을경우, 유효하며, ADC START 이후 ADC EOC 가발생하지않을경우, Controller 의상태를 IDLE 상태로만드는데사용된다. 3:1 R Reserved - R/W Latch Select 일경우, ADC START 이후 EOC 가발생할때마다 data 를 latch 하며, 1 일경우 ADC START 이후처음 EOC 가발생했을때만 data 를 latch 하 고, EOC 가지속적으로발생하더라도, 다음 ADC START 이후 EOC 가발생 할때까지, data 를 latch 하지않는다 ADC Controller 23.2 Register Description Copyright 215, Advanced Digital Chips, Inc.

197 24 TFT LCD CONTROLLER 24.1 Introduction LCD Controller 는 Register, Timing Generation, Address Generation, FIFO Control, Sync Control, Request Generation, External Sync Detector 블록등으로구성되어있다. LCD Controller 는 Screen Refresh 를위하여, 프레임메모리의데이터를읽어오기위하여 Request Generation, Request Address Generation, FIFO Control 블록이있으며, VGA 모드를위한 Sync Control 블록이있다. Timing Generation 블록은 LCD Controller 의전반적인 Timing 을제어한다. LCD 컨트롤러는 synchronous LCD 인터페이스를처리한다. LCD 디스플레이는 provides timing 과 data 를일정하게 graphics refresh 한다. 또한, 프로그래밍타이밍제어를이용하여풀컬러디스플레이의유형과크기를다양하게지원한다. 그래픽스데이터는처리되어프레임버퍼에저장된다. 프레임버퍼는시스템의연속적인메모리블록이며, 내장된엔진 DMA 은외부 LCD 장치에그래픽데이터를공급한다. DMA 엔진은외부 LCD 패널프레임버퍼로부터의데이터의일정한흐름을제공한다. 또한, CPU 는액세스 APB 버스를통해레지스터를판독및기록하기위해제공된다. 디스플레이출력을위한프레임데이터는 AHB 인터페이스를통해메모리로부터패치된다. 타이밍발생블록은정확한외부타이밍생성을담당한다. APB Bus REG Timing Gen SYNC Ctrl VSYNC HSYNC DispEn Interrupt Ctrl FIFO Ctrl Graphics data from frame buffer AHB Bus DMA FIFO RGB data[23:] DOTCLK Figure 24-1 LCD Controller Block Diagram DOTCLK 24.2 Features General features of the LCD Controller include: - Supports up to 24-bit data output; 8 bits-per-pixel (RGB). - Supports up to SVGA(8x6) resolution. - Supports TFT color displays. - Internal Color Bar Generator - Programmable timing for different display panels. - AHB bus master interface to access frame buffer. - A page-flip double buffering mechanism, synchronizing read and write access to system memory, to prevent tearing effects Introduction 24 TFT LCD Controller Copyright 215, Advanced Digital Chips, Inc.

198 Functional Description LCD clock source and divider 다음그림 Figure 24-2 는 LCD 클럭과 lcd_clk_sel 및 lcd_clk_div_val 제어비트에의한클럭소스 컨트롤러를보여준다. ( Section4.2, Clock control 참고 ). DOTCLK 는 LCD 디스플레이에의해사용되는연속한기준클럭이사용으로전환된다. lcd_clk_sel[2:] clk16_ lcd_clk_div_val[3:] clk16_1 clk15 clk25 clk45 clk5 clk256 main osc clk 1/1~ 1/16 LCD Controller DOTCLK g SPI 9bit clk LCDCON[22] Figure 24-2 LCD Clock S B A Z Z GP5.6 (DOTCLK) #9 A Double buffering 적어도 2 개의프레임버퍼를갖는것이바람직하다 (front buffer, back buffer). 수직동기가발생될때까지 flip 디스플레이지연이발생한다. 디스플레이되고완료되기전에다시버퍼에기록하지않게끔지연을보장할필요가있다이러한동기화는이중버퍼링을사용할때 tearing 영향을피할수있다는것을의미한다. Base Address Base Address Front buffer Write Graphics data Front buffer LCD Controller LCD Controller Base Address 1 Flip at vertical syn Base Address 1 Write Graphics data Back buffer Back buffer Figure 24-3 Flipping Structure with double buffering LCD 제어레지스터 (LCDCON) 의 [19] 번비트가설정되어있는경우더블버퍼링을사용할수있다. 이 경우, Flip Control register 의소프트웨어플립요청의설정은각 LCD 수직동기에서더블버퍼비디오 디스플레이를만들수있다. 선택적으로, 쿼드버퍼링까지각각의프레임버퍼의시작주소를포함하는 베이스어드레스레지스터세트를통해구성된다 (LCDBADR, LCDBADR1, LCDBADR2, LCDBADR3 registers). 프레임버퍼의수는 Flip Control register [7:6] 에의해결정된다 TFT LCD Controller 24.3 Functional Description Copyright 215, Advanced Digital Chips, Inc.

199 LCD Interrupt LCD 컨트롤러는, 수직동기시작시인터럽트를생성한다. 인터럽트는이중버퍼링된영상을생성할때, 기본주소를재프로그램하는데사용될수있다 HSYNC, VSYNC 수평라인에서모든픽셀은 LCD 에전달되고, HSYNC 의타이밍이 LCDHT 을통해프로그램된다. LCDHS 및 LCDHA 은등록후, HSYNC 는전환한다. HSYNC 는 DOTCLK 의상승또는하강 edge 에동기 하도록프로그램될수있다. 이것은 DOTCLK 반전시킴으로써 active 된다 ( 극성도프로그래밍할수있다 ). 프레임의모든라인들이 LCD 로전송되고, VSYNC 의타이밍이 LCDVT, LCDVS 및 LCDVA 레지스터를 통해프로그램을된후에 VSYNC 는토글한다. VSYNC 는 DOTCLK 의상승또는하강 edge 에동기하도록프로그램될수있다. 이것은 DOTCLK 반전시킴으로써 active 된다 ( 극성도프로그래밍할수있다 ). 타이밍구성에대한자세한내용은 Section , VGA Timings, 참고. 아래의그림은 64 X 48 해상도에대한 Horizontal Total, Sync Start(End), Active Start(End), Vertical Total, Sync Start(End), Active Start(End) 레지스터 setting 에따라생성되는 Sync. Signal Timing 이다. HSYNC, VSYNC 신호는 Default Low active 이며, LCD Control Register [5:4] Bit 를이용하여 active polarity 를제어할수있다. Horizontal, Vertical Active 신호는 High active 이다. Figure 24-4 LCDC Horizontal, Vertical Sync / Active Signal Timing Functional Description 24 TFT LCD Controller Copyright 215, Advanced Digital Chips, Inc.

200 DISPEN (Hor.active) 이신호는데이터가데이터버스에서유효하고, 외부 LCD 디바이스를시그널링하기위해사용된다 (R[7:], G[7:], B[7:]). DISPEN 는 DOTCLK 의상승또는하강 edge 에동기화할때프로그래밍할수있다. 이것은 DOTCLK 반전시킴으로써 active 된다 VGA Timings The following timing parameters can be programmed: - Horizontal front and back porch - Horizontal synchronization pulse width - Number of pixels per line - Vertical front and back porch - Vertical synchronization pulse width - Number of lines per frame Table 24-1 Typical VGA Timings Format Dot Clock (MHz) Active Video THd Horizontal (in Pixels) Front Sync Porch Pulse THf THp Back Porch THb Active Video TVd Vertical (In Lines) Front Sync Porch Pulse TVf TVp QVGA 24x WQVGA 48x Back Porch TVb VGA 64X48, 6Hz WVGA 8x48 SVGA 8x6, 6Hz Horizontal Timing registers Horizontal Synchronization 펄스폭 (THp), Horizontal Front Porch(THf) 주기, Horizontal Back Porch(THb) 주기, Pixels-Per-Line(THd) 는 LCDHT, LCDHS, LCDHA 레지스터로제어한다. 타이밍구성은다음식을사용한다 : LCDHT[1:] = THf + THp + THb + THd LCDHS[26:16] = THf LCDHS[1:] = THf + THp LCDHA[26:16] = THf + THp + THb LCDHA[1:] = THf + THp + THb + THd hor_total (total pixels per line) hor_act_start hor_act_end HorActive HorSync Start End / Start hor_sync_end hor_sync_start 2 24 TFT LCD Controller 24.3 Functional Description Copyright 215, Advanced Digital Chips, Inc.

201 Figure 24-5 Horizontal Timing Vertical Timing registers Vertical Synchronization 펄스폭 (TVp), Vertical Front Porch(TVf) 주기, Vertical Back Porch(TVb) 주기, Lines- Per-Frame(TVd) 는 LCDVT, LCDVS, LCDVA 레지스터로제어한다. 타이밍구성은다음식을사용한다 : LCDVT[1:] = TVf + TVp + TVb + TVd LCDVS[26:16] = TVf LCDVS[1:] = TVf + TVp LCDVA[26:16] = TVf + TVp + TVb LCDVA[1:] = TVf + TVp + TVb + TVd ver_total (total lines per frame) ver_act_start ver_act_end VerActive VerSync Start End / Start ver_sync_end ver_sync_start Figure 24-6 Vertical Timing 아래의표는몇가지일반적인디스플레이해상도에대한설정이다. Table 24-2 Register Values for VGA timing Register LCDBA LCDHT LCDHS LCDHA LCDVT LCDVS LCDVA LCDCON 64x48 (8x525) A32 2D 7D 2B2B 8 8x6 (156x628) 42 23C A 1A272 8 * Register Value 는 Hexa-Decimal 임. * Memory Read Request 는 FIFO 의 Half Position 을기준으로함. * Screen Display Mode 는 Normal operation 을기준으로함. * H(V)SYNC. Output Polarity 는 Low Active 기준임. * H(V)SYNC. Output Select 는 Internal block 에서생성된 SYNC. Output 을기준으로함 Functional Description 24 TFT LCD Controller Copyright 215, Advanced Digital Chips, Inc.

202 Color Bar Test Pattern Generation Block LCD Control Register [1:] Bit 이 1 일때 Color Bar Test Pattern Generation 블록은활성화되고, 프레임메모리의데이터를읽어오기위한 Request Generation, Address Generation, FIFO Control 블록은비활성화된다. Video Data Mux & Serialization 블록에서 Color Bar Pattern Video Data 가선택되어출력된다. Color Bar Pattern 은왼쪽부터검정색, 흰색, 노란색, 청록색, 녹색, 보라색, 빨간색, 파란색순으로생성되며, 해상도에상관없이균일한분포를갖는다. 만약, Active 구간이정확하게 8 의배수가되지않는다면화면의오른쪽검정색이출력될수있다 Register Description LCD Controller Register Summary Table 24-3 LCD Controller Registers Table Absolute Address Register Name Description x82_244h LCD Horizontal Total Register (LCDHT) Horizontal Active 와 Blank 구간을포함한 Horizontal Total Scan Value x82_248h LCD Horizontal Sync. Start / End Register (LCDHS) Horizontal Sync 구간의 Start(End) value x82_24ch LCD Horizontal Active Start / End Register (LCDHA) Horizontal Active 구간의 Start(End) value x82_241h LCD Vertical Total Register (LCDVT) Vertical Active 와 blank 구간을포함한 Vertical Total scan value x82_2414h LCD Vertical Sync. Start/End Register (LCDVS) Vertical Sync 구간의 Start(End) value x82_2418h LCD Vertical Active Start/End Register (LCDVA) Vertical Active구간의 Start(End) value x82_241ch LCD Display Current X / Y Position Register (LCDXY) Horizontal/Vertical Counter value x82_242h LCD Status Register (LCDSTAT) LCD controller 의 Sync 상태 x82_2424h LCD Control Register (LCDCON) LCD 의 Display, Sync, Memory, FIFO 모드를제어 x82_243h LCDC Base Address Frame buffer 의시작위치를지정 x82_2434h LCDC Base Address 1 Frame buffer 의시작위치를지정 x82_2438h LCDC Frame sync. Counter Frame Sync 가발생할때마다 count x82_243ch LCD Horizontal Width Horizontal width를결정 x82_244h LCD Flip Command Process flip operation x82_2444h LCDC Base Address 2 Frame buffer 의시작위치를지정 x82_2448h LCDC Base Address 3 Frame buffer 의시작위치를지정 LCD Horizontal Total Register(LCDHT) Horizontal Active 와 Blank 구간을포함한 Horizontal Total scan value. Address : x82_244h 31 : 11 R Reserved - 1 : R/W Horizontal Total The value loaded into this field is the total pixel counts per line. h TFT LCD Controller 24.4 Register Description Copyright 215, Advanced Digital Chips, Inc.

203 LCD Horizontal Sync. Start / End Register(LCDHS) Horizontal Sync 구간의 Start(End) value. Address : x82_248h 31 : 27 R Reserved - 26 : 16 R/W Horizontal Sync Start h The value loaded into this field is the value of horizontal sync period start by the horizontal counter 15 : 11 R Reserved - 1 : R/W Horizontal Sync End The value loaded into this field is the value of horizontal sync period end by the horizontal counter h LCD Horizontal Active Start / End Register(LCDHA) Horizontal Active 구간의 Start(End) value. Address : x82_24ch 31 : 27 R Reserved - 26 : 16 R/W Horizontal Active Start h The value loaded into this field is the value of horizontal active period start by the horizontal counter 15 : 11 R Reserved - 1 : R/W Horizontal Active End The value loaded into this field is the value of horizontal active period start by the horizontal counter h LCD Vertical Total Register(LCDVT) Horizontal Active 와 Blank 구간을포함한 Horizontal Total scan value. Address : x82_241h 31 : 11 R Reserved - 1 : R/W Vertical Total The value loaded into this field is the value of the total vertical line counts. h LCD Vertical Sync. Start / End Register(LCDVS) Horizontal Sync 구간의 Start(End) value Address : x82_2414h 31 : 27 R Reserved - 26 : 16 R/W Vertical Sync Start h The value loaded into this field is the value of vertical sync period start by the vertical counter 15 : 11 R Reserved - 1 : R/W Vertical Sync end The value loaded into this field is the value of vertical sync period end by the vertical counter h Register Description 24 TFT LCD Controller Copyright 215, Advanced Digital Chips, Inc.

204 LCD Vertical Active Start / End Register(LCDVA) Horizontal Active 구간의 Start(End) value Address : x82_2418h 31 : 27 R Reserved - 26 : 16 R/W Vertical Active Start h The value loaded into this field is the value of vertical active period start by the vertical counter 15 : 11 R Reserved - 1 : R/W Vertical Active end The value loaded into this field is the value of vertical active period end by the vertical counter h LCD Display Current X / Y Position Register(LCDXY) display Current X Position 레지스터는 Read Only 레지스터이며, Horizontal Counter 값을반영하고있다. Display Current Y Position 레지스터도 Read Only 레지스터이며, Vertical Counter 값을반영하고있다. Address : x82_241ch 31 : 27 R Reserved - 26 : 16 R The value loaded into this field is the value of the vertical counter. h 15 : 11 R Reserved - 1 : R The value loaded into this field is the value of the horizontal counter. h LCD Status Register(LCDSTAT) LCD Status 레지스터는 Read Only 이며, LCD controller 의 Sync 상태를읽어볼수있다. Horizontal Sync 와 Vertical Sync 신호는, Control Register [21:2] Bit 이 일때, 둘다 Low active 상태를 갖는다. Horizontal / Vertical Active 는신호는 Control Register [21:2] Bit 에상관없이 High active 상태를 갖는다. Address : x82_242h 31 : 7 R Reserved. - 6 R Current Display Bank b : BANK, 1 : BANK1 5 : 4 R Reserved. 1b 3 R Vertical Active (active high) b 2 R Vertical Sync 1b 1 R Horizontal Active (active high). b R Horizontal Sync 1b TFT LCD Controller 24.4 Register Description Copyright 215, Advanced Digital Chips, Inc.

205 LCD Control Register(LCDCON) LCD Control 레지스터는 LCDC 의동작모드제어를위해사용된다. * Frame Memory Bank <n> Ping-Pone Enable : Graphic Engine Flip Command 에의한 Frame Memory Bank 전환을비활성 / 활성시킨다. - 비활성시 LCD Frame Memory Bank 는고정된다. - 활성시 Graphic Engine Flip Command 에의해 LCD Frame Memory Bank 전환이이루어진다 Address : x82_2424h 31 : 25 R Reserved - 24 R/W Software Reset. 1b = Normal operation 1=Reset,. 23 R Reserved - 22 R/W Invert DOTCLK output - = Normal 1 = Inverted 21 R/W HSYNC. Output Polarity. b = Low Active 1 = High Active 2 R/W VSYNC. Output Polarity. b = Low Active 1 = High Active 19 R/W Frame buffer double buffering. b = Disabled 1 = Enabled 18 : 17 R/W FIFO Request Control(Total depth : 256) b : one half request(128) 1 : one fourth request(64) 1 : one eighth request(32) 11 : Don t use 16 : 15 R Reserved b 14 R/W When RGB 32bit mode, Input data sequence b : = drgb 1 = RGBd 13 : 12 R/W Frame data format b = undefined. 1 = 16bpp, 5:6:5 mode, RGB 16bit 1 = 24bpp, 8:8:8 mode, RGB 32bit 11 = undefined. 11 : 1 R Reserved - 9 : 8 R Bus Burst Length Select. - 1 : 16burst 1 : 32 burst : Max burst(256 burst) 7 : 5 R Reserved - 4 R/W Use hwidth register b 3 : 2 R/W Reserved - 1 : R/W Screen Display Mode Control. =Normal operation. 1=Regular Pattern Generation 1x=Screen off b LCD Base Address Register (LCDBADR) Address : x82_243h 31 : 2 R/W Base Address h This is the start address of the frame data in memory and is word aligned. Only SDRAM area is available 1 : R Reserved Register Description 24 TFT LCD Controller Copyright 215, Advanced Digital Chips, Inc.

206 LCD Base Address 1 Register (LCDBADR1) Address : x82_2434h 31 : 2 R/W Base Address 1 h This is the start address of the frame data in memory and is word aligned. Only SDRAM area is available 1 : R Reserved LCD Frame Sync. Count Register (LCDFRAMECNT) Address : x82_2438h 31 : R/W Frame Sync. Count h LCD Horizontal Width Register (LCDHWIDTH) Address : x82_243ch 31 : 12 R Reserved - 11 : R/W Horizontal Width 4h LCD Flip Control Register (LCDFCTL) Address : x82_244h 31 : 8 R Reserved - 7 : 6 R/W Select the number of Frame buffer 1b 1 : use 2 Frame buffers 1 : use 3 Frame buffers 11 : use 4 Frame buffers 5 R Reserved - 4 R/W Software flip enable 3:2 R Current Frame buffer number 1 R Reserved - R/W Software flip request 1 : set : cleared by H/W automatically LCD Base Address 2 Register (LCDBADR2) Address : x82_2444h 31 : 2 R/W Base Address 2 h This is the start address of the frame data in memory and is word aligned. Only SDRAM area is available 1 : R Reserved LCD Base Address 3 Register (LCDBADR3) Address : x82_2448h 31 : 2 R/W Base Address 3 h This is the start address of the frame data in memory and is word aligned. Only SDRAM area is available 1 : R Reserved TFT LCD Controller 24.4 Register Description Copyright 215, Advanced Digital Chips, Inc.

207 25 JPEG DECODER 25.1 Features - 64x48 4:2: format 1frame(lena image) 35ms 안에 decoding 가능 - ISO base line JPEG decoder - Only support typical Huffman table defined in annex K of standard. - Supports YCbCr 4:2:2 format - Supports YCbCr 4:2: format - Maximum resolution:248x Block Description FIFO Fill Request IRQ JPEG decoder end IRQ Address information JPEG Decoder AHB BUS Control RGB CSC INTERFACE Sync FIFO (64x32) Sync FIFO (64x32) Decompressed data(ycbcr) JPEG Decoder Core Sync FIFO (64x32) Compressed data AHB BUS HOST/DMA Figure 25-1 JPEG Decoder Block Diagram JPEG Decoder 내부에는 JPEG image data, decompressed data(ycbcr) 및데이터 MCU(Minimum Code Unit) 에대한 address information 을저장하기위한 64x32 FIFO 가 3 개가존재하며, 3 개의 FIFO 의 level 은 JDFCON Register 의 [6:] 의 setting 값에의해서결정된다. JPEG Decoder 는동작시 JPEG image data 의요청을위한 level 방식의 FIFO fill request IRQ 를발생시킨다. 이 IRQ 는 JDCTRL 에서설정한 FIFO level 만큼데이터가 FIFO 내부에차있을때까지유지되며, FIFO level 을넘어가게되면자동으로 clear 된다. 그리고 FIFO 에데이터가 level 보다작게되는순간다시 IRQ 는발생된다. JPEG Decoder 는 JPEG image 내의 EOI(End Of Image) maker 를 decode 하면 decoding 이끝났음을알리는 JPEG decoder end IRQ 를발생한다. 이 IRQ 는 JPEG image capturer 의 interrupt source 가되며, JPEG image capturer 에서는마지막 MCU 의데이터를 memory 에저장할때이 IRQ 를사용하여 JPEG image capture IRQ(JICIRQ) 를생성한다. JICIRQ 는 JPEG decoder end IRQ 를 clear 하기전까지유지된다 Features 25 JPEG Decoder Copyright 215, Advanced Digital Chips, Inc.

208 AHB Slave Interface JPEG Decoder 64x32 FIFO Memory Binary Tree Look Up Table Memory JPEG Decoder Controller & FSM Data Ready VLD ( Huffman Decoding, Run-length Code) Data Ready IZZQ (Inverse ZigZag Scaner, Inverse Quantizer) Data Ready DRB (Data Reformat Block) 64x32 FIFO (Address info) Data Ready IDCT Data Ready MDF (Macro Block Deformater) Ready Data Data Ready 64x32 FIFO (YCbCr Data) FIFO Level Information Figure 25-2 Decoder Core Block Diagram JPEG Decoder 의내부의각각의연산블록들은다음단계의연산블록에서생성하는 ready 신호에의해서출력데이터 transaction 을결정한다. 외부 System 요건에의해서 JPEG image input stream 이멈추거나, 또는 out data 가 JDWCON 에설정된 level 만큼 YCbCr FIFO 에채워지면 JPEG decoder 는 wait 상태가된다. 그러나 input data stream 이재개되거나 out data 가설정된 level 이하로될경우멈추었던시점부터다시 decoder 는동작하게된다 JPEG Decoder 25.2 Block Description Copyright 215, Advanced Digital Chips, Inc.

209 Functional Description Decoder Start JPEG Decoder Enable (JDENA=x1) FIFO Clear Enable (JDFCLR = x8) FIFO Clear Disable (JDFCLR = x) JPEG Decoder FIFO Fill Request IRQ Service Routine Start Read FIFO Level (FIFO Level = JDDFST) 64 - JDDFST > Setting FIFO Level NO FIFO Level & Input Bit Format Setting (JDFCTRL=User Dependent Value) for(i<= ;i< Setting FIFO Level ;i++) {JDIDF = *JPEG Image data Source Addr ++} FIFO Waiting Level Setting (JDWCTRL =x8) JPEG Decoder FIFO Fill Request IRQ Service Routine END Huffman Table Setting Q Scale Factor Setting (JDQSC =x4) Decoding Start Command (JDCOMC=User Dependent Value) JPEG Decoder End IRQ Clear (JDCOMC = x4) FIFO Clear Enable (JDFCLR = x8) FIFO Clear Disable (JDFCLR = x) FIFO Fill IRQ Service Routine (JPEG Image Transfer) Service Routine Clear END All Source Image Transmit? Decoder END Functional Description 25 JPEG Decoder Copyright 215, Advanced Digital Chips, Inc.

210 Register Description JPEG Decoder Quantization Scale Control Register (JDQSC) Address: xa4_23c Bit R/W Description Default 31 : 12 R Reserved. 11 : W JPEG Quantization Scale Control h JPEG Image header 에포함된 quantization table(q table) 값의 Scale 을조정. 64 를기준 으로큰값은 q table 값을증가시키며, 작은값은 q table 를감소시킨다. 64 이외의값 을설정하는경우설정값에따라이미지의왜곡이생길수있다. JPEG Decoder Command Control Register (JDCC) Address: xa4_24 Bit R/W Description Default 31 : 3 R Reserved. 2 W JPEG Decoder End IRQ Clear 1:End IRQ Clear :IDLE b JPEG Decoder end IRQ 는 JICIRQ 의 source 로사용되며, 이 bit 을 1 로설정하면 JPEG decoder end IRQ 와 JICIRQ 는동시에 clear 된다. 이 bit 은 1 로설정후다음 clock 에서 자동적으로 으로 clear 된다. *JPEG Decoder 가다음 Image 를 Decoding 하기위해서 JPEG decoder end IRQ 는반 드시 clear 되어야한다 1 W DECODING IMAGE FORMAT 1:YCBCR 42 :YCBCR 422 W Decoding Start 1:Decoding Start :IDLE JDENA Register 의 번 bit 이 1 로 setting 된후이 bit 을 1 로 setting 하면 decoder 가동 작한다. - 이 bit 이 1 이되면최초로 JPEG decoder FIFO fill request IRQ 가발생하게된다. -Decoder 가 image decoding 을시작한후자동 Clear 된다.. JPEG Decoder Y DC Node Table (JDYDCNT) Address: xa4_8 ~ xa4_83 Bit R/W Description Default 31 : 18 R Reserved. 17 : W Y DC Node Table for Huffman Decoding h Huffman Decoding 시 Y DC 2 진 tree 를위한 node table JPEG Decoder Y DC Leaf Table (JDYDCLT) Address : xa4_c ~ A4_C3 Bit R/W Description Default 31 : 8 R Reserved - 7 : W Y DC LEAF Table for Huffman Decoding Huffman Decoding 시 Y DC 2 진 tree 를위한 leaf table JPEG Decoder Y AC Node Table (JDYACNT) Address : xa4_28 ~ A4_2A88 Bit R/W Description Default 31 : 18 R Reserved - 17 : W Y AC Node Table for Huffman Decoding - Huffman Decoding 시 Y AC 2 진 tree 를위한 node table b b JPEG Decoder 25.4 Register Description Copyright 215, Advanced Digital Chips, Inc.

211 JPEG Decoder Y AC Leaf Table (JDYACLT) Address : xa4_3 ~ A4_3288 Bit R/W Description Default 31 : 8 R Reserved - 7 : W Y AC LEAF Table for Huffman Decoding - Huffman Decoding 시 Y AC 2 진 tree 를위한 leaf table JPEG Decoder UV DC Node Table (JDUVDCNT) Address : xa4_48 ~ A4_483 Bit R/W Description Default 31 : 18 R Reserved - 17 : W UV DC Node Table for Huffman Decoding - Huffman Decoding 시 UV DC 2 진 tree 를위한 node table JPEG Decoder UV DC Leaf Table (JDUVDCLT) Address : xa4_5 ~ A4_53 Bit R/W Description Default 31 : 8 R Reserved - 7 : W UV DC LEAF Table for Huffman Decoding - Huffman Decoding 시 UV DC 2 진 tree 를위한 leaf table JPEG Decoder UV AC Node Table (JDUVACNT) Address : xa4_68 ~ A4_A88 Bit R/W Description Default 31 : 18 R Reserved - 17 : W UV AC Node Table for Huffman Decoding - Huffman Decoding 시 UV AC 2 진 tree 를위한 node table JPEG Decoder UV AC Leaf Table (JDUVACLT) Address : xa4_7 ~ A4_7288 Bit R/W Description Default 31 : 8 R Reserved - 7 : W UV AC LEAF Table for Huffman Decoding - Huffman Decoding 시 UV AC 2 진 tree 를위한 leaf table JPEG Decoder Status Register (JDSTAT) Address : xa4_8 Bit R/W Description Default 31 : 4 R Reserved - 3 R JPEG Decoder Finished b 2 R JPEG Decoder MCU Decoding b 1 R JPEG Decoder Header Parsing b R JPEG Decoder Ready b Register Description 25 JPEG Decoder Copyright 215, Advanced Digital Chips, Inc.

212 JPEG Decoder IRQ Status Register (JDIRQSTAT) Address : xa4_84 Bit R/W Description Default 31 : 3 R Reserved. - 2 R JPEG Decoder Timeout b 비정상적동작이나 Compressed data 가장시간입력되지않을경우내부 timer counter 에의해 timeout 이걸려자동으로 end IRQ 가발생되고상태를알려준다. Timeout 에의한종료일경우에도상태가초기화될수있도록 SW reset 및인터럽트 clear 등을해서다시재시작할수있게설정해주어야한다. 1 R JPEG Decoder FIFO Fill Request IRQ Compressed data FIFO 에 JDCTRL register 의 [6:] 에서설정한 level 만큼데이터가차 있지않으면인터럽트가발생한다. R JPEG Decoder End IRQ JPEG Decoder 의종료시점을나타낸다. JPEG decoder 에설정한만큼의 MCU 가 decoding 된후 JPEG EOF flag 가들어오면이 interrupt 는발생한다. * 이 interrupt 는 JPEG image capturer 으로인가되어 JICIRQ 의 source 로사용된다. b b JPEG Decoder Data FIFO Status Register (JDDFSTAT) Address : xa4_88 Bit R/W Description Default 31 : 7 R Reserved. - 6 : R Current FIFO Level Status h 현재의 compressed data FIFO level 을나타낸다. FIFO 에데이터를쓰는경우 current FIFO level status 가 x3fh 를넘어가면이후데이 터들은기존데이터를덮어쓰게되므로, x3fh 을넘어가지않게데이터를 Write 해야한 다 JPEG Decoder Enable Register (JDENA) Address : xa4_81 Bit R/W Description Default 31 : 1 R Reserved. - R/W JPEG Decoder Enable b JPEG Decoder 를 enable 시킨다. 이 bit 을 set 한후 JDCOMCON register 의 번 bit 를 set 하면 JPEG decoder 는 decoding 을시작한다 JPEG Decoder FIFO Clear Register (JDFCLR) Address : xa4_814 Bit R/W Description Default 31: 4 R Reserved. - 3 R/W FIFO Clear b 1:ALL FIFO Clear :IDLE 2 : R Reserved JPEG Decoder 25.4 Register Description Copyright 215, Advanced Digital Chips, Inc.

213 JPEG Decoder FIFO Control Register (JDFCON) Address : xa4_818 Bit R/W Description Default 31 : 1 R Reserved - 9 R/W Input data Format Selection b 1:Big Endian Format :Little Endian Format 8 : 7 R Reserved - 6 : R/W Compressed Data FIFO Threshold Level h Compressed data FIFO 의 threshold level 을설정. 이설정값만큼의데이터가 FIFO 에 없으면, FIFO fill request interrupt 가발생한다. 설정값은 FIFO Size(64) 보다작은값을사용해야한다 JPEG Decoder Waite Control Register (JDWCON) Address : xa4_81c Bit R/W Description Default 31 : 7 R Reserved - 6 : R WAITE FIFO Threshold Level 8h Decompressed data FIFO 의 LEVEL 을나타낸다. 설정값 * 8 만큼의데이터가 FIFO 에 남아있으면, decoder 는대기상태가되며, 설정값 *8 보다데이터가적은경우 decoder 는다시동작을하게된다. 설정값은최소 1, 최대 8 이되며설정값이작을 수록대기상태의빈도는늘어나게된다 JPEG Decoder Software Reset Register (JDSRST) Address : xa4_824 Bit R/W Description Default 31 : 1 R Reserved. - R/W Software Reset 1b 1:IDLE :Reset 잘못된데이터의인가로인한 JPEG Decoder 가이상상태에서동작할때강제로 decoder 를초기화한다. 이 bit 을 으로설정하여 decoder 를 reset 을시킨후다시 1 로설정을해야 decoder 를 동작시킬수있다 JPEG Decoder Version Information Register (JDVERINFO) Address : xa4_828 Bit R/W Description Default 31 : R/W JPEG Decoder Version JPEG Decoder CSC Base Address Register (JDCSCBASEADDR) Address : xa4_82c Bit R/W Description Default 31 : R/W JPEG Decoder RGB data Base address for transferring C2 h JPEG Decoder Stride Size Register (JDCSTRID) Address : xa4_83 Bit R/W Description Default 31 : R/W JPEG Decoder Stride size 4h crtc 에서설정한화면최대 vertical pixel size 로설정한다 Register Description 25 JPEG Decoder Copyright 215, Advanced Digital Chips, Inc.

214 JPEG Decoder RGB565 mode and Timeout count enable (JDCRGBTIMEOUT) Address : xa4_834 Bit R/W Description Default 31 : 2 R Reserved - 1 R/W JPEG Decoder timeout counter ctrl b : disable Timeout counter 1 : enable Timeout counter R/W JPEG Decoder RGB888/565 mode : RGB888 mode 1 : RGB565 mode b JPEG Decoder Timeout counter Register (JDCTIMEOUTCNT) Address : xa4_838 Bit R/W Description Default 31 : R/W JPEG Decoder timeout counter register 8h JPEG이어떤비정상적인데이터로인해정지할경우를감지할수있도록 timeout 값을통해대기시간을설정하여 detect할수있다 JPEG Decoder Timeout counter clear (JDCTIMEOUTCLR) Address : xa4_83c Bit R/W Description Default 31 : 1 R Reserved - R/W JPEG Decoder timeout counter clear register b JPEG 이 timeout 에걸렸을경우다음동작을수행하기위해서는반드시 timeout 을 clear 한후다시 release 하여야한다. 1 : timeout clear set : timeout clear off JPEG Decoder Input Data FIFO Register (JDIDF) Address : xa4_9 Bit R/W Description Default 31 : W INPUT DATA FIFO Compressed data(jpeg Input stream) FIFO JPEG Decoder 25.4 Register Description Copyright 215, Advanced Digital Chips, Inc.

215 26 USB DEVICE adstar-l 에내장된 USB Device 는 2. Full-speed(12Mbps) 를지원하며, 5 개의 endpoint 으로구성되어 있다. 하드웨어적으로 USB 프로토콜을지원하며, 자동적인 data retry, data toggle 그리고 power management 기능 (suspend 와 resume) 을지원한다. 내부에 PHY 가포함되어있다 Features - USB 2. Full Speed(12Mbps) - 5 개의 Endpoint 지원 - 하드웨어적으로 USB 프로토콜지원 - Suspend 와 Resume signaling 지원 Table 26-1 Endpoint List Endpoint Max Size (bytes) Direction Transaction Type 16 IN/OUT Control 1 64 OUT Bulk 2 64 IN Bulk 3 16 OUT Interrupt 4 16 IN Interrupt 26.2 Register Summary Table 26-2 USB Core Register List Register Address R/W Description Default Value USBFA xa18 R/W Function address register x USBPM xa184 R/W Power management register x USBEPI xa188 R/W Endpoint interrupt register x USBINT xa181 R/W USB interrupt register x USBEPIEN xa1814 R/W Endpoint interrupt enable register x1f USBINTEN xa1818 R/W USB interrupt enable register x4 USBLBFN xa181c R Frame number1 register x USBHBFN xa182 R Frame number2 register x USBIND xa1824 R/W Index register x USBMP xa1828 R/W MAXP register x USBEPC xa182c R/W EP control register x USBIC1 xa182c R/W EP2, 4 IN Control register1 x USBIC2 xa183 R/W EP2, 4 IN Control register2 x USBOC1 xa1838 R/W EP1, 3 OUT Control register 1 x USBOC2 xa183c R/W EP1, 3 OUT Control register 2 x USBLBOWC xa184 R Low Byte OEP Write count register x USBHBOWC xa1844 R High Byte OEP write count register x USBEPD xa1848 R/W EP FIFO data register x USBEP1D xa184c R/W EP1 FIFO data register x_ USBEP2D xa185 R/W EP2 FIFO data register x_ USBEP3D xa1854 R/W EP3 FIFO data register x USBEP4D xa1858 R/W EP4 FIFO data register x Features 26 USB Device Copyright 215, Advanced Digital Chips, Inc.

216 USB Function Address Register USBFAR 레지스터에는호스트에의해할당된 USB 디바이스주소가저장된다. MCU 는 SET_ADDRESS Descript 수행을통해받은값을이레지스터에저장한다. 이값은다음토큰에서사용된다 USB Power Management Register Power Management 레지스터는 Suspend, Resume 그리고 reset 신호에의해사용된다. Suspend 와 Reset 상태는 USB_INTERRUPT Register 에저장된다 USB Interrupt Registers USB Host 의요청상태와각 Endpoint 의상태와알려준다 USB Interrupt Enable Registers 각 Endpoint 의인터럽트를 Enable 한다. 대부분의인터럽트는초기값이 Enable 상태이나, Suspend 인터럽트는 Disable 이다 Frame Number Registers Frame Packet 의끝에서 frame 번호를저장한다 Index Register 인덱스레지스터는각각의 endpoint 에해당하는컨트롤레지스터를선택할때사용한다 MAXP Register 8byte 배수단위로사용할 FIFO 크기를조절할수있다. 그러나각 Endpoint 에서지원하는최대 FIFO 사이즈보다크게는설정할수없다 EP Control Register Endpoint 의제어와상태를나타낸다 IN Control Registers IN Endpoint 의제어와상태를나타낸다 Out Control Registers Out Endpoint 의제어와상태를나타낸다 Out Write Count Registers 두개의레지스터로이루어져 write count 값을가지다. OUT endpoint 에서 OPOPR 비트가 set 되면, 이레지스터에는 MCU 에의해가져간 packet 의수를가지고있다 Endpoint FIFO Access Registers FIFO 에접근하는 register 이다 USB Device 26.2 Register Summary Copyright 215, Advanced Digital Chips, Inc.

217 Register Description USB Function Address Register (USBFA) Address : xa_18h Bit R/W MCU USB Description 31 : 8 Reserved 7 R/W R/ ADDUP : ADDR_UPDATE bit. Clear 이레지스터의 FUNADD field가업데이트되면 MCU는이비트를 1로설정 한다. FUNADD field는, Endpoint CSR의 DATA_END 비트를 clear에의해 발생되는제어전송의 status phase 이후부터사용된다. 6 : R/W R FUNADD : FUNCTION_ADDR bits. MCU가주소를여기에 write 한다. Default Value USB Power Management Register (USBPM) Address : xa_184h Bit R/W MCU USB Description 31 : 4 Reserved 3 R Set UBRST : USB_RESET bit. 호스토로부터 Reset 신호를받으면 USB가이비트를설정한다. Reset 신호가버스상에서유지되는한, 이비트는 set 상태를유지한다. 2 W/R R UBRSUM : USB_RESUME bit. Resume 신호를초기화하기위해 MCU가 1ms ( 최대 15ms) 동안이비트 를설정한다. Suspend 모드에서이비트가설정되어있는동안 USB 가 Resume 신호를발생한다. 1 R R/W UBSPDMOD : SUSPEND_MODE bit. Suspend모드로들어가게되면 USB 가이비트를설정한다. 다음조건에의해 clear 가된다. -Resume 신호를끝내기위해서 MCU가 MUC_RESUME 를 clear 하는경우 -USB_RESUME 인터럽트발생때 MCU가인터럽트레지스터 3 을읽게되는경우. R/W R UBENSPD : ENABLE_SUSPEND bit = 1 Enable Suspend mode = Disable Suspend mode (Default) 이비트가 zero 이면, 디바이스는 suspend 모드상태로들어가지않는다. Default Value Register Description 26 USB Device Copyright 215, Advanced Digital Chips, Inc.

218 USB Endpoint Interrupt Register (USBEPI) Address : xa_188h Bit R/W MCU USB Description 31 : 5 Reserved 4 R/ Set EP4INT : EP4 Interrupt bit. (Interrupt in mode) Clear 이비트는 endpoint4 인터럽트에해당된다. (USBIC1R, USBIC2R 의 bit 참고 ) - ICIPR(In Control 1 In Packet Ready bit) 비트가 clear 될때 - FIFO가 flush 되었을때 ICSTSTAL(In Control 1 Sent Stall bit) 비트가 set 되었을경우에 3 R/ Clear 2 R/ Clear 1 R/ Clear R/ Clear Set Set Set Set EP3INT : EP3 Interrupt bit. (Interrupt out mode) 이비트는 endpoint3 인터럽트에해당된다. (USBOC1R, USBOC2R 의 bit 참고 ) - OCOPR(Out Control 1 Out Packet Ready bit) 비트를 set 할때 OCSTSTAL(Out Control 1 Sent Stall bit ) 비트를 set 할때 EP2INT : EP2 Interrupt bit. (Bulk in mode) 이비트는 endpoint2 인터럽트에해당된다. (USBIC1R, USBIC2R 의 bit 참고 ) - ICIPR(In Control 1 In Packet Ready bit) 비트가 clear 될때 - FIFO가 flush 되었을때 ICSTSTAL(In Control 1 Sent Stall bit) 비트가 set 되었을경우에 EP1INT : EP1 Interrupt bit. (Bulk out mode) 이비트는 endpoint1 인터럽트에해당된다. (USBOC1R, USBOC2R 의 bit 참고 ) - OCOPR(Out Control 1 Out Packet Ready bit) 비트를 set 할때 OCSTSTAL(Out Control 1 Sent Stall bit ) 비트를 set 할때 EPINT : EP Interrupt bit. (Control mode) 이비트는 endpoint 인터럽트에해당된다. (USBEPCR 의 bit 참고 ) EPOPR bit is set. EPIPR bit is cleared EPSTSTAL bit is set EPSTED bit is set EPDED bit is cleared(indicates End of control transfer) Default Value USB Interrupt Register (USBINT) Address : xa_181h Bit R/W MCU USB Description 31 : 3 Reserved 2 R/ Set RSTINT: USB Reset Interrupt bit. Clear 1 R/ Clear R/ Clear Set Set Reset신호가입력되면 USB가이비트를 set 한다. RSUMINT: Resume Interrupt bit. Suspend 모드상태에서 Resume 신호를받으면 USB 가이비트을 set 한다. USB Reset 에의한 Resume 이면, Resume 인터럽트에의해 MCU 에먼저 인터럽트가걸린다. 속되면, USB Reset 인터럽트가발생한다.. SPDINT : Suspend Interrupt bit 일단 Clock 이다시동작하고 SE 상태가 3ms 동안지 Suspend 신호를수신하면 USB 는이비트를 set 한다. 버스상에서 3ms 동안아무런동작이이루어지지않으면이비트는 set 된다. 그래서 MCU 가첫번째 suspend 인터럽트이후에 Clock 을멈추지않으면, USB 버스상에서아무런동작이이루지않는한매 3ms 마다인터럽트가계속발생한다. 디폴트로이인터럽트는 disable 이다 Default Value USB Device 26.3 Register Description Copyright 215, Advanced Digital Chips, Inc.

219 Endpoint Interrupt Enable Register (USBEPIEN) Address : xa_1814h 31 : 5 R Reserved 4 R/W EP4INTEN : Endpoint 4 Interrupt enable bit 1 3 R/W EP3INTEN : Endpoint 3 Interrupt enable bit 1 2 R/W EP2INTEN : Endpoint 2 Interrupt enable bit 1 1 R/W EP1INTEN : Endpoint 1 Interrupt enable bit 1 R/W EPINTEN : Endpoint Interrupt enable bit USB Interrupt Enable Register (USBINTEN) Address : xa_1818h 31 : 3 R Reserved 2 R/W RSTINTEN : USB RESET Interrupt enable bit 1 1 R Reserved R/W SPDINTEN : SUSPEND Interrupt enable bit USB Low Byte Frame Number Register (USBLBFN) Address : xa_181ch 31 : 8 R Reserved 7 : R/W Frame Number 1 register x USB High Byte Frame Number Register (USBHBFN) Address : xa_182h 31 : 8 R Reserved 7 : R/W Frame Number 2 register x USB Index Register (USBIND) Address : xa_1824h 31 : 3 R Reserved 2 : R/W Index register : Endpoint 1 : Endpoint 1 1 : Endpoint 2 11 : Endpoint 3 1 : Endpoint 4 11 : Reserved 11 : Reserved 111 : Reserved USB MAXP Register (USBMP) Address : xa_1828h 31 : 8 R Reserved 7 : R/W Max FIFO Size x _1 MAXP=8 _1 MAXP=16 _1 MAXP=32 _1 MAXP= Register Description 26 USB Device Copyright 215, Advanced Digital Chips, Inc.

220 USB EP Control Register (USBEPC) Address : xa_182ch Bit R/W MCU USB Description 31 : 8 R Reserved 7 Clear EPSUEC : EP Set Up End Clear bit. MCU가 EPSTED 비트를 clear 하기위해 1를 write 한다.. 6 Clear EPOPRC : EP Out Packet Ready Clear bit. MCU는 EPOPR 비트를 clear하기위해이비트에 1를 write한다. 5 Set Clear EPSDSTAL: EP Send Stall bit. 4 R Set 다. 3 Set/R Clear EPDED: EP Data End bit. MCU 는잘못된 token 이라고인식되면, EPOPR 비트를 clear 와동시에이 비트를 set 한다. USB 는 STALL handshake 를현재컨트롤전송에발생시 킨다. MCU 는 STALL 상황을끝내기위해 를 write 한다 EPSTED: EP Setup End bit. 이비트는읽기전용이다. EPDED 비트가 set 되기전에컨트롤전송이끝났을때 USB 가 이비 트를 set 한다. USB 가이비트를 set 할때 MCU 에인터럽트가전달된다. 이러한상황이발생했을때 USB 는 FIFO 를 flush 하고 MCU 의 FIFO 접근 을무효화한다. MCU 의 FIFO 접근이무효화될때이비트는 clear 된 MCU 는다음과같은상황에서이비트 set 한다 : - 마지막데이터패킷를가져온후 EPOPR 비트를 clear 할때 - Zero length data 구간에서 EPOPR 비트를 clear 하고 EPIPR 비트를 set 할때 - MCU 가 FIFO 에대한패킷데이터를 load 한후에 EPIPR 비트를 set함과동시에이비트 (EPDED) 를 set 한다. 2 Clear/R Set EPSTSTAL: Sent Stall bit. 프로토콜오류로컨트롤 transaction 이끝나면 USB 가이비트 set 한다. 이비트가 set 되면인터럽트가발생한다. 1 Set/R Clear EPIPR: EP In Packet Ready bit. MCU 는 endpoint FIFO 에데이터패킷을 write 한후에이비트을 set 한 다. 데이터패킷이성공적으로호스트에전달되면 USB 가이비트을 clear 시킨다. USB 가이비트를 clear 시키면인터럽트가발생한다. 그래서 MCU 는계속해서다음데이터를 load 할수있게된다. Zero length data phase 에서는 MCU는동시에이비트 (EPIPR) 와 EPDED 비트를 set 한다. R Set EPOPR: EP Out Packet Ready bit. Read only. Default Value 이비트는읽기전용이다. 유효한 token 이 FIFO 에쓰여지면 USB 가이 비트를 set 한다. USB 가 set 하면인터럽트가발생한다. MCU 는 EPOPRC 비트에 1 를 write 함으로써이비트를 clear 시킨다 USB Device 26.3 Register Description Copyright 215, Advanced Digital Chips, Inc.

221 USB IN Control 1 Register (USBIC1) Address : xa_182ch Bit R/W MCU USB Description 31 : 7 R Reserved 6 Set R/Clear ICCDT: In Control 1 Clear Data Toggle bit. Write Only. 5 R/ Clear Set MCU 가이비트에 1 을 write 하면 data toggle 비트가 clear 된다. 이비트 는쓰기전용이다. ICSTSTAL: In Control 1 Sent Stall bit. MCU 가 ICSDSTAL 비트를 set 했기때문에, IN token 에 STALL handshake 를발생된다. 이때 USB 가이비트를 set 한다. USB 가 STALL handshake 를발생시키면 ICIPR 비트는 clear 된다. MCU 가 를 write함으로써이비트를 clear 시킨다. 4 R/W R ICSDSTAL: In Control 1 Send Stall bit. MCU 가 USB 에 STALL handshake 를발생시키기위해이비트에 1 를 write한다. STALL 상황을끝내기위해 MCU가이비트를 clear 한다 3 R/Set Clear ICFFLU: In Control 1 FIFO Flush bit. Default Value IN FIFO를 flush하고자하면 MCU가이비트를 set 한다. FIFO가 flush가되면 USB 에의해이비트는 clear 된다. 이런상황이 발생하면 MCU에인터럽트가걸린다. Toke이진행중이라면, USB는 FIFO 가 flush 되기전에전송이완료될때까지기다린다. 만약에두개의패킷이 FIFO에 load되어있으면, 가장상위의패킷 ( 호스트로보내려고하는것 ) 만 flush이되고그패킷에관련있는 ICIPR 비트가 clear 된다. 2 Reserved 1 R Set ICFNE: In Control 1 FIFO Not Empty bit. FIFO에적어도한개의데이터패킷이있음을나타내다. : FIFO에패킷이없다. 1 : FIFO에패킷이있다. R/Set Clear ICIPR: In Control 1 In Packet Ready bit. FIFO에데이터패킷을쓰고난뒤 MCU가이비트를 set 한다. 호스트로데이터패킷전송이성공적으로끝나면 USB는이비트를 clear 한다. 이비트를 USB 가 clear 하면인터럽트가발생하고, MCU는다음패킷을로드할수있게된다. 이비트가 set 되어있는동안에는 MCU는 FIFO에쓰기를할수없다. MCU에의해 ICSDSTAL 비트가 set 되면, 이비트는 set 될수없다 Register Description 26 USB Device Copyright 215, Advanced Digital Chips, Inc.

222 USB IN Control 2 Register (USBIC2) Address : xa_183h Bit R/W MCU USB Description 31 : 8 R Reserved 7 R/W R ICASET: In Control 2 Auto Set bit. Default Value 이비트가 set 되어있으면, MCU 가 MAXP 만큼의데이터를쓰기를하면자동적으로 ICIPR 비트가 set 된다. MAXP 데이터보다적은데이터를쓸경우는 MCU 가 ICIPR 비트 를 set 해줘야한다. 6 Reserved 5 R/W R ICMODIN: In Control 2 Mode In bit. 1 Endpoint 의방향을프로그램머블할수있게끔해준다. 1 = endpoint 의방향을 IN 으로설정된다. = endpoint의방향을 OUT으로설정된다. 4 : Reserved USB Device 26.3 Register Description Copyright 215, Advanced Digital Chips, Inc.

223 USB Out Control Register 1 (USBOC1) Address : xa_1838h Bit R/W MCU USB Description 31 : 8 R Reserved 7 R/W R OCCDT: Out Control 1 Clear Data Toggle bit. MCU 가이비트에 1 를 write 하면, data toggle sequence 비트가 DATA로 reset 된다.. 6 Clear/R Set OCSTSTAL: Out Control 1 Sent Stall bit. OUT token 이 STALL handshake 로종료될때 USB 가이비트 set 한다. OUT Token 에서 MAXP 데이터보다더많은데이터를보낼경우 USB 가 host 에 stall handshake 를발생시킨다. MCU가 를 write하면 clear 된다. 5 W/R R OCSDSTAL: Out Control 1 Send Stall bit. USB 에 STALL handshake 를발생시키기위해 MCU 가이비트에 1 를 write 한다. STALL 상황을끝내기위해 MCU 가이비트에 을 write 한다. 4 R/W Clear OCFFLU: Out Control 1 FIFO Flush bit. MCU 가 FIFO 를 flush 하기위해 1 를 write 하고 flush 를멈추기위 해 을 write 한다. OCOPR 비트가 set 되어있는동안만이비트 가 set 될수있다. MCU 가가져간데이터패킷은 flush 가될것 이다. 3 R R/W OCERR : Out Control 1 Data Error bit 전송받은데이터에에러 (bit stuffing 또는 CRC) 가있음을나타낸 다. OCOPR 비트가 clear될때자동적으로 clear 된다. 2 R R Reserved 1 R R/W OCFFUL: Out Control 1 FIFO Full bit. Default Value R/ Clear Set 더이상의패킷을수용할수없음을나타낸다. : FIFO is not full. 1 : FIFO is full. OCOPR: Out Control 1 Out Packet Ready bit. FIFO 에데이터패킷이 load 가되면 USB 가이비트를 set 한다. MCU 가패킷전체를읽고나면이비트는 MCU 에의해 clear 되 어야한다. MCU 가 을 write 함으로써 clear 된다 USB OUT Control Register 2 (USBOC2) Address : xa_183ch Bit R/W MCU USB Description 31 : 8 R Reserved 7 R/W R OCACLR: Out Control 2 Auto Clear bit. Default Value 이비트가 set 이면, MCU 가 OUT FIFO 에서데이터를읽을때마다 자동적으로 USB core에의해 OCOPR 비트가 clear 된다. 6 : Reserved Register Description 26 USB Device Copyright 215, Advanced Digital Chips, Inc.

224 USB Low Byte Out Write Count Register (USBLOWC) Address : xa_184h 31 : 8 R Reserved 7 : R/W (LBOWC) Low Byte OEP write count register x USB High Byte Out Write Count Register (USBHBOWC) Address : xa_1844h 31 : 8 R Reserved 7 : R/W (HBOWC) High Byte OEP write count register x EP FIFO Data Register (USBEP) Address : xa_1848h 31 : 8 R Reserved - 7 : R/W EP FIFO Data Register x EP1 FIFO Data Register (USBEP1) Address : xa_184ch 31 : R/W EP1 FIFO Data Register x EP2 FIFO Data Register (USBEP2) Address : xa_185h 31 : R/W EP2 FIFO Data Register x EP3 FIFO Data Register (USBEP3) Address : xa_1854h 31 : 8 R Reserved - 7 : R/W EP3 FIFO Data Register x EP4 FIFO Data Register (USBEP4) Address : xa_1858h 31 : 8 R Reserved - 7 : R/W EP4 FIFO Data Register x USB Device 26.3 Register Description Copyright 215, Advanced Digital Chips, Inc.

225 27 USB HOST CONTROLLER adstar_l 의 USB 1.1 Host Controller 는 OpenHCI(ver 1.a) 를지원한다 Features - OpenHCI1. compatible - USB 1.1 compatible 27.2 Operational Registers Address A A4 A8 AC A1 A14 A18 A1C A2 A24 A28 A2C A3 A34 A38 A3C A4 A44 A48 A4C A5 A54 A58 Table 27-1 USB Host Register List Registers HcRevision HcControl HcCommandStatus HcInterruptStatus HcInterruptEnable HcInterruptDisable HcHCCA HcPeriodCurrentED HcControlHeadED HcControlCurrentED HcBulkHeadED HcBulkCurrentED HcDoneHead HcFmInterval HcFmRemaining HcFmNumber HcPeriodicStart HcLSThreshold HcRhDescriptorA HcRhDescriptorB HcRhStatus Reserved. HcRhPortStatus[1] Features 27 USB Host Controller Copyright 215, Advanced Digital Chips, Inc.

226 28 ELECTRICAL CHARACTERISTIC 28.1 DC Electrical Characteristic The ESD of device meets HBM-2KV and MM-2V. The following table summarizes the electrical design specifications of DC specifications: Table 28-1 I/O DC Electrical Characteristic Parameter Symbol Conditions Min Typ Max Unit High level output voltage VOH IOH = -8mA 2.4 V Low level output voltage VOL IOL = 8mA.4 V High level input voltage VIH LVTTL/CMOS interface 2. IOVDD+.5 V Low level Input voltage VIL LVTTL/CMOS interface.8 V CMOS interface V Switch threshold Vth Schmitt-falling-trigger V Schmitt-rising-trigger V Hysteresis Schmitt-trigger interface V Input pull-up resistance RPU VIN = kω Input pull-down resistance RPD VIN = VDDH kω Input current Vdd = MAX, V Vin 3.6V -1 1 µa Input current with pull down II Vin = Vdd 4 16 µa Input current with pull up Vin = µa 28.2 Operating Conditions The following table gives the recommended operating conditions for the integrated circuit (IC) chips using this library: Table 28-2 I/O Recommended Operating Conditions Operating Conditoins Min Typ Max Core DC Supply (CoreVDD) 1.62V 1.8V 1.98V I/O DC Supply Voltage (IOVDD) 3.V 3.3V 3.6V 28.3 LDO Electrical Specification Table 28-3 LDO Electrical Specifications VDD33=3.3V, COUT=1uF, TA=25 C unless otherwise noted Parameters Symbol Test Condition Min Typ Max Units Quiescent Current Iq Iout = PD = 35 ua Shutdown Current Isd PD = VDD33 1 ua Input Voltage VDD Vdrp V Output Voltage VDD18 Iout = V Band Gap Output VBG 1.2 V External Capacitor 4.7 uf Line Regulation Vcc=3.~3.6V Iout=1mA.2 Vcc=3.~3.6V Iout=15mA.4 % Dropout Voltage Vdrp Iout=15mA 24 mv Iout=1mA Without bypass Cap (1kHz) 38 Ripple Rejection PSRR Iout=15mA Without bypass Cap (1kHz) 38 db Iout=15mA With bypass Cap (1kHz) - Output Current Iout 15 ma PD Logic input High ViH.85 V PD Logic input Low ViL.45 V VDD18 Temperature Coefficient TC -45~125 C 4 ppm Electrical Characteristic 28.1 DC Electrical Characteristic Copyright 215, Advanced Digital Chips, Inc.

227 POR Electrical Specification Table 28-4 POR Specification (Unless otherwise specified, Topr=25 C, VDD=1.8V) Symbol Parameter Condition Min Typ Max Unit VDD Supply voltage V Is Supply current VDD=1.8V 3 5 ua Vtd Minimum power up trigger level 1 V Vtdr Maximum power drop trigger level.9 V Tr Rising time of VDD 1u 1m s Tf Falling time of VDD to VTH-1Mv (.9V) 5 us Td Reset delay time after VTH trigger Tr=8us 2 us No load VDD V Isource=3uA, VOH POR output high voltage VDD 1V.8*VDD V Isource=1uA, VDD 1.8V.8*VDD V VOL POR output low voltage No load GND V 28.5 PLL Electrical Specification Table 28-5 PLL DC Characteristics (Unless otherwise specified, Topr=25 C, VDD=1.8V) Symbol Parameter Condition Min Typ Max Unit AVDD Supply Voltage V DVDD Digital Supply Voltage V Is Supply Current normal 3 ma VIH Input High Voltage DVDD-.3 V VIL Input Low Voltage DGND+.3 V Table 28-6 PLL Input Frequency (Unless otherwise specified, Topr=25 C, VDD=1.8V) Symbol Parameter Min Typ Max Unit Fin Input Frequency Mhz POR Electrical Specification 28 Electrical Characteristic Copyright 215, Advanced Digital Chips, Inc.

228 ADC Electrical Specification Table 28-7 ADC Recommended operating conditions Symbol Parameter Min Typ Max Unit AVDD Analog Supply Voltage V DVDD Digital Supply Voltage V IR Input Voltage.3 VDDA-.3 V Table 28-8 ADC DC Characteristics (Unless otherwise specified, Topr=25 C, VDD=1.8V) Symbol Parameter Condition Min Typ Max Unit VIH Input High Voltage 1.5 V VIL Input Low Voltage.8 V 28.7 RTC Operation Voltage Symbol Parameter Min Typ Max Unit VBAT Analog Supply Voltage V 28.8 Power Consumption Table 28-9 Power Consumption from different conditions Condition Freq. Typ. CPU running from flash 11Mhz 512.7mW LCD displaying and Sound playing from NAND Flash file system 18Mhz 525.3mW CPU running from flash 96Mhz 341mW Electrical Characteristic 28.6 ADC Electrical Specification Copyright 215, Advanced Digital Chips, Inc.

229 29 PACKAGE DIMENSION Unit: mm Figure 29-1 Package Dimension Power Consumption 29 Package Dimension Copyright 215, Advanced Digital Chips, Inc.