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공학박사학위논문 The Characteristics and Reliability of In- Ga-Zn-O Thin-Film Transistors on Glass and Flexible Polyimide Substrate under Temperature and Illumination Stress 유리와플라스틱기판에제작한 인듐갈륨징크산화물박막트랜지스터의 온도와빛의특성및신뢰성에관한연구 2013 년 2 월 서울대학교대학원 전기 컴퓨터공학부 국승희
Abstract The Characteristics and Reliability of In- Ga-Zn-O Thin-Film Transistors on Glass and Flexible Polyimide Substrate under Temperature and Illumination Stress Seung-Hee Kuk School of Electrical Engineering and Computer Science College of Engineering Seoul National University Recently, flexible displays have attracted considerable attention in the emerging electronic device market. Flexible plastic substrates have the advantages such as flexibility, ruggedness and light-weight and its low cost, compared to glass substrate. Indium-Gallium-Zinc-Oxide thin-film transistors (IGZO TFTs) are promising candidates for next generation display backplane due to high mobility, good uniformity, and low process temperature, which suitable for flexible display. In this thesis, the characteristics and reliability of flexible IGZO TFTs were presented and discussed. Firstly, the electrical characteristics and reliability of IGZO TFTs on glass substrate are discussed. The IGZO TFTs were fabricated on a glass substrate with an inverted staggered structure. The initial electrical characteristics and gate bias induced instability was investigated. And drain bias induced instability is investigated. Unique degradation phenomenon was observed under the high i
drain bias stress. After the high drain bias stress, the drain current, measured at the low drain bias, was significantly decreased. Based on the experimental results, I proposed a degradation model for the high drain bias induced degradation. And light-induced hysteresis of IGZO TFTs is investigated. Hysteresis was observed under the 450-nm illumination, and was increased with temperature. And hysteresis was increased with wavelength decrease. Lightinduced hysteresis occurs due to increased sub-band gap states at the interface between the gate insulator layer and the active layer. Also, bias illumination stress induced instability is investigated. The transfer curve did not change after positive bias illumination stress. However, the transfer curve shifted to a negative direction after negative bias illumination stress. The transfer curve could be shifted to the negative direction after negative bias illumination stress due to the increase of VO 2+ states. Secondly, the electrical characteristics and reliability of IGZO TFTs on flexible substrate are discussed. The IGZO TFTs were fabricated on a polyimide (PI) substrate with an inverted staggered structure. An inorganic buffer layer, composed of SiO 2 and SiN x multi-layer, was employed, in order to prevent the environmental stress, such as water or oxygen molecules. The effects of PI and inorganic buffer layer on the characteristics and reliability of IGZO TFTs were investigated. And the effects of passivation layer on the electrical stability of IGZO TFTs with single passivation layer and double passivation layer fabricated on PI substrate were investigated. The positive bias stress and negative bias stress were applied to the IGZO TFTs at various temperatures from 20 o C to 80 o C. The threshold voltage shift of double passivation device was larger than that of single passivation device under NBTS. The threshold voltage shift of double passivation device was slightly less than that of single passivation device under PBTS. The threshold voltage shift of NBTS is considerably increased than that of PBTS at high temperature due to ii
the difference between conduction band offset and valence band offset. Lastly, the effects of mechanical bending on the electrical stability of flexible IGZO TFTs were investigated. Keywords: thin-film transistor, Indium-Gallium-Zinc-Oxide (IGZO), flexible display, reliability Student Number: 2009-30178 iii
Contents Abstract... i Contents... iv List of Tables... vii List of Figures... viii Chapter 1 Introduction... 1 1.1 Evolution of display technology... 2 1.2 Outline of this thesis... 10 Chapter 2 Review of IGZO TFTs and flexible display technology...11 2.1 Recent issues of IGZO TFTs... 12 2.1.1 Reliability under bias temperature stress... 14 2.1.2 Reliability under negative bias illumination stress... 18 2.1.3 Reliability under various environments... 24 2.2 Various backplane materials for flexible display... 30 Chapter 3 The electrical characteristics and reliability of IGZO TFTs on glass substrate...33 3.1 Overview... 34 3.2 Fabrication process of IGZO TFTs on glass substrate... 36 3.3 Electrical characteristics of IGZO TFTs... 39 iv
3.4 Gate bias induced instability without illumination... 42 3.5 Drain bias induced instability without illumination... 46 3.5.1 Introduction... 46 3.5.2 Experimental methods... 48 3.5.3 Experimental results and discussions... 49 3.5.4 Conclusion... 63 3.6 Light-Induced Hysteresis of IGZO TFTs with Various Wavelengths... 64 3.6.1 Introduction... 64 3.6.2 Experimental methods... 65 3.6.3 Experimental results and discussions... 66 3.6.4 Conclusion... 75 3.7 Light-Induced Hysteresis of IGZO TFTs with Various Temperatures... 76 3.7.1 Introduction... 76 3.7.2 Experimental methods... 78 3.7.3 Experimental results and discussions... 79 3.7.4 Conclusion... 89 3.8 Bias illumination stress induced instability... 90 Chapter 4 The electrical characteristics and reliability of IGZO TFTs on flexible substrate...99 4.1 Overview...100 4.2 Fabrication process of IGZO TFTs on polyimide substrate...102 4.3 Comparison between IGZO TFTs on glass substrate and flexible substrate...105 4.4 Effects of the buffer layer on the electrical characteristics of v
flexible IGZO TFTs...109 4.5 Effects of passivation layer on the electrical stability of flexible IGZO TFTs...115 4.5.1 Introduction... 115 4.5.2 Experimental methods... 117 4.5.3 Experimental results and discussions... 119 4.5.4 Conclusion... 127 4.6 Effects of humidity on the electrical characteristics of IGZO TFTs...128 4.7 Effects of mechanical bending on the electrical stability of flexible IGZO TFTs...139 Chapter 5 Summary... 154 Bibliography... 156 초록... 175 vi
List of Tables Table 2-1 The continuous use temperature and characteristics of the plastic substrates. [93, 94]... 32 Table 3-1 The layers information of the fabricated oxide TFTs.... 38 Table 3-2 The extracted parameter of the fabricated IGZO TFTs.... 41 Table 4-1 The layers information of the fabricated flexible oxide TFTs.... 104 Table 4-2 The extracted parameters of the fabricated IGZO TFTs employing oxide interface and nitride interface... 114 Table 4-3 Fabricated device parameters measured at 20 o C.... 126 vii
List of Figures Figure 1-1 The evolution of display technology.... 8 Figure 1-2 Four-inch QVGA bottom-emission AMOLED display driven by oxide TFTs without any pixel compensation circuit. [27]... 9 Figure 2-1 Schematic orbital drawings for the carrier transport paths in crystalline and amorphous semiconductors. (a) Covalent semiconductor, for example, silicon (b) oxide semiconductor. [22]... 13 Figure 2-2 Comparison of the effect of a positive and a negative gate bias stress on the transfer characteristics. [31]... 16 Figure 2-3 (a) The variations in the VTH shift for IGZO TFTs with various gate dielectrics (SiNx 150 C, SiNx 350 C, and SiOx 350 C) as a function of stress time. [32] (b) The variations in the Von and mobility shift for IGZO TFTs with plasma treatment as a function of stress time. [35]... 17 Figure 2-4 The evolution of transfer curves as a function of the applied -20 V NBS time (a) in the dark and (b) under green light exposure. [57]... 20 Figure 2-5 Schematic energy band diagram to explain photo-induced hole trapping. [51]... 21 Figure 2-6 Schematic energy band diagram showing the photo-desorption of oxygen molecules into the ambient atmosphere for the un-passivated device under the application of NBS. [60]... 22 Figure 2-7 Schematic energy band diagram showing the sub-band gap states related to oxygen vacancy. [57]... 23 Figure 2-8 Shifts of transfer curves at different oxygen partial pressures. [70]... 26 viii
Figure 2-9 The comparison of the transfer curves before and after the water exposure for the device with (a) 35-nm-thick and (b) 150-nm-thick channels, respectively. [73]... 27 Figure 2-10 Schematic showing the electric-field-induced adsorption of oxygen molecules from the ambient atmosphere under the application of positive bias stress (left). Schematic showing the electric-field-induced desorption of water molecules into the ambient atmosphere under positive bias stress (right). [71]... 28 Figure 2-11 The variations in the VTH shift for IGZO TFTs with different passivation layer (SiNx and SiOx) as a function of stress time. [86]... 29 Figure 3-1 (a) The cross-sectional view and (b) the microscope image of the fabricated oxide TFTs... 37 Figure 3-2 Transfer curves of fabricated IGZO TFTs by repeated measurement.. 40 Figure 3-3 Transfer curves before and after (a) positive bias temperature stress and (b) negative bias stress conditions. A detailed stress condition is shown in the figures.... 43 Figure 3-4 Transfer curves before and after (a) 30 V and (b) 50 V gate bias stress. A detailed stress condition is shown in the figures... 44 Figure 3-5 Schematic drawing of trapped electrons at the interface between the gate insulator layer and IGZO layer due to high gate bias induced degradation.... 45 Figure 3-6 (a) Output curve before and after 30 V drain bias stress. (b) Output curve and (c) transfer curve before and after 40 V drain bias stress. (d) Output curve and (e) transfer curve before and after 50 V drain bias stress. Detailed stress condition is shown in figures.... 55 ix
Figure 3-7 (a) Schematic drawing of trapped electrons at the etch stopper layer due to high drain bias induced degradation. (b) Band diagram of low drain bias measurement condition (VDS = 1V) and (c) high drain bias measurement condition (VDS = 10V) after degradation... 56 Figure 3-8 (a) Gate-source capacitance (CGS) and (b) gate-drain capacitance (CGD) versus gate bias curves (C-V curves) before and after 40 V drain bias stress. CGD versus gate bias curves before and after (c) 30 V drain bias stress and (d) 50 V drain bias stress.... 58 Figure 3-9 Simulated (a) output curves and (b) transfer curves by assuming the interface trapped electrons (Qn = 0, 2E11, 8E11, 3E12 cm -2 ). And electron concentration in IGZO layer calculated by computer aided device simulation (SILVACO) under (c) 1 V drain bias measurement condition and (d) 10 V drain bias measurement condition.... 60 Figure 3-10 Comparison of output curves before and after high drain bias stress between (a) simulation and (b) experimental data. Comparison of transfer curves before and after high drain bias stress between (a) simulation and (b) experimental data.... 62 Figure 3-11 (a) Transfer characteristics of IGZO TFTs under dark and various wavelengths at 60 o C (Wavelength = 550 nm, 500 nm, 450 nm, and 400 nm, Intensity = 1 mw/cm 2 ) (b) Magnitude of hysteresis and mobility as a function of wavelength.... 70 Figure 3-12 Transfer characteristics of IGZO TFTs under various sweep ranges with 450 nm illumination (a) [VGS = -10 ~ 10V, -20 ~ 20V, -30 ~ 30V], (b) [VGS = -30 ~ 30V, -30 ~ 10V, -10 ~ 30V]... 71 Figure 3-13 (a) The energy level of sub-band states of neutral oxygen vacancy x
(VO), singly ionized oxygen vacancy (VO + ) and doubly ionized oxygen vacancy (VO 2+ ). (b) Formation energies vs Fermi level for oxygen vacancies in ZnO in the 0, 1+, and 2+charge states, under Zn-rich conditions. [117]... 72 Figure 3-14 Schematic configuration coordinate diagrams for (a) negative gate bias and (b) positive gate bias... 73 Figure 3-15 Band diagram of IGZO TFTs with light illumination under (a) negative gate bias and (b) positive gate bias.... 74 Figure 3-16 (a) Transfer curves under the 450-nm illumination condition at 30 C, 60 C, and 90 C. (b) Transfer curves measured under various sweep ranges.... 83 Figure 3-17 (a) The magnitude of hysteresis and mobility as a function of temperature. (b) Schematic sub-band gap states to explain why lightinduced hysteresis increases as temperature increases.... 84 Figure 3-18 C-V characteristics under dark and light-illumination measured at (a) 60 C (W/L = 1000/6) and (b) 90 C (W/L = 2000/6).... 85 Figure 3-19 Energy band diagrams under (a) large negative VGS, (b) small negative VGS, and (c) positive VGS.... 87 Figure 3-20 Transfer curves before and after (a) positive bias illumination temperature stress and (b) negative bias temperature illumination stress conditions. A detailed stress condition is shown in the figures.... 88 Figure 3-21 Transfer curves before and after (a) positive bias illumination temperature stress and (b) negative bias temperature illumination stress. A detailed stress condition is shown in the figures.... 92 Figure 3-22 Transfer curves before and after (a) -10 V, (b) -20 V, and (c) -30 xi
negative bias temperature illumination stress. A detailed stress condition is shown in the figures.... 94 Figure 3-23 Transfer curves before and after negative bias temperature illumination stress under (a) 30 C, (b) 60 C, and (c) 90 C. A detailed stress condition is shown in the figures.... 96 Figure 3-24 Time dependence of threshold voltage shift (ΔVTH) due to negative bias illumination stress (a) under different stress gate bias (VGS = -10 V, - 20 V, -30 V) and (b) under different temperatures (T = 30 C, 60 C, 90 C).... 97 Figure 3-25 Time dependence of threshold voltage shift (ΔVTH) due to negative bias illumination stress under 90 C. Fitting to (a) power law and (c) logarithmic law are shown as solid lines.... 98 Figure 4-1 (a) The cross-sectional view and (b) the photograph of the fabricated flexible oxide TFTs after laser detaching.... 103 Figure 4-2 The cross-sectional view of fabricated IGZO TFTs on (a) glass substrate and (b) polyimide substrate.... 106 Figure 4-3 Comparison of transfer curves between glass substrate and PI substrate under (a) 30 C (b) 90 C.... 107 Figure 4-4 Comparison of threshold voltage shift (ΔVTH) between glass substrate and PI substrate under negative bias temperature stress. Temperature is from 30 C to 90 C.... 108 Figure 4-5 Schematic of inorganic multi-buffer layer with an (a) oxide interface and (b) nitride interface. Detailed layer information is shown in figures.... 111 Figure 4-6 Transfer curves of fabricated IGZO TFTs employing oxide interface and xii
nitride interface.... 112 Figure 4-7 Hydrogen atomic ratio versus depth profile of oxide interface and nitride interface measured by secondary ion mass spectroscopy (SIMS).... 113 Figure 4-8 Cross sectional view of fabricated IGZO TFT on glass/ PI substrate. SiOx (2000 Å) single passivation layer and SiOx/ SiNx (2000 Å/ 300 Å) double passivation layer are fabricated respectively.... 118 Figure 4-9 Transfer curves of fabricated IGZO TFTS with single passivation layer and double passivation layer measured at 20 o C.... 121 Figure 4-10 Threshold voltage shift vs stress time for stress applied at various temperature: (a) 20 o C, (b) 60 o C, and (c) 80 o C. For PBTS (NBTS) test, VGS was applied to 30 V (-30 V) and VDS was applied to 0.1V for 3 hours.... 123 Figure 4-11 Plot of ΔVTH vs 1/T for single passivation layer and double passivation layer devices, under (a) NBTS and (b) PBTS.... 124 Figure 4-12 Band diagram of IGZO/ SiOx stack structure.... 125 Figure 4-13 The cross-sectional view of the fabricated un-passivated oxide TFTs.... 131 Figure 4-14 The transfer curves of the fabricated un-passivated IGZO TFTs under (a) 30 C (b) 50 C (c) 70 C as a function of relative humidity.... 133 Figure 4-15 Threshold voltage as a function of relative humidity measured by (a) forward sweep method (from -20 V to 20 V) and (b) reverse sweep method (from 20 V to -20 V) under 30 C, 50 C, and 70 C. (c) Hysteresis (VTH forward VTH reverse) as a function of relative humidity under 30 C, 50 C, and 70 C.... 135 xiii
Figure 4-16 Leakage current as a function of relative humidity under 30 C, 50 C, and 70 C.... 136 Figure 4-17 (a) Saturated water vapor as a function of temperature. (b) Current amount of water vapor as a function of relative humidity under 30 C, 50 C, and 70 C.... 137 Figure 4-18 Schematic showing the adsorption of the water molecules under (a) high water vapor and (b) low water vapor... 138 Figure 4-19 (a) A photograph of bending measurement system. (b) Schematic showing bending direction perpendicular to channel (left) and parallel to channel (right)... 142 Figure 4-20 (a) A change of transfer curves on standing state for 3 hours under 5 mm bending radius. (b) A change of transfer curves on standing state for additional 16 hours under 5 mm bending radius.... 143 Figure 4-21 Shifts of transfer curves under PBTS (VGS = 30 V, VDS = 0.1 V) under 5 mm bending radius. (a) Bending direction is perpendicular to channel and (b) bending direction is parallel to channel.... 144 Figure 4-22 Shifts of transfer curves under NBTS (VGS = -30 V, VDS = 0.1 V) under 5 mm bending radius. (a) Bending direction is perpendicular to channel and (b) bending direction is parallel to channel.... 145 Figure 4-23 Shifts of transfer curves under PBTS (VGS = 30 V, VDS = 0.1 V) under (a) flat condition and (b) 5 mm bending radius. (c) Threshold voltage shift under PBTS as a function of time of flat condition and bending condition.... 147 Figure 4-24 Shifts of transfer curves under NBTS (VGS = -30 V, VDS = 0.1 V) under (a) flat condition and (b) 5 mm bending radius. (c) Threshold voltage shift xiv
under NBTS as a function of time of flat condition and bending condition.... 149 Figure 4-25 Shifts of transfer curves under PBITS (VGS = 30 V, VDS = 0.1 V, λ = 400nm, Intensity = 0.2 mw/cm 2 ) under (a) flat condition and (b) 5 mm bending radius. (c) Threshold voltage shift under PBITS as a function of time of flat condition and bending condition.... 151 Figure 4-26 Shifts of transfer curves under NBITS (VGS = -30 V, VDS = 0.1 V, λ = 400nm, Intensity = 0.2 mw/cm 2 ) under (a) flat condition and (b) 5 mm bending radius. (c) Threshold voltage shift under NBITS as a function of time of flat condition and bending condition.... 153 xv
Chapter 1 Introduction Recently, flexible displays have attracted considerable attention in the emerging electronic device market. Flexible plastic substrates have the advantages such as flexibility, ruggedness and light-weight and its low cost, compared to glass substrate. Indium-Gallium-Zinc-Oxide thin-film transistors (IGZO TFTs) are promising candidates for next generation display backplane due to high mobility, good uniformity, and low process temperature, which suitable for flexible display. There have been a lot of attempts to apply the IGZO TFTs for flexible display, but still need more verification. Therefore, it is very critical to investigate the characteristics and reliability of flexible IGZO TFTs. 1
1.1 Evolution of display technology Flat panel displays (FPDs) were considered a very attractive alternative to the cathode ray tube (CRT) as illustrated in Figure 1-1. There are various FPDs such as a liquid crystal display (LCD), a plasma display panel (PDP), an organic light emitting diode (OLED) display, and a field emission display (FED), which can be defined by the types of materials and the display method they use [1-4]. They have the merits providing large area, the slim and light-weight and highresolution images, which are not achieved easily with CRTs and projection display. Among all the FPDs, the most successful display technology to emerge so far is the LCDs. LCDs are thin, light-weight, bright and cost-effective due to the lowtemperature process on glass substrates. Therefore, they have enabled successful applications to laptop computers or desktop monitors, which occupy the large portion of FPD market. Also, the low voltage drive for portable applications is possible, so that the target market is not limited by an increasing diverse set of systems. The development of active matrix liquid crystal displays (AMLCDs) for high resolution and full-color display has been achieved by the thin-film transistors (TFTs). The active matrix display employing the TFT as a pixel switch has enhanced the capability of high quality image processing, so that the importance of LCDs in commercial fields increases. Hydrogenated amorphous silicon thin film transistors (a-si:h TFTs) have been widely used for AMLCDs due to their high productivity on large area glass substrates by low temperature process below 400 C. The a-si TFT can represent the gray scale by switching the voltage data and charging the capacitors of each pixel element. However, the poor current driving characteristics of a-si:h TFT due to the low field effect mobility 2
(< 0.5 cm 2 /V sec) are the limitation in realization of the high resolution display [5, 6]. The problem of low carrier mobility of a-si:h TFTs can be solved by employing the polycrystalline silicon (Poly-Si) film as an active layer in the TFT. Generally, Poly-Si film is fabricated by recrystallization of the a-si:h film deposited at low temperature below 400 C. Poly-Si TFTs have attracted considerable attentions due to its high electron mobility (30 ~ 500 cm 2 /V sec) and current driving capability [7, 8]. Compared with an a-si:h TFT, the superior electrical characteristics of the poly-si TFT allow a fast switching, required for the high resolution image. In addition, poly-si TFTs enable implementing the complementary metal oxide semiconductor (CMOS) technology and integrating the peripheral driver circuits and pixel switching devices simultaneously on a glass substrate. ELA technologies have been extensively studied to fabricated high qualty poly-si thin film on a large area glass substrate [8-10]. It employs the pulsed laser induced rapid heating of the a-si film, and more than 90% of the excimer laser energy is absorbed within shallow depth (~20 nm) from the surface of a-si film during the tens of nano-seconds of laser pulse duration. It is noted that the low temperature (< 400 C) crystallization of a-si film on a glass can be obtained by ELA without any thermal damage to the glass. Therefore, it is possible to integrate the digital and analog drivers such as inverter, level-shifter, shift register, digital-to-analog converter (DAC), and amplifier by employing low temperature poly-si (LTPS) TFTs on the glass panel. However, although the ELA LTPS TFT technology is attractive and researched widely due to its high performances, the electrical properties of the ELA LTPS TFTs are still insufficient to realize the high quality displays and need to be 3
improved yet in terms of the non-uniformity of grain-boundaries induced by the fluctuation of ELA energy. Additionally, the LTPS technology has a cost issue to fabricate TFTs compared with a-si technology. The crystallization of a-si film is critical to proceed to the stable process. The troublesome vacuum break process such as the crystallization and the doping process lead to low throughput and high sensitivity of electrical properties variation. Therefore, the conventional LTPS TFT process requires more process steps than a-si TFT, decreasing the process yield. In 1987, C. W. Tang and S. A. VanSlyke reported luminescence from an organic material [11]. They deposit small molecules to form a layered structure in a vacuum. The layered structure is sandwiched between an anode and cathode. The thin (< 1 μm) of organic material permits a high electric field at low voltage. Thus, a light from thin film organic materials is usually produced at low voltage. OLED displays exhibit superb electro-optical properties such as a fast response (~ several μsec) to the image addressing and a wide viewing angle due to selfemissive characteristics. Many research groups have been investigating new organic materials and new configurations of devices to improve efficiency and stability of OLED displays [12-15]. Therefore, AMOLED displays employing the TFT backplane have the potential for new technology comparable to the AMLCDs. The electro-optical performance of AMOLED is very sensitive to the characteristics of TFT. A small variation of the OLED current in the each pixel may cause a critical non-uniform image problem because the OLED luminance is controlled by the current driving. Thus, each TFT pixel in AMOLED panel requires a constant current source that maintains a desired image data during the whole emission time. For a reliable current driving with a low voltage in a limited pixel area, such as a 4
high density display, LTPS TFTs may be attracted as the pixel element rather than a-si TFTs because they can supply sufficient OLED current by a small circuit area due to their high current driving capability. Although some LTPS TFT based AMOLED display have been shown, they need to be improved due to the current non-uniformity [14, 16]. The random creation of grain boundaries during the crystallization varies the output current in pixel to pixel due to the non-uniform field effect mobility and threshold voltage of the poly-si TFT [8-10]. Therefore, the IOLED compensation pixel circuits, which can compensate the non-uniform characteristics of poly-si TFTs, are required for the uniform luminance in the display panel. There are two approaches to compensate the current variation: the voltage programming and the current programming, and each method have merits and drawbacks in itself [17, 18]. The a-si technology widely used in AMLCDs is considered for large area AMOLED displays due to its low fabrication cost and excellent uniformity. However, the critical problem of the long-term device degradation would be a huge barrier to meet the needs for high quality. Therefore, the degradation of the a-si:h TFT should be compensated by the pixel circuit and the new driving scheme to suppress the degradation of a-si TFTs itself should be developed. This would require a rather complicated compensation circuit compared with the poly-si TFT based pixel design. However, it is not easy to fabricate the compensation circuit in every pixel of limited dimension due to large size a-si:h TFT components and the space required for the layout of additional signals and capacitors of the circuit. Nowadays, TFT technology is challenging the realization of flexible displays on transparent plastic substrate and metal foil [19, 20]. Flexible plastic substrates have some merits such as flexibility, ruggedness and light-weight and its low cost, ultimately, compared with glass substrate. These merits make plastic substrate 5
attractive for portable systems such as a smart phone, and a tablet PC. However, the TFT technology on plastic substrate must overcome the limitation of process temperature. Plastic substrate has a much lower thermal budget, so that the process temperature of the TFT fabrication should be sufficiently low [21]. The most of commercially developed plastic substrates can stand low temperature below 200 C, and the critical temperature of plastic substrates is determined by the inherent characteristics of plastics [21]. Limited process temperature affects the deposition of films and the physical properties of the films tend to be deteriorated with the decrease of the process temperature. Due to the lack of thermal treatment, characteristics of the TFTs on plastic may be degraded much compared with those of the TFTs on glass. Oxide semiconductor materials are promising candidates for next generation display materials due to a relative high mobility, which is large enough to fabricate a high-speed transistor for driving the AMLCDs [22-24]. In addition, oxide semiconductor materials have an amorphous phase, which shows uniform electrical properties even with a large-size display [22, 25, 26]. High resolution, such as ultra-high defition (UD : 3840 2160), a high frame rate (> 240 Hz), and large size display (more than 70 inches) require the higher electrical performance than that of the a-si TFTs. At least 3 cm 2 /V s of field-effect mobility is required to satisfy such demands, which is not so easy to achieve by the conventional amorphous silicon material [27]. Furthermore, the oxide semiconductor TFTs has advantageous to the AMOLED. In general, LTPS TFTs employed to drive AMOLEDs because they exhibit high mobility and good electrical stability than a-si:h TFTs. However, the LTPS TFT has a problem with the uniformity which is originated from the non-uniform grain sizes in the poly-si film. Consequently, the LTPS TFT is not suitable for the AMOLED TV. Even for a small size AMOLED panel, a compensation circuit is 6
required in order to maintain uniform image quality for the LTPS TFT. Therefore, many demonstrations of AMOLEDs driven by the oxide semiconductor TFTs have been shown [27, 28]. Figure 1-2 shows four-inch QVGA bottom-emission AMOLED display driven by oxide TFTs without any pixel compensation circuit [27]. Another advantage of the oxide semiconductor based TFTs over the siliconbased TFTs is that the oxide semiconductors are transparent in the visible light region. Zinc oxide based semiconductor, such as indium-gallium-zinc-oxide, exhibits large optical band gap (> 2.8 ev) compared to silicon-based semiconductor [29, 30]. Due to large band gap characteristics, the oxide semiconductor exhibits low leakage current. 7
Figure 1-1 The evolution of display technology. 8
Figure 1-2 Four-inch QVGA bottom-emission AMOLED display driven by oxide TFTs without any pixel compensation circuit. [27] 9
1.2 Outline of this thesis This study focuses on the characteristics and reliability of flexible IGZO TFTs under various environments. Recent technical trend in flat panel display industry is the high resolution display and flexible display. In order to meet the two trends, IGZO TFTs are promising candidates. In this thesis, IGZO TFTs were fabricated on glass and flexible substrate, and investigated the characteristics and reliability under various environments. Chapter 2 gives a brief introduction to the IGZO semiconductor. Recent issues of IGZO TFTs, such as reliability under negative bias illumination stress and reliability under various environments, are reviewed. Also, various backplane materials for flexible display are reviewed. Chapter 3 focuses on the electrical characteristics and reliability of IGZO TFTs on glass substrate. Fabrication process and initial electrical characteristics of IGZO TFTs are introduced. Instability of IGZO TFTs under gate bias and drain bias without illumination is investigated. In addition, light-induced hysteresis phenomenon under various temperatures and wavelengths is investigated. Reliability of IGZO TFTs under illumination is also investigated. Chapter 4 concentrates on the electrical characteristics and reliability of IGZO TFTs on flexible substrate. Comparison between IGZO TFTs on glass substrate and flexible substrate is investigated. The effects of buffer layer, passivation layer, and mechanical bending on the electrical characteristics and reliability of flexible IGZO TFTs are also investigated. Lastly, I summarize the results of the characteristics and reliability of IGZO TFTs under various environments in Chapter 5. 10
Chapter 2 Review of IGZO TFTs and flexible display technology The flexible IGZO TFTs is now considered as a next generation display technology in active matrix displays. In this chapter, the recent issues of IGZO TFTs, such as reliability under bias temperature stress, negative bias illumination stress, and various environments, are reviewed. Also, various backplane materials for flexible display are reviewed. 11
2.1 Recent issues of IGZO TFTs In 2004, Nomura et al. reported an amorphous oxide semiconductors based on IGZO deposited at room temperature, and exhibited high mobility compared to amorphous silicon TFTs (μsat 7 cm 2 /V s) [22]. Despite the amorphous state, the origin of the high mobility was attributed to the electronic orbital structure of the material. Figure 2-1 shows schematic orbital drawings for the carrier transport paths in crystalline and amorphous semiconductors. Covalent semiconductors have carrier transport paths composed of strongly directive sp 3 orbitals, so structural randomness greatly degrades the magnitude of bond overlap, that is, carrier mobility [22]. However, amorphous oxide semiconductors composed of post-transition-metal cations. Spheres denote metal s orbitals. The contribution of oxygen 2p orbitals is small. Direct overlap between neighbouring metal s orbitals is rather large, and is not significantly affected even in an amorphous structure [22]. Therefore, amorphous oxide semiconductor could exhibits high mobility even in an amorphous phase. 12
Figure 2-1 Schematic orbital drawings for the carrier transport paths in crystalline and amorphous semiconductors. (a) Covalent semiconductor, for example, silicon (b) oxide semiconductor. [22] 13
2.1.1 Reliability under bias temperature stress For the stable operation, the device instability under the bias temperature stress should be investigated. During the operation of the display, TFTs have been applied positive or negative bias continuously. It is reported that threshold voltage is positively shifted under positive bias stress, while threshold voltage is scarcely shifted under negative bias stress. Figure 2-2 shows the comparison of the effect of a positive and a negative gate bias stress on the transfer characteristics. [31] The field effect mobility or the sub-threshold slope was not altered. When positive gate bias is applied to the IGZO TFTs, the electrons are accumulated at the channel, and electrons could be trapped at the interface between the IGZO and gate insulator layer. On the other hand, when negative gate bias is applied to the IGZO TFTs, the electrons are depleted at the channel, and electrons could not be trapped. Holes could not accumulate under negative bias, because IGZO is inherently n-type semiconductor. Threshold voltage shift and hysteresis could be improved by high quality gate insulator or plasma treatment at the gate insulator [32-35]. Figure 2-3 (a) shows the variations in the VTH shift for IGZO TFTs with various gate dielectrics (SiNx 150 C, SiNx 350 C, and SiOx 350 C) as a function of stress time [32]. The positive Vth shift in the a-igzo TFTs with the SiNx gate dielectric deteriorated significantly during constant bias stress due to the higher hydrogen content in the SiNx films providing more charge trap sites, which would produce a high shallow hydrogen-related states. Figure 2-3 (b) shows the variations in the Von and mobility shift for IGZO TFTs with plasma treatment as a function of stress time [35]. The interface treatment by O2 plasma significantly improves the stability of the a-igzo TFT. This suggests that the VTH shift is determined by the properties of the gate dielectrics, such as the density of charge traps. 14
The degradation mechanism is classified into the charge trapping and the defect state creation. The degradation mechanisms are originated from a-si:h TFTs [36-39]. The charge trapping process shows the logarithmic time dependence and has very small temperature dependence. On the other hand, the defect state creation process shows the power law time dependence and is thermally activated [37, 39]. The stretched exponential time dependence could be fitted to the charge trapping process [36]. The fabrication process and structure of the IGZO TFTs are not same each other, so the experimental results are. Therefore, the degradation mechanism of IGZO TFTs under bias temperature stress is still debated [31-33, 40-47]. 15
Figure 2-2 Comparison of the effect of a positive and a negative gate bias stress on the transfer characteristics. [31] 16
(a) (b) Figure 2-3 (a) The variations in the VTH shift for IGZO TFTs with various gate dielectrics (SiNx 150 C, SiNx 350 C, and SiOx 350 C) as a function of stress time. [32] (b) The variations in the Von and mobility shift for IGZO TFTs with plasma treatment as a function of stress time. [35] 17
2.1.2 Reliability under negative bias illumination stress For the stable operation, the device instability under the bias, thermal, illumination, and environmental stress have been intensively studied [31-35, 41, 43, 46, 48-78]. As a result, significant advances in reliability have been made. Nevertheless, reliability under negative bias illumination stress is still remained issue [51-68]. Since switching TFTs of active-matrix liquid crystal displays or organic light emitting diodes are almost always negatively biased and exposed to light during their operation, instability caused by the negative bias illumination stress is a crucial problem to be resolved [57]. Figure 2-4 shows transfer curves as a function of the applied -20 V negative bias stress (NBS) time (a) in the dark and (b) under green light exposure. The device did not suffer from any Von shift by NBS in the dark. Meanwhile, Von shift of -5.2 V with insignificant change in SS was observed under illumination. In the case of amorphous silicon, prolonged light illumination reduces the conductivity of the a-si film, which can be attributed to the formation of a metastable deep-level defect (so called Staebler Wronski effect) [79, 80]. Therefore, a-si TFTs under light illumination conditions would be affected adversely by stretching-out of the sub-threshold drain current [56]. In case of oxide TFTs, however, prolonged negative bias stress with light illumination results in a huge negative shift of the threshold voltage. A couple of degradation models have been proposed to account for this observation. First degradation model is the trapping of photo-generated hole carriers [51, 52]. Figure 2-5 shows the schematic energy band diagram to explain photo-induced hole trapping [51]. Second degradation model is photo-desorption of the oxygenrelated molecules [60]. Figure 2-6 shows the schematic energy band diagram showing the photo-desorption of oxygen molecules into the ambient atmosphere 18
for the un-passivated device under the application of NBS [60]. Third degradation model is the creation of sub band gap states [57, 59]. Figure 2-7 shows the schematic energy band diagram showing the sub-band gap states related to oxygen vacancy [57]. However, the degradation mechanism to explain overall phenomenon is unclear at this stage. 19
Figure 2-4 The evolution of transfer curves as a function of the applied -20 V NBS time (a) in the dark and (b) under green light exposure. [57] 20
Figure 2-5 Schematic energy band diagram to explain photo-induced hole trapping. [51] 21
Figure 2-6 Schematic energy band diagram showing the photo-desorption of oxygen molecules into the ambient atmosphere for the un-passivated device under the application of NBS. [60] 22
Figure 2-7 Schematic energy band diagram showing the sub-band gap states related to oxygen vacancy. [57] 23
2.1.3 Reliability under various environments The oxide semiconductor TFTs are sensitive to environmental air, such as oxygen, hydrogen, or water molecules [51, 54, 70-78]. Figure 2-8 shows the shifts of transfer curves at different oxygen partial pressures. [70] As oxygen partial pressure increases, transfer curve is positively shifted. The adsorbed oxygen forms depletion layer below the surface, resulting in positive shift of threshold voltage. Figure 2-9 shows the comparison of the transfer curves before and after the water exposure [73]. Leakage current and sub-threshold slope was increased, after water exposure of the IGZO TFTs. Left of Figure 2-10 shows the schematic showing the electric-field-induced adsorption of oxygen molecules from the ambient atmosphere under the application of positive bias stress. Right of Figure 2-10 shows schematic showing the electric-field-induced desorption of water molecules into the ambient atmosphere under positive bias stress [71]. O2(gas) + e =2O (solid) ------------------ (1) The interaction between the backchannel of active layer and ambient plays a critical role in the threshold voltage shifts. The adsorbed oxygen can capture an electron from the conduction band and that the resulting oxygen species can exist in various forms such as O 2, O, or O2, as described by the equation (1). As a result, a depletion layer is formed beneath the oxide semiconductor surface, leading to an increase in the threshold voltage. In order to prevent the effects of the environmental air, the passivation layer is employed. The effects of passivation layer on the stability of IGZO TFTs have been intensively studied [71, 81-87]. Figure 2-11 shows the variations in the VTH shift for IGZO TFTs with different passivation layer (SiNx and SiOx) as a function 24
of stress time [86]. The IGZO TFTs employing SiOx passivation layer shows better reliability. The hydrogen incorporation during the nitride growth has generated bulk defects within the semiconductor and/or at the interface between the semiconductor and gate insulator layer. In order to reduce the damage during the deposition of the passivation layer, organic passivation layer and inorganic multi-layer passivation was reported [82, 84]. 25
Figure 2-8 Shifts of transfer curves at different oxygen partial pressures. [70] 26
Figure 2-9 The comparison of the transfer curves before and after the water exposure for the device with (a) 35-nm-thick and (b) 150-nm-thick channels, respectively. [73] 27
Figure 2-10 Schematic showing the electric-field-induced adsorption of oxygen molecules from the ambient atmosphere under the application of positive bias stress (left). Schematic showing the electric-field-induced desorption of water molecules into the ambient atmosphere under positive bias stress (right). [71] 28
Figure 2-11 The variations in the VTH shift for IGZO TFTs with different passivation layer (SiNx and SiOx) as a function of stress time. [86] 29
2.2 Various backplane materials for flexible display Recently, flexible displays have attracted considerable attention in the emerging electronic device market. Flexible plastic substrates have the advantages such as flexibility, ruggedness and light-weight and its low cost, compared to glass substrate. These merits make plastic substrate attractive for portable systems such as a smart phone, and a tablet PC. However, the TFT technology on plastic substrate must overcome the limitation of process temperature. Plastic substrate has a much lower thermal budget, so that the process temperature of the TFT fabrication should be sufficiently low [21]. The most of commercially developed plastic substrates can stand low temperature below 250 C, and the critical temperature of plastic substrates is determined by the inherent characteristics of plastics [21]. Limited process temperature affects the deposition of films and the physical properties of the films tend to be deteriorated with the decrease of the process temperature. Due to the lack of thermal treatment, characteristics of the TFTs on plastic may be degraded much compared with those of the TFTs on glass. Polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyether sulfone (PES), polycarbonate (PC), polyimide (PI), stainless steel, and thin glass were used as flexible substrate materials [20, 88-94]. PI exhibits 275 C of the continuous use temperature, orange color, high CTE, good chemical resistance, expensive cost, and high moisture absorption. PES exhibits 230 C of the continuous use temperature, clear, good dimensional stability, poor solvent resistance, expensive cost, and moderate moisture absorption. PC exhibits 155 C of the continuous use temperature, clear, poor CTE, inexpensive cost, moderate moisture absorption. PEN exhibits 150 C of the 30
continuous use temperature, clear, moderate CTE, good chemical resistance, inexpensive cost, moderate moisture absorption. PET exhibits 120 C of the continuous use temperature, clear, moderate CTE, good chemical resistance, inexpensive cost, moderate moisture absorption. Table 2-1 summarizes the continuous use temperature and characteristics of the plastic substrates [93, 94]. Various active materials, such as amorphous silicon, low temperature poly silicon, single crystalline silicon, and oxide semiconductor, were considered as flexible display backplane [90, 95-97]. Flexible displays are demonstrated with the combination of various active materials and substrate materials [19, 20, 22, 88-92, 95-106]. Among the various active materials, oxide semiconductor has an advantage of low process temperature. Most of plastic substrates can stand low temperature below 250 C. Therefore, oxide semiconductor could be fabricated on various plastic substrates. In this thesis, the PI, coated on glass as rigid carrier, was used, overcoming difficulties in handling flexible freestanding plastic substrates, eliminating the problem of plastic shrinkage with high temperature processing and allowing the use of standard semiconductor fabrication equipment. Until now, deposition of gate insulator and post thermal annealing process are high temperature process (> 300 C). Therefore, the PI is the most suitable for flexible substrate of oxide TFTs. 31
Table 2-1 The continuous use temperature and characteristics of the plastic substrates. [93, 94] Continuous use temperature Material 275 C Polyimide (PI) 230 C 155 C 150 C 120 C Polyether Sulfone (PES) Polycarbonate (PC) Polyethylene naphthalate (PEN) Polyethylene terephthalate (PET) Characteristics Orange color, high CTE, good chemical resistance, expensive, high moisture absorption Clear, good dimensional stability, poor solvent resistance, expensive, moderate moisture absorption Clear, poor CTE, inexpensive, moderate moisture absorption Clear, moderate CTE, good chemical resistance, inexpensive, moderate moisture absorption Clear, moderate CTE, good chemical resistance, inexpensive, moderate moisture absorption 32
Chapter 3 The electrical characteristics and reliability of IGZO TFTs on glass substrate 33
3.1 Overview Indium-Gallium-Zinc-Oxide thin-film transistors (IGZO TFTs) have gained considerable attention for active matrix displays due to the high field effect mobility and good uniformity [26, 107]. In order to adopt the IGZO TFTs for actual display backplane, the stable characteristics under various stress conditions, such as bias, temperature, and illumination, are required. In this chapter, the electrical characteristics and reliability of IGZO TFTs on glass substrate are discussed. Firstly, the fabrication process is introduced. The IGZO TFTs were fabricated on a glass substrate with an inverted staggered structure. The etch stopper layer were employed, in order to improve the reliability of IGZO TFTs. After the introduction of device fabrication, the initial electrical characteristics, such as threshold voltage, mobility, sub-threshold slope, on-off ratio, and leakage current level, are introduced. Following the introduction of the initial characteristics, gate bias induced instability without illumination is investigated. And, drain bias induced instability without illumination is investigated. Unique degradation phenomenon was observed under the high drain bias stress. After the high drain bias stress, the drain current, measured at the low drain bias, was significantly decreased. Based on the experimental results, I proposed a degradation model for the high drain bias induced degradation. Following the drain bias induced instability, light-induced hysteresis of IGZO TFTs is investigated. Hysteresis was observed under the 450-nm illumination, and was increased with temperature. And hysteresis was increased with wavelength decrease. Light-induced hysteresis occurs due to increased sub-band gap states at the interface between the gate insulator layer and the active layer. 34
Lastly, bias illumination stress induced instability is investigated. The transfer curve did not change after positive bias illumination stress. However, the transfer curve shifted to a negative direction after negative bias illumination stress. The transfer curve could be shifted to the negative direction after negative bias illumination stress due to the increase of VO 2+ states. 35
3.2 Fabrication process of IGZO TFTs on glass substrate The a-igzo TFTs were fabricated on a glass substrate with an inverted staggered structure. Figure 3-1 (a) shows the cross sectional view of the fabricated IGZO TFTs. First, Mo/AlNd were deposited and patterned as the gate electrode. SiO2 of 2,000 Å thickness was then deposited by plasma-enhanced chemical vapor deposition (PECVD) and served as the gate dielectric layer. The IGZO (In:Ga:Zn = 1:1:1) layer with a thickness of 500 Å was deposited by sputtering. The SiO2 etch stop layer was deposited by PECVD. The source and drain were formed by depositing a layer of Mo and were patterned by dry etching. The SiO2 layer was used as a passivation layer. Annealing of the device was performed as the final process at 300 C in ambient air. Table 3-1 summaries the layers information of the fabricated oxide TFTs. Figure 3-1 (b) shows the microscope image of the fabricated oxide TFTs. The channel width was 24 μm and the length was 12 μm. The transfer characteristics of the TFTs were evaluated using an Agilent B1500A semiconductor parameter analyzer. For the light illumination test, the device was irradiated by a xenon lamp using narrow band pass filters. 36
(a) (b) Figure 3-1 (a) The cross-sectional view and (b) the microscope image of the fabricated oxide TFTs 37
Table 3-1 The layers information of the fabricated oxide TFTs. Layer Material Equipment Gate Mo/AlNd DC sputter Gate Insulator SiO2 200 nm PECVD Active IGZO 50nm DC sputter Etch stopper SiO2 50 nm PECVD Source/Drain Mo DC sputter Passivation SiO2 200 nm PECVD 38
3.3 Electrical characteristics of IGZO TFTs Figure 3-2 shows the transfer curves of fabricated IGZO TFTs by repeated measurement. The transfer curve maintains its origin state under repeated measurement. The threshold voltage (VTH) is -0.2 V, and the field effect mobility is 12 cm 2 /V s. The sub-threshold slope is 200 mv/dec, and the on-off ratio is greater than 10 8. The leakage current level is less than 10-12 A. Table 3-2 summaries the extracted parameter of the fabricated IGZO TFTs. Despite the amorphous state, the origin of the high mobility was attributed to the electronic orbital structure of the material [22]. Zinc oxide based semiconductor, such as IGZO, exhibits large optical band gap (>2.8 ev) compared to silicon-based semiconductor [29, 30]. Due to large band gap characteristics, the oxide semiconductor exhibits low leakage current. Large on-off ratio is attributed to the high mobility and low leakage current. Zinc oxide based semiconductor, such as IGZO, exhibits low sub-band gap states compared to amorphous silicon [108-110]. Small sub-threshold slope of IGZO TFTs is originated from low sub-band gap states characteristics. 39
I DS (A) 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 V DS = 10V V DS = 1V 1st sweep 2nd sweep 3rd sweep -20-10 0 10 20 V GS (V) Figure 3-2 Transfer curves of fabricated IGZO TFTs by repeated measurement. 40
Table 3-2 The extracted parameter of the fabricated IGZO TFTs. Parameter Value Unit VTH -0.2 V Mobility 12 cm 2 /V s Sub-threshold slope 200 mv/dec On-off ratio > 10 8 - Leakage current < 10-12 A 41
3.4 Gate bias induced instability without illumination Figure 3-3 shows the transfer curves before and after (a) positive bias temperature stress and (b) negative bias stress conditions. For positive bias stress, gate-source voltage (VGS) was applied to 20 V, and drain-source voltage (VDS) was applied to 0 V under no illumination for 10,000 seconds. The temperature was set to 60 C, in order to accelerate degradation. For negative bias stress, VGS was applied to -20 V, and the other stress condition was same to positive bias stress. Transfer curve was scarcely changed after positive bias tress (20 V) and negative bias stress (-20 V). In order to investigate gate bias induced degradation, we applied 30 V and 50 V to the gate bias stress. The other stress condition was same to the above condition. Figure 3-4 shows the transfer curves before and after 30 V and 50 V gate bias stress. In case of 30 V gate bias stress, transfer curve was scarcely changed. The fabricated devices show superior reliability compared to the literatures [31, 41, 46]. In case of 50 V gate bias stress, threshold voltage was positively shifted by the amount of 1.5 V. The other parameters, such as mobility or sub-threshold slope, were scarcely changed. The dominant degradation mechanism is electron trapping at the interface between gate insulator and IGZO. Figure 3-5 shows the schematic drawing of trapped electrons at the interface between the gate insulator layer and IGZO layer due to high gate bias induced degradation. 42
I DS (A) 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 <Stress condition> V GS =20V, V DS =0V Temperature=60 o C Duration=10,000sec Illumination=Dark V DS = 10V V DS = 1V 0 sec 10,000 sec -20-10 0 10 20 V GS (V) (a) I DS (A) 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 <Stress condition> V GS =-20V, V DS =0V Temperature=60 o C Duration=10,000sec Illumination=Dark V DS = 10V V DS = 1V Initial 10000 sec -20-10 0 10 20 V GS (V) (b) Figure 3-3 Transfer curves before and after (a) positive bias temperature stress and (b) negative bias stress conditions. A detailed stress condition is shown in the figures. 43
I DS (A) 10-3 10-4 <Stress condition> 10-5 V GS =30V, V DS =0V 10-6 Duration=10,000 sec 10-7 W/L=24/12 10-8 Temp.=60 o C 10-9 10-10 10-11 10-12 10-13 10-14 0 sec 100 sec 1000 sec 10000 sec -6-4 -2 0 2 4 6 V GS (V) (a) I DS (A) 1E-3 <Stress condition> V GS =50V, V DS =0V 1E-4 1E-5 1E-6 1E-7 1E-8 1E-9 1E-10 1E-11 1E-12 1E-13 1E-14 Duration=10,000 sec W/L=24/12 Temp.=60 o C 0 sec 100 sec 1000 sec 10000 sec -6-4 -2 0 2 4 6 V GS (V) (b) Figure 3-4 Transfer curves before and after (a) 30 V and (b) 50 V gate bias stress. A detailed stress condition is shown in the figures. 44
Figure 3-5 Schematic drawing of trapped electrons at the interface between the gate insulator layer and IGZO layer due to high gate bias induced degradation. 45
3.5 Drain bias induced instability without illumination 3.5.1 Introduction Amorphous Indium-Gallium-Zinc-Oxide (IGZO) thin-film transistors (TFTs) have gained considerable attention for active matrix displays due to the high field effect mobility and good uniformity [26, 107]. The electrical stability of IGZO TFTs under the bias, temperature, and illumination has been intensively studied [45, 46, 62]. The effects of gate bias stress on IGZO TFTs have been widely researched [31, 41, 43]. However, there are a few reports on the drain bias induced degradation in IGZO TFTs [41, 111]. It is reported that the effect of the drain bias on the stability of IGZO TFTs is not significant compared to the gate bias induced stress [41]. In the previous works, the high gate bias was applied simultaneously with the drain bias stress, which is different from our experimental condition [41, 111]. In our experimental results, however, a-igzo TFTs with the etch stopper structure was degraded under the high drain bias stress. Our experimental results show that a linear region of an output curve was severely decreased after the high drain bias stress. Furthermore, in the transfer curve, the drain current measured at the low drain bias (VDS = 1 V) was significantly decreased after the high drain bias stress. High drain bias could be applied to the transistor of the shift register [112]. And the applied drain bias to the driving transistor of the OLED TV is enhanced as the size of the panel increases. The purpose of our work is to investigate the high drain induced degradation in IGZO TFTs with the etch stopper structure. I propose a degradation model for the 46
high drain bias induced degradation. Computer aided device simulations and capacitance-voltage (C-V) measurements were employed to support my degradation model. 47
3.5.2 Experimental methods The IGZO TFTs were fabricated on a glass substrate with the bottom gate structure. The bottom gate structure is widely used for a-igzo TFTs, to adapt a conventional mass production process and design [23, 61, 113]. Most of the bottom gate structures have employed the etch stopper layer, to improve the reliability of a-igzo TFTs [23, 61, 113]. The detailed fabrication process is reported elsewhere [114]. The SiO2 etch stopper layer was employed to reduce the damage of the IGZO layer during the source-drain dry etching process. 48
3.5.3 Experimental results and discussions In order to investigate the drain bias induced degradation, we applied the various drain bias (10 V ~ 50 V) to the IGZO TFTs under 30 and 60 C for 100 seconds. For the purpose of minimizing the effect of gate bias, we fixed the gate bias to 1 V. The degradation was not observed under 30 V drain bias stress as shown in Figure 3-6 (a). Over 40 V drain bias stress, however, the drain current at low drain bias regime was decreased. Figure 3-6 (b) shows the output curve before and after 40 V drain bias stress. The output curve was measured at 2 V, 6 V, and 10 V gate bias. Regardless of the measuring gate bias, the linear region of the output curve was slightly decreased after 40 V drain bias stress. Figure 3-6 (c) shows the transfer curve before and after 40 V drain bias stress. The transfer curve was measured at 1 V and 10 V drain bias. The drain current measured at 1 V drain bias was slightly decreased, while the drain current measured at 10 V drain bias was scarcely decreased. In case of 50 V drain bias stress, the drain current at low drain bias regime was decreased significantly. Figure 3-6 (d) and (e) show the output curve and transfer curve before and after 50 V drain bias stress. Linear region of output curve was severely distorted after 50 V drain bias stress. In terms of the transfer curve, the drain current measured at 1 V drain bias was significantly decreased, while the drain current measured at 10 V drain bias was slightly decreased. The degradation was occurred in a short time compared to the high gate bias induced stress. However, the degradation did not proceed additionally, as the stress time increased. When high gate bias stress is applied, threshold voltage is shifted according to the polarity of the applied gate bias [31, 41, 43]. On-current level of the output curve could be changed according to the shift of threshold voltage, while linear region of output curve is hardly changed. The high gate bias induced degradation 49
mechanism is the charge trapping at the interface between the gate insulator layer and active layer. Our experimental result is a unique degradation phenomenon compared to the previous reports. To explain the unique degradation phenomenon, we assumed that the electrons could be trapped at the etch stopper layer due to the high drain bias. In this case, the drain bias has an effect on the electrons vertically, not laterally. In the gatedrain overlapped region, the electrons could have a vertical electric field. Figure 3-7 (a) shows the schematic drawing of trapped electrons at the etch stopper layer due to high drain bias induced degradation. The electrons are trapped at the etch stopper layer near the drain electrode due to high vertical field. Figure 3-7 (b) shows the band diagram of the low drain bias measurement condition (VDS = 1 V) after the high drain bias induced degradation. When the electrons are trapped at the etch stopper layer, the energy barrier is formed near the drain electrode due to the trapped electrons. In case of the low drain bias measurement condition (VDS = 1 V), the energy barrier blocks the carriers and the drain current could be decreased significantly. In case of the high drain bias measurement condition (VDS = 10 V), however, the energy barrier is lowered due to the applied drain bias and the drain current could be decreased slightly. The Capacitance-Voltage (C-V) characteristics were investigated, in order to verify the degradation model. Figure 3-8 (a) and (b) show gate-source capacitance (CGS) and gate-drain capacitance (CGD) before and after the 40 V drain bias stress. The CGS was measured with a floating drain, while the CGD was measured with a floating source. The C-V curve of CGS was not altered after stress, while the C-V curve CGD was positively shifted by amount of 1.23 V after 40 V drain bias stress. Figure 3-8 (c) and (d) show the C-V curve of CGD before and after the 30 V and 50 V drain bias stress. The C-V curve of CGD was positively shifted by amount of 0.28 V (4.96 V) after 30 V (50 V) drain bias stress. As the 50
applied drain bias increased, the amount of shift of C-V curve was increased. When the electrons are trapped at the insulator in MIS structure, C-V curve could be positively shifted. Density of interface trapped electrons (ΔQn) could be calculated using the following equation (ΔQn = C ΔVshift). The calculated Qn is about to 2E11 cm -2 (30 V drain bias stress), 8E11 cm -2 (40 V drain bias stress), and 3E12 cm -2 (50 V drain bias stress). The C-V characteristics suggest that the electron is trapped at the etch stopper layer near the drain region and support my degradation model. In order to support our degradation model, we employed the computer aided device simulation. We used ATLAS device simulator made by Silvaco. The interface trapped electrons were introduced at the etch stopper layer near the drain electrode in consideration of high drain bias induced degradation. Density of interface trapped electron is applied to the extracted data from our experimental results. Figure 3-9 (a) and (b) show the simulated output curves and transfer curves, and they are well matched to our experimental results. Figure 3-9 (c) and (d) show the free electron concentration in IGZO layer calculated by the computer aided device simulation (assuming Qn = 3E12 cm -2 ). Blue-dashed-squared region in Figure 3-7 (a) represents the simulation region. Figure 3-9 (c) shows the electron concentration in the IGZO layer under 1 V drain bias measurement condition. The free electrons in IGZO layer are depleted under the etch stopper layer due to the electric field induced by the interface trapped electrons at the etch stopper layer. Figure 3-9 (d) shows the electron concentration in IGZO layer under the 10 V drain bias measurement condition. The electrons are not depleted anymore at 10 V drain bias measurement condition because 10 V drain bias lowers the energy barrier made by the interface trapped electrons. The simulation results support my degradation model. 51
Figure 3-10 shows the comparison of output curves and transfer curves before and after high drain bias stress between (a, c) simulation and (b, d) experimental data. The simulated output curve and transfer curve are well matched that of the experimental results. These curves are support my degradation model. 52
ID (A) 3.0x10-5 <Stress condition> 2.5x10-5 V GS =1V, V DS =30V 2.0x10-5 1.5x10-5 1.0x10-5 Duration=100 sec W/L=24/12 Temp.=60 o C 0 sec 100 sec 5.0x10-6 0.0 0 5 10 15 VD (V) (a) I DS (A) 3.0x10-5 <Stress condition> 0 sec 2.5x10-5 V GS =1V, V DS =40V 100 sec 2.0x10-5 1.5x10-5 1.0x10-5 5.0x10-6 Duration=100 sec W/L=24/12 Temp.=60 o C 0.0 0 5 10 15 V DS (V) (b) 53
I DS (A) 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 0 sec 100 sec -20-10 0 10 20 V GS (V) (c) I DS (A) 3.0x10-5 <Stress condition> 0 sec 2.5x10-5 2.0x10-5 V GS =1V, V DS =50V Duration=100 sec W/L=24/12 100 sec 1.5x10-5 1.0x10-5 5.0x10-6 Temp.=60 o C 0.0 0 5 10 15 V DS (V) (d) 54
I DS (A) 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 0 sec 100 sec -20-10 0 10 20 V GS (V) (e) Figure 3-6 (a) Output curve before and after 30 V drain bias stress. (b) Output curve and (c) transfer curve before and after 40 V drain bias stress. (d) Output curve and (e) transfer curve before and after 50 V drain bias stress. Detailed stress condition is shown in figures. 55
(a) (b) (c) Figure 3-7 (a) Schematic drawing of trapped electrons at the etch stopper layer due to high drain bias induced degradation. (b) Band diagram of low drain bias measurement condition (VDS = 1V) and (c) high drain bias measurement condition (VDS = 10V) after degradation. 56
6.0x10-12 5.0x10-12 0 sec 100 sec C GS 4.0x10-12 3.0x10-12 2.0x10-12 <Stress condition> V GS =1V, V DS =40V Duration=100 sec W/L=2000/6 Temp.=R.T. 1.0x10-12 -10-8 -6-4 -2 0 2 4 6 8 10 V bias (V) (a) 6.0x10-12 5.0x10-12 0 sec 100 sec C GD 4.0x10-12 <Stress condition> 3.0x10-12 V GS =1V, V DS =40V Duration=100 sec 2.0x10-12 W/L=2000/6 Temp.=R.T. 1.0x10-12 -10-8 -6-4 -2 0 2 4 6 8 10 V bias (V) (b) 57
2.0x10-13 1.8x10-13 0 sec 100 sec CGD (F) 1.6x10-13 1.4x10-13 1.2x10-13 <Stress condition> V GS =1V, V DS =30V Duration=100 sec W/L=24/10 Temp.=60 o C -10-8 -6-4 -2 0 2 4 6 8 10 Vbias (V) (c) C GD (F) 1.4x10-13 1.2x10-13 1.0x10-13 8.0x10-14 6.0x10-14 4.0x10-14 0 sec 100 sec <Stress condition> V GS =1V, V DS =50V Duration=100 sec W/L=24/12 Temp.=60 o C -10-8 -6-4 -2 0 2 4 6 8 10 V bias (V) (d) Figure 3-8 (a) Gate-source capacitance (CGS) and (b) gate-drain capacitance (CGD) versus gate bias curves (C-V curves) before and after 40 V drain bias stress. CGD versus gate bias curves before and after (c) 30 V drain bias stress and (d) 50 V drain bias stress. 58
3.0x10-5 Qn= 0 cm -2 I DS (A) 2.5x10-5 2.0x10-5 1.5x10-5 Qn= 2E11 cm -2 Qn= 8E11 cm -2 Qn= 3E12 cm -2 V GS =10V 1.0x10-5 5.0x10-6 0.0 0 2 4 6 8 10 (a) V DS (V) I DS (A) 10-3 10-4 Qn= 0 cm -2 V DS =10V 10-5 10-6 10-7 Qn= 2E11 cm -2 Qn= 8E11 cm -2 Qn= 3E12 cm -2 V DS =1V 10-8 10-9 10-10 10-11 10-12 10-13 10-14 -8-6 -4-2 0 2 4 6 8 V GS (V) (b) 59
(c) (d) Figure 3-9 Simulated (a) output curves and (b) transfer curves by assuming the interface trapped electrons (Qn = 0, 2E11, 8E11, 3E12 cm -2 ). And electron concentration in IGZO layer calculated by computer aided device simulation (SILVACO) under (c) 1 V drain bias measurement condition and (d) 10 V drain bias measurement condition. 60
3.0x10-5 2.5x10-5 Before degradation After degradation I DS (A) 2.0x10-5 1.5x10-5 1.0x10-5 5.0x10-6 0.0 0 2 4 6 8 10 V DS (V) (a) V GS =10V I DS (A) 3.0x10-5 <Stress condition> 0 sec 2.5x10-5 2.0x10-5 V GS =1V, V DS =50V Duration=100 sec W/L=24/12 100 sec 1.5x10-5 1.0x10-5 Temp.=60 o C V GS =10V 5.0x10-6 0.0 0 2 4 6 8 10 V DS (V) (b) 61
I DS (A) 10-3 10-4 Before degrdation 10-5 After degrdation 10-6 10-7 V DS =10V 10-8 10-9 V DS =1V 10-10 10-11 10-12 10-13 10-14 -8-6 -4-2 0 2 4 6 8 V GS (V) (c) I DS (A) 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 V DS =10V V DS =1V 0 sec 100 sec -8-6 -4-2 0 2 4 6 8 V GS (V) (d) Figure 3-10 Comparison of output curves before and after high drain bias stress between (a) simulation and (b) experimental data. Comparison of transfer curves before and after high drain bias stress between (a) simulation and (b) experimental data. 62
3.5.4 Conclusion I have investigated the high drain bias induced degradation in IGZO TFTs with the etch stopper structure. The drain current, measured at the low drain bias, was significantly decreased after the high drain bias stress. The electrons were trapped at the etch stopper layer due to the high drain bias. The drain bias has an effect on the electrons vertically, not laterally. The computer aided simulation and C-V measurements support our degradation mechanism. Highly reliable etch-stopper-free-structure should be developed, to solve the high drain bias induced degradation and establish simple fabrication process. 63
3.6 Light-Induced Hysteresis of IGZO TFTs with Various Wavelengths 3.6.1 Introduction Indium-Gallium-Zinc Oxide thin-film transistors (IGZO TFTs) are promising candidate for next generation display backplane, due to its large mobility and good uniformity. Threshold voltage (VTH) of IGZO TFTs was not shifted under positive gate bias stress (PBS) or negative gate bias stress (NBS) without illumination. However, VTH of IGZO TFT was negatively shifted significantly under NBS with light illumination. In order to investigate this unique degradation phenomenon, stability of IGZO TFT under negative bias illumination stress (NBIS) has been intensively studied [57, 59, 68]. However, light-induced changes in device characteristics, such as hysteresis, are scarcely reported. Recently, I reported light-induced hysteresis and its mechanism of IGZO TFTs under various temperatures [114]. My experimental results showed that sub-threshold slope (S.S.) under 450-nm illumination increased compared to dark state during the forward sweep. However, S.S. under 450-nm illumination did not change compared to dark state during the reverse sweep. This phenomenon could be called light-induced hysteresis. In this paper, I report the effects of wavelength and negative bias on lightinduced hysteresis of IGZO TFTs. Hysteresis was increased, as wavelength decreased. And hysteresis was increased, as applied negative bias increased. 64
3.6.2 Experimental methods The IGZO TFTs were fabricated on a glass substrate with an inverted staggered structure. First, Mo/AlNd were deposited and patterned as the gate electrode. SiO2 of 2000 Å thickness was then deposited by plasma enhanced chemical vapor deposition (PECVD) and served as the gate dielectric layer. The IGZO (In:Ga:Zn = 1:1:1) layer with a thickness of 500 Å was deposited by sputtering. The SiO2 etch stop layer was deposited by PECVD. The source and drain were formed by depositing a layer of Mo and patterned by dry etching. The SiO2 layer was used as a passivation layer. Annealing of the device was performed as the final process at 300 C in an ambient air. For the light illumination test, the device was irradiated by a Xenon lamp with narrow band pass filters. 65
3.6.3 Experimental results and discussions Figure 3-11 (a) shows the transfer curves under dark and illumination conditions at 60 C. The center wavelengths of band pass filters were 550nm, 500nm, 450nm, and 400nm and light intensity was adjusted to 1 mw/cm 2. The transfer curves were measured by the double sweep method from 20V to 20V and the drain bias was fixed to 10 V. The transfer curves measured under dark condition and illumination conditions of 550 nm and 500 nm did not show any hysteresis. On the other hand, the transfer curves measured under 450 nm and 400 nm illumination conditions showed hysteresis. The magnitude of hysteresis increased as the wavelength decreased. Figure 3-11 (b) shows the magnitude of hysteresis (ΔV) and mobility extracted from Figure 3-11 (a). Mobility was not altered regardless of wavelength. Moreover, mobility was not changed under dark condition. The mobility of the IGZO TFT strongly depends on carrier concentration [22]. Electron concentration could be increased by light and thermal energy. To increase the mobility of IGZO TFTs under the illumination conditions, the lightinduced free carrier concentration (ΔnL) should be increased as much as the intrinsic carrier concentration. The intrinsic carrier concentration of IGZO is known to be 10 16 20 cm -3 [22, 115]. According to Lambert-Beer s law, the approximated quantum efficiency (η) could be estimated using the following equation (η = 1 exp[ αsub d], where αsub is the sub-band gap absorption coefficient and d is the thickness of the IGZO film) [116]. When αsub is assumed to be 10 4 cm 1 [110], η is calculated to be 4.9%. If light of a 400-nm wavelength and 1 mw/cm 2 intensity is illuminated to IGZO TFTs, ΔnL could be estimated using following equation (ΔnL = τ η I λ/[h c d]). τ is the electron life-time (assumed to 10 6 sec), I and λ are the intensity and wavelength of the illuminated light, h is 66
Planck s constant, and c is the speed of light. ΔnL is calculated to be approximately 10 13 cm 3, which is far less than the intrinsic carrier concentration. Under the illumination condition of wavelength longer than 400nm, ΔnL should be decreased, due to the decrease of αsub. It is suggested that light induced channel defect concentration is not large enough to change the mobility of IGZO TFTs. Figure 3-12 (a) shows the transfer characteristics of IGZO TFTs under various sweep ranges (VGS = -10 ~ 10V, -20 ~ 20V, -30 ~ 30V) with 450 nm illumination at 60 o C. The magnitude of hysteresis increased as sweep range increased. In order to investigate hysteresis mechanism in detail, we measured IGZO TFTs asymmetrically. Figure 3-12 (b) shows the transfer characteristics of IGZO TFTs under various sweep ranges (VGS = -30 ~ 30V, -30 ~ 10V, -10 ~ 30V) with 450 nm illumination at 60 o C. The magnitude of hysteresis was similar between (VGS = -30 ~ 30V) and (VGS = -30 ~ 10V). The magnitude of hysteresis was decreased when sweep range is (VGS = -10 ~ 30V). We have found that the magnitude of hysteresis was strongly dependent on the magnitude of applied negative gate bias. And we have found that the magnitude of hysteresis was independent on the magnitude of applied positive gate bias. When a ZnO based semiconductor is deposited, the deposited film has the native point defect, such as the oxygen vacancy. The oxygen vacancy has 3 possible charge states (VO, VO +, and VO 2+ ). Neutral oxygen vacancy (VO) is located near valence band maximum (VBM), and doubly ionized oxygen vacancy (VO 2+ ) is located near conduction band minimum (CBM). Figure 3-13 (a) shows the energy level of sub-band states of neutral oxygen vacancy (VO), singly ionized oxygen vacancy (VO + ) and doubly ionized oxygen vacancy (VO 2+ ). The energy level of subband states could be calculated using the first-principle calculations. Figure 3-13 (b) shows the formation energies vs Fermi level for oxygen vacancies in ZnO in 67
the 0, 1+, and 2+charge states, under Zn-rich conditions. [117] Figure 3-14 shows the schematic configuration coordinate diagrams for (a) negative gate bias and (b) positive gate bias. When the negative VGS is applied, the Fermi level moves toward the valence band. The formation energy of VO 2+ states could be smaller than that of VO states. It is suggested that VO 2+ states are more stable than VO states under negative gate bias. The formation energy of VO 2+ states is reduced further, as the Fermi level decreases. When the energy over the energy barrier is applied, VO states could be turned to VO 2+ states. The energy barrier from VO states to VO 2+ states is considered to about 2.75 ev, because lightinduced hysteresis could not be observed under the illumination of longer than 450 nm. Therefore, VO 2+ states could be observed during the forward sweep. When the positive VGS is applied, the Fermi level moves toward the conduction band. The formation energy of VO 2+ states is increased, and the formation energy of VO states could be smaller than that of VO 2+ states. It is suggested that VO states are more stable than VO 2+ states under positive gate bias. The energy barrier from VO 2+ states to VO states could be smaller than 2.75 ev. Therefore, VO 2+ states could not be observed during the reverse sweep. Figure 3-15 shows band diagram of IGZO TFTs with light illumination under negative gate bias (a) and positive gate bias (b). Photon irradiation and negative gate bias causes the transition of neutral oxygen vacancy (VO) to the doubly ionized oxygen vacancy (VO 2+ ) and the donation of two electrons to the conduction band. The VO 2+ states are created at the interface, and the generated VO 2+ states from the bulk could be migrated to the interface due to the applied negative gate bias. Interface states could be increased during this time, resulting in increase of sub-threshold slope. When the gate bias is changed from negative bias to positive bias, VO 2+ states at the interface are neutralized to VO states by 68
capturing two electrons. Therefore, transfer curves under dark and illumination are almost identical at the positive gate bias regime. In contrast to forward sweep, transfer curves under dark and illumination are almost identical during a whole reverse sweep. At the beginning of the reverse sweep, positive gate bias is applied so that VO 2+ states could not be generated at the interface. When the gate bias is changed from positive bias to negative bias during reverse sweep, transfer curves turn to off state. Therefore, transfer curves under dark and illumination could be identical during the whole reverse sweep. As wavelength decreased, absorption coefficient of IGZO film increased. It is obvious that more VO states could be excited to the VO 2+ states, as the wavelength decreased. Therefore, the magnitude of hysteresis is enhanced, as the wavelength is shifted to deep blue. Our experimental results suggested that VO states ranged from 2.75 ev (wavelength ~ 450nm) below the conduction band minimum. When sweep range is changed from (-10V ~ 10V) to (-30V ~ 30V), the magnitude of initial negative bias and time to be applied negative bias are increased, resulting in increase of interface state and sub-threshold slope. Therefore, hysteresis could be increased with the magnitude of applied initial negative gate bias. 69
I DS (A) 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 Dark 550nm 500nm 450nm 400nm -20-10 0 10 20 V GS (V) (a) DV (V) 6 DV 5 Mobility 4 3 2 1 0 400 450 500 550 Wavelength (nm) 17 16 15 14 13 12 11 10 Mobility (cm 2 /Vs) (b) Figure 3-11 (a) Transfer characteristics of IGZO TFTs under dark and various wavelengths at 60 o C (Wavelength = 550 nm, 500 nm, 450 nm, and 400 nm, Intensity = 1 mw/cm 2 ) (b) Magnitude of hysteresis and mobility as a function of wavelength. 70
I DS (A) 10-3 10-4 10-5 10-6 10-7 -10 ~ 10-20 ~ 20-30 ~ 30 10-8 10-9 10-10 10-11 10-12 10-13 10-14 -30-20 -10 0 V GS (V) 10 20 30 (a) I DS (A) 10-3 10-4 10-5 10-6 10-7 -30 ~ 30-30 ~ 10-10 ~ 30 10-8 10-9 10-10 10-11 10-12 10-13 10-14 -30-20 -10 0 V GS (V) 10 20 30 (b) Figure 3-12 Transfer characteristics of IGZO TFTs under various sweep ranges with 450 nm illumination (a) [V GS = -10 ~ 10V, -20 ~ 20V, -30 ~ 30V], (b) [V GS = - 30 ~ 30V, -30 ~ 10V, -10 ~ 30V] 71
(a) (b) Figure 3-13 (a) The energy level of sub-band states of neutral oxygen vacancy (V O), singly ionized oxygen vacancy (V O +) and doubly ionized oxygen vacancy (V O 2+). (b) Formation energies vs Fermi level for oxygen vacancies in ZnO in the 0, 1+, and 2+charge states, under Zn-rich conditions. [117] 72
2.75 ev (450 nm) V O V O 2+ (a) (b) Figure 3-14 Schematic configuration coordinate diagrams for (a) negative gate bias and (b) positive gate bias. 73
Light e - e - E c E f E v (a) (b) Figure 3-15 Band diagram of IGZO TFTs with light illumination under (a) negative gate bias and (b) positive gate bias. 74
3.6.4 Conclusion I have observed light-induced hysteresis under various wavelengths and sweep ranges, and have investigated its mechanism. Light-induced hysteresis is caused by the increase of VO 2+ states at the interface due to initial negative gate bias and light. Increased sub band gap states at the interface cause increase of subthreshold slope during forward sweep. The magnitude of light-induced hysteresis increased, as the wavelength decreased. And the magnitude of lightinduced hysteresis increased, as the magnitude of applied initial negative bias increased. 75
3.7 Light-Induced Hysteresis of IGZO TFTs with Various Temperatures 3.7.1 Introduction Recently, amorphous Indium-Gallium-Zinc Oxide thin-film transistors (a-igzo TFTs) have attracted considerable attention due to their high mobility and good uniformity [22, 27]. Device characteristics under light illumination and various temperatures are critical issues because display backplanes suffer from light illumination and thermal energy simultaneously. The reliability of a-igzo TFTs under bias, temperature, environment, and illumination has been intensively studied [57, 59, 65, 68, 118]. However, lightinduced changes in device characteristics, such as hysteresis, are scarcely reported. It has been reported that the sub-threshold slope (S.S.) and off current increases as wavelength decreases from 700 nm to 450 nm [119]. Our experimental results show that S.S. increased compared to dark state during the forward sweep under 450-nm illumination condition. However, S.S. did not change compared to dark state during the reverse sweep. This could be called light-induced hysteresis. Our experimental results show that this light-induced hysteresis increases as temperature increases. The mobility of IGZO TFTs also increased, as temperature increased. The purpose of my work is to investigate the light-induced hysteresis of a-igzo TFTs under various temperatures. One of the important parameters for stable driving of an active matrix display is the hysteresis of TFTs. When the hysteresis occurs, threshold voltage shift and current variation could be observed according to the previously applied gate bias. 76
And current could be altered, when the mobility changes. A small variation of drain current may alter the brightness of organic light emitting diode (OLED) because OLED is a current-driven device. 77
3.7.2 Experimental methods The a-igzo TFTs were fabricated on a glass substrate with an inverted staggered structure. First, Mo/AlNd were deposited and patterned as the gate electrode. SiO2 of 2,000 Å thickness was then deposited by plasma-enhanced chemical vapor deposition (PECVD) and served as the gate dielectric layer. The IGZO (In:Ga:Zn = 1:1:1) layer with a thickness of 500 Å was deposited by sputtering. The SiO2 etch stop layer was deposited by PECVD. The source and drain were formed by depositing a layer of Mo and were patterned by dry etching. The SiO2 layer was used as a passivation layer. Annealing of the device was performed as the final process at 300 C in ambient air. The channel width was 24 μm and the length was 12 μm. The transfer characteristics of the TFTs were evaluated using an Agilent B1500A semiconductor parameter analyzer. For the light illumination test, the device was irradiated by a xenon lamp using narrow band pass filters. 78
3.7.3 Experimental results and discussions Figure 3-16 (a) shows the transfer curves under the 450-nm illumination at 30 C, 60 C, and 90 C. The center wavelengths of the band pass filters were 450-nm and the light intensity was adjusted to 1 mw/cm 2. The transfer curves were measured by the double sweep method from 20V to 20V, and the drain bias was fixed to 10 V. The transfer curves measured under dark condition did not show any hysteresis. However, the transfer curves measured at 450-nm illumination showed hysteresis, and it increased as temperature increased. In order to confirm whether or not this phenomenon is hysteresis, we measured IGZO TFT under various sweep ranges. Figure 3-16 (b) shows the transfer curves measured under various sweep ranges at 60 C. The magnitude of hysteresis (ΔV) was 4.02 V (0.57 V) when the transfer curve was measured from -30V to 30 (from -10V to 10V). ΔV increased according to the initial negative gate bias. ΔV was extracted by the difference between the gate voltages of the forward sweep and the reverse sweep at a drain current of 10 11 A. These experimental results support that this phenomenon is light-induced hysteresis. Figure 3-17 (a) shows the magnitude of hysteresis (ΔV) under lights of various temperatures. ΔV was increased from 0.89 V to 4.35 V as temperature increased from 30 C to 90 C. When the transfer curve was measured from 20 V to 20 V, an increased sub-threshold slope was observed under the 450-nm illumination. It has recently been reported that light-induced device characteristics and reliability were related to oxygen vacancy [57, 59, 65]. It has also been reported that neutral oxygen vacancies (VO) are distributed above the valence band maximum, while doubly ionized oxygen vacancies (VO 2+ ) are distributed below the conduction band minimum [59, 120]. Photon irradiation and negative gate bias causes the transition of VO states to the VO 2+ states and the donation of two 79
electrons to the conduction band. The generated VO 2+ states at the channel diffuse to the interface due to applied negative gate bias during the forward sweep. VO 2+ could diffuse in amorphous phase with the aid of negative gate bias [59, 65]. Figure 3-17 (a) shows mobility as a function of temperature. Mobility increased from 13.3 cm 2 /V s to 15.5 cm 2 /V s as temperature increased from 30 C to 90 C. The mobility of the a-igzo TFT strongly depends on carrier concentration [22]. Electron concentration could be increased by light and thermal energy. The lightinduced electron concentration can be ignored since the light illumination conditions were fixed. To increase the mobility of a-igzo TFTs, thermal-induced free carrier concentration should be increased as much as the intrinsic carrier concentration. The intrinsic carrier concentration of IGZO is known to be 10 16 20 cm -3 [22, 115]. f æ E ö Dn = N exp ç - sites (1) è k B DT ø A ZnO-based oxide semiconductor exhibits unintentional n-type conductivity due to its native point defects [120, 121]. The native point defect concentration increased as the operating temperature increased. Thermal-induced free carrier concentration could be estimated using equation (1) [120]. E f is the formation energy, Nsites is the number of sites the defect can be incorporated on, kb is the Boltzmann constant, and T is the temperature. As temperature increases from 30 C to 90 C, Δn could be increased as much as the intrinsic carrier concentration. The mobility of the a-igzo TFTs increased as the electron concentration increased. Figure 3-17 (b) shows why light-induced hysteresis was increased as temperature increased. As discussed above, the point defect concentration is 80
increased with the temperature. And state transition frequency is increased with the temperature. As temperature increased, more VO 2+ states could be generated under the same illumination condition. The sub-threshold slope of the forward sweep increased due to the increased VO 2+ states. Therefore, light-induced hysteresis was increased with the temperature. Figure 3-18 shows C-V characteristics under dark and illumination condition (center wavelength = 450 nm, intensity = 1mW/cm 2 ) measured at (a) 60 C (W/L = 1000/6) and (b) 90 C (W/L = 2000/6). C-V curves were measured by double sweep method from -20V to 20V. Large width samples were employed in order to measure C-V characteristics accurately. Hysteresis was observed under illumination condition, while hysteresis was not observed under dark condition. And the magnitude of hysteresis increases, as temperature increases from 60 C to 90 C. The C-V characteristics suggested that interface states are generated during forward sweep. And the C-V characteristics supported the mechanism of light-induced hysteresis. Figure 3-19 shows the energy band diagrams under (a) large negative VGS, (b) small negative VGS, and (c) positive VGS. When large negative VGS is applied under the illumination, positive interface states are generated. It results in the positive shift of threshold voltage. The generated interface states are filled by electrons, as the surface potential increases. When the states are filled, the charge states become neutral. When the positive VGS is applied, all of the interface states are occupied. Figure 3-20 (a) shows the transfer curve before and after a positive bias illumination temperature stress (PBITS) condition. Gate bias was applied at 25 V and drain bias was applied at 0 V for 3,000 seconds. The device was irradiated with 450 nm wavelength light and temperature was set to 60 C. The transfer 81
curve and magnitude of hysteresis did not change after PBITS stress. Figure 3-20 (b) shows the transfer curve before and after a negative bias illumination temperature stress (NBITS) condition. Gate bias was applied at 20 V and drain bias was applied at 0 V for 3,000 seconds. The other stress conditions were the same as the PBITS condition. The transfer curve shifted to a negative direction after NBITS stress, and the magnitude of hysteresis was increased as much as 0.74 V. Similar to the explanation of light-induced hysteresis, light-induced VO 2+ is temporarily trapped to the interface due to the negative gate bias. When prolonged negative bias and illumination stress are applied to the device, the VO 2+ states turn to the stable states due to the proceeding of outward relaxation [59, 120]. The transfer curve could be shifted to a negative direction after NBITS stress due to the trapped VO 2+ states. The magnitude of hysteresis could be increased due to the increased sub-band gap states. These experimental results also support our proposed explanation of light-induced hysteresis. 82
I DS (A) 10-3 10-4 10-5 10-6 10-7 10-8 30 o C 60 o C 90 o C 10-9 10-10 10-11 10-12 10-13 10-14 -20-10 0 V GS (V) 10 20 (a) I DS (A) 10-3 10-4 10-5 10-6 10-7 -10 ~ 10-20 ~ 20-30 ~ 30 10-8 10-9 10-10 10-11 10-12 10-13 10-14 -30-20 -10 0 V GS (V) 10 20 30 (b) Figure 3-16 (a) Transfer curves under the 450-nm illumination condition at 30 C, 60 C, and 90 C. (b) Transfer curves measured under various sweep ranges. 83
DV (V) 5 4 3 2 1 DV Mobility 17 16 15 14 Mobility (cm 2 /Vs) 0 30 40 50 60 70 80 90 Temperature ( o C) 13 (a) (b) Figure 3-17 (a) The magnitude of hysteresis and mobility as a function of temperature. (b) Schematic sub-band gap states to explain why light-induced hysteresis increases as temperature increases. 84
Capacitance (F) 4.0p 3.5p 3.0p 2.5p 2.0p 1.5p 1.0p 500.0f Dark Photo 0.0-10 -5 0 5 10 Voltage (V) (a) Capacitance (F) 8.0p 6.0p 4.0p 2.0p Dark Photo 0.0-10 -5 0 5 10 Voltage (V) (b) Figure 3-18 C-V characteristics under dark and light-illumination measured at (a) 60 C (W/L = 1000/6) and (b) 90 C (W/L = 2000/6). 85
E C E F E V (a) E C E F E V (b) 86
E C E F Positive (empty) Neutral (filled) E V (c) Figure 3-19 Energy band diagrams under (a) large negative VGS, (b) small negative VGS, and (c) positive VGS. 87
I DS (A) 10-3 10-4 <Stress condition> 10-5 V GS = 25V, V DS = 0V 10-6 Temperature= 60 o C 10-7 Duration= 3,000sec 10-8 Illumination= 450nm 10-9 10-10 10-11 10-12 initial 10-13 3000 sec 10-14 -20-10 0 V GS (V) 10 20 (a) I DS (A) 10-3 10-4 <Stress condition> 10-5 V GS = -20V, V DS = 0V 10-6 Temperature= 60 o C 10-7 Duration= 3,000sec 10-8 Illumination= 450nm 10-9 10-10 10-11 10-12 initial 10-13 3000 sec 10-14 -20-10 0 10 20 V GS (V) (b) Figure 3-20 Transfer curves before and after (a) positive bias illumination temperature stress and (b) negative bias temperature illumination stress conditions. A detailed stress condition is shown in the figures. 88
3.7.4 Conclusion I have investigated the light-induced hysteresis of a-igzo TFTs, which is caused by the increased VO 2+ states at the interface due to initial negative gate bias and light. Increased sub-band gap states at the interface increase the sub-threshold slope during the forward sweep. The magnitude of light-induced hysteresis and transition rate from VO states to VO 2+ states are increased, as the temperature increases. We have observed light-induced hysteresis under various temperatures, and have investigated its mechanism. 89
3.8 Bias illumination stress induced instability Figure 3-21 shows the transfer curves before and after (a) positive bias illumination temperature stress and (b) negative bias temperature illumination stress. For positive (negative) bias illumination temperature stress, the gate bias was applied at 25 V (-20 V) and drain bias was applied at 0 V for 3,000 seconds. The device was irradiated with 450 nm wavelength light and temperature was set to 60 C. The transfer curve and magnitude of hysteresis did not change after positive bias illumination temperature stress. The transfer curve shifted to a negative direction by the amount of 0.83 V after negative bias illumination temperature stress. The threshold voltage shift accelerated under negative bias illumination stress, and these results coincide with the previous reports [56, 57, 61, 66]. In order to investigate the negative bias illumination temperature stress in detail, we have applied negative bias illumination temperature stress under various gate bias and various temperatures. Figure 3-22 shows the transfer curves before and after (a) -10 V, (b) -20 V, and (c) -30 negative bias temperature illumination stress for 3,000 seconds. The device was irradiated with 450 nm wavelength light and temperature was set to 30 C. The change of transfer curve after negative bias illumination stress was not significant, as the magnitude of applied stress bias increased. Figure 3-23 shows the transfer curves before and after negative bias temperature illumination stress under (a) 30 C, (b) 60 C, and (c) 90 C. The gate bias was applied to -20 V, and the drain bias was applied at 0 V for 3,000 seconds. The illumination condition was same to the above experiment. As the temperature increased, the magnitude of threshold voltage shift was increased. Figure 3-24 shows the time dependence of threshold voltage shift (ΔVTH) due to the above negative bias illumination stress conditions (a) 90
under different stress gate bias (VGS = -10 V, -20 V, -30 V) and (b) under different temperatures (T = 30 C, 60 C, 90 C). As the magnitude of stress gate bias increased from -10 V to -30 V, the threshold voltage shift was increased from 0.23 V to 0.52 V. As the temperature increased from 30 C to 90 C, the threshold voltage shift was increased from 0.36 V to 1.86 V. We could conclude that the effect of temperature on negative bias illumination stress is more significant than that of the magnitude of negative bias. Figure 3-25 shows the time dependence of threshold voltage shift (ΔVTH) due to negative bias illumination stress under 90 C. Fitting to (a) power law and (c) logarithmic law are shown as solid lines. The power law fitting has the lower value of the standard error than the logarithmic fitting law. The state creation process shows the power law time dependence and is thermally activated [37, 39]. Light-induced VO 2+ is temporarily trapped to the interface due to the negative gate bias. When prolonged negative bias and illumination stress are applied to the device, the VO 2+ states turn to the stable states due to the proceeding of outward relaxation [59, 120]. The transfer curve could be shifted to a negative direction after negative bias illumination temperature stress due to the trapped VO 2+ states. As the temperature increases, the state creation process is increased, resulting in increase of threshold voltage shift. 91
I DS (A) 10-3 10-4 <Stress condition> 10-5 V GS = 25V, V DS = 0V 10-6 Temperature= 60 o C 10-7 Duration= 3,000sec 10-8 Illumination= 450nm 10-9 10-10 10-11 10-12 initial 10-13 3000 sec 10-14 -20-10 0 V GS (V) 10 20 (a) I DS (A) 10-3 10-4 <Stress condition> 10-5 V GS = -20V, V DS = 0V 10-6 Temperature= 60 o C 10-7 Duration= 3,000sec 10-8 Illumination= 450nm 10-9 10-10 10-11 10-12 initial 10-13 3000 sec 10-14 -20-10 0 V GS (V) 10 20 (b) Figure 3-21 Transfer curves before and after (a) positive bias illumination temperature stress and (b) negative bias temperature illumination stress. A detailed stress condition is shown in the figures. 92
I DS (A) 10-3 10-4 <Stress condition> 10-5 V GS = -10V, V DS = 0V 10-6 Temperature= 30 o C 10-7 Duration= 3,000sec 10-8 Illumination= 450nm 10-9 10-10 10-11 10-12 initial 10-13 3000 sec 10-14 -20-10 0 V GS (V) 10 20 (a) I DS (A) 10-3 10-4 <Stress condition> 10-5 V GS = -20V, V DS = 0V 10-6 Temperature= 30 o C 10-7 Duration= 3,000sec 10-8 Illumination= 450nm 10-9 10-10 10-11 10-12 initial 10-13 3000 sec 10-14 -20-10 0 V GS (V) 10 20 (b) 93
I DS (A) 10-3 10-4 <Stress condition> 10-5 V GS =-30V, V DS =0V 10-6 Temperature=30 o C 10-7 Duration=3,000sec 10-8 Illumination=450nm 10-9 10-10 10-11 10-12 10-13 10-14 initial 3000 sec -20-10 0 10 20 V GS (V) (c) Figure 3-22 Transfer curves before and after (a) -10 V, (b) -20 V, and (c) -30 negative bias temperature illumination stress. A detailed stress condition is shown in the figures. 94
I DS (A) 10-3 10-4 <Stress condition> 10-5 V GS = -20V, V DS = 0V 10-6 Temperature= 30 o C 10-7 Duration= 3,000sec 10-8 Illumination= 450nm 10-9 10-10 10-11 10-12 initial 10-13 3000 sec 10-14 -20-10 0 V GS (V) 10 20 (a) I DS (A) 10-3 10-4 <Stress condition> 10-5 V GS = -20V, V DS = 0V 10-6 Temperature= 60 o C 10-7 Duration= 3,000sec 10-8 Illumination= 450nm 10-9 10-10 10-11 10-12 initial 10-13 3000 sec 10-14 -20-10 0 V GS (V) 10 20 (b) 95
I DS (A) 10-3 10-4 <Stress condition> 10-5 V GS = -20V, V DS = 0V 10-6 Temperature= 90 o C 10-7 Duration= 3,000sec 10-8 Illumination= 450nm 10-9 10-10 10-11 10-12 initial 10-13 3000 sec 10-14 -20-10 0 V GS (V) 10 20 (c) Figure 3-23 Transfer curves before and after negative bias temperature illumination stress under (a) 30 C, (b) 60 C, and (c) 90 C. A detailed stress condition is shown in the figures. 96
2.0 1.5 V GS = -10 V V GS = -20 V V GS = -30 V DV TH (V) 1.0 0.5 0.0 0 500 1000 1500 2000 2500 3000 Time (sec) (a) DV TH (V) 2.0 1.5 1.0 0.5 30 o C 60 o C 90 o C 0.0 0 500 1000 1500 2000 2500 3000 Time (sec) (b) Figure 3-24 Time dependence of threshold voltage shift (ΔV TH) due to negative bias illumination stress (a) under different stress gate bias (V GS = -10 V, -20 V, - 30 V) and (b) under different temperatures (T = 30 C, 60 C, 90 C). 97
2.0 1.5 Experimental Fitted curve DV TH (V) 1.0 0.5 Equation y = A*(x/t)^b Adj. R-Sq 0.9989 0.0 0 500 1000 1500 2000 2500 3000 Time (sec) Value Standard delta VTH A 5.21284 -- delta VTH t 28830.52 -- delta VTH b 0.45617 0.01013 (a) 2.0 1.5 Experimental Fitted curve DV TH (V) 1.0 0.5 Equatio y = A*log Adj. R-S 0.98041 Value Standar delta VT A 0.559 0.08407 delta VT t 126.0 50.1607 0.0 0 500 1000 1500 2000 2500 3000 Time (sec) (b) Figure 3-25 Time dependence of threshold voltage shift (ΔV TH) due to negative bias illumination stress under 90 C. Fitting to (a) power law and (c) logarithmic law are shown as solid lines. 98
Chapter 4 The electrical characteristics and reliability of IGZO TFTs on flexible substrate 99
4.1 Overview In this chapter, the electrical characteristics and reliability of IGZO TFTs on flexible substrate are discussed. Firstly, the fabrication process is introduced. The IGZO TFTs were fabricated on a polyimide (PI) substrate with an inverted staggered structure. An inorganic buffer layer, composed of SiO2 and SiNx multilayer, was deposited over the entire substrate area by plasma enhanced chemical vapor deposition (PECVD), in order to prevent the environmental stress, such as water or oxygen molecules. In order to investigate the effects of PI on the characteristic and reliability of IGZO TFTs, I have fabricated the IGZO TFTs on glass substrate and PI substrate. The transfer curves of IGZO TFTS on glass substrate and PI substrate were not changed under the temperature from 30 C to 90 C. Threshold voltage shift between glass substrate and PI substrate was almost identical regardless of temperature (from 30 C to 90 C). We could conclude that the effects of PI on the characteristic and reliability of IGZO TFTs were negligible. In order to investigate the effects of the buffer layer on the characteristic of IGZO TFTs, we have fabricated the IGZO TFTs on PI substrate with 2 kinds of multibuffer layer structures (oxide interface and nitride interface). In case of employing nitride interface, threshold voltage was decreased and mobility was increased. When nitride interface is employed, more hydrogen could be introduced. Secondary ion mass spectroscopy (SIMS) profile supports the hydrogen incorporation. And the effects of passivation layer on the electrical stability of IGZO TFTs with single passivation layer and double passivation layer fabricated on PI substrate were investigated. The positive bias stress and negative bias stress were applied to the 100
IGZO TFTs at various temperatures from 20 o C to 80 o C. The threshold voltage shift of double passivation device was larger than that of single passivation device under NBTS. The threshold voltage shift of double passivation device was slightly less than that of single passivation device under PBTS. The threshold voltage shift of NBTS is considerably increased than that of PBTS at high temperature due to the difference between conduction band offset and valence band offset. Lastly, the effects of mechanical bending on the electrical stability of flexible IGZO TFTs were investigated. 101
4.2 Fabrication process of IGZO TFTs on polyimide substrate The IGZO TFTs were fabricated on a polyimide (PI) substrate with an inverted staggered structure. Figure 4-1 (a) shows the cross sectional view of the fabricated IGZO TFTs. PI is spin-coated onto glass substrate, in order to overcome difficulties in handling flexible freestanding plastic substrates, eliminating the problem of plastic shrinkage with high temperature processing and allowing the use of standard semiconductor equipment. An inorganic buffer layer, composed of SiO2 and SiNx multi-layer, was deposited over the entire substrate area by plasma enhanced chemical vapor deposition (PECVD). Mo/AlNd were deposited and patterned as the gate electrode. SiO2 of 2,000 Å thickness was then deposited by plasma-enhanced chemical vapor deposition (PECVD) and served as the gate dielectric layer. The IGZO (In:Ga:Zn = 1:1:1) layer with a thickness of 500 Å was deposited by sputtering. The SiO2 etch stop layer was deposited by PECVD. The source and drain were formed by depositing a layer of Mo and were patterned by dry etching. The SiO2 layer was used as a passivation layer. After device fabrication, the PI substrates were released by laser irradiation process. Table 4-1 summaries the layers information of the fabricated flexible IGZO TFTs. Figure 4-1 (b) shows the photograph of the fabricated flexible oxide TFTs after laser detaching. The transfer characteristics of the TFTs were evaluated using an Agilent B1500A semiconductor parameter analyzer. For the light illumination test, the device was irradiated by a xenon lamp using narrow band pass filters. 102
(a) (b) Figure 4-1 (a) The cross-sectional view and (b) the photograph of the fabricated flexible oxide TFTs after laser detaching. 103
Table 4-1 The layers information of the fabricated flexible oxide TFTs. Layer Material Equipment Buffer layer SiO2 / SiNx multi-layer PECVD Gate Mo/AlNd DC sputter Gate Insulator SiO2 200 nm PECVD Active IGZO 50nm DC sputter Etch stopper SiO2 50 nm PECVD Source/Drain Mo DC sputter Passivation SiO2 200 nm PECVD 104
4.3 Comparison between IGZO TFTs on glass substrate and flexible substrate In order to investigate the effects of polyimide (PI) on the characteristic and reliability of IGZO TFTs, we have fabricated the IGZO TFTs on glass substrate and PI substrate. The fabrication process was identical between two samples except for PI coating and inorganic buffer layer deposition. Figure 4-2 shows the crosssectional view of fabricated IGZO TFTs on (a) glass substrate and (b) polyimide substrate. The channel width was 43 μm, and the channel length was 10 μm. Figure 4-3 shows the transfer curves of fabricated IGZO TFTS on glass substrate and PI substrate under (a) 30 C (b) 90 C. The transfer curves of IGZO TFTS on glass substrate and PI substrate were not changed regardless of temperature (from 30 C to 90 C). Figure 4-4 shows the comparison of threshold voltage shift (ΔVTH) between glass substrate and PI substrate under negative bias temperature stress. Gate-source voltage was applied to -30 V, and drain-source voltage was applied to 0.1 V for 3,600 seconds for negative bias temperature stress. Temperature is from 30 C to 90 C. Threshold voltage shift between glass substrate and PI substrate was almost identical regardless of temperature. We could conclude that the effects of PI on the characteristic and reliability of IGZO TFTs were negligible. 105
(a) (b) Figure 4-2 The cross-sectional view of fabricated IGZO TFTs on (a) glass substrate and (b) polyimide substrate. 106
I DS (A) 10-3 10-4 <Measurement condition> 10-5 Temperature = 30 o C 10-6 W/L = 43/10 10-7 10-8 10-9 10-10 10-11 10-12 10-13 Glass PI 10-14 -20-10 0 10 20 V GS (V) (a) I DS (A) 10-3 10-4 <Measurement condition> 10-5 Temperature = 90 o C 10-6 W/L = 43/10 10-7 10-8 10-9 10-10 10-11 10-12 10-13 Glass PI 10-14 -20-10 0 10 20 V GS (V) (b) Figure 4-3 Comparison of transfer curves between glass substrate and PI substrate under (a) 30 C (b) 90 C. 107
0.0-0.5 DVTH (V) -1.0 Glass 30 PI 30 Glass 60-1.5 PI 60 Glass 90 PI 90-2.0 0 1000 2000 3000 4000 Time (sec) Figure 4-4 Comparison of threshold voltage shift (ΔVTH) between glass substrate and PI substrate under negative bias temperature stress. Temperature is from 30 C to 90 C. 108
4.4 Effects of the buffer layer on the electrical characteristics of flexible IGZO TFTs In order to investigate the effects of the buffer layer on the characteristic of IGZO TFTs, we have fabricated the IGZO TFTs on PI substrate with 2 kinds of multibuffer layer structures. The fabrication process was identical between two samples except for the inorganic multi-buffer layer. Figure 4-5 shows the schematic of inorganic multi-buffer layer with an (a) oxide interface and (b) nitride interface. The (SiNX of 100 nm thickness/ SiO2 of 100 nm thickness/ SiNX of 100 nm thickness/ SiO2 of 100 nm thickness/ SiO2 of 300 nm thickness) were deposited for oxide interface multi-buffer layer, and (SiNX of 100 nm thickness/ SiO2 of 100 nm thickness/ SiNX of 100 nm thickness/ SiO2 of 100 nm thickness/ SiO2 of 300 nm thickness/ SiNX of 100 nm thickness) were deposited for nitride interface multi-buffer layer. The channel width was 43 μm, and the channel length was 10 μm. Figure 4-6 shows the transfer curves of fabricated IGZO TFTs employing oxide interface and nitride interface. The transfer curves measured under 30 C. Threshold voltage of the oxide interface was 0.53 V, while that of the nitride interface was -0.12 V. Mobility of the oxide interface was 11.75 cm 2 /V s, while that of the nitride interface was 13.54 cm 2 /V s. In case of employing nitride interface, threshold voltage was decreased and mobility was increased. SiNX has higher nitrogen concentration than SiO2. Some of hydrogen could be diffused to IGZO layer during post thermal annealing process. Figure 4-7 shows the hydrogen atomic ratio versus depth profile of oxide interface and nitride interface measured by secondary ion mass spectroscopy (SIMS). Hydrogen atomic ratio of nitride interface was 2.81 %, while hydrogen atomic ratio of oxide interface was 2.48 %. The difference of hydrogen atomic ratio results in 109
the difference of threshold voltage and mobility. When the hydrogen is introduced in the oxide semiconductor, hydrogen contributes shallow donor states, resulting in increase of their electrical conductivity [122, 123]. Therefore, threshold voltage could be negatively shifted and mobility could be increased, in case of nitride interface. 110
(a) (b) Figure 4-5 Schematic of inorganic multi-buffer layer with an (a) oxide interface and (b) nitride interface. Detailed layer information is shown in figures. 111
I DS (A) 10-1 10-2 10-3 10-4 Oxide interface Nitride interface 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 -20-10 0 10 20 V GS (V) Figure 4-6 Transfer curves of fabricated IGZO TFTs employing oxide interface and nitride interface. 112
3.0 Nitride interface Oxide interface 2.5 2.0 atomic % 1.5 1.0 0.5 0.0 Passivation SiO 2 2000 A ESL Active SiO 2 IGZO 500 A 500 A G. I. SiO 2 2000 A 0 100 200 300 400 500 depth [nm] Figure 4-7 Hydrogen atomic ratio versus depth profile of oxide interface and nitride interface measured by secondary ion mass spectroscopy (SIMS). 113
Table 4-2 The extracted parameters of the fabricated IGZO TFTs employing oxide interface and nitride interface. Sample VTH Mobility Oxide interface 0.53 V 11.75 cm 2 /V s Nitride interface -0.12 V 13.54 cm 2 /V s 114
4.5 Effects of passivation layer on the electrical stability of flexible IGZO TFTs 4.5.1 Introduction Recently, considerable amount of attention is paid on the flexible display. Indium-Gallium-Zinc-Oxide thin-film transistor (IGZO TFT) is a promising candidate for the flexible display, due to its high mobility, good uniformity, and low temperature process. Device characteristics and reliabilities of IGZO TFTs are closely related to their passivation layer. [71, 81, 87] It is well known that back-interface of IGZO TFTs are easily react with oxygen or water molecules. [70, 73, 76] The absorbed oxygen forms depletion layer below the back interface, resulting in positive shift of threshold voltage. [70] On the other hand, the absorbed water donates free electron, resulting in negative shift of threshold voltage. [73, 76] For the stable operation of flexible IGZO TFTs, high quality passivation layer should be employed. Silicon oxide (SiOx) and silicon nitride (SiNx) are widely used for passivation layer of semiconductor devices. When SiNx are deposited directly on the active layer, IGZO could be turned into a conductor due to hydrogen rich plasma. [84] Therefore, SiOx single passivation layer and SiOx/ SiNx double passivation layer are mainly studied for passivation layer of IGZO TFTs. It has been reported on negative bias illumination temperature stress (NBITS) of IGZO TFTs with SiOx single passivation layer and SiOx/ SiNx double passivation layer. [84, 85] However, the reliability of IGZO TFTs with double passivation layer and single passivation layer under various temperatures was not reported 115
yet. The electrical stability at high temperature is important, because the actual display backplane could be operated over 70 o C due to backlight or battery. The purpose of our work is to investigate the effects of passivation layer on the PBTS and NBTS at various temperatures. In this work, we have fabricated IGZO TFTs on polyimide (PI) substrate with with single passivation layer and double passivation layer. The PBTS and NBTS were applied to the fabricated devices at various temperatures from 20 o C to 80 o C. 116
4.5.2 Experimental methods We have fabricated inverted staggered bottom-gate structure IGZO TFT on PI substrate, as shown in Figure 4-8. An inorganic buffer layer was deposited by plasma enhanced chemical vapor deposition (PECVD). AlNd/ Mo bi-layer was deposited by sputter, and served as a gate electrode. A SiOx of 2000 Å thickness film was deposited by PECVD, and served as gate insulator. The IGZO layer was deposited by DC sputtering. A SiOx layer was deposited by PECVD, and served as etch stopper layer. Mo/ Al/ Mo tri-layer was deposited by sputter, and served as a source drain electrode. The SiOx of 2000 Å thickness single passivation layer and SiOx/ SiNx of 2000 Å/ 300 Å thickness double passivation layer was deposited by PECVD, respectively. To compare the different dimension devices, we normalized drain current (IDS normalized) by channel width and channel length. Threshold voltage (VTH) is taken as the gate voltage corresponding to IDS normalized = 10-8 A. 117
Figure 4-8 Cross sectional view of fabricated IGZO TFT on glass/ PI substrate. SiOx (2000 Å) single passivation layer and SiOx/ SiNx (2000 Å/ 300 Å) double passivation layer are fabricated respectively. 118
4.5.3 Experimental results and discussions Figure 4-9 shows the transfer curves of fabricated IGZO TFTs with single passivation layer and double passivation layer measured at 20 o C. The transfer curves were measured by the double sweep method from 20 V to 20 V and the drain bias was varied from 1 V to 10 V. VTH, mobility and sub-threshold slope (SS) of fabricated device was summarized at Table 4-3. VTH of double passivation layer is negatively shifted, compared to that of single passivation layer. Difference of VTH is attributed to the hydrogen, which is known to shallow donor of oxide semiconductor. [122] During SiNx deposition, a small part of hydrogen could be reached at IGZO layer, because the size of hydrogen is very small. When hydrogen is introduced at IGZO layer, electron concentration is increased. And it results in negative shift of VTH. Mobility of double passivation layer is larger than that of single passivation layer. Difference of mobility could be explained same way. Sub-threshold slope of double passivation layer is slightly increased due to the sub-band gap state made by hydrogen. Figure 4-10 shows threshold voltage shifts with respect to time at various temperatures. For PBTS test, gate-source voltage (VGS) was applied to 30 V and drain-source voltage (VDS) was applied to 0.1 V for 3 hours. For NBTS test, VGS was applied to -30 V and VDS was applied to 0.1 V for 3 hours. Even 80 o C stress, the absolute value of ΔVTH ( ΔVTH ) was less than 1.30 V. These results suggest that our fabricated devices are highly reliable. The ΔVTH of double passivation device was larger than that of single passivation device under NBTS test at all temperature range. Negative shift of VTH during NBTS test is attributed to trapping of positive ions. In case of double passivation layer, hydrogen ions (H + ) could be introduced during SiNx deposition. Therefore, positive ion concentration of double passivation device could be larger than that 119
of single passivation device. And it results in negative shift of VTH under NBTS test. The ΔVTH of double passivation device was slightly less than that of single passivation device under PBTS test. These results might be attributed to passivation effect due to hydrogen plasma during SiNx deposition. Hydrogen plasma could reduce interface trap density between gate insulator layer and active layer. [124] Electron trapping could be decreased at double passivation layer due to the passivation effect. However, passivation effect of hydrogen plasma could be very small, due to the existence of passivation layer and IGZO layer. Figure 4-11 shows the plot of ΔVTH vs 1/T for single passivation layer and double passivation layer devices under NBTS and PBTS tests. ΔVTH of NBTS is more thermally activated than that of PBTS. This result is caused by the difference between conduction band offset (ΔEC) and valence band offset (ΔEV). Figure 4-12 shows the band diagram of IGZO/ SiOx stack structure. The band offsets were calculated using the values reported in the literature. [59] The calculated ΔEC is about to 4.4 ev and ΔEV is about to 1.4 ev. Negative ions are hardly trapped to the interface due to large ΔEC. On the other hand, positive ions could be more easily trapped to the interface than negative ions due to small ΔEV. If thermally activated positive ion concentration equals negative ion concentration, more positive ions could be trapped to the interface. Therefore, ΔVTH of NBTS could be larger than that of PBTS at high temperature regime. 120
I DS (A) 10-1 10-2 SiO 10-3 x Single layer 10-4 SiO x / SiN x double layer 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 -20-10 0 10 20 V GS (V) Figure 4-9 Transfer curves of fabricated IGZO TFTS with single passivation layer and double passivation layer measured at 20 o C. 121
0.5 DVTH (V) 0.0-0.5 Single passi. (PBTS) Double passi. (PBTS) Single passi. (NBTS) Double passi. (NBTS) -1.0 100 1000 10000 Time (sec) (a) 0.5 DVTH (V) 0.0-0.5 Single passi. (PBTS) Double passi. (PBTS) Single passi. (NBTS) Double passi. (NBTS) -1.0 100 1000 10000 Time (sec) (b) 122
0.5 0.0 DVTH (V) -0.5 Single passi. (PBTS) -1.0 Double passi. (PBTS) Single passi. (NBTS) Double passi. (NBTS) -1.5 100 1000 10000 Time (sec) (c) Figure 4-10 Threshold voltage shift vs stress time for stress applied at various temperature: (a) 20 o C, (b) 60 o C, and (c) 80 o C. For PBTS (NBTS) test, VGS was applied to 30 V (-30 V) and VDS was applied to 0.1V for 3 hours. 123
10 Single passivation layer Double passivation layer DV TH (V) 1 0.1 0.01 2.8 3.0 3.2 3.4 1000 / T (K -1 ) (a) 10 Single passivation layer Double passivation layer DV TH (V) 1 0.1 0.01 2.8 3.0 3.2 3.4 1000 / T (K -1 ) (b) Figure 4-11 Plot of ΔVTH vs 1/T for single passivation layer and double passivation layer devices, under (a) NBTS and (b) PBTS. 124
Figure 4-12 Band diagram of IGZO/ SiOx stack structure. 125
Table 4-3 Fabricated device parameters measured at 20 o C. Split V TH (V) Mobility (cm 2 /V s) SS (V/dec) Single passivation layer 0.66 13.41 0.121 Double passivation layer -0.63 14.23 0.352 126
4.5.4 Conclusion I have investigated effects of passivation layer on the electrical stability of IGZO TFTs with single passivation layer and double passivation layer at various temperatures. In case of double passivation layer, hydrogen ions (H + ) could be introduced during SiNx deposition. Absorbed hydrogen increases carrier concentration and mobility, resulting in negative shift of VTH. The absorbed hydrogen accelerates NBTS stress. ΔVTH of NBTS is more thermally activated than that of PBTS due to the difference between ΔEC and ΔEV. 127
4.6 Effects of humidity on the electrical characteristics of IGZO TFTs In order to investigate the effects of the humidity on the characteristic of IGZO TFTs, we have fabricated the un-passivated IGZO TFTs. The highly boron doped silicon wafer served as a gate electrode, and 2,000 Å thickness of thermal oxide served as a gate dielectric. The IGZO (In:Ga:Zn = 1:1:1) layer with a thickness of 500 Å was deposited by sputtering. The source and drain were formed by depositing a layer of ITO employing sputtering. The active and source-drain were pattered by using shadow mask. The channel width was 2,000 μm, and the channel length was 200 μm. Figure 4-13 shows the cross-sectional view of the fabricated un-passivated oxide TFTs. Figure 4-14 shows the transfer curves of the fabricated un-passivated IGZO TFTs under (a) 30 C (b) 50 C (c) 70 C as a function of relative humidity. In case of 30 C and 50 C, the transfer curves were scarcely changed as the relative humidity increased. However, In case of 70 C, the transfer curves were significantly changed as the relative humidity increased. Figure 4-15 shows the threshold voltage as a function of relative humidity measured by (a) forward sweep method (from -20 V to 20 V) and (b) reverse sweep method (from 20 V to -20 V) under 30 C, 50 C, and 70 C. In case of 30 C and 50 C, the threshold voltage was scarcely changed. In case of 70 C, the threshold voltage measured by forward sweep method was negatively shifted from 0 V to -5.13 V, as the relative humidity increased from 30 % to 90 %. In case of 70 C, the threshold voltage measured by reverse sweep method was negatively shifted from 0.36 V to -2.67 V, as the relative humidity increased from 30 % to 90 %. The hysteresis was defined as the difference of the threshold 128
voltage measured by the forward sweep method and the reverse sweep method (VTH forward VTH reverse). The hysteresis also increased from 0.36 V to 2.46 V, as the relative humidity increased from 30 % to 90 %. Figure 4-16 shows the leakage current as a function of relative humidity under 30 C, 50 C, and 70 C. In case of 30 C and 50 C, the leakage current was scarcely changed as the relative humidity increased. In case of 70 C, the leakage current was increased from 8.34 pa to 41.3 pa, as the relative humidity increased from 30 % to 90 %. Figure 4-17 (a) shows the saturated water vapor as a function of temperature. As the temperature increased from 30 C to 70 C, the saturated water vapor was increased from 30 g/m 3 to 200 g/m 3. The relative humidity is defined as the ratio of the partial pressure of water vapor (H2O) (Ppresent) in the mixture to the saturated vapor pressure of water (Psaturated) at a prescribed temperature. Relative humidity is normally expressed as a percentage and is calculated by using the following equation. Ppresent R. H. = 100(%) P saturated Figure 4-17 (b) shows the current amount of water vapor as a function of relative humidity under 30 C, 50 C, and 70 C. Over 140 g/m 3 of water vapor (corresponds to 70 C of temperature and 70 % of relative humidity), the effects of humidity on the electrical characteristics of IGZO TFTs get more significant. As the water vapor increased, the amount of the adsorbed water molecules at the back-interface of IGZO TFTs is increased. When the water molecules are adsorbed at the back-interface of IGZO TFTs, the free electrons are donated and the electric field is generated due to dipole moments. The leakage current could be increased due to the Fermi level pinning of the back-interface. And threshold voltage could be negatively shifted due to the dipole moment of the adsorbed 129
water molecules. I could estimate the number of absorbed water molecules about 3.28 X 10 11 cm -2, when 70 C of temperature and 90 % of relative humidity is, by the following equation : Q = Ci ΔVTH/q (Ci is the gate insulator capacitance per unit area, ΔVTH is the threshold voltage shift). Figure 4-18 shows the schematic showing the adsorption of the water molecules under (a) high water vapor and (b) low water vapor. As the water vapor increased, the adsorbed water molecules at the back-interface are increased, resulting in increase of leakage current and threshold voltage shift. 130
Figure 4-13 The cross-sectional view of the fabricated un-passivated oxide TFTs. 131
I DS (A) 10-3 10-4 <Fixed condition> 10-5 Temp. = 30 o C 10-6 10-7 10-8 10-9 10-10 35% 10-11 50% 10-12 70% 10-13 90% 10-14 -20-10 0 10 20 V GS (V) (a) I DS (A) 10-3 10-4 <Fixed condition> 10-5 Temp. = 50 o C 10-6 10-7 10-8 10-9 10-10 30% 10-11 50% 10-12 70% 10-13 90% 10-14 -20-10 0 10 20 V GS (V) (b) 132
I DS (A) 10-3 10-4 <Fixed condition> 10-5 Temp. = 70 o C 10-6 10-7 10-8 10-9 10-10 30% 10-11 50% 10-12 70% 10-13 90% 10-14 -20-10 0 10 20 V GS (V) (c) Figure 4-14 The transfer curves of the fabricated un-passivated IGZO TFTs under (a) 30 C (b) 50 C (c) 70 C as a function of relative humidity. 133
VTH (V) 2 1 0-1 -2-3 -4-5 -6 30 oc 50 oc 70 oc 30 40 50 60 70 80 90 RH (%) (a) VTH (V) 2 1 0-1 -2-3 -4-5 -6 30 oc 50 oc 70 oc 30 40 50 60 70 80 90 RH (%) (b) 134
Hysteresis (V) 3 2 1 30 oc 50 oc 70 oc 0 30 40 50 60 70 80 90 RH (%) (c) Figure 4-15 Threshold voltage as a function of relative humidity measured by (a) forward sweep method (from -20 V to 20 V) and (b) reverse sweep method (from 20 V to -20 V) under 30 C, 50 C, and 70 C. (c) Hysteresis (VTH forward VTH reverse) as a function of relative humidity under 30 C, 50 C, and 70 C. 135
Leakge current (A) 60.0p 50.0p 40.0p 30.0p 20.0p 10.0p 0.0 30 oc 50 oc 70 oc 30 40 50 60 70 80 90 RH (%) Figure 4-16 Leakage current as a function of relative humidity under 30 C, 50 C, and 70 C. 136
Saturated water vapor(g/m 3 ) 300 250 200 150 100 50 0 20 30 40 50 60 70 80 Temperature ( o C) (a) Water vapor (g/m3) 200 150 100 50 30 oc 50 oc 70 oc 0 30 40 50 60 70 80 90 RH (%) (b) Figure 4-17 (a) Saturated water vapor as a function of temperature. (b) Current amount of water vapor as a function of relative humidity under 30 C, 50 C, and 70 C. 137
(a) (b) Figure 4-18 Schematic showing the adsorption of the water molecules under (a) high water vapor and (b) low water vapor. 138
4.7 Effects of mechanical bending on the electrical stability of flexible IGZO TFTs In order to investigate the effects of mechanical bending on the electrical stability of IGZO TFTs, I have fabricated the IGZO TFTs on the PI substrate. The fabrication process is same as that of the explained at chapter 4.2. Figure 4-19 (a) shows a photograph of bending measurement system. I could measure the electrical characteristics of IGZO TFTs under the 5 mm bend radius condition. Figure 4-19 (b) shows the schematic showing bending direction perpendicular to channel (left) and parallel to channel (right). Temperature is set to room temperature. Figure 4-20 (a) shows a change of transfer curves on standing state for 3 hours under 5 mm bending radius. The bending direction is parallel to channel direction. The transfer curves were not changed for 3 hours. We measured the transfer curves on standing state for additional 16 hours under 5 mm bending radius. Figure 4-20 (b) shows a change of transfer curves on standing state for additional 16 hours. The transfer curves were not changed for total 19 hours. I could conclude that the effects of mechanical bending on the electrical characteristics of flexible IGZO TFTs on PI substrate are negligible. In order to investigate the effects of bending direction, I applied positive bias temperature stress (PBTS) to the flexible IGZO TFTs under 5 mm bending radius with 2 types of bending directions. Figure 4-21 shows the shifts of transfer curves under PBTS (VGS = 30 V, VDS = 0.1 V) under 5 mm bending radius. Bending direction of Figure 4-21 (a) is perpendicular to channel and bending direction of Figure 4-21 (b) is parallel to channel. The effects of bending direction on the stability under PBTS were negligible. I applied negative bias temperature stress 139
(NBTS) to the flexible IGZO TFTs under 5 mm bending radius with 2 types of bending directions. Figure 4-22 shows the shifts of transfer curves under NBTS (VGS = -30 V, VDS = 0.1 V) under 5 mm bending radius. Bending direction of Figure 4-22 (a) is perpendicular to channel and bending direction of Figure 4-22 (b) is parallel to channel. The effects of bending direction on the stability under NBTS were also negligible. In order to compare the flat state and bending state, I applied positive bias temperature stress (PBTS) to the flexible IGZO TFTs under the flat state and bending state. Figure 4-23 shows the shifts of transfer curves under PBTS (VGS = 30 V, VDS = 0.1 V) under (a) flat condition and (b) bending condition. Figure 4-23 (c) shows the threshold voltage shift under PBTS as a function of time of flat condition and bending condition. The threshold voltage shifts under PBTS between the flat condition and the bending condition were very similar each other. And I applied negative bias temperature stress (NBTS) to the flexible IGZO TFTs under the flat state and bending state. Figure 4-24 shows the shifts of transfer curves under NBTS (VGS = -30 V, VDS = 0.1 V) under (a) flat condition and (b) bending condition. Figure 4-24 (c) shows the threshold voltage shift under NBTS as a function of time of flat condition and bending condition. The threshold voltage shifts under NBTS between the flat condition and the bending condition were very similar each other. Figure 4-25 shows the shifts of transfer curves under PBITS (VGS = 30 V, VDS = 0.1 V, λ = 400nm, Intensity = 0.2 mw/cm 2 ) under (a) flat condition and (b) bending condition. Figure 4-25 (c) shows the threshold voltage shift under PBITS as a function of time of flat condition and bending condition. The threshold voltage shifts under PBITS between the flat condition and the bending condition were very similar each other. Figure 4-26 shows the shifts of transfer curves under NBITS (VGS = -30 V, VDS = 0.1 V, λ = 400nm, Intensity = 0.2 mw/cm 2 ) under (a) flat condition and (b) bending condition. 140
Figure 4-26 (c) shows the threshold voltage shift under NBITS as a function of time of flat condition and bending condition. The threshold voltage shifts under NBITS between the flat condition and the bending condition were very similar each other. I could conclude that the effects of mechanical bending on the stability of IGZO TFTs were negligible. 141
(a) (b) Figure 4-19 (a) A photograph of bending measurement system. (b) Schematic showing bending direction perpendicular to channel (left) and parallel to channel (right). 142