^ Pyo Young

Size: px

Start display at page:

Download "^ Pyo Young"

웅재 길
6 years ago
Views:

1 /

2 ^ Pyo Young

3 NIX Server Trend

4 icroprocessors Big trend being changed in near future Until now, Intel Chips vs. Non-Intel Chips Intel chips for low & mid-range server market IBM/HPQ/SUN focusing on mid-range and high-end server market with own chips In near future, Intel Chips vs. IBM Chips Slow growth of PC market and rapid growth of embedded market Intel s entering high-end server market with HP IBM/SUN s chip plan 64-bit processors lead high-end server market IBM Power4+ HP PA-8700/8800 SUN UltraSPARC III Intel Itanium2 AMD Hammer Processors become big, fast, powerful, and complex IBM Power4+ : 184M transistors with 0.18um process HP PA-8800 : 300M transistors with 0.13um process (4Q/03) Intel Itanium2 : 221M transistors with 0.18um process AMD Opteron : 100M transistirs with 0.13um process (04/22/03)

P/SUN/Intel/AMD to CMP (Chip Multi Processor) HP PA-8800 Two PA-8700 processors on one chip 1.0 GHz, 0.13um process On-chip cache per core : L1 per core, L2 on cartridge Instruction cache : 0.

5 P/SUN/Intel/AMD to CMP (Chip Multi Processor) HP PA-8800 Two PA-8700 processors on one chip 1.0 GHz, 0.13um process On-chip cache per core : L1 per core, L2 on cartridge Instruction cache : 0.75MB / Data cache : 0.75MB L2 cache off chip : 32MB shared by two cores Copper & SOI & low-k technology No. of transistors : 300M SUN UltraSPARC IV or V Two UltraSPARC III processors on one chip 0.13um process Function to switch between two different modes depending on the type of work the computer is doing For heavy-duty calculations by exploiting ILP For business transactions by TLP Intel Montecito Dual-core Itanium by nm process AMD dual-core Hammer by??? Shared L2 Distributed switch

BM Power4 Implementation A dual-cpu chip Two small simple cores linearly scaled by efficient data sharing Higher clock rate possible than one complex CPU Memory bandwidth Cores with 100+ GB/s

6 BM Power4 Implementation A dual-cpu chip Two small simple cores linearly scaled by efficient data sharing Higher clock rate possible than one complex CPU Memory bandwidth Cores with 100+ GB/s bandwidth to large L2 on-chip cache 55+ GB/s bandwidth to memory and other Power4 chips on the same board Focus on exploiting Thread Level Parallelism (TLP) Chip Multiprocessor (CMP) Shared L2 Distributed switch Traditional RISC with 32 integer & floating point registers 5-way instruction issues per cycle

7 ower5 in 1H/2004 Support SMT with AIX 5.3 Two virtual processors by single physical processor First support of Fast Path Some higher order software functions in silicon to free up processor time Will handle TCP/IP packaging functions when implemented on the Power5 More error detection and correction Power consumption reduced significantly Advanced logical partition Ability to split a single physical server into several smaller logical ones Will be the heart of new advanced servers ASCI Purple by 12,544 Power5 processors New 64-way Armada server in % of a mainframe in terms of chip technology Ravi Arimilli

9 ower6 in 2006 IBM s flagship processor First processor for all IBM servers p / z / iseries and blade except xseries More implementation of Fast Path WebSphere and Oracle Four processors per chip for more TLP 90nm process More SMT by four virtual processors RAS more than current mainframe

10 tanium Family Roadmap Performance Montecito Itanium 2 Processor Madison / Deerfield Itanium Processor

11 P Microprocessor Roadmap Madison Deerfield PA GHz McKinley PA-8700 Merced PA MHz 1GHz PA MHz PA MHz PA MHz PA MHz Future

12 P Server Roadmap hp server PA-RISC HP Superdome PA-8700 speed-up HP Server rp8400 PA-8700 speed-up HP Server rp7410 PA-8700 speed-up HP Server rp5400 PA-8700 HP9000 A-class PA-8700 speed-up PA-8800 PA-8800 PA-8800 HP Server rp5610 PA-8800 PA-8900 PA-8900 PA-8900 PA-8900 Itanium -based hp servers HP Server rx9610 Itanium processor HP Superdome Madison 32p future Itanium 64p Madison Itanium 16p Madison Itanium 8p future Itanium p future Itanium p future Itanium 16p future Itanium 8p future Itanium 16p future Itanium 8p McKinley 4p Madison 4p future Itanium 4p future Itanium 4p McKinley 2p Madison 2p future Itanium 2p future Itanium 2p HP AlphaServer GS EV68 (1-32p) EV7 (8-64p) EV79 hp AlphaServer HP AlphaServer ES EV68 (1-4p) HP AlphaServer DS EV68 (1-2p) EV7 (2-16p) EV79

13 BM Processor Roadmap

14 ajor Microprocessors L1 L2 L3 Line Die size Transistors Remark z K/256K 3.2M** n/a M Pentium4 8K 512K n/a M 3.06GHz Prescott 28K 1M n/a M 3.06GHz, 4Q/03 Itanium 16K/16K 96K 4M** M 800MHz Itanium2 16K/16K 256K 3M M 1.0GHz Madison 16K/16K 256K 6M M 1.5GHz, 2Q/03 Madison 9M 16K/16K 256K 9M GHz, 2004 Opteron 64K/64K 1M n/a M 2.0GHz, 04/22/03 Athlon 64 64K/64K 256K n/a /03 Power4 64K/32K 1.5M* 32M** M Power4+ 64K/32K 1.5M* 32M** M 1.7GHz UltraSPARC III 32K/64K 8M** n/a M 1.2GHz PA M/1.5M No n/a M 875MHz PA M/1.5M* 32M* n/a M 1GHz Note : * shared by two cores ** Off the chip

15 oore & Proebsting Moore s Law : Advances in hardware technology will double computing power every 18 months Much of it has from silicon process technology, not architectural innovation Proebsting s Law: Advances in compiler technology will double performance of typical programs every 18 years Software paradigms shift in the time that it takes for compiler to mature

16 oore vs. Proebsting Moore s Law 2 x every 18 months Proebsting s Law 2 x every 18 years Increase in computing power : Processor s contribution versus Compiler s contribution

17 mplicit Parallelism (IBM) Compiler has limited, indirect view of hardware original source code compiler sequential machine code hardware parallelized code parallelized parallelized code code multiple functional units...

18 xplicit Parallelism by Compiler (IA) Compiler exposes, enhances, and exploits parallelism in the source program and makes it explicit in the machine code. original source code compiler parallel machine code Expose Enhance Exploit

19 echnology Leadership , ,288 3,000 (R&D) 50

20 000/Magic Quadrant midrange server Gartner, 2000/6

21 Series is the Industry Leader for UNIX Challengers Leaders Gartner, 2002/2 Ability to Execute SUN SPARC Dell PowerEdge HP ProLiant IBM iseries Linux zseries SUN x86 FSC Primergy HP Tru64 Unix Bull Escala Niche Players Red Hat on x86 Unisys ES7000 Completeness of Vision IBM pseries IBM xseries HP UX Fujitsu Primepower SUSE on x86 NEC/Bull (Intel) Stratus ftserver As of January 2003 Visionaries Windows UNIX Linux Other

IBM SUN E10K HP Superdome PA-RISC 8700 HP Superdome Itanium 2 IBM p690 IBM p690+ Number of Processor 64 64 64 32 32 Clock rate

22 IBM SUN E10K HP Superdome PA-RISC 8700 HP Superdome Itanium 2 IBM p690 IBM p690+ Number of Processor Clock rate 400MHz 875MHz 1.5GHz 1.3GHz 1.7GHz tpmc 156, , , , ,898 tpmc/processor 2,451 6,616 11,048 13,368 23,872

23 IBM ~ pseries Positioning Scalability, Availability P640 B80 Regatta p630 P660 6H1 Regatta p650 Regatta p670 Regatta p690+ Enterprise 450 Fire 3800 Fire 4800 Fire 6800 Fire 12K Fire 15K rp5450 rp5470 rp7400 rp8400 Superdome

27 Series 690 System Layout 15,000 / 5,600 Fault Isolation Register Bits

28 ynamic Processor Deallocation/Sparing Regatta / 32 32

29 ECC Memory Integrity and Availability

30 BM pseries Error Checkers, FFDC, Light Path Diagnostics CPU Dynamic CPU Deallocation Chipkill Memory I/O Bus PCI Error Recovery Partition LPAR Error Isolation /

31 On Demand IBM

32 690 CUoD - Processors IBM 4/2/2 4/2/2, 4/2/2 4/2/2 4/2/2 4/2/2 4/2/2 4/2/2 32way Install 16way Enabled 8 8way Install 8way Enabled 4/2/2 16way Install 8way Enabled 24way Install 12way Enabled Note: An inactive CUoD processor may be used by the system to replace a faulty processor that has been deallocated, without system disruption Note: p650 also provides CUoD features

33 690 CUoD - Memory 16/16 8/8 32GB Enabled 32GB Available 64GB Installed 16GB Enabled 16GB Available 32GB Installed 16/16 8/8 CUoD Processor and Memory are separate operations Requires AIX 5L 5.2 on entire system Memory cards are configured in pairs: half enabled / half CUoD Activation granularity of 4GBs of standby capacity Choices of 8/16GB & 16/32GB Choices of 0/4GB & 0/8GB for p650 POWER4/POWER4+ systems supported Activation process same as for processors

34 n/off Capacity on Demand Standby COD CPU, On/Off can be performed unlimited times until account balance reaches zero ibm pseries OOCoD Debit Account p650, p670, p690 Multiple activations supported with single or several codes based on time of order GOOD THRU No Expiration pseries OOCoD Customer OOCoD Account Balance 30 Days Supported on p650/670/690 Unlimited free use of on/off capacity on demand from 5/30/2003 to 9/30/2003 with purchase of 2 COD processors

35 erver Virtualization (AIX 5.3 LPAR)

36 hy IBM pseries? - (p690, 680,613 tpmc) - CPU (p690, 1.7GHz, tpmc/cpu) Clear CPU/Server -Investment Protection ebod -CUoD, MUoD, Dynamic LPAR

pseries, Systems Group pseries 2003 Corporation (p) Systems Group POWER4/POWER4+ pseries! +! + + The Only Complete UNIX on Demand

pseries, Systems Group pseries 2003 Corporation pseries, Systems Group KwanYong Lee / lky@kr kr.ibm.com Product Line Manager, pseries June 12, 2003 2003 Corporation pseries, Systems Group pseries 2003