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Itroductio The field effect trasistor(fet) is a uiolar device because, ulike biolar trasistor that use both electro ad hole curret, they oerate oly with oe tye of charge carrier. (BJT) (FET).

1 Itroductio The field effect trasistor(fet) is a uiolar device because, ulike biolar trasistor that use both electro ad hole curret, they oerate oly with oe tye of charge carrier. (BJT) (FET). The two mai tyes of FETs are the juctio field effect trasistor(jfet) ad the metal oxide semicoductor field effect trasistor(mosfet). 2 (JFET) (MOSFET). The BJT is a curretcotrolled device; that is, the base curret cotrols the amout of collector curret. BJT. O the cotrary, the FET is a voltagecotrolled device, where the voltage betwee two of the termials(gate ad source) cotrols the curret through the device., FET (V GS ) (I D ). 93

2 (Juctio field effect trasistor) Figure 132(a) shows the basic structure of a chael juctio field effect trasistor(jfet). 132(a) (JFET). Drai(D) Drai(D) Gate (G) chael Gate (G) chael (a) chael (b) chael Source(S) Source(S) Figure 132. A reresetatio of the basic structure of the two tyes of JFET. 94

3 Wire leads are coected to each ed of the chael; the drai is at the uer ed, ad the source is at the lower ed.,,. Two tye regios are diffused i the tye material to form a chael, ad both tye regios are coected to the gate lead.,. A chael JFET is show i Figure 132(b). JFET 132(b). The schematic symbols for both chael ad chael JFETs are show i Figure 133. JFET 133. Notice that the arrow o the gate oits i for chael ad out for chael.,. 95

4 D D G G chael S chael S Figure 133. JFET schematic symbols. 96

5 JFET (JFET basic oeratio) To illustrate the oeratio of a JFET, Figure 134 shows bias voltages alied to a chael device. JFET, 134. R D D G V GS S Figure 134. A biased chael JFET. 97

6 is a draitosource voltage ad sulies curret from drai to source., (I D ). V GS sets the reversebias voltage betwee the gate ad the source, as show. V GS. The JFET is always oerated with the gatesource juctio reversebiased. JFET. Reversebiasig of the gatesource juctio with a egative gate voltage roduces a deletio regio alog the juctio, which exteds ito the chael ad thus icreases its resistace by restrictig the chael width. (),. The chael width ad thus the chael resistace ca be cotrolled by varyig the gate voltage, thereby cotrollig the amout of drai curret, I D., I D. 98

7 Figure 135 illustrates this cocet R D R D V GS V GS D I D D I D G G V GS S V GS S (a) JFET biased for coductio (b) Greater V GS arrows the chael which icreases the resistace of the chael ad decreases I D. Figure 135. Effect of V GS o chael width, resistace, ad drai curret. 99

8 The white areas rereset the deletio regio created by the reverse bias.. V GS V GS G D S R D I D (c) Less V GS wide the chael which decreases the resistace of the chael ad Icreases I D. It is wider toward the drai ed of the chael because the reversebias voltage betwee the gate ad the drai is greater tha that betwee the gate ad the source. (V GD ) (V GS ). Pichoff,.. Figure 135. Effect of V GS o chael width, resistace, ad drai curret. 100

9 JFET (JFET characteristics) First, let s cosider the case where the gatesource voltage is zero(v GS =0)., 136 (V GS ) 0. R D I D V GD I D B C V GS =0 Ohmic regio Costatcurret regio (ichoff regio) Break dow V P (ichoff voltage) A (a) JFET with V GS =0 ad a variable (b) Drai characteristics curve Figure 136. The drai characteristics curve of o JFET for V GS =0 showig ichoff. 101

10 As is icreased from zero, I D will icrease roortioally through the tye material, as show i the grah of Figure 136(b) betwee oits A ad B. I D 136(b) A, B. I this regio, the chael resistace is essetially costat because the deletio regio is ot large eough to have sigificat effect.,. This is called the ohmic regio because ad I D are related by Ohmic law. I D. As icreases from oit B to C, the reversebias voltage from gate to drai(v GD ) roduces a deletio regio large eough to offset the icrease i, thus keeig I D relatively costat. (B C ), V GD I D. For V GS =0[V], the value of at which I D becomes essetially costat is the ichoff voltage. V GS =0[V], I D (V P ). 102

11 Now, let s coect a bias voltage, V GS, as show i Figure 136(a)., V GS 137. I D V P R D I D(sat) V GS =0[V] V GS =1[V] V GS Pichoff whe V GS =1[V] V GS =2[V] V GS =3[V] V GS =4[V] (a) JFET biased V GS =1[V] V GS =V GS(off) V P (b) Family of drai characteristics curve Figure 137. The drai characteristics curve of o JFET for V GS =0 showig ichoff. 103

12 As V GS is set to icreasigly more egative values, a family of drai characteristic curves is roduced, as show i Figure 137(b). V GS (), 137(b). I D decreases as the magitude of V GS is icreased to larger egative values because of the arrowig of the chael. I D V GS. Also, for each icrease i V GS, the JFET reaches ichoff at value of less tha V P. V GS, JFET V P. So, the amout of drai curret(i D ) is cotrolled by V GS., (I D ) (V GS ). The value of V GS that makes I D aroximately zero is the cutoff voltage, V GS(off). I D 0 V GS, V GS(off). The JFET must be oerated betwee V GS =0[V] ad V GS(off). JFET V GS 0[V] V GS(off). For this rage of V GS, I D will vary from a maximum of I D(sat) to a miimum of almost 0. V GS, I D I D(sat)

13 (Metal (MetalOxideSemicoductor FET) The MOSFET differ from the JFET i that it has o juctio structure; istead, the gate of the MOSFET is isulated from the chael by a silico dioxide(sio 2 ) layer. MOSFET JFET., MOSFET SiO 2. Drai(D) Drai(D) SiO 2 chael SiO 2 chael Gate (G) Gate (G) tye substrate tye substrate (a) chael (b) chael Source(S) Source(S) Figure 138. Reresetatio of the basic structure of DMOSFET. 105

14 MOSFET(Deletio MOSFET, DMOSFET) D Oe tye of MOSFET is the deletio MOSFET(DMOSFET) ad Figure 138 illustrates its basic structure. MOSFET MOSFET(DMOSFET), 138. The drai ad source are diffused ito the substrate material ad the coected by a arrow chael adjacet to the isulated gate., SiO 2. The chael oeratio is the same, excet the voltage olarities are oosite those of the chael.. The DMOSFET ca be oerated i either of two modes the deletio mode or the ehacemet mode. DMOSFET,,. 106

15 Sice the gate is isulated from chael, either a ositive or a egative gate voltage ca be alied., () (). The chael MOSFET oerates i the deletio mode whe a egative V GS is alied ad i the ehacemet mode whe a ositive V GS is alied. MOSFET () V GS, () V GS. These devices are geerally oerated i the deletio mode.. Visualize the gate as oe late of a arallellate caacitor ad the chael as the other late.,. The SiO 2 isulatig layer is the dielectric. SiO

16 With a egative gate voltage, the egative charges o the gate reel coductio electros from the chael, leavig ositive ios i their lace. (),. Thereby, the chael is deleted of some of its electros, thus decreasig the chael coductivity.. The greater the egative voltage o the gate, the greater the deletio of chael electros. (). At a sufficietly egative V GS, the chael is totally deleted ad the drai curret is zero. () V GS, I D 0.<V GS(off) > This deletio mode is illustrated i Figure 139(a). DMOSFET 139(a). 108

17 R D R D I D I D V GS V GS (a) Deletio mode: VGS egative (b) Ehacemet mode: VGS ositive Figure 139. Oeratio of chael DMOSFET. 109

18 With a ositive gate voltage, more coductio electros are attracted ito the chael, thus ehacig the chael coductivity, as illustrated i Figure 139(b). (), 139(b).< DMOSFET> Drai Drai Gate Gate chael Source chael Source Figure 140. DMOSFET schematic symbols. 110

19 MOSFET(Ehacemet MOSFET, EMOSFET) E The EMOSFET oerates oly i the ehacemet mode ad has o deletio mode. EMOSFET. Gate (G) SiO 2 Drai(D) Iduced chael tye substrate V GS I D R D Source(S) (a) Basic costructio (b) Iduced chael Figure 141. EMOSFET costructio ad oeratio(chael). 111

20 It differs i costructio from the DMOSFET i that it has o structural chael. EMOSFET DMOSFET. For a chael device, a ositive gate voltage above a threshold value iduces a chael by creatig a thi layer of egative charges i the substrate regio adjacet to the SiO 2 layer, as show i Figure 141(b)., () 141(b) SiO 2 () ( ). The coductivity of the chael is ehaced by icreasig the V GS ad thus ullig more electros ito the chael area. V GS,. For ay gate voltage below the threshold value, there is o chael.. The schematic symbols for the chael ad chael EMOSFETs are show i Figure 142. EMOSFET

21 Drai Drai Gate Gate chael Source chael Source Figure 142. EMOSFET schematic symbols. The covetioal ehacemet MOSFETs have a log thi lateral chael as show i structural view i Figure 143. MOSFET 143. This results i a relatively high draitosource resistace ad limited the EMOSFET to low ower alicatios., EMOSFET. 113

22 Source Gate Drai tye substrate chael SiO 2 Figure 143. Cross sectio of covetioal EMOSFET structure. 114

Microsoft PowerPoint - ch03ysk2012.ppt [호환 모드]

Microsoft PowerPoint - ch03ysk2012.ppt [호환 모드] 전자회로 Ch3 iode Models and Circuits 김영석 충북대학교전자정보대학 2012.3.1 Email: kimys@cbu.ac.kr k Ch3-1 Ch3 iode Models and Circuits 3.1 Ideal iode 3.2 PN Junction as a iode 3.4 Large Signal and Small-Signal Operation