-. emlinux,......,..,..,.

Transcription

1 U-BOOT bsplinux,..

2 -. emlinux,......,..,..,.

3 -BOOT bzip2 d u-boot tar.bz2 tar tar xvf u-boot tar make clobber => make clean make smdk2410_config => arch. & board make (TOPDIR)/inculde/arm/configs/smdk2410.h -> (TOPDIR)/inculde/config.h (top directory) uboot => ELF format u-boot.bin => binary format u-boot.srec =>S.recode format (motorola serial downloading image file) Make u-boot.dis => dis-assembler

4 tool.tools to build S-Record or U-Boot images, etc. U-BOOT -BOOT U-boot board common cpu disk doc driver dtt examples fs include Lib_arm net post rtc.board.architecture.architecture.code for disk drive partition handling.uboot. driver. sensor( ) driver.uboot test.uboot file system.header file.arm architecture.network.power On Self Test.real time clock driver

5 -BOOT hardware point Boot loder handling hardware list core Processor mode Interrupt Cache,mmu SOC Interrupt,watchdog Clock Memory interface(dram controller) TIMER UART RTC Flash NAND Flash Ethernet controller RTC LCD Controller Keyboard controller

6 oard (smdk2410->atb-2410x)(1) Board directory (TOPDIR)/board sub borad.. Board smdk2410 re-name. Ex)(TOPDIR)/board/atb2410 Board header file (TOPDIR)/include/configs/smdk2410.h re-name(ex:atb2410.h). #define CONFIG_SMDK => #define CONFIG_ATB (TOPDIR)/cpu/arm920t/interrupts fileget_tbclk() CONFIG_ATB2410. (TOPDIR)Makefile smdk2410_config: $(@:_config=) arm arm920t smdk2410. atb2410_config: $(@:_config=) arm arm920t atb2410

7 oard (smdk2410->atb-2410x)(2) (TOPDIR)/include/configs/Atb2410.h (sdram 32Mbyte,flash sst(39vf160) 2Mbyte) #define CONFIG_INIT_CRITICAL /* undef for developing(dram loading) */ #define CONFIG_ARM920T 1 /* This is an ARM920T Core */ #define CONFIG_S3C /* in a SAMSUNG S3C2410 SoC */ /*#define CONFIG_SMDK2410 1*/ /* on a SAMSUNG SMDK2410 Board */ #define CONFIG_ATB /* input clock of PLL */ #define CONFIG_SYS_CLK_FREQ /* the SMDK2410 has 12MHz input clock atb241012mhz clock #define USE_920T_MMU 1 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff IRQ /* * Size of malloc() pool 128kbyte #define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)

8 oard (smdk2410->atb-2410x)(3) (TOPDIR)/include/configs/ Atb2410.h /* Hardware drivers */ #define CONFIG_DRIVER_CS8900 cs8900 /*#define CS8900_BASE cs8900 base address #define CS8900_BASE test #define CS8900_BUS16 16bit data-bus /* * select serial console configuration */ #define CONFIG_SERIAL1 console s3c2410uart0 /************************************************************ * RTC ************************************************************/ #define s3c2410 RTC /* allow to overwrite serial and ethaddr */ #define not used #define CONFIG_BAUDRATE consoleuartbaud rate

9 oard (smdk2410->atb-2410x)(4) (TOPDIR)/include/configs/ Atb2410.h /* Command definition*/ #define CONFIG_COMMANDS \ (CONFIG_CMD_DFL default configs CFG_CMD_CACHE icache,dcache command CFG_CMD_REGINFO register information command CFG_CMD_DATE RTC,date,time command CFG_CMD_ELF) /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> #define CONFIG_BOOTDELAY boot delay 3 /*#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttysa0,9600" */ /*#define CONFIG_ETHADDR 08:00:3e:26:0a:5b */ #define CONFIG_NETMASK #define CONFIG_IPADDR #define CONFIG_SERVERIP /*#define CONFIG_BOOTFILE "elinos-lart" */ /*#define CONFIG_BOOTCOMMAND "tftp; bootm" */

10 oard (smdk2410->atb-2410x)(5) (TOPDIR)/include/configs/ 1Mbyteboot loader #define command help /*#define CFG_PROMPT "SMDK2410 # prompt text #define CFG_PROMPT ATB2410 # #define CFG_CBSIZE consolei/o buffer #define CFG_PBSIZE print buffer size #define CFG_MAXARGS command #define CFG_BARGSIZE boot Argument buffer size #define CFG_MEMTEST_START sdram memory start test addr. /*#define CFG_MEMTEST_END sdram memory end addr.(63m) #define CFG_MEMTEST_END atb2410 ->31Mbyte #undef not used /*#define CFG_LOAD_ADDR 0x */ /* default load address */ #define CFG_LOAD_ADDR 0x /* the PWM TImer 4 uses a counter of for 10 ms, so we need */ /* it to wrap 100 times (total ) to get 1 sec. */ #define CFG_HZ 1sec /* valid baudrates */ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, baud rate

11 oard (smdk2410->atb-2410x)(6) (TOPDIR)/include/configs/ Atb2410.h / * Stack sizes * * The stack sizes are set up in start.s using the settings below */ #define CONFIG_STACKSIZE (128*1024) /* regular stack */ #ifdef CONFIG_USE_IRQ #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ #endif /* * Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ #define PHYS_SDRAM_1 0x /* SDRAM Bank #1 */ /*#define PHYS_SDRAM_1_SIZE 0x *//* 64 MB */ #define PHYS_SDRAM_1_SIZE 0x /* 32 MB */ #define PHYS_FLASH_1 0x /* Flash Bank #1 */ #define CFG_FLASH_BASE PHYS_FLASH_1

12 oard (smdk2410->atb-2410x)(7) (TOPDIR)/include/configs/ Atb2410.h / * FLASH and environment organization */ /*#define CONFIG_AMD_LV400 1 /* uncomment this if you have a LV400 flash */ #if 0 #define CONFIG_AMD_LV800 1 /* uncomment this if you have a LV800 flash */ #endif*/ #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ /*#ifdef CONFIG_AMD_LV800*/ /*#define PHYS_FLASH_SIZE 0x */ /* 1MB */ #define PHYS_FLASH_SIZE 0x /* 2MB */ /*#define CFG_MAX_FLASH_SECT (19) *//* max number of sectors on one chip */ #define CFG_MAX_FLASH_SECT (32) /*39VF160 64K x 32 = 2Mbyte*/ /*#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x0F0000) *//* addr of environment */ #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x1F0000) /*64Kbyte*/ /*#endif #ifdef CONFIG_AMD_LV400 #define PHYS_FLASH_SIZE 0x /* 512KB */ #define CFG_MAX_FLASH_SECT (11) /* max number of sectors on one chip */ #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x070000) /* addr of environment */ #endif*/

13 oard (smdk2410->atb-2410x)(8) (TOPDIR)/include/configs/ Atb2410.h /* timeout values are in ticks */ #define CFG_FLASH_ERASE_TOUT (5*CFG_HZ) /*5sec, Timeout for Flash Erase */ #define CFG_FLASH_WRITE_TOUT (5*CFG_HZ) /*5sec,Timeout for Flash Write */ #define CFG_ENV_IS_IN_FLASH flash ( :eeprom,nvram) #define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector 64Kbyte #endif /* CONFIG_H */

14 oard (smdk2410->atb-2410x)(9) (TOPDIR)/board/atb2410/ config.mk # # SMDK2410 has 1 bank of 64 MB DRAM # atb2410 has 1 bank of 32 MB DRAM # 3000'0000 to 3400'0000 # 3000'0000 to 3200'0000 # Linux-Kernel is expected to be at 3000'8000, entry 3000'8000 # optionally with a ramdisk at 3080'0000 # # we load ourself to 33F8'0000 # we load ourself to 31F8'0000 # download area is 3300'0000 # download area is 3100'0000 /*TEXT_BASE = 0x33F80000*/ TEXT_BASE = 0x31F80000 /* u-boot sdram start address*/

15 -boot.lds(1) (TOPDIR)/board/smdk2410/u-boot.lds Start.S (TOPDIR)/board/smdk2410/u-boot.lds, LD(loader&Linker)input,object.. OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") /*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/ OUTPUT_ARCH(arm) ENTRY(_start) SECTIONS {. = 0x ;. = ALIGN(4);.text : { cpu/arm920t/start.o (.text) *(.text). = ALIGN(4);.rodata : { *(.rodata). = ALIGN(4);.data : { *(.data). = ALIGN(4);.got : { *(.got) armboot_end_data =.;. = ALIGN(4);.bss : { *(.bss) armboot_end =.;

16 -boot.lds(2) (TOPDIR)/cpu/arm920t/start.S OUTPUT_FORMATELF32little endian. OUTPUT_ARCHbinary CPU architecturearm. ENTRY pointprogram, _start. SECTIONS,text,rodata,data,got,bss section..text :.rodata: read-only data (const ).data: initialized data.got: global offset table.bss: uninitialized data dot `.' address point. address point. `*'. `*(.text)' `.text'. 0x byte text section. U-boot Entry point _start. _start(topdir)/cpu/arm920t/start.s. TEXT_BASE Linkersymbol. Poweron 0x00 (,flash) memory flash dramrelocate dram. Symbol TEXT_BASE, dramrelocate offset branch.(b,bl,adr)

17 (TOPDIR)/CPU/arm920t directory Stats.S Cpu.c Speed.c Interrupts.c Serial.c

18 tart.s (1) (TOPDIR)/cpu/arm920t/start.S ARM processpower on(reset)actions r14_svc(lr) <= value SPSR_svc <= CPSR( mode) CPSR[4:0] <= 0b10011(Supervisor mode) CPSR[5] <= 0 (T bit = ARM state) CPSR[6] <= 1 (F bit) CPSR[7] <= 1 (I bit) PC = 0x0 (Vector Table) Supervisor mode,arm state,pc 0x0 Linker script fileentry point _start..globl flash start _start: b offset jump dram. ldr pc, _undefined_instruction ldr pc, _software_interrupt ldr pc, _prefetch_abort ldr pc, _data_abort ldr pc, _not_used ldr pc, _irq ldr pc, _fiq

19 tart.s (2) (TOPDIR)/cpu/arm920t/start.S.global _start Linker _start symbol export. _start instruction b reset branch reset. ARM exception routine exception branch. _undefined_instruction _software_interrupt _prefetch_abort _data_abort _not_used _irq _fiq

20 tart.s (3) (TOPDIR)/cpu/arm920t/start.S CPSR N Z C V Q J Undefined Undefined I F T Mode CPSR_f CPSR_s CPSR_x CPSR_c MODE

21 tart.s (3) (TOPDIR)/cpu/arm920t/start.S Reset () => mode setting interrupt disable reset:/*set the cpu to SVC32 mode*/ mrs cpsr r0. bic Mode bitclear. orr interrupt disable,supervisor mode msr r0 cpsr. #if defined(config_s3c2400) #define pwtcon turn off the watchdog #define INTMSK Interupt-Controller base addresses #define CLKDIVN clock divisor register #elif defined(config_s3c2410) #define pwtcon Watchdog Timer Mode #define INTMSK Interrupt Mask Control #define INTSUBMSK Interrupt sub mask #define CLKDIVN clock divisor Control #endif

22 tart.s (4) (TOPDIR)/cpu/arm920t/start.S Reset ()=> Watchdog disable & all interrupt source masking ldr r0, 0x mov r1, #0x0 str r1, watchdog timerdisable. /* * mask all IRQs by setting all bits in the INTMR - default */ mov r1, #0xffffffff ldr r0, 0x4A str r1, interrupt masking.(disable) #if defined(config_s3c2410) ldr r1, =0x3ff ldr r0, 0x4A00001C str r1, cpus3c2410 sub interruptmasking. #endif

23 tart.s (5) (TOPDIR)/cpu/arm920t/start.S Reset () => Clock setting CLKDIVN (CLOCK DIVIDER CONTROL REGISTER) 0x4C [2] reserved [1] HDIVN : 0 [HCLK = FCLK], 1 [HCLK = FCLK/2] [0] PDIVN : 0 [PCLK = HCLK], 1 [PCLK = HCLK/2] FCLK,HCLK,and PCLK FCLK : ARM920T. HCLK : AHB bus.(memory,interrupt,lcd,dma, USB Host controller) PCLK : APB bus.(wdt,iis,i2c,pwm timer,mmc,adc,uart,gpio,rtc,spi) HDIVN PDIVN FCLK HCLK PCLK Divide Ratio 0 0 FCLK FCLK FCLK 1:1:1(default) 0 1 FCLK FCLK FCLK/2 1:1:2 1 0 FCLK FCLK/2 FCLK/2 1:2:2 1 1 FCLK FCLK/2 FCLK/4 1:2:4 (recommended) POWER MODE = NORMAL MODE FCLK = MPLL clock(mpll). PLL Control Register(MPLLCON and UPLLCON) Mpll = (m * Fin)/(p * 2 s ) m = (MDIV + 8), p = (PDIV + 2), s = SDIV, Fin =

24 tart.s (5) (TOPDIR)/cpu/arm920t/start.S Reset () => Clock setting MPLLCON 0x4c [19:12] => MDIV(Main divider) : initial value (0x5c) [9:4] => PDIV(pre-divider control) : initial value (0x08) [1:0] => SDIV(Post divider control) : initial value (0x00) Mpll = (m * Fin)/(p * 2 s) m = (0x5c + 8), p = (0x08 + 2), s = 0x00, Fin = 12Mhz Mpll = (m(100) * Fin(12Mhz)) / (p(10) * 2 0) => 1200Mhz / 10 =>120Mhz FCLK = 120Mhz /* FCLK:HCLK:PCLK = 1:2:4 */ /* default FCLK is 120 MHz! */ ldr r0, 0x4C mov r1, HDIVN,PDIVN 1setting str r1, FCLK:HCLK:PCLK = 1:2:4 (120M:60M:30MHz) #ifdef (TOPDIR)/inculde/configs/smdk2410.h bl sub rountine cpu_init_crit. #endif

25 tart.s (6) (TOPDIR)/cpu/arm920t/start.S Reset () => Memory setting(1) <MCR MRC>{cond p#,<expression1>,rd,crn,crm{,<expression2> MRC : coprocessor registercpu register (L=1) MCR : CPU register coprocessor register (L=0) {cond : Two character condition mnemonic p# : coprocessor <opcode_1> : coprocessor-specific opcode. <opcode_1> 0. Rd : CPU register number crn and crm : coprocessor register numbers <opcode_2> : coprocessor-specific opcode.. CP15 REGISTER MAPs3c2410 manual. REGISTER1(c1) : CONTROL REGISTER => page 2-10 REFISTER7(c7) : CACHE OPERATIONS => page 2-15 REFISTER8(c8) : TLB OPRERATIONS => page 2-18

26 tart.s (7) (TOPDIR)/cpu/arm920t/start.S Cpu_init_crit () => Memory initialize (1) cpu_init_crit:- mov r0, flush:,. mcr p15, 0, r0, c7, c7, flush v4 I/D caches mcr p15, 0, r0, c8, c7, flush v4 s3c2410 datasheet p2-4 mrc p15, 0, r0, c1, c0, disable MMU stuff and caches bic r0, r0, clear bits 13, 9:8 (--V- --RS) bic r0, r0, clear bits 7, 2:0 (B--- -CAM) orr r0, r0, set bit 2 (A) orr r0, r0, set bit 12 (I) I-Cache enable mcr p15, 0, r0, c1, c0, 0 mov ip, BL lrip bl SDRAM initialize sub rountine. mov lr, sub rountine pc - mov pc, ip lr pc,return.

27 U-BOOT emsetup.s (1) (TOPDIR)/board/smdk2410/memsetup.S memsetup() => Memory Bank initialize(bank0 Bank7) define BWSCON * BWSCON */ define DW8 define DW16 define DW32 define WAIT define UBLB 0x (0x0) (0x1) (0x2) (0x1<<2) (0x1<<3) define B1_BWSCON (DW32) /* bank 1 32bit data bus width */ define B2_BWSCON (DW16) define B3_BWSCON (DW16 + WAIT + UBLB) define B4_BWSCON (DW16) define B5_BWSCON (DW16) define B6_BWSCON (DW32) define B7_BWSCON (DW32) * BANK0CON */ define B0_Tacs 0x0 /* 0clk */ define B0_Tcos 0x0 /* 0clk */ define B0_Tacc 0x7 /* 14clk */ define B0_Tcoh 0x0 /* 0clk */ define B0_Tah 0x0 /* 0clk */ define B0_Tacp 0x0 define B0_PMC 0x0 /* normal */

28 emsetup.s (2) (TOPDIR)/board/smdk2410/memsetup.S memsetup() => Memory Bank initialize(bank0 Bank7) * BANK1CON */ define B1_Tacs 0x0 /* 0clk */ define B1_Tcos 0x0 /* 0clk */ define B1_Tacc 0x7 /* 14clk */ define B1_Tcoh 0x0 /* 0clk */ define B1_Tah 0x0 /* 0clk */ define B1_Tacp 0x0 define B1_PMC 0x0 * BANK2CON */ * BANK3CON */ define B3_Tacs 0x0 /* 0clk */ define B3_Tcos 0x3 /* 4clk */ define B3_Tacc 0x7 /* 14clk */ define B3_Tcoh 0x1 /* 1clk */ define B3_Tah 0x0 /* 0clk */ define B3_Tacp 0x3 /* 6clk */ define B3_PMC 0x0 /* normal */ * BANK4CON */ * BANK5CON */

29 U-BOOT emsetup.s (1) (TOPDIR)/board/smdk2410/memsetup.S memsetup() => Memory Bank initialize(bank0 Bank7) K4S561632C-TC75 133Mhz clock cycle 7.5ns(1/133M), Trcd(RAS to CAS delay) 20ns, Trp(row precharge time) 20ns Trc (Row Cycle Time) 65ns, Refresh period 64ms, row addr. Ra0 Ra12, column addr. Ca0 Ca8 define B6_MT SDRAM select define B6_Trcd 20ns / 7.5ns => 2.66 cycle=>3cycle define B6_SCAN column addr. Ca0 Ca8 => 9bit define B7_MT SDRAM select define B7_Trcd 20ns / 7.5ns => 2.66 cycle=>3cycle define B7_SCAN column addr. Ca0 Ca8 => 9bit * REFRESH parameter */ define REFEN Refresh enable define TREFMD CBR(CAS before RAS)/Auto refresh define Trp 20ns / 7.5ns => 2.66 cycle=>3cycle?? 2 clk define Trc 65ns / 7.5ns => 8.66 cycle => 9cycle?? 7clk define Tchr 3clk, reserved?? * period=15.6us(1/64ms), HCLK=60Mhz, ( *60) */ define REFCNT 1113

30 emsetup.s (5) (TOPDIR)/board/smdk2410/memsetup.S memsetup() => Memory Bank initialize(bank0 SMRDATAmemory flash TEXT_BASE:.word TEXT_BASE globl Linker memsetup symbol export. memory control r0.flash_start ex) SMRDATA(33f80420) - TEXT_BASE(33f80000) = 0x ldr r0, literal pools data(=)addressr0 Ldr r1, _TEXT_BASE@ _TEXT_BASE address r1 Sub r0, r0, r0. Ldr r1, Bus Width Status Control Registerbase addressr1. add r2, r0, 13 word Registerr0 register r2 compare setting(end address) ldr r3, [r0], r0 address r3r0 4. str r3, [r1], r1 addressr3 r1 4. cmp r2, r2,r0 CPSRsetting bne loop,13 memory. mov pc, memsetup cpu_init_crit

31 emsetup.s (4) (TOPDIR)/board/smdk2410/memsetup.S memsetup() => Memory Bank initialize(bank0 Bank7) 0x MRDATA:.word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20) \ +(B6_BWSCON<<24)+(B7_BWSCON<<28)).word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)).word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)).word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)).word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)).word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)).word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)).word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)).word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)).word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT).word 128MB/128MB, SCLKaccess active, SDRAM power down mode, burst disable.word burst type(sequential), CAS latency 3.word burst type(sequential), CAS latency 3

32 tart.s (8) (TOPDIR)/cpu/arm920t/start.S relocate() => armboot ram relocate armboot to _startldr memory flash loading adr r0, => SUB r0, PC, #offset to _Start,_start address ldr r2, _startaddress (0x33f80000),system.map ldr r3, armboot_end(0x33f995c8), linker script sub r2, r3, r2 <- armboot memory size ldr r1, r1 <- destination address add r2, r0, r2 <- source end address /* * r0 = source address * r1 = target address * r2 = source end address */ opy_loop: ldmia r0!, r0 address r3-r10,write back stmia r1!, r1 addressr3-r10,write back cmp r0, destination addresssource end address check ble armboot memory size loop.

33 tart.s (9) (TOPDIR)/cpu/arm920t/start.S relocate() => stack address c routine jump Stack point 3word abort exception exception PC CPSR debug. Stack point C routine board.c start_armboot branch. *CONFIG_STACKSIZE (128*1024), (TOPDIR)/include/configs/smdk2410.h*/ * set up the stack */ ldr r0, linker script add r0, r0, #CONFIG_STACKSIZE sub sp, r0, leave 3 words for abort-stack ldr pc, dram. start_armboot:.word

34 tart.s (9) (TOPDIR)/cpu/arm920t/start.S relocate() => map(smdk2410 ) 1Mbyte Stack(128K) armboot 0x armboot_end + 128Kb.armboot_end + 128Kb - 12.armboot_end 0x33f80000.armboot_end U-boot Code area FLASH 0x SDRAM(64Mbyte) 0x

35 tart.s (10) (TOPDIR)/cpu/arm920t/start.S Start_armboot exception routine. Arm exception. Undefined instruction exception IRQ exception.

36 tart.s (11) (TOPDIR)/cpu/arm920t/start.S Undefined instruction exception coprocessor. instruction. CPU actions r14_und = undefined instruction + 4 SPSR_und = CPSR CPSR[5:0] = 0b CPSR[6] = unchanged CPSR[7] = 1 PC = 0x4 /* exception 25, 0..align 5 undefined_instruction: macro macro bl C routine

37 tart.s (12) (TOPDIR)/cpu/arm920t/start.S Macro get_bad_stack.macro und mode ldr r13, r13_und armboot_end addressload. add r13, r13, r13_und <= r13_und + 128Kbyte sub r13, r13, r13_und <= r13_und - 8 str lr, r13_und addresslr_und. mrs lr, r13_und address4 str lr, [r13, mode. mov r13, r13_und SVC-Mode value. msr spsr, spsr_und r13_und. mov lr, lr_und pc 8. movs pc, SVS instruction undefined exception, undefined instruction PC stack supervisor *_undundefined excetion, macro exception.

38 tart.s (13) (TOPDIR)/cpu/arm920t/start.S Macro bad_save_user_regs.macro SVC mode sub sp, sp, stack point (sp_svc) 72(18words). stmia sp, {r0 - r0-r12 stack. ldr r2, r2 armboot_end addressload. add r2, r2, r2 <= r Kbyte sub r2, r2, r2 <= r2-8 ldmia r2, {r2 - pc(lr_und) -> r2, cpsr(spsr_und) ->r3 add r0, sp, stack point(sp_svc) + S_FRAME_SIZE -> r0 add r5, sp, r0-r12 stack mov r1, lr_svc -> r1 stmia r5, {r0 - sp_svc, lr_svc, pc, cpsrstack mov r0, base undefined intruction base do_undefined_instruction() -> (TOPDIR)/cpu/arm920t/interrupts.c

39 tart.s (14) (TOPDIR)/cpu/arm920t/start.S Do_undefined_instruction Pt_regs Stack. Exception. (TOPDIR)/include/asm-arm/proc-armv/ptrace.h struct pt_regs { long uregs[18]; ; (TOPDIR)/cpu/arm920t/interrupts.c void do_undefined_instruction (struct pt_regs *pt_regs) { printf ("undefined instruction\n"); show_regs (pt_regs); bad_mode ();

40 tart.s (15) (TOPDIR)/cpu/arm920t/interrupts.c.armboot_end+ 128Kb Spsr_und Lr_und top top-4 top-8 CPSR(spsr_und) PC(lr_und) Lr_SVC Stack(128Kb) Sp_SVC Sp_SVC r12 r11 S_FRAME 18words r10 r9 r8.armboot_end Sp_SVC- 72 r7 r6 r5 r4 r3 r2 r1 r0 SER mode(exception ) Undefined instruction mode SVC mode

41 tart.s (11) (TOPDIR)/cpu/arm920t/start.S IRQ exception IRQ pinactive. CPU actions r14_irq = address of next inst. to be executed + 4 SPSR_irq = CPSR CPSR[5:0] = 0b CPSR[6] = unchanged CPSR[7] = 1 PC = 0x18 irq:.align 5 get_irq_stack irq_save_user_regs bl do_irq irq_restore_user_regs

42 tart.s (12) (TOPDIR)/cpu/arm920t/start.S Macro get_irq_stack #ifdef CONFIG_USE_IRQ /* IRQ stack memory (calculated at run-time) */.globl IRQ_STACK_START (TOPDIR)/cpu/arm920t/cpu.c (TOPDIR)/lib_arm/board.c start_armboot() interruptenable. int cpu_init (TOPDIR)/include/configs/smdk2410.h { / * setup up stack if CONFIG_STACKSIZE_IRQ,_FIQ(4*1024) #ifdef CONFIG_USE_IRQ IRQ_STACK_START = _armboot_end + CONFIG_STACKSIZE + CONFIG_STACKSIZE_IRQ - 4; FIQ_STACK_START = IRQ_STACK_START + CONFIG_STACKSIZE_FIQ; _armboot_real_end = FIQ_STACK_START + 4; #else _armboot_real_end = _armboot_end + CONFIG_STACKSIZE; #endif /* CONFIG_USE_IRQ */ return (0);

43 tart.s (13) (TOPDIR)/cpu/arm920t/start.S Macro irq_save_user_regs.macro get_irq_stack ldr sp, setup IRQ stack.macro irq_save_user_regs sub sp, sp, stack point (sp_irq) 72(18words). stmia sp, {r0 - r0-r12 stack. add r8, sp, R8 <- sp_irq + S_PC(60) stmdb r8, {sp, sp_usr, lr_usrr8 stack point-12 str lr, [r8, r8 stack point lr_irq mrs r6, spsr str r6, [r8, (r8 + 4) stack point spsr_irq str r0, [r8, (r8 + 8) stack point R0 (OLD_R0) mov r0, base addressr0.endm

44 tart.s (14) (TOPDIR)/cpu/arm920t/start.S Macro irq_restore_user_regs void do_irq (struct pt_regs *pt_regs) { printf ("interrupt request\n"); show_regs (pt_regs); bad_mode ();.macro irq_restore_user_regs ldmia sp, {r0 - user mode r0-lr stack mov r0, dummy instruction ldr lr, [sp, stack lr_irq lr_irq,lr_irq => add sp, sp, sp_irq stack. subs pc, lr, spsr_irqcpsr return..endm

45 tart.s (15) (TOPDIR)/cpu/arm920t/interrupts.c Stack(4Kb) FIQ Stack(4Kb) IRQ Stack(128Kb).armboot_real_end.stack_fiq_end.stack_irq_end.stack_end S_FRAME 18words Sp_irq Sp_irq- 72 OLD_R0(r0_irq) CPSR(spsr_irq) PC(lr_irq) Lr(old lr) Sp(old sp) r12 r11 r10 r9 r8 r7 r6.armboot_end r5 r4 r3 r2 r1 r0 USER mode(irq ) IRQ mode USER -mode

46 tart.s (16) (TOPDIR)/cpu/arm920t/start.S Void reset_cpu(ulong addr).align 5.globl reset_cpu reset_cpu: #ifdef 2410 #else /*! CONFIG_S3C2400 */ mov ip, #0 mcr p15, 0, ip, c7, c7, I&D cache flush. mcr p15, 0, ip, c8, c7, I&D TLB (v4)flush. mrc p15, 0, ip, c1, c0, get ctrl register bic ip, ip, Little endian, data cache, fault check, mmu disable bic ip, ip, exception ->low address,inst. Cache disable mcr p15, 0, ip, c1, c0, ctrl register mov pc, r00software reset. #endif /* CONFIG_S3C2400 */

47 (1).. OUTPUT INPUT asm volatile ( asms: output : input : clobber); asm :. ANSI asm asm keyword. volatile :.. asms :. %x input,output. Output :,.. Input : output. Clobber : output,input asms..

48 (2) Asms output, input, clobber. clobber clobber (:). input,clobber output. output,clobber input input. asm volatile (asms : output: : clobber); asms AT&T gasm gasm. (;) (\n). %0,%1 input,output. Output input %0,%1,. \t\n. OUTPUT/INPUT Output,inputconstraints. Constraints modifier.

49 U-BOOT (3) Constraints(gnu- gcc manual, info gcc) m : o : V : < : (.) > : (.) r : d, a, f, : I : immediate.. n : immediate. i n. I, J, K, P : E : immediate. F : immediate G, H : s : immediate g :, immediate

50 U-BOOT (4) Constraints(gnu- gcc manual, info gcc) 0, 1, 2, 9 :. p :. load address push address. Q, R, S, U : ARM Family Constaints f : F : 0.0, 0.5, 1.0, 2.0, 3.0, 4.0, 5.0, 10.0 G : F I : immediate J : K : I 1. L : I (2 ) M : 0 32 Q : R : constant pool S :

51 (5) Modifier(gnu- gcc manual, info gcc) = :.. + :,. = output + input/output. input. & : earlyclobber input. input. Gccinput output input output outputinput. output input inputoutput. % : %. # : # Constraints.

52 pu.c (1) (TOPDIR)/cpu/arm920t/cpu.c Co-processor 15, register #1(control register) bit name function Value RST Int 1 ia bit Asynchronous clock select ia:0 nf:0 = FastBus, ia:1 nf:0 = Reserved nf bit notfastbus select ia:0 nf:1 = Sync., ia:1 nf:1 = Async :15 - Reserved Read = unpredictable 0 0 write= Should be zero 4 RR bit Round robin replacement 0= Random, 1= Round robin replacement V bit Base location of exception 0= Low addr., 1= High addr.(hardware) 0,1 0 2 I bit Instruction cache enable 0= instruction cache disable,1 = enable 0 1 1:10 - Reserved Read = 00, Write = R bit ROM protection S:0 R:0 = no access, S:1 R:1= Reserved 0 0 S bit System protection S:1 R:0= SVC(read only), User(no access) S:0 R:1= SVC(read only),user(read only) 0 0 B bit Big-endian/little-endian 0 = Little-endian, 1 = big-endian 0 0 :3 - Reserved Read = 1111, write = C bit Data cache enable 0 = data cache disable, 1 = enable 0 0 A bit Alignment fault enable 0 = fault checking disable, 1 = enable 0 1 M bit MMU enable 0 = MMU disable, 1 = enable 0 0

53 pu.c (2) (TOPDIR)/cpu/arm920t/cpu.c cpu.c read_p15_c1() Co-processor 15 register #1 value return. static unsigned long read_p15_c1 (void) { unsigned long inline asmvolatile type. asm volatile "mrc p15, 0, %0, c1, c0, read control output : value. : "=r" input : none clobber : input,output asm.(stack) : "memory"); #ifdef MMU_DEBUG printf ("p15/c1 is = %08lx\n", value); #endif return value;

54 pu.c (3) (TOPDIR)/cpu/arm920t/cpu.c cpu.c write_p15_c1() Co-processor 15 register #1value. static void write_p15_c1 (unsigned long value) { #ifdef MMU_DEBUG printf ("write %08lx to p15/c1\n", value); inline asmvolatile type. asm volatile "mcr p15, 0, %0, c1, c0, write it output : none input : value. : "r" clobber : input,output asm. : co-processor 15 #1read.??? read_p15_c1 ();

55 pu.c (4) (TOPDIR)/cpu/arm920t/cpu.c cpu.c cpu_init() Interrupt IRQ,FIQstack, armboot end IRQ CONFIG_STACKSIZE (128*1024) /* regular stack CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ int cpu_init (void) interrupt IRQ,FIQ armboot end address. ( interrupt.) #ifdef CONFIG_USE_IRQ IRQ_STACK_START = _armboot_end + CONFIG_STACKSIZE + CONFIG_STACKSIZE_IRQ - 4; FIQ_STACK_START = IRQ_STACK_START + CONFIG_STACKSIZE_FIQ; _armboot_real_end = FIQ_STACK_START + 4; #else _armboot_real_end = _armboot_end + CONFIG_STACKSIZE; #endif /* CONFIG_USE_IRQ */ return (0);

56 pu.c (5) (TOPDIR)/cpu/arm920t/cpu.c cpu.c cleanup_before_linux() Linux I/D-cachedisable I/D-cacheflush. #define C1_DC (1<<2) /* dcache off/on */ #define C1_IC (1<<12) /* icache off/on */ int cleanup_before_linux (void) { unsigned long i; disable_interrupts turn off I/D-cache asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); i &= ~(C1_DC C1_IC); asm ("mcr p15, 0, %0, c1, c0, 0": :"r" flush I/D-cache i = 0; asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); return (0);

57 pu.c (6) (TOPDIR)/cpu/arm920t/cpu.c cpu.c do_reset() Interrupt,mmu,cachedisable mmucacheflush 0 pc. int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) start.s function extern. extern void reset_cpu (ulong interrupt (irq/fiq)disable. disable_interrupts co-processor 15 0x mmu,cacheflush disable. reset_cpu (0); /*NOTREACHED*/ return (0);

58 pu.c (7) (TOPDIR)/cpu/arm920t/cpu.c cpu.c icache_enable,disable() I-cacheon/off. void icache_enable (void){ ulong reg; reg = read_p15_c1 (); cp_delay (); write_p15_c1 (reg C1_IC); void icache_disable (void){ ulong icache enable reg = read_p15_c1 (); cp_delay (); write_p15_c1 (reg & ~C1_IC); int icache_status (void){ return (read_p15_c1 () & C1_IC)!= icache icacheon 1return

59 pu.c (8) (TOPDIR)/cpu/arm920t/cpu.c cpu.c dcache_enable,disable() d-cacheon/off. void dcache_enable (void){ ulong reg; reg = read_p15_c1 (); cp_delay (); write_p15_c1 (reg C1_DC); void dcache_disable (void){ ulong dcache enable reg = read_p15_c1 (); cp_delay (); reg &= ~C1_DC; write_p15_c1 (reg); int dcache_status (void){ return (read_p15_c1 () & C1_DC)!= dcache dcacheon 1return

60 peed.c (1) (TOPDIR)/cpu/arm920t/speed.c PLL(1)-CPU PLL routine S3C2410 datasheet S3C2410MPLL(main PLL),UPLL(USB PLL) 2.

61 peed.c (2) (TOPDIR)/cpu/arm920t/speed.c PLL(2) S3C2410MPLL(main PLL)CLOCK Controller FCLK,HCLK,PCLK.

62 peed.c (3) (TOPDIR)/cpu/arm920t/speed.c PLL(3) s Mpll = (m * Fin)/(p * 2 ) m = (MDIV + 8), p = (PDIV + 2), s = SDIV, Fin = m = (0x5c + 8), p = (0x08 + 2), s = 0x00, Fin = 12Mhz Mpll = (m(100) * Fin(12Mhz)) / (p(10) * 2 ) => 1200Mhz / 10 =>120Mhz(FCLK)

63 peed.c (4) (TOPDIR)/cpu/arm920t/speed.c S3c2410.h (TOPDIR)/include/s3c2410.h S3c2410hardware register header.. #define S3C24X0_CLOCK_POWER_BASE 0x4C static inline S3C24X0_CLOCK_POWER * const S3C24X0_GetBase_CLOCK_POWER(void) { return (S3C24X0_CLOCK_POWER * const)s3c24x0_clock_power_base; S3c24x0.h (TOPDIR)/include/s3c24x0.h. typedef struct { S3C24X0_REG32 LOCKTIME; S3C24X0_REG32 MPLLCON; S3C24X0_REG32 UPLLCON; S3C24X0_REG32 CLKCON; S3C24X0_REG32 CLKSLOW; S3C24X0_REG32 CLKDIVN; /* attribute (( packed ))*/ S3C24X0_CLOCK_POWER;

64 peed.c (5) (TOPDIR)/cpu/arm920t/speed.c speed.c get_pllclk() setting MPLL,UPLL.(MPLL = 0,UPLL = 1) static ulong get_pllclk(int pllreg) { S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); ulong r, m, p, s; if (pllreg == #define MPLL 0 r = MPLLCON registerread. else if (pllreg == #define UPLL 1 r = UPLLCON registerread. else = (m * Fin)/(p * 2 s = (MDIV + 8), p = (PDIV + 2), s = SDIV, Fin = m = ((r & 0xFF000) >> 12) + MDIV[19:12] p = ((r & 0x003F0) >> 4) + PDIV[9:4] s = r & SDIV[1:0] return((config_sys_clk_freq * m) / (p << CONFIG_SYS_CLK_FREQ = ,(TOPDIR)/include/configs/smdk2410.h

65 peed.c (6) (TOPDIR)/cpu/arm920t/speed.c speed.c get_fclk,hclk,pclk,uclk() CLOCK. ulong get_fclk(void){ FCLK(MPLL) return. ulong get_hclk(void){ S3C24X0_CLOCK_POWER * const clk_power = CLKDIVN register HDIVN bit 1 FCLK/2 0 FLCK return. return((clk_power->clkdivn & 0x2)? get_fclk()/2 : get_fclk()); ulong get_pclk(void){ S3C24X0_CLOCK_POWER * const clk_power = CLKDIVN register PDIVN bit 1 HCLK/2 0 HLCK return. return((clk_power->clkdivn & 0x1)? get_hclk()/2 : get_hclk()); ulong get_uclk(void){ UPLL.

66 nterrupts.c (1) (TOPDIR)/cpu/arm920t/interrupts.c Interrupts.c enable,disable_interrupts() Interrupt(IRQ)enable disable. void enable_interrupts (void){ unsigned long temp; asm volatile ("mrs %0, cpsr\n "bic %0, %0, #0x80\n "msr cpsr_c, %0 : "=r" (temp) : "memory"); int disable_interrupts (void){ unsigned long old,temp; asm volatile ("mrs %0, cpsr\n "orr %1, %0, #0xc0\n "msr cpsr_c, %1 : "=r" (old), "=r" (temp) : : "memory"); return (old & 0x80) == disable IRQ interruptenable cpsr I r0 cpsr I bit,f r1 disable I bit return

67 nterrupts.c (2) (TOPDIR)/cpu/arm920t/interrupts.c Interrupts.c do_<exception handler>() exception C. void do_undefined_instruction (struct pt_regs *pt_regs){ printf ("undefined console exception. show_regs exception modereg.. bad_mode panic warm reset. void do_prefetch_abort (struct pt_regs *pt_regs) void do_data_abort (struct pt_regs *pt_regs) void do_not_used (struct pt_regs *pt_regs) void do_fiq (struct pt_regs *pt_regs) void do_irq (struct pt_regs *pt_regs){ printf ("interrupt console exception. show_regs exception modereg.. bad_mode panic warm reset.

68 nterrupts.c (3) (TOPDIR)/cpu/arm920t/interrupts.c Interrupts.c bad_mode(),show_reg() Exception moderegister bank struct pt_req(topdir)/include/asm-arm/proc-armv/ptrace.h. void bad_mode (void){ panic ("Resetting CPU...\n"); reset_cpu warm exception moderegister bank registerconsole. void show_regs (struct pt_regs r0 r10,fp,ip,sp,lr,pc condition IRQ on/off FIQ on/off processor thumb state console.

69 nterrupts.c (4) (TOPDIR)/cpu/arm920t/interrupts.c Timer(1)-timer routine S3C2410 datasheet S3C241016bit timer5.

70 nterrupts.c (5) (TOPDIR)/cpu/arm920t/interrupts.c Timer(2) Timer count(tcntn) timer clock.

71 nterrupts.c (6) (TOPDIR)/cpu/arm920t/interrupts.c Timer(3) 4bit DIVIDER & 8bit Prescaler 1,2 timerinput clock. 8bit Prescaler 1,2.

72 nterrupts.c (7) (TOPDIR)/cpu/arm920t/interrupts.c Timer(4) TimerDivider,DMA request channel.

73 nterrupts.c (8) (TOPDIR)/cpu/arm920t/interrupts.c Timer(5) Timerstart/stop,reload,update

74 nterrupts.c (9) (TOPDIR)/cpu/arm920t/interrupts.c Timer(6) Timer routine S3C2410 Datasheet

75 nterrupts.c (10) (TOPDIR)/cpu/arm920t/interrupts.c Timer(7) Timer register.

76 nterrupts.c (11) (TOPDIR)/cpu/arm920t/interrupts.c S3c2410.h (TOPDIR)/include/s3c2410.h S3c2410hardware register header.. #define S3C24X0_TIMER_BASE 0x static inline S3C24X0_TIMERS * const S3C24X0_GetBase_TIMERS(void) { return (S3C24X0_TIMERS * const)s3c24x0_timer_base;.. S3c24x0.h (TOPDIR)/include/s3c24x0.h. #typedef struct { S3C24X0_REG32 TCFG0; S3C24X0_REG32 TCFG1; S3C24X0_REG32 TCON; S3C24X0_TIMER ch[4]; S3C24X0_REG32 TCNTB4; S3C24X0_REG32 TCNTO4; /* attribute (( packed ))*/ S3C24X0_TIMERS;

77 nterrupts.c (12) (TOPDIR)/cpu/arm920t/interrupts.c Interrupts.c interrupt_init() Timer4.(timer4.) int interrupt_init (void){ S3C24X0_TIMERS * const timers = timer register base address -> timers timers->tcfg0 = timer2,3,4prescaler 15(0xf) if (timer_load_val == init. Value = 0 10ms clock period : PCLK /{prescaler + 1/divider => PCLK / {prescaler+1 * get PCLK= 50Mhz, 4 bit divider default vale = ½, prescaler = 15(0x0f) + PCLK 50Mhz => hz/16*2 = hz => 0.64us(1cycle) x = 1sec timer_load_val = get_pclk()/(2 * 16 * 100); lastdec = timers->tcntb4 = TCNTB = Timer4 => autoload,manual update,timer stop timers->tcon = (timers->tcon & ~0x ) Timer4 => autoload, timer start, 10ms timer4. timers->tcon = (timers->tcon & ~0x ) 0x500000; timestamp = 0; return (0);

78 nterrupts.c (13) (TOPDIR)/cpu/arm920t/interrupts.c Interrupts.c timer (1) Timer setting reset. static inline ulong READ_TIMER(void) timer4count. S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS(); return (timers->tcnto4 & 16bit timer(real counter) void set_timer (ulong t) time value start setting. time timestamp. timestamp = t; void reset_timer_masked timer reset count timestamp clear. lastdec = READ_TIMER(); timestamp = 0; void reset_timer (void) timer reset count timestamp clear. reset_timer_masked ();

79 nterrupts.c (14) (TOPDIR)/cpu/arm920t/interrupts.c Interrupts.c timer (2) Timer value. ulong get_timer_masked (void) { ulong now = timer count. ( timer count timer count. if (lastdec >= now) normal mode, timer count timer count(ex: => timestamp + 10) timestamp += lastdec - now; else overflow, timer count + timer setting - timer count(ex: => 35) timestamp += lastdec + timer_load_val - now; lastdec = timer count count value. return timestamp; ulong get_timer (ulong base) { return get_timer_masked () - time valuereturn

80 nterrupts.c (15) (TOPDIR)/cpu/arm920t/interrupts.c Interrupts.c timer (3) 1sec timer value. unsigned long long get_ticks(void) { return #define CFG_HZ ;(TOPDIR)/include/configs/smdk2410.h??? ulong get_tbclk (void) { ulong tbclk; #if defined(config_smdk2400) defined(config_trab) tbclk = timer_load_val * #elif defined(config_smdk2410) defined(config_atb2410) defined(config_vcma9) tbclk = 10ms(15625) * 100 = 1sec(CFG_HZ) #else #error "tbclk not configured" #endif return tbclk;

81 nterrupts.c (16) (TOPDIR)/cpu/arm920t/interrupts.c Interrupts.c udelay Us = = , 100us = , 10us = , 1us = = = * (15625 *100) = = /1000 = count value + timer clock delay.=>0.64us x 15 = 10us void udelay (unsigned long usec){ ulong tmo; tmo = usec / 1000; tmo *= (timer_load_val * 100); tmo /= 1000; tmo += get_timer (0); while (get_timer_masked () < tmo);

82 erial.c (1) (TOPDIR)/cpu/arm920t/serial.c serial(1)-serial routine S3C2410 datasheet S3C241016byte-FIFO 3 UART.(IRDA Driver )

83 erial.c (2) (TOPDIR)/cpu/arm920t/serial.c serial(2)-ulcon UARTserial ( bit,stop bit,parity, Normal/Irda) register

84 erial.c (3) (TOPDIR)/cpu/arm920t/serial.c serial(3)-ucon UARTbaud rate clock,tx/rx interrupt type,error,mode register

85 erial.c (4) (TOPDIR)/cpu/arm920t/serial.c serial(4)-ufcon UARTFIFO register

86 erial.c (5) (TOPDIR)/cpu/arm920t/serial.c serial(5)-umcon UART0,1 AUTO FLOW CONTOL(RTS) REGISTER

87 erial.c (6) (TOPDIR)/cpu/arm920t/serial.c serial(6)-utrstat UARTTX/RX STATUS REGISTER

88 erial.c (7) (TOPDIR)/cpu/arm920t/serial.c serial(7)-umstat UART0,1 AUTO FLOW CONTOL(CTS) REGISTER

89 erial.c (8) (TOPDIR)/cpu/arm920t/serial.c serial(8)-ufcon UARTTX/RX BUFFER REGISTER

90 erial.c (9) (TOPDIR)/cpu/arm920t/serial.c serial(9)-ubrdiv UARTBAUD RATE DIVISIOR REGISTER UBRDIVn = (INT)(PCLK / (BPS X16)) 1 UBRDIVn = (INT)(UCLK / (BPS X16)) 1 EX)UCLK(40MHZ) => ( / ( X 16)) 1 = = 21 1 = 20

91 erial.c (10) (TOPDIR)/cpu/arm920t/serial.c S3c2410.h (TOPDIR)/include/s3c2410.h S3c2410hardware register header.. ##define S3C24X0_UART_BASE 0x static inline S3C24X0_UART * const S3C24X0_GetBase_UART(S3C24X0_UARTS_NR nr) { return (S3C24X0_UART * const)(s3c24x0_uart_base + (nr * 0x4000));

92 erial.c (11) (TOPDIR)/cpu/arm920t/serial.c S3c24x0.h (TOPDIR)/include/s3c24x0.h S3c2410,S3C2400 hardware header.. typedef struct { S3C24X0_REG32 ULCON; S3C24X0_REG32 UCON; S3C24X0_REG32 UFCON; S3C24X0_REG32 UMCON; S3C24X0_REG32 UTRSTAT; S3C24X0_REG32 UERSTAT; S3C24X0_REG32 UFSTAT; S3C24X0_REG32 UMSTAT; #ifdef BIG_ENDIAN S3C24X0_REG8 res1[3]; S3C24X0_REG8 UTXH; S3C24X0_REG8 res2[3]; S3C24X0_REG8 URXH; #else /* Little Endian */ S3C24X0_REG8 UTXH; S3C24X0_REG8 res1[3]; S3C24X0_REG8 URXH; S3C24X0_REG8 res2[3]; #endif S3C24X0_REG32 UBRDIV; /* attribute (( packed ))*/ S3C24X0_UART;

93 erial.c (12) (TOPDIR)/cpu/arm920t/serial.c Global_data.h (TOPDIR)/include/asm-arm/global_data.h. typedef struct global_data { bd_t *bd; unsigned long flags; unsigned long baudrate; unsigned long have_console; /* serial_init() was called */ unsigned long reloc_off; /* Relocation Offset */ unsigned long env_addr; /* Address of Environment struct */ unsigned long env_valid; /* Checksum of Environment valid? */ unsigned long fb_base; /* base address of frame buffer */ #ifdef CONFIG_VFD unsigned char vfd_type; /* display type */ #endif gd_t; #define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm ("r8")

94 erial.c (13) (TOPDIR)/cpu/arm920t/serial.c Serial.c - Serial_setbrg(),serial_init() ConsoleUART. void serial_setbrg (void){ global structpoint S3C24X0_UART * const uart = consoleuart int i; unsigned int reg = <= <= = (int)((pclk)/(bps x 16)) 1 = ( /( x 16)) 1 = 26 reg = get_pclk() / (16 * gd->baudrate) - 1; /* FIFO enable, Tx/Rx FIFO clear */ uart->ufcon = enable,tx/rx FIFO clear uart->umcon = auto flow contol uart->ulcon = timeout int.,enable rx error int.,normal,interrupt or polling uart->ucon = 0x245; uart->ubrdiv = reg; for (i = 0; i < 100; i++); int serial_init (void){ serial_setbrg (); return

95 erial.c (14) (TOPDIR)/cpu/arm920t/serial.c Serial.c - Serial_gets(), Serial_putc(), Serial_tstc(), Serial_puts() Console string. int serial_getc (void){ S3C24X0_UART * const uart = receive buffer register data data rx buffer return while (!(uart->utrstat & 0x1)); return uart->urxh & 0xff; void serial_putc (const char c){ S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR); while (!(uart->utrstat & tx buffer register. uart->utxh = if (c == tx datanew line return. serial_putc ('\r'); int serial_tstc (void){@ receive buffer register data. S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR); return uart->utrstat & 0x1; voidserial_puts (const char while (*s) {serial_putc (*s++);

96 (TOPDIR)/board/smdk2410 directory Memsetup.S Smdk2410.c Flash.c

97 mdk2410.c (1) (TOPDIR)/board/smdk2410/smdk2410.c c Global_data.h (TOPDIR)/include/asm-arm/global_data.h. typedef struct global_data { bd_t *bd; unsigned long flags; unsigned long baudrate; unsigned long have_console; /* serial_init() was called */ unsigned long reloc_off; /* Relocation Offset */ unsigned long env_addr; /* Address of Environment struct */ unsigned long env_valid; /* Checksum of Environment valid? */ unsigned long fb_base; /* base address of frame buffer */ #ifdef CONFIG_VFD unsigned char vfd_type; /* display type */ #endif gd_t; #define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm ("r8")

98 mdk2410.c (2) (TOPDIR)/board/smdk2410/smdk2410.c c U_boot.h (TOPDIR)/include/asm-arm/u_boot.h #ifndef _U_BOOT_H_ #define _U_BOOT_H_ 1 typedef struct bd_info { int bi_baudrate; /* serial console baudrate */ unsigned long bi_ip_addr; /* IP Address */ unsigned char bi_enetaddr[6]; /* Ethernet adress */ struct environment_s *bi_env; ulong bi_arch_number; /* unique id for this board */ ulong bi_boot_params; /* where this board expects params */ struct /* RAM configuration */ { ulong start; ulong size; bi_dram[config_nr_dram_banks]; bd_t; #define bi_env_data bi_env->data #define bi_env_crc bi_env->crc #endif /* _U_BOOT_H_ */

99 mdk2410.c (3) (TOPDIR)/board/smdk2410/smdk2410.c Smdk2410.c board_init() #define FCLK_SPEED 1 #if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */ #elif FCLK_SPEED==1 /* Fout = 202.8MHz */ #define M_MDIV 0xA1 #define M_PDIV 0x3 #define M_SDIV 0x1 #endif #define USB_CLOCK 1 #if USB_CLOCK==0 #elif USB_CLOCK==1 #define U_M_MDIV 0x48 #define U_M_PDIV 0x3 #define U_M_SDIV 0x2 #endif

100 mdk2410.c (4) (TOPDIR)/board/smdk2410/smdk2410.c Smdk2410.c board_init() int board_init (void){ DECLARE_GLOBAL_DATA_PTR; S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); /* to reduce PLL lock time, adjust the LOCKTIME register */ clk_power->locktime = 0xFFFFFF; configure MPLL = (m * Fin)/(p * 2 ), m = (MDIV + 8), p = (PDIV + 2), s = SDIV, Fin FCLK = ((0xa1 + 8) * 12Mhz)/((0x03+2) * 2 1 ) = 2028/10 = 202.8Mhz clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV); /* some delay between MPLL and UPLL */ delay (4000); UCLK = ((0x48 + 8) * 12Mhz)/((0x03+2) * 2 ) = 960/20 = 48Mhz clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV); /* some delay between MPLL and UPLL */ delay (8000);

101 mdk2410.c (5) (TOPDIR)/board/smdk2410/smdk2410.c Smdk2410.c board_init() gpio->gpacon = GPA22-0 : (bus ) gpio->gpbcon = GPB10,8,6 : input, GPB9,7,5,4,3,2,1,0: output gpio->gpbup = GPB10-0 : pull-up disable gpio->gpccon = GPC15-0 : (lcd ) gpio->gpcup = GPC15-0 : pull-up disable gpio->gpdcon = GPD15-0 : (lcd ) gpio->gpdup = GPD15-0 : pull-up disable gpio->gpecon = GPE15-0 : ( bus ) gpio->gpeup = GPE15-0 : pull-up disable gpio->gpfcon = GPF3-0 : EINT3-0, GPF7-4 = output gpio->gpfup = GPF7-0 : pull-up : nypon,ymon,nxpon,xmon, GPG11 : EINT19, GPG10,9,8 : SPICLK1, GPG6:SPIMOSI1, GPG4:SPIMISO1, GPG3,1,0:EINT11,9,8, GPG2:nSS0 gpio->gpgcon = 0xFF95FFBA; gpio->gpgup = GPG15-0 = pull-up GPH10-8:output, GPH7:nCTS1, GPH6:nRTS1, GPH5:RXD1, GPH4:TXD1, GPH1:nRTS0, GPH0:nCTS0 gpio->gphcon = 0x002AFAAA; gpio->gphup = GPH10-0 = pull-up disable

102 mdk2410.c (6) (TOPDIR)/board/smdk2410/smdk2410.c Smdk2410.c board_init() /* arch number of SMDK2410-Board */ gd->bd->bi_arch_number = kernel architecture number /* adress of boot parameters */ gd->bd->bi_boot_params = kernelboot parameterstart address icache enable dcache enable return 0;

103 mdk2410.c (7) (TOPDIR)/board/smdk2410/smdk2410.c CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM PHYS_SDRAM_1 0x /* SDRAM Bank #1 PHYS_SDRAM_1_SIZE 0x /* 64 MB */ int dram_init (void) { DECLARE_GLOBAL_DATA_PTR; gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = start size return 0;

104 LASH Memory (1)

105 LASH Memory (2)

106 LASH Memory (3)

107 LASH Memory (4)

108 LASH.h (1) (TOPDIR)/include/flash.h Flash header file (bankflash ) typedef struct { ulong size; /* total bank size in bytes */ ushort sector_count; /* number of erase units */ ulong flash_id; /* combined device & manufacturer code */ ulong start[cfg_max_flash_sect]; /* physical sector start addresses */ uchar protect[cfg_max_flash_sect]; /* sector protection status */ #ifdef CFG_FLASH_CFI uchar portwidth; /* he width of the port */ uchar chipwidth; /* the width of the chip */ ushort buffer_size; /* # of bytes in write buffer */ ulong erase_blk_tout; /* maximum block erase timeout */ ulong write_tout; /* maximum write timeout */ ulong buffer_write_tout; /* maximum buffer write timeout */ #endif flash_info_t;

109 LASH.h (2) (TOPDIR)/include/flash.h Flash header file (flash error protect flags) #define ERR_OK 0 #define ERR_TIMOUT 1 #define ERR_NOT_ERASED 2 #define ERR_PROTECTED 4 #define ERR_INVAL 8 #define ERR_ALIGN 16 #define ERR_UNKNOWN_FLASH_VENDOR 32 #define ERR_UNKNOWN_FLASH_TYPE 64 #define ERR_PROG_ERROR 128 /* * Protection Flags for flash_protect(): */ #define FLAG_PROTECT_SET 0x01 #define FLAG_PROTECT_CLEAR 0x02

110 LASH.h (3) (TOPDIR)/include/flash.h Flash header file ( ID & Device ID) #define AMD_MANUFACT 0x /* AMD manuf. ID in D23..D16, D7..D0 */ #define FUJ_MANUFACT 0x /* FUJITSU manuf. ID in D23..D16, D7..D0 */ #define ATM_MANUFACT 0x001F001F /* ATMEL */ #define STM_MANUFACT 0x /* STM (Thomson) manuf. ID in D23.. -"- */ #define SST_MANUFACT 0x00BF00BF /* SST manuf. ID in D23..D16, D7..D0 */ #define MT_MANUFACT 0x /* MT manuf. ID in D23..D16, D7..D0 */ #define INTEL_MANUFACT 0x /* INTEL manuf. ID in D23..D16, D7..D0 */ #define INTEL_ALT_MANU 0x00B000B0 /* alternate INTEL namufacturer ID */ #define MX_MANUFACT 0x00C200C2 /* MXIC manuf. ID in D23..D16, D7..D0 */ #define TOSH_MANUFACT 0x /* TOSHIBA manuf. ID in D23..D16, D7..D0 */.. #define AMD_ID_LV800T 0x22DA22DA /* 29LV800T ID ( 8 M, top boot sector) */ #define AMD_ID_LV800B 0x225B225B /* 29LV800B ID ( 8 M, bottom boot sect) */.. #define FUJI_ID_29F800BA 0x /* MBM29F800BA ID (8M) */ #define FUJI_ID_29F800TA 0x22D622D6 /* MBM29F800TA ID (8M) */.. #define SST_ID_xF800A 0x /* 39xF800A ID ( 8M = 512K x 16 ) */ #define SST_ID_xF160A 0x /* 39xF800A ID (16M = 1M x 16 ) */

111 LASH.c (1) (TOPDIR)/board/smdk2410/flash.c Flash.c - bankflash flash_info_t Functions prototype /* * Functions */ static ulong flash_get_size (vu_long *addr, flash_info_t *info); static int write_word (flash_info_t *info, ulong dest, ulong data); static void flash_get_offsets (ulong base, flash_info_t 16bit flash command address data bus width #define ADDR0 0x5555 #define ADDR1 0x2aaa #define FLASH_WORD_SIZE unsigned short

112 LASH.c (2) (TOPDIR)/board/smdk2410/flash.c Flash.c flash_init() unsigned long flash_init (void) { unsigned long size; int i; uint bankflash id. for (i=0; i<cfg_max_flash_banks; ++i) { flash_info[i].flash_id = device idflash read FLASH_BASE0_PRELIM : bank0 flash address =>/(TOPDIR)/include/configs/smdk2410.h size = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, flash idread flash flash console if (flash_info[0].flash_id == FLASH_UNKNOWN) { printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", size_b0, size_b0<<20);