Microsoft PowerPoint - ch05ysk2012.ppt [호환 모드]

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1 전자회로 h5 ipola Aplifies 김영석 충북대학교전자정보대학 0.3. ail: k h5-

2 h5 ipola Aplifies 5. Geneal onsideations 5. Opeat Pot Analysis and Desin 5.3 ipola Aplifie Topoloies 5.4 Suay and Additional aples h5-

3 5. Geneal onsideations: Voltae Aplifie To be VA*V,, 0 Ideal Voltae Aplifie h5-3

4 Input/Output Ipedances V0Shot I0Open V i The fiue aboe shows the techniques of easu put and put t ipedances. h5-4

5 소신호 이득, 저항 Ipedance 개념 중요한개념이니꼭기억할것. 이득은소신호입력전압에대한소신호출력전압의비율임 입출력저항 Ipdeances 은소신호전류에대한소신호전압의비율임 대신호혹은 D 전류, 전압이아님 예: IN V IN, OUT V IN OUT 신호 D 성분 소신호 ac 성분 OUT 소신호 이득 A 소신호 입력저항 IN iin i, i IN I IN i h5-5

6 Ipedance at ase i base When calculat put/put ipedance, sall-sinal analysis is assued. h5-6

7 Ipedance at ollecto collecto o With aly effect, the ipedance seen at the collecto is equal to the tsic put ipedance of the tansisto if eitte is ounded. h5-7

8 Ipedance at itte i, eitte o The ipedance seen at the eitte of a tansisto is appoiately equal to one oe its tansconductance if the base is ounded. d h5-8

9 Thee Maste ules of Tansisto Ipedances ule # : look to the base, the ipedance is if eitte is ac ounded. ule # : look to the collecto, the ipedance is o if eitte is ac ounded. ule # 3: look to the eitte, the ipedance is / if base isac ounded and aly effect is nelected. h5-9

10 D Analysis s. Sall-Sinal Analysis Fist, D analysis is pefoed to detee opeat pot and obta sall-sinal paaetes. Second, souces ae set to zeo and sall-sinal odel is used. h5-0

11 5. Opeat Pot D Analysis and Desin: ias with ase esisto I V V V V, I f, V Assu a constant alue fo V,0.7V, one can sole fo both I and I and ddetee the teal oltaes of the tansisto. Howee, bias pot is sensitie to aiations. h5-

12 5.. esistie Diide ias Ipoed V X V V I I S ep V T f V Us esisto diide to set V, it is possible to poduce an I that is elatiely dependent of if base cuent is sall. h5-

13 Account fo ase uent I I S V ep The I V T The With pope atio of and, I can be sensitie to ; howee, its eponential dependence on esisto deiations akes it less useful. h5-3

14 5..3 itte Deeneation ias Good The pesence of helps to absob the eo V X so V stays elatiely constant. This bias technique is less sensitie to I >> I and V aiations. h5-4

15 itte Deeneation: Desin Pocedue hoose an I to poide the necessay sall sinal paaetes,,, etc. onside the aiations of,, and V, choose a alue fo V. With V chosen, and V calculated, V can be deteed. Select and to poide V. h5-5

16 5..4 Self-ias Technique V I I I ΔV >> V V / << V V I V / V V This bias technique utilizes the collecto oltae to poide the necessay V and I. V > V, thus uaantee actie opeation of the tansisto. id i iti it t poides sensitiity to. poides sensitiity to aiation V 이절에서언급된모든바이어스회로는 Discete 회로구성시에사용함 I 에서는저항은사용 면적증가 하지않고 T 로만구성된바이어스회로 uent Mio 사용함 h5-6

17 5.3 ipola Aplifie Topoloies oon itte: ad oon ase: bd oon ollecto: ae h5-7

18 5.3. oon-itte Aplifie A o o, o h5-8

19 itte Deeneated Stae y set a esisto seies with the eitte, we deeneate the stae. DeeneationNeatie Feedback: V >I >*I V > I V > I This topoloy will decease the a of the aplifie but ipoe othe aspects, such as leaity, and put ipedance. h5-9

20 itte Deeneated Stae : i i i, i A : 0, i 0 if / << A,-ollecto esistance/itte esistance-// h5-0

21 : itte Deeneated Stae A h5-

22 : Deeneated Stae with A. o A V h5-

23 Output Ipedance of Deeneated Stae with V A < p o o i i O i O o i i O O itte deeneation boosts the put ipedance by a facto of. This ipoes the a of the aplifie and akes the cicuit a bette cuent souce. h5-3

24 oplete Stae A ] [ ] [ ] [ L ] [ ] [ >> L S if s h5-4

25 5.3. oon ase Aplifie A, o o Note that A o, A,, o h5-5

26 Stae with Souce esistance A S / / S [ ] o o o S h5-6

27 Stae with 0 o e e / / ] [ o i i ] [ ] [ o i ] [ / o o i h5-7

28 Input Ipedance Seen at itte and ase h5-8

29 5.3.3 itte Followe oon ollecto Aplifie When the put is ceased by ΔV, put is also ceased by an aount that is less than ΔV due to the cease collecto cuent and hence the cease potential dop acoss. Howee the absolute alues of put and put diffe by a V. h5-9

30 itte Followe V A, / / << h5-30

31 itte Followe with Souce esistance V A S S h5-3

32 itte Followe with aly ffect O S O A O O s h5-3

33 Aplifie aple I ] [ ] [ ] [ ] [ ] [ S b b f ] [ << S if h5-33

34 Aplifie aple II ] [ ] [ b ] [ ] [ << if S b S h5-34

35 Aplifie aple III i eq A h5-35

36 Aplifie aple IV A S h5-36

37 Aplifie aple V eq S h5-37

38 Aplifie aple VI O O b ] [ O O O S b ] [ O S O S h5-38

39 Aplifie aple VII eq eq A 3 h5-39

40 Suay Ipedances h5-40

41 Suay JT Aplifies A o A A o / o o h5-4

Microsoft PowerPoint - ch07ysk2012.ppt [호환 모드]

Microsoft PowerPoint - ch07ysk2012.ppt [호환 모드] 전자회로 Ch7 CMOS Aplifiers 김영석 충북대학교전자정보대학 202.3. Eail: kiys@cbu.ac.kr k Ch7- 7. General Considerations 7.2 Coon-Source Stae Ch7 CMOS Aplifiers 7.3 Coon-Gate Stae 7.4 Source Follower 7.5 Suary and Additional