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준엽 범
7 years ago
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1 Clock Jitter Effect for Testing Data Converters Jin-Soo Ko Teradyne

2 Contents Noise Sources of Testing Converter Calculation of SNR with Clock Jitter Minimum Clock Jitter for Testing N bit Data Converter Table for Clock jitter, input signal and ENOB Simulation of Clock Jitter Effect using 14 Bit DAC and Input Signal Model. Real SNR Testing for 14 Bit DAC by Adding Clock Jitter

3 Model & Parameters to Data Converter Measure Analog Distortion Quantization Noise Quantizer Random Noise S/H Aperture Jitter Noise Non-Linearity Distortion

4 Sources of Noise for Testing Data Converter Vin Clock Jitter Noise V Heat DC-DC Converter Radiation Reference AC Power Analog ADCDigital AC GND Digital GND Clock HLHL Digital Power Non-linearity of Data Converter Reference Pin Noise Input Signal Jitter, Distortion and Noise Clock Jitter Data Jitter Data Signal Power Feedback Clock Signal Power Feedback Power and Ground Noise Separated Ground Plane Loop Noise Pick-up AC Power 60Hz/50Hz Noise DC-DC Converter Switching Noise Thermal Noise

5 Jitter Effect in Time Domain Distribution of sampled signal Output Clock jitter distribution Slop = 2πF analog Analog signal Time Equivalent number of bits SNR=20log 10 2π ft jrms 1MHz 10MHz 100MHz 1GHz 10GHz Equivalent noise = 2πF analog t jmrs Jitter amplitude = t jrms 1 SNRj =20log 10 2π ft jrms 10fS 100fS 1pS 10pS 100pS Clock jitter (rms)

6 SNR of Data Converter with Clock Jitter Component 2 SNR SNR ideal/20 /20 2 SNR = 10 log [ (2*PI*Fi*Tj) + (10 ) ] SNR ideal = -(6.02 * N ) db N : Data Converter Bit size Fi : Conversion Frequency Tj : RMS Jitter of Conversion Clock

7 Minimum Clock Jitter for Testing N-bit Data Converter SNR ideal/20 SNR Tj = 10 / ( 2*PI*Fi ) SNR ideal = -(6.02 * N ) db N : Data Converter Bit size Fi : Conversion Frequency Tj : RMS Jitter of Conversion Clock

8 Theoretical Jitter to ENOB Table

9 SNR of 14 bit Data Converter SNR of Ideal 14 bit data converter is db Sweep Random Clock Jitter Tj from 0 to 255ps by 1.0ps step Calculate SNR for 100KHz, 500KHz, 2 MHz and 10MHz Signal 2 SNR SNR ideal/20 /20 2 SNR = 10 log [ (2*PI*Fi*Tj) + (10 ) ]

10 SNR Calculation Data by Clock Jitter 10MHz 2MHz 500KHz 100KHz 14 bit SNR 86.04dB with 0 Clock jitter

11 Simulation Model of the Jitter Effect Create Ideal N-bit Sine Wave Signal Function Add RMS Jitter Noise Tj to Sampling Clock Fs F(t) ) = sin [2*PI*Fi*(t+Tj t+tj)/fs] Calculate SNR for Fi 2Mhz Signal for 0-100psrms Clock Jitter

12 Simulation Result

13 Power Spectrum View of the 14-bit Converter Simulation Model 100ps 20ps 10ps 0ps

14 SNR Data Overlap of the Calculation and Simulation data 10MHz simulation data 10MHz calculation data 500kHz calculation data 500kHz simulation data

15 SNR Data Difference Between The Calculation and Simulation Data 0.55% 100KHz 10MHz 2MHz 0.32% 500KHz

16 Fi 10Mhz, Clock Jitter 20psrms Power Spectrum of 14 bit ADC SNR 53.2dB / 15MHz BW (SNR 48.5dB / 45MHz BW)

17 Fi 10Mhz, Clock Jitter 255psrms Power Spectrum of 14 bit ADC SNR 40.2dB / 15MHz BW (SNR 35.5dB / 45MHz BW) Decrease SNR 15dB

18 Fi 2Mhz, Clock Jitter 20psrms & 255psrms for 14 bit ADC 20 psrms Clock Jitter 255psrms Clock Jitter

19 Fi=5Mhz, Clock Jitter 20psrms & 255psrms for 14 bit ADC 20 psrms Clock Jitter 255psrms Clock Jitter

20 Signal Filtering Effect by BPF Fs=1.5GHz, fi=250mhz Ext Clk, CW Src BPF makes the difference W/ BPF Clock HSD SNR = 45.72dB THD =-67.84dB SFDR =-57.88dB SINAD = 45.70dB ENOB = 7.30dB SNR = 41.21dB THD =-65.13dB SFDR =-52.89dB SINAD = 41.19dB ENOB = 6.55dB W/o BPF FAIL! PASS!

21 Fi = 250Mhz, Fs=800Mhz : Clock Jitter Performance Test Fs=800MHz, fi=250mhz, BPF used Either Pico Clock or ext clock can be used Avoid HSD Clock due to high jitter Bump around 250M is due to BPF Clock HSD Clock* EXT SNR = 45.88dB THD =-55.45dB SFDR =-56.80dB SINAD = 45.43dB ENOB = 7.25dB Clock 2 *Ext. Clock: Marconi

22 Reduce Jitter Effect Pick a Low Jitter Clock Source (Pico-Clk, HP8644B) Use the Instrument in Low Jitter Condition - DIB Design Use Narrow BPF if Device Accept Sinewave as Clock Use Jitter Reduction Module db MHz Clock energy

23 Q&A?

DIB-100_K(90x120)

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