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1 THE JOURNAL OF KOREAN INSTITUTE OF ELECTROMAGNETIC ENGINEERING AND SCIENCE Nov.; 25(11), ISSN (Print)ISSN X (Online) Realtime Wideband SW DDC Using High-Speed Parallel Processing 이현휘 이광용 윤상범 박영일 김선교 Hyeon-Hwi LeeKwang-Yong LeeSangbom YunYeongil Park*Seongyo Kim* 요약 DDC FPGA ASIC. DDC,.,. DDC,. CUDA DDC. Abstract Performing wideband DDC while quantizing signal over a wide dynamic range and high speed sampling rate have primarily been implemented in a hardware such as, FPGA or ASIC because of time-consuming job. Real-time wideband DDC SW, even though signal environment changes, adapt to signal environment flexibly and can be reused. In addition, it has a lower price than the hardware implementation. In this paper, we study the system design that can be stored in real time designing a high-speed parallel processing architecture for SW-based wideband DDC. Finally, applying a Ping-Pong Buffering mechanism for receiving a signal in real time and CUDA for a high-speed signal processing, we verify wideband DDC design procedure that meets the signal processing. Key words: Realtime, Wideband DDC SW, Signal Processing, Parallel Processing, CUDA. 서론,. [1],[2].. (Nyquist), [3]. ADC(Analog Digital Converter). ADC, ADC.. LIG (Electronic Warfare R&D Lab, LIG Nex1) *(Agency for Defense Development) Manuscript received August 25, 2014 ; Revised October 2, 2014 ; Accepted October 21, (ID No ) Corresponding Author: Hyeon-Hwi Lee ( c Copyright The Korean Institute of Electromagnetic Engineering and Science. All Rights Reserved. 1135

2 THE JOURNAL OF KOREAN INSTITUTE OF ELECTROMAGNETIC ENGINEERING AND SCIENCE. vol. 25, no. 11, Nov , SQNR(Signal to Quantized Noise Ratio). ADC SQNR, SQNR ADC 200MS/sec, 16. DDC(Digital Down Converter) [4]. DDC,. GPU(Graphic Processor Unit) DDC. DDC GMART(Giant Metrewave Radio Telescope) [5] CPU(Central Processing Unit) 250, [6] CPU 387. GPU CPU GPU CPU., DDC DDC. DDC. ADC, DDC I/Q. 1. (Ping-Pong Buffering), DDC CUDA(Compute Unified Device Architecture) [7] DDC. CUDA GPU.. 실시간광대역 DDC 설계 DDC IF ADC PC Ram A/D Data, A/D Data DDC,. 2-1 신호수신부. 2 ADC. Ping-Pong Buffering. 2 RAM1 RAM, RAM2 DDC RAM. RAM. RAM., RAM. I/O, I/O. RAM. RAM 2 MB, 2 MB Byte 2,097,152 Byte, 200 Msps(sample/sec), 2 Byte/sample 5.24 ms 그림 1. Fig. 1. Data flow diagram. 그림 2. Fig. 2. Ping-pong buffering diagram. 1136

3 . RAM 2 MB 5.24 msec DDC. RAM, RAM,., DDC, RAM. 2-2 신호처리부 Mixer, Mixer Sine, Cosine, I/Q. (1). cos sin (1) Mixer Real, Mixer Image, A/D,. Mixer,, Low Pass Filter(LPF). LPF, FIR CIC. Downsample Rate 10, FIR, Downsample Rate CIC. Downsample Rate 4 FIR. (3) M Downsampling Rate. 실시간광대역 DDC 구현 3-1 신호수신부 RAM 2 MB 16 ADC 1,048, RAM ADC. 200 MS/sec 1 (MS/sec) (sec) RAM 190. RAM,., RAM, RAM. 190, 3 RAM1 A/D Data, RAM 2 A/D Data DDC.. A/D Data RAM RAM DDC, Multi-Thread. CPU Thread 1, CPU Thread 2., (2) (2),, L. FIR Downsampling. Downsamping Sampling Rate DDC. (3) 그림 3. Fig. 3. Buffer switching in multi-thread environment. 1137

4 THE JOURNAL OF KOREAN INSTITUTE OF ELECTROMAGNETIC ENGINEERING AND SCIENCE. vol. 25, no. 11, Nov CPU Thread 1 CPU Thread 2 Worst, CPU Thread 1 CPU Thread 2., CPU Thread 1, 신호처리부 Mixer Sine, Cosine.. RAM 2 MB, 1,048,576. GPU Thread 2. 1,048,576 GPU Thread.,. Dynamic Parallelism [8]. Dynamic Parallelism GPU GPU Thread. 128 GPU Thread GPU Thread 8,192 GPU Thread , ,192. GPU GPU GPU Thread. 4 1 GPU Thread 8, GPU Thread, GPU Thread. Mixer Decimation. Decimation FIR downsampling., FIR. FIR Downsampling FIR 그림 4. Mixer Fig. 4. Mixer parallel processing design.. (4) (2) (3), FIR Downsampling Downsampling FIR. 1 Decimation FIR Downsampling, Decimation FIR Downsampling. Decimation, Downsample Rate. Decimation, Miexer, 표 1. (ms) Tabel 1. Processing time at different processing mode. Downsample rate decimation decimation

5 그림 6. A/D data Fig. 6. A/D data spectrum. 그림 5. decimation Fig. 5. Efficient decimation filtering design., Downsampling. Downsample Rate. I/Q MS 32 Downsample Rate I/Q. FIR DDC GPU Constant Convolution. 5 Downsample Rate 4. DDC, Downsample Rate. 5 GPU Thread DDC. GPU Thread Downsample Rate.. 실시간광대역 DDC 성능평가 4-1 신호수신부 60 dbm, CW, 30 MHz. ADC 200 MS/sec, A/D Data. ±30 MHz. 4-2 신호처리부 ADC DDC, DDC Mixer. 30 MHz, 7 30 MHz, 30 MHz 60 MHz. Mixer LPF Downsample. 그림 7. Mixer data Fig. 7. Mixer data spectrum. 1139

6 THE JOURNAL OF KOREAN INSTITUTE OF ELECTROMAGNETIC ENGINEERING AND SCIENCE. vol. 25, no. 11, Nov , CUDA., PC DDC. References 그림 8. Downsample rate Fig. 8. Spectrum at different downsample rate. LPF ±10 MHz 20 MHz, Tab 200. Tab, Downsample Rate 1, 2, 4, 8 DDC. CPU 2.80 GHz, GPU K20, Samsung SSD 840 Pro RAID 0.. 결론 GPU DDC. [1] James H. McClellan, Ronald W. Schafer, and Mark A. Yoder, "Signal processing first", [2] Bernard Sklar, Digital Communications, 2nd Edition, [3],,, "FFT ",, pp , [4],, " DDC ", (), pp , [5] Amit Upadhyay, Yawatkar Shakun Rajan, "Implementation of digital down converter in GPU", Department of Avionics, Indian Institute of Space Science and Technology, [6] X. Ma, L. Deng, and Y. Zhao, "Implementation of a digital down converter using graphics processing unit", Communication Technology(ICCT), pp , Nov [7] Jason Sanders, Edward Kandrot, CUDA by Example, Addison-Wesley, [8] NVIDIA Corporation, "CUDA C programming guide v 6.0", pp , : () 2013: LIG [ 주관심분야 ], : ( ) : LIG [ 주관심분야 ], 1140

7 1999 2: () : ( ) : LIG [ 주관심분야 ],,, : ( ) : ( ) : [ 주관심분야 ] ES : ( ) : () : () : [ 주관심분야 ], 1141

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