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1 아날로그및파워 IC 워크샵 저전력아날로그 IC 설계기술 서강대학교전자공학과안길초

2 Contents Introduction Low-Power Design Techniques 3 Conclusions

3 1. Introduction 3

4 Why Low-Power? (1) 4 Increasing demand for mobile applications Longer battery lifetime is required

5 Why Low-Power? (2) 5 Integration density increased with Moore s law Power consumption on unit area increased Reliability issue

6 Why Low-Power? (3) 6 Save Earth Green technology Energy saving

7 2. Low-Power Design Techniques 7

8 Source of Power Consumption 8 Capacitive switching activity P dynamic Short-circuit currents β Pshort = K Vdd 2V 12 Leakage currents P Static power P leakage static = = = I KC out V 2 dd f 3 ( ) fτ ( I diode + I subthreshold ) Vdd dcbias V dd T

9 Design Methodologies 9 Adapting process technology Reducing switching activity Reducing static power Power down modes Circuit optimization Power efficiency Architectures

10 Adapting Process Technology 10 Reducing capacitance: kt/c noise Reducing leakage power Operation speed Reducing supply voltage Reduced signal power Higher density of integration Signal coupling

11 Reducing Switching Activity 11 Conventional SAR ADC E avg, conv = n i= 1 n+ 1 2i i 2 2 (2 1) CVref For a 10-bit case: CVref

12 Reducing Switching Activity 12 SAR ADC with monotonic switching procedure n 1 Eavg, conv = i= 1 CV n 2i 2 ( 2 ) ref For a 10-bit case: CVref LIU et al., JSSC, Apr. 2010

13 Reducing Static Power: Opamp sharing 13 Conventional SHA and MDAC in pipelined ADC C V IN 2C - AS + D 1 V REF C - AM + V O_M1 SHA : Sampling <Phase 1> MDAC1 : Amplifying 2C C - AS + V O_S C - AM + SHA : Holding <Phase 2> MDAC1 : Sampling

14 Reducing Static Power: Opamp sharing 14 MDAC with opamp sharing 1 V IN + C-bank X(Sample) C-bank Y(Used) C Y 2 C-bank Y(Reset) C Y C-bank X(Used) C C X C X C C C X C X C X = C Y = C S D 2 V REF C Y - A + V O_M2 C Y D 1 V REF C - A + V O_M1 3 V IN + C-bank Y(Sample) C C C Y C Y C-bank X(Used) D 2 V REF C X - A + C X V O_M2 4 C-bank X(Reset) C X C X C-bank Y(Used) C D 1 V REF C - A + C Y C Y V O_M1 MDAC1 : Sampling, MDAC2 : Amplifying <Phase 1> N. Sasidhar et al., JSSC, Sep MDAC1 : Amplifying, MDAC2 : Sampling <Phase 2>

15 Reducing Static Power: Class-AB 15 Class-A opamp <Slew mode> Class-AB opamp <Settling mode> <Slew mode> <Settling mode>

16 Reducing Static Power: Class-AB 16 Class-AB opamp example Young-Ju Kim and Seung-Hoon Lee, JSSC, Mar. 2010

17 Reducing Static Power: Bias Current 17 Switched bias power-reduction technique Dong-Young Chang and Seung-Hoon Lee, JSSC, Aug. 1998

18 Power Down Modes 18 Frequency-scalable operation Joshua Lian et al., ISCAS 2010

19 Circuit Optimization 19 Scaling-down with optimized factors Hee-Cheol Choi and Seung-Hoon Lee, Int. J. Circuit Theory and Applications, Feb. 2011

20 Power Efficiency 20 Class-D output stage V DD V INP V INN Input Buffer + - A - + ΣΔ Modulator V DD LPF Speaker Load Class-A: about 20% Class-B: about 50% Class-AB: about 50% Class-D: 90-95% are possible

21 Power Efficiency 21 Double-sampling switched capacitor integrator OSR is doubled in DSM without burning extra power

22 Architectures 22 Algorithmic ADC with improved clocking Improved conversion speed with same power Min Gyu Kim et al., Symposium on VLSI Circuits 2006

23 Architectures 23 Reference scaling technique 2 nd Stage VRES1 S/H - α2g2 VRES2 ADC DAC D2 VREF α1 α2 α9 VIN 2.5bit α1g1 1.5bit α2g2 1.5bit α9g9 2bit D1 D2 D9 D10 Clock Gen Digital Correction Logic Relaxed opamp gain requirement Gil-Cho Ahn et al., Symposium on VLSI Circuits 2006 DOUT

24 Architectures 24 Noise coupling technique Third-order Delta-Sigma Modulator X z V 1 1 z V z 5 1 z -1 1 bit ADC Y 1 st Integrator 2 nd Integrator z 2 Noise coupling -2-1 z 25 ( 1 z ) 3 Y( z ) X( z) Q( z ) 25 60z 51z 15z 25 60z 51z 15z Reduced number of opamp Sejin Yoo et al., ISOCC 2010

25 Architectures 25 Noise coupling technique VIN VREF VREF VREF VREF VREF VREF VREF VREF V OUT -V OUT φ1 C I2 φ2 D(n) φ2 D(n) φ2 D(n) φ2 D(n) φ1 φ2 φ2 A D(n-1) φ2 A D(n-1) φ1 A φ2 A φ2 B D(n-1) φ2 B D(n-1) C S2 C F1A 1X φ2 φ1p 2X C F1B 3X C F2A 2X C F2B3X C F3A 2X A2 + 5X VOUT V z V z D 2 nd Integrator φ1 φ1p φ2 φ1a φ2a φ1b 1-1 z Noise coupling -V OUT φ1 B φ2 B C F3B 3X φ2b D

26 Architectures 26 Pipelined ADC using open-loop residue amp. B. Murmann et al., JSSC, Dec % residue amplifier power saving Digitally enhanced analog circuit

27 Architectures 27 CT integrator in delta-sigma ADC Opamp BW requirement is relaxed: low-power No folded noise: low noise Matching problem: R/C matching required Jitter sensitive

28 Architectures 28 Single-loop vs. MASH Opamp gain requirement Input signal range

29 3. Conclusions 29

30 Design Challenges 30 Low-voltage design in scaled down process Noise (kt/c, thermal) limit the performance More power consumption in analog circuits Proper architecture Consider applications and required spec. Circuit optimization Save power as much as possible Enhance the power efficiency Sharing and reusing Minimize static power consumption

31 아날로그및파워 IC 워크샵

Slide 1

Clock Jitter Effect for Testing Data Converters Jin-Soo Ko Teradyne 2007. 6. 29. 1 Contents Noise Sources of Testing Converter Calculation of SNR with Clock Jitter Minimum Clock Jitter for Testing N bit