歯03-ICFamily.PDF

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1 Integrated Circuits SSI(Small Scale IC) 10 / ( ) MSI(Medium Scale IC) / (, ) LSI(Large Scale IC) / (LU) VLSI(Very Large Scale IC) - / (CPU, Memory) ULSI(Ultra Large Scale IC) - / ( ) GSI(Giant Large Scale IC)

2 Commonly used 7400-Series SSI ICs V cc V cc V cc GND GND GND V cc V cc V cc GND GND GND V cc V cc V cc GND GND GND

3 Positive Logic and Negative Logic Positive logic Negative logic Logic Value Signal Value Logic Value Signal Value 1 H 0 L 0 H 1 L Positive logic Positive logic Negative logic Negative logic ND OR ND OR Positive logic ND = Negative logic OR Positive logic OR = Negative logic ND

4 Characteristics of IC Logic Family Fanout, Power dissipation Propagation delay Noise margin Degree of integration Component cost

5 IC Digital Logic Family RTL (Resistor Traansistor Logic) DTL (Diode Transistor Logic) TTL (Transistor Transistor Logic) : ECL (Emitter Coupled Logic) : MOS (Metal Oxide Semiconductor) : CMOS (Complementary Metal Oxide Semiconductor) :, I 2 L (Integrated Injection Logic) : icmos

6 Diode Logic Y=+ +5V Y=

7 ipolar Transistor I C R C I [m] I C [m] R C I = 0.6m 0.5 I V o 0.4 V i R 0.3 I E V E [V] 0.2 V CE [V] Region V E [V] V CE [V] Current Relationship Cutoff < 0.6 Open circuit I =I C =0 ctive > 0.8 I C =h FE I Saturation I >> I CS /h FE

8 RTL(Resistor Transistor Logic) L:0.2V, H: V Power dissipation:12mw Propagation delay: 25ns Noise Margin: 0.4V Fanout= 5 =3.6V 640 =3.6V 640 Y= C Y= ++C C C

9 DTL(Diode Transistor Logic) L:0.2V, H:4-5V Power dissipation:12mw Propagation delay: 30ns Noise margin: 1V Fanout: 8 =5V,,C L 5K 2K Y= C P= = 0.9V Q1 ON P P= = 2.1V C P D1 D2 5K Q1 Q1 is OFF Y=5V,,C H Q1 is ON Y= 0.2V

10 DTL =5V 1.6K 2K 2K Y= C P Q1 D2 Q2 C 5K

11 TTL(Transistor Transistor Logic) TTL series name Prefix Fanout Power dissipation [mw] Propagation delay [ns] Speed-Power product [pj] Standard Low-power 74L High speed 74H Schottky 74S Low-power Schottky 74LS dvanced Shottky 74S dvanced low-power Schottky 74LS TTL output 1) Open-collector output 2) Totem-pole output 3) Tristate output

12 =5V =5V 4K 1.6K R L C Q1 Q2 1K Q3 Y= C

13 Open Collector TTL C D OC OC Y I 1 I 2 I OC1 OC2 OC us line OC5 Y C D OC OC Y I OC4 0 1

14 Totem-Pole Output TTL =5V 4K 1.6K 130 Q4 C Q1 Q2 Q3 D1 Y= C 1K

15 Schottky TTL =5V 2.8K Q5 Q4 Q1 Q2 3.5K Q Q6

16 3-State TTL Gate Q5 Q4 C Y= if C=high Y=high impedance if C=low Q1 Q2 Q3 Y Y= if C=low Y=high impedance if C=high C D1 C Q6 Q7 Q8

17 ECL(Emitter Coupled Logic) 2 =GND 1 =GND R C1 220 R C Q8 OR output Q7 Q1 Q2 Q3 Q4 Q5 V = -1.3V Q6 NOR output Rp 50K Rp 50K Rp 50K Rp 50K R E K 4.98K C D V EE = -5.2V

18 ECL gates (+) : NOR (+) : OR (+) +(C+D) =[(+)(C+D)] (+)(C+D)

19 CMOS Logic Gates

20 CMOS

21 CMOS Logic Gate

23 Transmission Gates

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歯03-ICFamily.PDF