Microsoft PowerPoint - dc_ch2 [호환 모드]

Size: px
Start display at page:

Download "Microsoft PowerPoint - dc_ch2 [호환 모드]"

Transcription

1 Chapter 2 Boolean Algebra and Logic Circuits

2 Chapter 2 Boolean Algebra and Logic Circuits 2.1 Boolean Algebra Definition of Boolean Algebra Fundamental Theorems Switching Algebra Switching Operations and Gates 2.2 Switching Formulas and Functions Switching Formulas Manipulation of Switching Formula Propositions, Truth Tables and Switching Functions 2.3 Realization of Logic Functions Logic Families Wired Logic Gate Properties Problems

3 2.1 Boolean algebra 2.1 Definition of a Boolean Algebra * George Boole ( ) 1864) : 논리와수학적해석 : 사고법칙에대한고찰 (An Investigation of the Laws of Thoughts) : 미분방정식론 : 차분법론 * Boolean Algebra - Algebra for symbolically representing problems in complex logic statements involving propositions which are only true or false -2진변수와논리연산자를다루는대수를말함 * Claude E. Shannon - Application of a Boolean algebra to the design of relay networks in telephone systems * Switching circuit theory - The study of Boolean algebra as applied to logic design

4 2.1 Boolean Algebra 용어정리 * 논리 (Logic): Science of arguments which involve ascertaining the validity of a series of interdependent d t propositions (clearly l defined d statements), t t which h may be simple or compound *2 진논리 (Binary Logic): 오직 2 개의값 (0 과 1, 참 (T) 및거짓 (F), On 및 Off 등등 ) 만을갖는변수와이들변수에대한수학적연산에의한논리 * 2진변수 (Binary Variables): zero(0) 또는 one(1) 만을가지는변수 * 논리연산자 (Logical Operators): 논리연산을수행하는연산자 (AND, OR, NOT) * 논리함수 (Logic Functions): 입출력사이의관계를나타내는함수 * 진리표 (Truth Tables): 모든가능한경우의논리적입 / 출력사이의관계를나타낸표 * 부울대수 (Boolean Algebra): 논리연산자를사용하여논리적기능을처리하는수학 * 부울식 (Boolean Expressions or Formulas): 논리적기능을 Boolean constant, variables, 그리고 Boolean operations 을이용하여나타낸식

5 2.1 Boolean Algebra 명제 진리표디지털시스템논리회로 Logic map K-map 부울함수

6 2.1 Boolean Algebra Basic Logic Operations and Symbols * NOT: changes one logic level to the opposite logic level * AND: produces a HIGH output only if all the inputs are HIGH * OR: produces a HIGH output when any of the inputs is HIGH

7 2.1 Boolean Algebra 진리표 부울식 ( 부울함수 ) 으로의변환 출력값이 1 이되게하는입력변수의조합으로표현 [ 예 ] f is 1 if a b = 1 OR if ab = 1 OR if ab = 1 f = a b ab ab a b a b a b a b a b f

8 2.1 Boolean Algebra: 진리표 부울식 ( 부울함수 ) 으로변환 f is 1 if a=0 AND b = 1 OR if a = 1 AND b = 0 OR if a = 1 AND b = 1 f is 1 if a = 1 AND b = 1 OR if a = 1 AND b = 1 OR if a = 1 AND b = 1 f is 1 if a b = 1 OR if ab = 1 OR if ab = 1 f = a b ab ab

9 2.1 Boolean Algebra 진리표의간소화 (simplification) (1) 대수적인방법 * 부울대수의여러가지성질을이용하는방법 * 일의적인방법이아님 (2) 카노우도표방법 (Karnaugh map) * 진리표상의최소항의개수만큼의정사각형을 2차원의표로나타낸것 * K-map map, Veitch diagram * 진리표 2차원표 * 최소항, 최대항 정사각형 ; 진리표상의출력값이 1 인정사각형에 1 을대응시킴 * [ 예 ] n 변수: 2 n 개의최소항 ( 최대항 ) 2 n 개의정사각형

10 2.1 Definition of a Boolean Algebra * Definition of a Boolean algebra - A mathematical system B satisfying the following postulates:

11

12 2.1 Definition of a Boolean Algebra * 부울함수 (Boolean functions) - 입력 (A, B,, Z 혹은 ab a,b,, z) 과출력 (F 혹은 Y) 을나타내는 2 진변수, 등호 (=), 상수 (0, 1), 괄호 ( ( ) ) 및논리연산기호,,, 등등을사용하여이루어진대수적표현을말함. - [ 예 ] F= X YZ, Y = ( a b )x( X Y ) - 부울함수의결과값은주어진입력변수가갖는모든값들의조합에대하여, 부울함수를구성하는항 (terms) 들각각에대한논리연산결과값을구한후, 이들을결합하는연산을수행하여구함.

13 2.1.2 Fundamental Theorems 쌍대성원리 (Principle of Duality) * 쌍대형태 (dual form): 어떤대수적표현의쌍대 (dual) 는 () 와 (.) 를서로교환하고, 0은 1 로 1 은 0 으로변환함으로써얻어짐. * < 주의 >: 일반적으로어떤대수적표현의쌍대진리값은그것의원래표현의진리값과는서로같지않으므로이를서로대치할수없음.

14 2.1.2 Fundamental Theorems

15

16 2.1.2 Fundamental Theorems

17 2.1.2 Fundamental Theorems

18 2.1.2 Fundamental Theorems

19 2.1.2 Fundamental Theorems

20 2.1.2 Fundamental Theorems

21

22 2.1.2 Fundamental Theorems * Redundancy Law - a x (a b) = a; a ( a b ) = a ab = a( b b ) ab = ab ab ab = a( b b ) = a 1 = a -a (a x b) = a; a ( a b ) = a( b b ) ab = ab ab ab = a( b b ) = a 1 = a * Nashelsky's theorem - ax(a c b)= axb; a ( a b ) = aa ab = ab -a (a c x b) = a b [ 예 1] F= X (Y Z ) = ( X Y ) Z G = X(YZ ) = ( XY )Z = XYZ = X Y Z [ 예 2] [ 예 3] F = ( A B )( A CD ) = A BCD X 1 X 2 X X N = X 1 X 2 X N = X 1 X 2 X N 1 X 2 X N

23 ABCD B A F = wxyz wxz wxyz wxz xyz f = ACD ABD ACD BC AB H wy xyz wxyz xyz wxy g = = AD BCD ABC ACD ABC G ACD ABD ACD BC AB H = = abd acd b cd abc h = xyz xyz xyz xyz xyz xyz p =

24 2.1.4 Switching Operations and Gates * Logic gates (1) 논리연산을수행하는전자회로혹은소자 (transistors, diodes, resistors, and capacitors) (2) 입력신호의 2진신호로의인식 (3) 2진출력신호를허용범위내의아날로그신호로전환출력 (4) [ 주의 ] 논리소자의입출력은아날로그신호 (5) 0 에서 1로혹은 1 에서 0으로의변화를 transition 이라함 (6) 0 에서 1로혹은 1에서 0으로변화하는비결정적영역을 transition region 이라함 (7) timing diagram : 시간의변화에따른신호의상태를나타내는것 (8) Integrated Circuits (IC) (9) Dual-in-line package (DIP)

25 2.1.4 Switching Operations and Gates * Logic families : manufacturing families (1) Transistor-transistor logic (TTL) based on the bipolar junction transistor(bjt) (2) 5Vdc power source (3) SN 74 LS 04 N manufacturer series subseries device type package where # SN : Semiconductor Network Program manufactured by Texas Instruments # 74 : standard TTL commercial device : 0 온도특성 70 (cf. 54 : high-reliability military : -55 온도특성 125 ) # LS : low power, high speed known as low-power Schottky # 04 : logic function (NOT) # N : plastic DIP device (4) Complementary metal-oxide semiconductor (CMOS) * designed around field effect transistor (FET) * 3Vdc ~ 18Vdc power source * consume much less power than TTL * slower than TTL * similar identification process to that of TTL

26 2.1.4 Switching Operations and Gates AND 와 NOT 기호로표현한 NAND 함수 x y s s = (xy) or s = xy NAND 게이트의논리기호 x y s x y z t w x y z u s = (xy) or s = xy t = (xyz) or t= xyz u = (wxyz) or u= wxyz (a) 2- 입력 NAND 게이트 (b) 3- 입력 NAND 게이트 (c) 4- 입력 NAND 게이트

27 2.1.4 Switching Operations and Gates OR 와 NOT 기호로표현한 NOR 함수 x y s = (x y) or s = x y NOR 게이트의논리기호 s x y s x y z s w x y z s S = (x y) or s = x y s = (x y z) or u = (w x y z) or s = x y z u = w x y z (a) 2- 입력 NOR 게이트 (b) 3- 입력 NOR 게이트 (c) 4- 입력 NOR 게이트

28 2.1.4 Switching Operations and Gates NAND 논리회로 NOR 논리회로

29 2.1.4 Switching Operations and Gates 2- 입력과 3- 입력 EX-OR 함수 x y z x y p y z y p y x z = z y x P = (a) 2- 입력 EX-OR 게이트 (b) 2- 입력 EX-OR 게이트를조합한 3 입력 EX-OR 게이트 y y

30 2.1.4 Switching Operations and Gates

31 2.1.4 Switching Operations and Gates 2- 입력과 3- 입력 EX-NOR 함수입력출력 x y s x y z x y p z z = x y P = x y z (a) 2- 입력 EX-NOR 게이트 (b) 2- 입력 EX-NOR 게이트를조합한 3 입력 EX-NOR 게이트

32 Universal Gates NAND 게이트를사용한 AND 와 OR 함수 x y ( xy)' (xy) (a) NAND 게이트를사용한 AND 함수 x x' y y' x y (b) NAND 게이트를사용한 OR 함수

33 Universal Gates NOR 게이트를사용한 AND 와 OR 함수 x x' y y' (x' y' ) = xy (a) NOR 게이트를사용한 AND 함수 x y (x y)' (x y) (b) NOR 게이트를사용한 OR 함수

34 Universal Gates V CC "1" x x' x (x 1) = x 그림 2-29 NAND 와 NOR 게이트를인버터로사용 x' (x x) = x (a) NAND 게이트인버터 x "0" x' x x' (x 0) = x (x x) = x (b) NOR 게이트인버터

35 2.2 Switching Formulas and Functions * 부울식 (Boolean Expressions or Formulas): 논리적기능을 Boolean constant, variables, 그리고 Boolean operations 을이용하여나타낸식 ( x y)z * 논리함수 (Logic Functions): 입출력사이의관계를나타내는함수 f f = ( x y)z * 진리표 (Truth Table): n 개의입력변수 2 n 개의조합

36 2.2 Switching Formulas and Functions * [Ex] 3 개의입력변수를가진함수 f 의진리표

37 2.2.1 Switching Formulas * 문자 (Literals): 부울변수자체또는보수화 ( ) 된부울변수 f = x wy w yz x,w,, y,w,, y,z * 곱항 (Product terms): 문자 / 다중문자의논리곱 (AND) f = x wy w yz x,wy,w w yz * 합항 (Sum terms): 문자 / 다중문자의논리합 (OR) f = z(x y)(w x y) z, x y, w x y * 최소항 (Minterms) - 곱항의특수한경우 ( 모든입력변수들을포함하는곱 ) - [ 예 ] XY, X Y, XY, X Y - n 개의변수에대하여 2 n 개의최소항 2개의변수에대한 4개의최소항 * 최대항 (Maxterm) - 합항의특수한경우 ( 모든입력변수들을포함하는합 ) - [ 예 ] XY, X Y, XY, X Y

38 2.2.1 Switching Formulas * m-notation - 최소항의간략화된표현 : m i - m i : 첨자 i 는진리표상에서변수가갖는값을십진수로변환한값 f = x yz xyz xy z = m m m = m(1,3,4 )

39 2.2.1 Switching Formulas * M-Notation - 최대항의간략화된표현 : M i - M i : 첨자 i i 는진리표상에서변수가갖는값을십진수로변환한값 f = (x y z)(x y z)(x y z)(x = M0M2M5M6M7 = M(0,2,5,6,7) y z)(x y z)

40 2.2.1 Switching Formulas [ 예 ] 최소항의 m- 표현

41 2.2.1 Switching Formulas 표 3 개의변수를가진최소항과최대항 입력변수최소항최대항 a b c 항 명칭 항 명칭 a'b'c' m 0 abc M a'b'c m 1 abc' a'bc' m 2 ab'c M 1 M a'bc ab'c' m 3 ab'c' a'bc M ab'c abc' abc m 4 m 5 m 6 m 7 a'bc' abc a'b'c a'b'c M 4 M 5 M 6 M 7

42 Map 2.1 Two-variable Karnaugh maps.

43 Map 2.3 Three-variable maps. Map 2.5 Product terms corresponding to groups of two.

44 Map 2.8 The four-variable map.

45 Map 2.12 x yz x yz xy z xy z xyz. Map 2.13 A better solution. Map 2.14 The minimum solutions.

46 2.2.1 Switching Formulas * 곱항의합 (SOP; Sum Of Product or disjunctive normal form) : 곱항들의논리합 f = x wy w yz * 합항의곱 (POS; Product Of Sum or conjunctive normal form) : 합항들의논리곱 f = z(x y)(w x y) * 최소곱항의합표현 (A minimum sum of products expression) - 곱항의수가최소인 SOP 표현 - 곱항의수가같은경우에는최소의문자를갖는 SOP 표현 - [ 예 ] 아래표현의경우 (3) 혹은 (4) (1) x yz x yz xy z xy z xyz 5 terms, 15 literals (2) x y xy xyz 3 terms, 7 literals (3) x y xy xz 3 terms, 6 literals (4) x y xy yz 3 terms, 6 literals

47 2.2.1 Switching Formulas * 표준곱항의합또는표준 SOP 형식 (Standard sum-of-products, Minterm canonical formulas, or Disjunctive canonical formulas) : 출력변수가논리적으로 1일때를정의하는최소항의완전한형태 ( 모든입력변수를포함하는최소항의합 ) f g 표준SOP SOP = x yz xyz = x yz xy z xy z * 표준합항의곱또는표준 POS 형식 (Standard product-of-sums): 출력변수가논리적으로 0 일때를정의하는최대항의완전한형태 ( 모든입력변수를포함하는최대항의곱 ) f 표준POS = ( x y z)( x y g POS = x ( y z )( x y z ) z)( x y z)

48 2.2.1 Switching Formulas 임플리컨트 (Implicant) * 어떤함수의임플리컨트는 임플리컨트가 1일때는언제든지함수가 1이되는곱항 를말함. * [ 예 ] 다음쪽의최소항 * 지도 (Map) 적관점에서설명하면, 4각형형태를지니면서내부에 1 만을포함하는 2 k 개 (1, 2, 4, 8,...) 의최소항으로구성된곱항 프라임임플리컨트 (Prime implicant of a function) * 임플리컨트중에서어느하나의다른임플리컨트에완전히포함되지않는것을말함 * [ 예 ] 지도 32 3,2 에타원으로표시된모든곱항 에센셜프라임임플리컨트 (Essential prime implicant) * 다른프라임임플리컨트에포함되지않는적어도하나의 1 을갖는프라임임플리컨트를말함. * [ 예 ] 지도 3,2에검은색타원으로표시된모든곱항

49 2.2.1 Switching Formulas The implicants of F are Minterms Groups of 2 Groups of 4 A B C D A CD CD A B CD BCD A BCD ACD ABC D B CD ABC D ABC ABCD ABD AB CD

50 2.2.2 Manipulation of Switching Formulas 1) 부울함수의대수적간소화 (1) 항결합 - XY XY = X (Y- Y ) = X 1 = X - X Y XYZ XYZ = XY ( X X )YZ = XY 1 YZ = XY YZ (2) 문자소거 - X XY = ( X X )( X Y ) = 1 ( X Y ) = X Y - X ( X Y ) = XX XY = 0 XY = XY (3) 중복항첨가 F = XYZ XYZ XYZ = XYZ XYZ XYZ XYZ = XZ(Y Y ) ( X X )YZ = XZ YZ = ( X Y )Z (4) 합의정리 (consensus theorem) XY XZ YZ = XY XZ

51 2.2.2 Manipulation of Switching Formulas 1) Algebraic manipulation X YZ XYZ XZ = XY XY XY = X(Y Y) = X 1 = X XY = X(1 Y) = X 1 = X XY = X(1 Y) = X 1 = X X XZ X (X Y) = XX XY = X XY = X(1 Y) = X 1 = X ( X Y)(X Y) = XX XY XY YY = X XY XY = X(1 Y Y) = X 1 = X (X Y) = XX XY = XY X X 2) Duality principle of Boolean algebra: F F It means that a Boolean equation remains valid if we take the dual of the expression on both sides of the equal sign (AND OR, X Xc) X Y - X Y ( X Y - )( X Z ) X Y XZ

52 Manipulation of Switching Formulas 3) Consensus theorem ( 흡수정리 ) - XY XZ YZ = XY (X Y)Z - = = = = = XY (X Y)(X X)Z XY (XY X XY)Z XY(1 Z) XZ(1 Y) by XY (XX XY X X XY)Z XY XZ (X Y)(X Z)(Y Z) = (X Y)(X Z)(Y Z) X X = 1 = (X Y)(XY XZ YZ Z) = (X Y) = (X Y) = (X Y) = (X Y) = (X Y) = (X Y) = (X Y)(X Z) - EX.: ( X Y )( X Z ) = XY XZ 4) Complement of a function c - (X YZ XYZ) = (X Y Z)(X Y Z) - c (X( Y Z YZ)) = X ( Y Z)(Y Z) X\YZ {(X(Y Z) Z(Y 1) } {(X(Y Z) Z} {(X(Y ( Z) Z XX } by XX = 0 { XY XZ Z XX} { X(X Y) Z(X 1) } { X(X Y) Z } 1 1 1

53 부울대수만을사용한부울식의간략화법 F = XY XZ YZ X\YZ XY, XZ, YZ 1) 곱항의합으로주어진부울식의각항 ( ) 을논리지도에오른쪽그림과같이표시 2) 첨가혹은분해하고자하는항 (YZ; 주로 Prime imlicant 임 ) 을발견하여간략화하고자하는항과결합 3) 더이상결합이불가능할때까지위의과정 2) 를반복 [ 예 ] XY XZ YZ = XY XZ ( X X ) YZ = XY XYZ XZ XYZ = XY (1 Z) XZ(1 Y ) = XY XZ 항의분해결합하고자하는항끼리정리 -

54 2.2.2 Manipulation of Switching Formulas * Theorems: Shannon s expansion theorem * [ 예 ]

55 2.2.2 Manipulation of Switching Formulas * [ 예 ] 부울식의간략화 (Simplification)

56 2.2.2 Manipulation of Switching Formulas * Theorems: Shannon s reduction theorems

57 2.2.2 Manipulation of Switching Formulas * [Ex]

58 2.2.2 Manipulation of Switching Formulas * Complementations of Canonical Formulas

59 2.2.2 Manipulation of Switching Formulas * [Ex] Complementation of the Boolean Expression

60 2.2.3 Propositions, Truth Tables and Switching Functions Minterm 을이용한 Switching Equation 구하기 1. 진리표로부터출력이논리적으로 1 이되는부분만을주목한다. 2. 위의변수들을 AND 연산을이용하여하나의항을만든다. 변수의값 :1 -> 그대로, 0 -> (not) ex) a b c K( 출력 ) > ab c 로출력이떨어지는항 (Term) 만을 OR 연산으로묶는다. ex) K= ab c abc ab c

61 2.2.3 Propositions, Truth Tables and Switching Functions * [ 예제 ] - For the given propositions : if a is 0 and b is 0 then z is 0 if a is 0 and b is 1 then z is 0 if a is 1 and b is 0 then z is 0 if a is 1 and b is 1 then z is 1 - Step 1 : inputs (a, b) output(z) - Step 2 : tabulate *2 변수의경우 Or a b z Z b a

62 2.2.3 Propositions, Truth Tables and Switching Functions * 3 변수의경우 Z a 0 1 bc * 4 변수의경우 Z ab cd S 3 i l i h i l l i f i AND - Step 3 : implement using the simple logic function AND - Step 4 : Combine the terms obtained from Step 3 : z = a x b

63 2.2.3 Propositions, Truth Tables and Switching Functions - [ 예 ] 부울함수의진리값을구하라 X Y Z F 1 = XY F 2 = YZ F 2 = F1 F = XY YZ

64 2.3.1 Logic Families 1) 디지털논리계열 (Logic families) * A set of logic gates using a single design technology * 종류 - RTL (Resistor-Transistor Logic) family - DTL (Diode-transistor logic) family - ECL (Emitter-Coupled Logic) family by Motorola - TTL (Transistor -Transistor Logic) family by Texas Instruments - MOS (Metal-oxide semiconductor) - CMOS (Complementary metal-oxide semiconductor) logic family - BiCMOS (Bipolar complementary metal-oxide semiconductor) * Transistor types: - ECL & TTL: utilize Bipolar transistors as the switching elements - CMOS utilizes MOSFET transistor t * Metrics for deciding what subfamily to use: - Product of speed and power consumption - Product of delay and power

65 2.3.1 Logic Families

66 2.5.1 Logic Families 4) Low-power TTL (74Lxx) - The same as standard TTL devices except that the resistor values are increased - Increased propagation delay 5) High-speed TTL (74Hxx) - The similar as standard TTL devices except that the resistor values are lower - Higher current flows required for faster switching operation 6) Schottky TTL (74Sxx) - The similar as standard TTL devices except that the transistors are replaced with Schottky-clamped transistors t - Approximately two times faster than H-series devices - The increased speed is accomplished by not allowing the transistors to go as deeply into saturation

67 집적회로 (ICs: Integrated Circuits) * 중요평가사항 (Some Characteristics of ICs) - Size and space - Reliability - Power Requirements -Cost -표준특성 * ASIC (Application-Specific ICs) * 집적도 (Levels of integration) 소규모집적 (Small-scale integrated : SSI) : 수십개이하의 gates 중규모집적 (Medium-scale integrated : MSI): 수백개의 gates 디코더, 계산기, 레지스터등 - 대규모집적 (Large-scale integrated : LSI) 수천개정도의 gates 프로세서, 기억장치칩, programmable module 등 - 초대규모집적 (Very large-scale integrated : VLSI) 만개이상의 gates 대규모기억장치, 마이크로칩

68 2.3.1 Logic Families TTL CMOS Description Hex inverter Hex inverter X x Four 2-input AND Three 3-input AND Two 4-input AND Four 2-input OR Three 3-input OR Two 4-input OR Four 2-input NAND Three 3-input NAND Two 4-input NAND One 8-input NAND x One 12-input NAND X x Four 2-input NOR Three 3-input NOR Two 4-input NOR Two 5-input NOR

69 2.3.1 Logic Families

70 2.3.1 Logic Families * Logic family comparison

71 2.3.2 Wired Logic: TTL circuits analysis * NOT gate utilizing a bipolar transistor

72 2.5.2 Wired Logic: Diode logic gates (1) AND 및 OR gates

73 2.5.2 Wired Logic: Diode logic gates

74 2.3.2 Wired Logic: Diode logic gates (2) NAND 및 NOR gates

75 2.3.2 Wired Logic 1) Tristate (High-Impedance or High-Z) Logic Gates * A state that the output has a very high impedance * When the additional enable input is active the gate behaves as a conventional gate, but when it is inactive the gate is in the high- impedance state 2) Open-Collector and Open-Drain Logic Gates * The collector or drain of the output transistor is an open circuit

76 2.3.2 Wired Logic: Diode logic gates 3) Open-collector TTL: useful when high current is necessary

77 2.3.3 Gate Properties * 표준특성 : 논리회로의평가기준 - 팬-인 (fan-in): the number of inputs available on a gate - 팬- 아웃 (fan-out): the number of standard d loads that t the output t of a typical gate can drive without impairing its performance; A standard load is usually defined as the amount of current needed by an input of another similar gate of the same family - 잡음여유 (noise margin): the maximum external noise voltage superimposed on a normal input value that will not cause an undesirable change in the output of the circuit - 전력소모량 (power dissipation): the power consumed by the gate and made available from the power supply - 전파지연시간 (propagation delay): the delay time for the change in value of a signal to propagate from input to output; t defined d as the maximum of tphl or tplh. high-to-low propagation time tphl : the delay measured from the reference voltage on the input voltage IN to the reference voltage on the output voltage OUT with the output voltage from H to L. low-to-high propagation time tplh : the delay measured from the reference voltage on the output voltage OUT to the reference voltage on the input voltage IN with the output voltage from L to H

78 2.3.3 Gate Properties

79 2.3.3 Gate Properties * Positive and negative logic - Positive logic Logic value Voltage level 0 L 1 H - Negative logic Logic value Voltage level 0 H 1 L

80 2.3.3 Gate Properties : IC Specifications IC Specifications 1) Summary: information describing the functional type and part number of the device - Operating temperature range - Truth or function table - Logic symbol or diagram - Boolean output equation - Packaging and pin configuration

81 2.3.3 Gate Properties : IC Specifications 2) Schematic diagram -Internal circuit diagram of the device - Absolute maximum ratings for VCC, input voltage, operating temperature, and storage temperatur

82 2.3.3 Gate Properties : IC Specifications 3) Electrical characteristics - Recommended operating conditions - Electrical characteristics - Switching characteristics

83 2.3.3 Gate Properties : IC Specifications

84 2.3.3 Gate Properties : Data sheet analysis 1) Power dissipation - Power consumed by the device P = V I D CC CC - Average power dissipation P D ( avg ) = VCC I CC( avg ) I CC ( avg ) = CCH 2) Noise immunity ( I I ) / 2 CCL - Measure of a circuit's ability to handle noise voltage on its inputs - Output voltages greater than V OH (min) are interpreted by the device as a logic 1 - Input voltages greater than V IH (min) are interpreted by the device as a logic 1

85 2.3.3 Gate Properties : Data sheet analysis - High-state noise margin V NMH = V OH (min) V IH (min) - For the 7400LS : VNMH = = 0.4 V - Output voltages less than V OL (min) are interpreted by the device as a logic 0 -Input voltages less than V IL( (min) will be interpreted by the device as a logic 0 - Low-state noise margin V NML = V OL(max) V IL(max) - For the 7400LS : VNMH = = 0.4 V

86 2.3.3 Gate Properties : Data sheet analysis

87 2.3.3 Gate Properties : Data sheet analysis 3) Fan-out - Maximum number of device inputs of the same logic family that a device output t can drive in parallel l - Calculation of fan-out Fan out = high Fan out = low - For the 74LS00 I I I I OH IH OL IL Fan I OH 0.4 ma out highh = = = 20 I 20 μa IH Fan out I 8 ma 0.4 ma OL low = = = I IL 20

88 2.3.3 Gate Properties : Data sheet analysis

89 2.3.3 Gate Properties : Data sheet analysis 4) Current sourcing and current sinking - Current sourcing: when the output of a gate is high and it is supplying current to the input of another gate or gates - Current sinking: when the output of a gate is low and current is flowing from the input of another gate or gates into the output

90 2.3.3 Gate Properties: CMOS circuit analysis CMOS circuit analysis - complementary metal-oxide semiconductor - slower propagation delays - far less power to operate than bipolar TTL devices - greater supply voltage range, higher fan-out capability, greater noise immunity than their TTL counterparts 1) Propagation delay - about 150 ns - 74HC high-speed CMOS series 2) Power dissipation - in the steady-state condition, a CMOS family device consumes virtually no power 3) Supply voltage - 3~18Vdc 4) Fan-out - ideally infinite due to its high input impedance(1012 ohms typical) - practically greater than 50 5) Noise immunity - for a supply voltage of 5 V, both the high noise margin and the low noise margin are approximately 1.5 V

91 2.3.3 Gate Properties : Interfacing logic families Interfacing logic families 1) Interfacing TTL devices to CMOS devices * typical solution is to connect the two logic families together using a pull-up resistor * typical value for the pull-up resistor when operating at 5 V is 2 kohm R R min max V = V = DD CC I I V OL max V IH min OL max IH min 2) Interfacing CMOS devices to TTL devices * the CMOS device output cannot sink enough current for the input of the TTL device in the logic 0 * the standard solution is to use a buffer

92 2.3.3 Gate Properties : Troubleshooting 1) Unused inputs to a TTL or CMOS device should always be connected to something. 2) An unused input on a TTL device will be perceived by the device as a logic 1 applied to its input. - Whereas unused TTL inputs that are left open become more susceptible to EMI and stray electronic interference, they generally can provide reliable operation. 3) Unused inputs of CMOS devices should be connected to either VDD or ground. - Open inputs on CMOS devices can lead to unpredictable operation and even oscillation. -increase the power consumption of the device and even destroy it 4) CMOS and TTL input-protection using input diodes 5) CMOS devices have a very high input impedance because MOS transistors are in effect an open circuit (1012 ohm). This makes CMOS devices highly susceptible to damage from static electricity. 6) Decoupling capacitors between the VCC and ground are used to eliminate unwanted transients, or spikes, on power supply lines of TTL devices to 1microF at the VCC input pin of an edge connector on a PCB - 001to F at the VCC input and ground for every one to three ICs. - install as close as possible to each IC, with the lead length of the capacitors being made as short as possible

93 Chapter 2 Boolean Algebra and Logic Gates Problems 2.1 What is logic? 2.2 What is a logic gate? 2.3 Identify and explain the three basic logic functions. 2.4 Identify and explain the two most common logic families. 2.5 Explain a DIP. 2.6 Describe a truth table. 2.7 Explain the active-state logic

94 Chapter 2 Boolean Algebra and Logic Gates 2.8 Give the logic symbol, truth table, and Boolean expression for the following: 1) AND gate 2) OR gate 3) Inverter 4) NAND gate 5) NOR gate 6) XOR gate 7) NXOR gate 29Designathree-input 2.9 input NAND gate and a three-input NOR gate using only AND gates, OR gates, and inverters In each of the following diagrams in Fig.(a) and (b), determine the output waveform Z using the input waveforms shown in Fig.(c).

歯02-BooleanFunction.PDF

歯02-BooleanFunction.PDF 2Boolean Algebra and Logic Gates 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 IC Chapter 2 Boolean Algebra & Logic Gates 1 Boolean Algebra 1854 George Boole Chapter 2 Boolean Algebra & Logic Gates 2 Duality Principle

More information

歯03-ICFamily.PDF

歯03-ICFamily.PDF Integrated Circuits SSI(Small Scale IC) 10 / ( ) MSI(Medium Scale IC) / (, ) LSI(Large Scale IC) / (LU) VLSI(Very Large Scale IC) - / (CPU, Memory) ULSI(Ultra Large Scale IC) - / ( ) GSI(Giant Large Scale

More information

ºÎ·ÏB

ºÎ·ÏB B B.1 B.2 B.3 B.4 B.5 B.1 2 (Boolean algebra). 1854 An Investigation of the Laws of Thought on Which to Found the Mathematical Theories of Logic and Probabilities George Boole. 1938 MIT Claude Sannon [SHAN38].

More information

Microsoft PowerPoint - dc_ch3 [호환 모드]

Microsoft PowerPoint - dc_ch3 [호환 모드] Chapter 3 Karnaugh Maps 명제 진리표디지털시스템논리회로 Logic map K-map 부울함수 : Switching Expressions and Logic Maps 논리적인접 * 오직 1비트만이다른입력변수의두조합을논리적으로인접하다고함 * [ 예 ](x 와 x ) x), (xy 와 x y) xy), (xyz 와 xy z) z), (abcd 와

More information

PowerPoint Presentation

PowerPoint Presentation 5 불대수 IT CookBook, 디지털논리회로 - 2 - 학습목표 기본논리식의표현방법을알아본다. 불대수의법칙을알아본다. 논리회로를논리식으로논리식을논리회로로표현하는방법을알아본다. 곱의합 (SOP) 과합의곱 (POS), 최소항 (minterm) 과최대항 (mxterm) 에대해알아본다. 01. 기본논리식의표현 02. 불대수법칙 03. 논리회로의논리식변환 04.

More information

Microsoft PowerPoint - ch03ysk2012.ppt [호환 모드]

Microsoft PowerPoint - ch03ysk2012.ppt [호환 모드] 전자회로 Ch3 iode Models and Circuits 김영석 충북대학교전자정보대학 2012.3.1 Email: kimys@cbu.ac.kr k Ch3-1 Ch3 iode Models and Circuits 3.1 Ideal iode 3.2 PN Junction as a iode 3.4 Large Signal and Small-Signal Operation

More information

歯15-ROMPLD.PDF

歯15-ROMPLD.PDF MSI & PLD MSI (Medium Scale Integrate Circuit) gate adder, subtractor, comparator, decoder, encoder, multiplexer, demultiplexer, ROM, PLA PLD (programmable logic device) fuse( ) array IC AND OR array sum

More information

untitled

untitled Logic and Computer Design Fundamentals Chapter 4 Combinational Functions and Circuits Functions of a single variable Can be used on inputs to functional blocks to implement other than block s intended

More information

PowerPoint Presentation

PowerPoint Presentation 5 불대수 Http://RAIC.kunsn..kr 2 학습목표 마스터제목스타일편집 기본논리식의표현방법을알아본다. 불대수의법칙을알아본다. 논리회로를논리식으로논리식을논리회로로표현하는방법을알아본다. 곱의합 (SOP) 과합의곱 (POS), 최소항 (minterm) 과최대항 (mxterm) 에대해알아본다. 01. 기본논리식의표현 02. 불대수법칙 03. 논리회로의논리식변환

More information

Microsoft PowerPoint - 제05장.ppt [호환 모드]

Microsoft PowerPoint - 제05장.ppt [호환 모드] Chapter 05 부울대수 1. 부울대수 부울대수 (boolean algebra) 를근거로한스위칭이론 (switching theory) 은논리설계에있어서이론적인근거가되는수학적체계. 부울대수 - 부울상수와부울변수로구성, 0과 1의두개값을가짐 - 논리레벨의여러정의 논리 0 False Off Low No Open Switch 논리 1 True On High Yes

More information

논리회로설계 3 장 성공회대학교 IT 융합학부 1

논리회로설계 3 장 성공회대학교 IT 융합학부 1 논리회로설계 3 장 성공회대학교 IT 융합학부 1 제 3 장기본논리회로 명제 참인지거짓인지정확하게나타낼수있는상황 ( 뜻이분명한문장 ) 2진논리 참과거짓 두가지논리로표시하는것 0 / 1 로표현가능 논리함수 여러개의 2진명제를복합적으로결합시켜표시하고, 이를수학적으로나타낸것 디지털논리회로 일정한입력에대하여논리적인판단을할수있는전자회로로구성 - 입력된 2진논리신호들에대해적당한

More information

3. 다음은카르노맵의표이다. 논리식을간략화한것은? < 나 > 4. 다음카르노맵을간략화시킨결과는? < >

3. 다음은카르노맵의표이다. 논리식을간략화한것은? < 나 > 4. 다음카르노맵을간략화시킨결과는? < > . 변수의수 ( 數 ) 가 3 이라면카르노맵에서몇개의칸이요구되는가? 2칸 나 4칸 다 6칸 8칸 < > 2. 다음진리표의카르노맵을작성한것중옳은것은? < 나 > 다 나 입력출력 Y - 2 - 3. 다음은카르노맵의표이다. 논리식을간략화한것은? < 나 > 4. 다음카르노맵을간략화시킨결과는? < > 2 2 2 2 2 2 2-3 - 5. 다음진리표를간략히한결과

More information

4장 논리 게이트

4장 논리 게이트 4 장논리게이트 게이트 : 논리연산수행 4.1 기본게이트 AND, OR, NOT, NOR, NAND, XOR, XNOR 버퍼게이트 버퍼 : 연결할회로사이에전류, 전압등의구동이나레벨을맞추기위한완충을목적으로사용 진리표와기호 진리표게이트기호 IEEE 표준기호 NC NC 16 15 14 13 12 11 10 9 MC14050B 버퍼게이트 1 2 3 4 5 6 7 Vcc

More information

Coriolis.hwp

Coriolis.hwp MCM Series 주요특징 MaxiFlo TM (맥시플로) 코리올리스 (Coriolis) 질량유량계 MCM 시리즈는 최고의 정밀도를 자랑하며 슬러리를 포함한 액체, 혼합 액체등의 질량 유량, 밀도, 온도, 보정된 부피 유량을 측정할 수 있는 질량 유량계 이다. 단일 액체 또는 2가지 혼합액체를 측정할 수 있으며, 강한 노이즈 에도 견디는 면역성, 높은 정밀도,

More information

01. Start JAVA!

01. Start JAVA! 03. 기본논리게이트 1 1. TTL 과 CMOS 논리레벨정의영역 TTL CMOS +V cc 전압 (Volt) 5 4 논리-1(2.5V~5V) 3 2 정의되지않은영역 1 논리-0(0V~0.8V) 0 전압 (Volt) 5 4 논리-1(3.5V~5V) 3 정의되지않은영역 2 1 논리-0(0V~1.5V) 0 V in collector V out base emitter

More information

Microsoft PowerPoint - AC3.pptx

Microsoft PowerPoint - AC3.pptx Chapter 3 Block Diagrams and Signal Flow Graphs Automatic Control Systems, 9th Edition Farid Golnaraghi, Simon Fraser University Benjamin C. Kuo, University of Illinois 1 Introduction In this chapter,

More information

PowerPoint Presentation

PowerPoint Presentation 논리회로기초요약 IT CookBook, 디지털논리회로 4-6 장, 한빛미디어 Setion 진수 진수표현법 기수가 인수, 사용. () = +. = 3 () () + + () +. () + + + () +. + () + - () +. + - () + -3 + -4 Setion 3 8 진수와 6 진수 8진수표현법 에서 7까지 8개의수로표현 67.36 (8) = 6

More information

5 장부울대수

5 장부울대수 5 장부울대수 5.1 부울대수 ã 부울대수 (boolen lgebr) 를근거로한스위칭이론 (swithing theory) 은논리설계에있어서이론적인근거가되는수학적체계. ã 부울대수 - 부울상수와부울변수로구성, 0과 1의두개값을가짐 - 논리레벨의여러정의 논리 0 Flse Off Low No Open Swith 논리 1 True On High Yes Closed

More information

5.1 부울대수 ã 부울대수 (oolen lger) 를근거로한스위칭이론 (swithing theory) 은논리설계에있어서이론적인근거가되는수학적체계. ã 부울대수 - 부울상수와부울변수로구성, 0과 1의두개값을가짐 - 논리레벨의여러정의 논리 0 Flse Off Low No

5.1 부울대수 ã 부울대수 (oolen lger) 를근거로한스위칭이론 (swithing theory) 은논리설계에있어서이론적인근거가되는수학적체계. ã 부울대수 - 부울상수와부울변수로구성, 0과 1의두개값을가짐 - 논리레벨의여러정의 논리 0 Flse Off Low No 5 장부울대수 5.1 부울대수 ã 부울대수 (oolen lger) 를근거로한스위칭이론 (swithing theory) 은논리설계에있어서이론적인근거가되는수학적체계. ã 부울대수 - 부울상수와부울변수로구성, 0과 1의두개값을가짐 - 논리레벨의여러정의 논리 0 Flse Off Low No Open Swith 논리 1 True On High Yes Closed swith

More information

Microsoft PowerPoint - CHAP-01 [호환 모드]

Microsoft PowerPoint - CHAP-01 [호환 모드] 컴퓨터구성 Lecture #2 Chapter : Digital Logic Circuits Spring, 203 컴퓨터구성 : Spring, 203: No. - Digital Computer Definition Digital vs. nalog Digital computer is a digital system that performs various computational

More information

THE JOURNAL OF KOREAN INSTITUTE OF ELECTROMAGNETIC ENGINEERING AND SCIENCE Sep.; 30(9),

THE JOURNAL OF KOREAN INSTITUTE OF ELECTROMAGNETIC ENGINEERING AND SCIENCE Sep.; 30(9), THE JOURNAL OF KOREAN INSTITUTE OF ELECTROMAGNETIC ENGINEERING AND SCIENCE. 2019 Sep.; 30(9), 712 717. http://dx.doi.org/10.5515/kjkiees.2019.30.9.712 ISSN 1226-3133 (Print) ISSN 2288-226X (Online) MOS

More information

` Companies need to play various roles as the network of supply chain gradually expands. Companies are required to form a supply chain with outsourcing or partnerships since a company can not

More information

MAX+plus II Getting Started - 무작정따라하기

MAX+plus II Getting Started - 무작정따라하기 무작정 따라하기 2001 10 4 / Version 20-2 0 MAX+plus II Digital, Schematic Capture MAX+plus II, IC, CPLD FPGA (Logic) ALTERA PLD FLEX10K Series EPF10K10QC208-4 MAX+plus II Project, Schematic, Design Compilation,

More information

Microsoft PowerPoint - ch07ysk2012.ppt [호환 모드]

Microsoft PowerPoint - ch07ysk2012.ppt [호환 모드] 전자회로 Ch7 CMOS Aplifiers 김영석 충북대학교전자정보대학 202.3. Eail: kiys@cbu.ac.kr k Ch7- 7. General Considerations 7.2 Coon-Source Stae Ch7 CMOS Aplifiers 7.3 Coon-Gate Stae 7.4 Source Follower 7.5 Suary and Additional

More information

6장 부울 함수의 간소화

6장 부울 함수의 간소화 6 장부울함수의간소화 개요 모든입력과출력조건이동일한경우에는가능한한논리회로를간단하게구성 논리회로간소화혹은최적화 부울식의간소화 : term을감소하거나 literal를감소한다. term은게이트의수, literal은게이트의입력수를나타낸다. 논리회로의동작속도향상, 소비전력감소등효율적인논리회로구성가능 논리회로를간소화하는방법 논리회로자체를간소화하는방법 논리회로를부울함수로표현한후부울함수를간소화

More information

歯AG-MX70P한글매뉴얼.PDF

歯AG-MX70P한글매뉴얼.PDF 120 V AC, 50/60 Hz : 52 W (with no optional accessories installed), indicates safety information. 70 W (with all optional accessories installed) : : (WxHxD) : : 41 F to 104 F (+ 5 C to + 40 C) Less than

More information

Microsoft PowerPoint Predicates and Quantifiers.ppt

Microsoft PowerPoint Predicates and Quantifiers.ppt 이산수학 () 1.3 술어와한정기호 (Predicates and Quantifiers) 2006 년봄학기 문양세강원대학교컴퓨터과학과 술어 (Predicate), 명제함수 (Propositional Function) x is greater than 3. 변수 (variable) = x 술어 (predicate) = P 명제함수 (propositional function)

More information

- 2 -

- 2 - - 1 - - 2 - 전기자동차충전기기술기준 ( 안 ) - 3 - 1 3 1-1 3 1-2 (AC) 26 1-3 (DC) 31 2 37 3 40-4 - 1 14, 10,, 2 3. 1-1 1. (scope) 600 V (IEC 60038) 500 V. (EV : Electric Vehicle) (PHEV : Plug-in Hybrid EV).. 2. (normative

More information

04-다시_고속철도61~80p

04-다시_고속철도61~80p Approach for Value Improvement to Increase High-speed Railway Speed An effective way to develop a highly competitive system is to create a new market place that can create new values. Creating tools and

More information

Microsoft PowerPoint - 제06장.ppt [호환 모드]

Microsoft PowerPoint - 제06장.ppt [호환 모드] 6 장부울함수의간소화 개요 모든입력과출력조건이동일한경우에는가능한한논리회로를간단하게구성 논리회로간소화혹은최적화 부울식의간소화 : term 을감소하거나 literal 를감소한다. term 은게이트의수, literal 은게이트의입력수를나타낸다. 논리회로의동작속도향상, 소비전력감소등효율적인논리회로구성가능 논리회로를간소화하는방법 논리회로자체를간소화하는방법 논리회로를부울함수로표현한후부울함수를간소화

More information

CD-6208_SM(new)

CD-6208_SM(new) Digital Amplifier MA-110 CONTENTS Specifications... 1 Electrical parts list... 2 top and bottom view of p.c. board... 10 Application... 12 block Diagram... 13 Schematic Diagram... 14 Exploded view of cabinet

More information

디지털공학 5판 7-8장

디지털공학 5판 7-8장 Flip-Flops c h a p t e r 07 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 292 flip flop Q Q Q 1 Q 0 set ON preset Q 0 Q 1 resetoff clear Q Q 1 2 SET RESET SET RESET 7 1 crossednand SET RESET SET RESET

More information

Video Stabilization

Video Stabilization 조합논리회로 2 (Combinational Logic Circuits 2) 2011 6th 강의내용 패리티생성기와검출기 (Parity generator & Checker) 인에이블 / 디제이블회로 (Enable/Disable Circuits) 디지털집적회로의기본특성 (Basic Characteristics of Digital ICs) 디지털시스템의문제해결 (Troubleshooting

More information

DC Link Application DC Link capacitor can be universally used for the assembly of low inductance DC buffer circuits and DC filtering, smoothing. They

DC Link Application DC Link capacitor can be universally used for the assembly of low inductance DC buffer circuits and DC filtering, smoothing. They DC Link Capacitor DC Link Application DC Link capacitor can be universally used for the assembly of low inductance DC buffer circuits and DC filtering, smoothing. They are Metallized polypropylene (SH-type)

More information

5. Kapitel URE neu

5. Kapitel URE neu URE Fuses for Semiconductor Protection European-British Standard Standards: IEC 60 269-4 BS 88-4 Class: ar Voltage ratings: AC 240 V AC 700 V Current ratings: 5 A 900 A Features / Benefits High interrupting

More information

°í¼®ÁÖ Ãâ·Â

°í¼®ÁÖ Ãâ·Â Performance Optimization of SCTP in Wireless Internet Environments The existing works on Stream Control Transmission Protocol (SCTP) was focused on the fixed network environment. However, the number of

More information

APOGEE Insight_KR_Base_3P11

APOGEE Insight_KR_Base_3P11 Technical Specification Sheet Document No. 149-332P25 September, 2010 Insight 3.11 Base Workstation 그림 1. Insight Base 메인메뉴 Insight Base Insight Insight Base, Insight Base Insight Base Insight Windows

More information

#Ȳ¿ë¼®

#Ȳ¿ë¼® http://www.kbc.go.kr/ A B yk u δ = 2u k 1 = yk u = 0. 659 2nu k = 1 k k 1 n yk k Abstract Web Repertoire and Concentration Rate : Analysing Web Traffic Data Yong - Suk Hwang (Research

More information

PowerChute Personal Edition v3.1.0 에이전트 사용 설명서

PowerChute Personal Edition v3.1.0 에이전트 사용 설명서 PowerChute Personal Edition v3.1.0 990-3772D-019 4/2019 Schneider Electric IT Corporation Schneider Electric IT Corporation.. Schneider Electric IT Corporation,,,.,. Schneider Electric IT Corporation..

More information

Microsoft PowerPoint - Appendix_SNU_Combinational Digital Logic Circuits.ppt

Microsoft PowerPoint - Appendix_SNU_Combinational Digital Logic Circuits.ppt CHAPTER 2 COMBINATIONAL LOGIC CIRCUITS What to study? - Binary Logic (Boolean Algebra) : 논리회로의기본수학 -Gates: 디지털시스템의기본구성소자 - How to design cost-effective circuits? Logic Circuits: - Combinational Logic Circuits

More information

개요 l 모든입력과출력조건이동일한경우에는가능한한논리회로를간단하게구성 à 논리회로간소화혹은최적화 부울식의간소화 : term 을감소하거나 literal 를감소한다. term 은게이트의수, literal 은게이트의입력수를나타낸다. l 논리회로의동작속도향상, 소비전력감소등효율

개요 l 모든입력과출력조건이동일한경우에는가능한한논리회로를간단하게구성 à 논리회로간소화혹은최적화 부울식의간소화 : term 을감소하거나 literal 를감소한다. term 은게이트의수, literal 은게이트의입력수를나타낸다. l 논리회로의동작속도향상, 소비전력감소등효율 6 장부울함수의간소화 개요 l 모든입력과출력조건이동일한경우에는가능한한논리회로를간단하게구성 à 논리회로간소화혹은최적화 부울식의간소화 : term 을감소하거나 literal 를감소한다. term 은게이트의수, literal 은게이트의입력수를나타낸다. l 논리회로의동작속도향상, 소비전력감소등효율적인논리회로구성가능 l 논리회로를간소화하는방법 논리회로자체를간소화하는방법

More information

4 CD Construct Special Model VI 2 nd Order Model VI 2 Note: Hands-on 1, 2 RC 1 RLC mass-spring-damper 2 2 ζ ω n (rad/sec) 2 ( ζ < 1), 1 (ζ = 1), ( ) 1

4 CD Construct Special Model VI 2 nd Order Model VI 2 Note: Hands-on 1, 2 RC 1 RLC mass-spring-damper 2 2 ζ ω n (rad/sec) 2 ( ζ < 1), 1 (ζ = 1), ( ) 1 : LabVIEW Control Design, Simulation, & System Identification LabVIEW Control Design Toolkit, Simulation Module, System Identification Toolkit 2 (RLC Spring-Mass-Damper) Control Design toolkit LabVIEW

More information

6 장부울함수의간소화

6 장부울함수의간소화 6 장부울함수의간소화 l l l 개요 모든입력과출력조건이동일한경우에는가능한한논리회로를간단하게구성 à 논리회로간소화혹은최적화 부울식의간소화 : term 을감소하거나 literal 를감소한다. term 은게이트의수, literal 은게이트의입력수를나타낸다. 논리회로의동작속도향상, 소비전력감소등효율적인논리회로구성가능 논리회로를간소화하는방법 논리회로자체를간소화하는방법

More information

개요 l 모든입력과출력조건이동일한경우에는가능한한논리회로를간단하게구성 à 논리회로간소화혹은최적화 부울식의간소화 : term 을감소하거나 literal 를감소한다. term 은게이트의수, literal 은게이트의입력수를나타낸다. l 논리회로의동작속도향상, 소비전력감소등효율

개요 l 모든입력과출력조건이동일한경우에는가능한한논리회로를간단하게구성 à 논리회로간소화혹은최적화 부울식의간소화 : term 을감소하거나 literal 를감소한다. term 은게이트의수, literal 은게이트의입력수를나타낸다. l 논리회로의동작속도향상, 소비전력감소등효율 6 장부울함수의간소화 개요 l 모든입력과출력조건이동일한경우에는가능한한논리회로를간단하게구성 à 논리회로간소화혹은최적화 부울식의간소화 : term 을감소하거나 literal 를감소한다. term 은게이트의수, literal 은게이트의입력수를나타낸다. l 논리회로의동작속도향상, 소비전력감소등효율적인논리회로구성가능 l 논리회로를간소화하는방법 논리회로자체를간소화하는방법

More information

Slide 1

Slide 1 Clock Jitter Effect for Testing Data Converters Jin-Soo Ko Teradyne 2007. 6. 29. 1 Contents Noise Sources of Testing Converter Calculation of SNR with Clock Jitter Minimum Clock Jitter for Testing N bit

More information

INDUCTION MOTOR 표지.gul

INDUCTION MOTOR 표지.gul INDUCTION MOTOR NEW HSERIES INDUCTION MOTOR HEX Series LEAD WIRE TYPE w IH 1PHASE 4 POLE PERFORMANCE DATA (DUTY : CONTINUOUS) MOTOR TYPE IHPF10 IHPF11 IHPF IHPF22 IHPFN1U IHPFN2C OUTPUT 4 VOLTAGE

More information

Slide 1

Slide 1 Linear Technology Corporation Power Seminar LDO 2016. 10. 12. LTC Korea 영업강전도부장 010-8168-6852 jdkang@linear.com 기술박종만차장 010-2390-2843 jmpark@linear.com LDO 목차 1) LDO feedback 동작원리, 2) LDO 종류 3) LDO 특성

More information

Chapter4.hwp

Chapter4.hwp Ch. 4. Spectral Density & Correlation 4.1 Energy Spectral Density 4.2 Power Spectral Density 4.3 Time-Averaged Noise Representation 4.4 Correlation Functions 4.5 Properties of Correlation Functions 4.6

More information

예제 1.1 ( 관계연산자 ) >> A=1:9, B=9-A A = B = >> tf = A>4 % 4 보다큰 A 의원소들을찾을경우 tf = >> tf = (A==B) % A

예제 1.1 ( 관계연산자 ) >> A=1:9, B=9-A A = B = >> tf = A>4 % 4 보다큰 A 의원소들을찾을경우 tf = >> tf = (A==B) % A 예제 1.1 ( 관계연산자 ) >> A=1:9, B=9-A A = 1 2 3 4 5 6 7 8 9 B = 8 7 6 5 4 3 2 1 0 >> tf = A>4 % 4 보다큰 A 의원소들을찾을경우 tf = 0 0 0 0 1 1 1 1 1 >> tf = (A==B) % A 의원소와 B 의원소가똑같은경우를찾을때 tf = 0 0 0 0 0 0 0 0 0 >> tf

More information

Manufacturing6

Manufacturing6 σ6 Six Sigma, it makes Better & Competitive - - 200138 : KOREA SiGMA MANAGEMENT C G Page 2 Function Method Measurement ( / Input Input : Man / Machine Man Machine Machine Man / Measurement Man Measurement

More information

2 / 26

2 / 26 1 / 26 2 / 26 3 / 26 4 / 26 5 / 26 6 / 26 7 / 26 8 / 26 9 / 26 10 / 26 11 / 26 12 / 26 13 / 26 14 / 26 o o o 15 / 26 o 16 / 26 17 / 26 18 / 26 Comparison of RAID levels RAID level Minimum number of drives

More information

- 2 -

- 2 - - 1 - - 2 - - 3 - - 4 - - 5 - - 6 - - 7 - - 8 - - 9 - - 10 - - 11 - - 12 - - 13 - - 14 - - 15 - - 16 - - 17 - - 18 - - 19 - - 20 - - 21 - - 22 - - 23 - - 24 - - 25 - - 26 - - 27 - - 28 - - 29 - - 30 -

More information

2

2 2 3 4 5 6 7 8 9 10 11 60.27(2.37) 490.50(19.31) 256.00 (10.07) 165.00 111.38 (4.38) 9.00 (0.35) 688.00(27.08) 753.00(29.64) 51.94 (2.04) CONSOLE 24CH 32CH 40CH 48CH OVERALL WIDTH mm (inches) 1271.45(50.1)

More information

- i - - ii - - iii - - iv - - v - - vi - - 1 - - 2 - - 3 - 1) 통계청고시제 2010-150 호 (2010.7.6 개정, 2011.1.1 시행 ) - 4 - 요양급여의적용기준및방법에관한세부사항에따른골밀도검사기준 (2007 년 11 월 1 일시행 ) - 5 - - 6 - - 7 - - 8 - - 9 - - 10 -

More information

歯동작원리.PDF

歯동작원리.PDF UPS System 1 UPS UPS, Converter,,, Maintenance Bypass Switch 5 DC Converter DC, DC, Rectifier / Charger Converter DC, /, Filter Trouble, Maintenance Bypass Switch UPS Trouble, 2 UPS 1) UPS UPS 100W KVA

More information

Microsoft PowerPoint - ch25ysk.pptx

Microsoft PowerPoint - ch25ysk.pptx Dynamic Analog ircuits (h. 5) 김영석 충북대학교전자정보대학 0.3.. Email: kimys@cbu.ac.kr 전자정보대학김영석 5- ontents 5. The MOSFET Switch 5. Fully Differential ircuits 5.3 Switched-apacitor ircuit 전자정보대학김영석 5- 5. The MOSFET

More information

Microsoft Word - logic2005.doc

Microsoft Word - logic2005.doc 제 8 장 Counters 실험의목표 - Catalog counter 의동작원리에대하여익힌다. - 임의의 counter를통하여 FSM 구현방법을익힌다. - 7-segment display 의동작원리를이해한다. 실험도움자료 1. 7-segment display 7-segment는디지털회로에서숫자를표시하기위하여가장많이사용하는소자이다. 이름에서알수있듯이 7개의 LED(

More information

Microsoft Power Point 2002

Microsoft Power Point 2002 PLC전기공압제어 강의 노트 제 7 회차 PLC 하드웨어의 구조 - 1 - 학습목표 1. PLC 하드웨어의 4가지 구성요소를 설명할 수 있다. 2. PLC 형명을 보고 PLC를 구분할 수 있다. 3. PLC 배선형태에 따라 입력기기와 출력기기를 구분할 수 있다. Lesson. PLC 하드웨어의 구조 PLC 하드웨어에 대한 이해의 필요성 PLC 하드웨어의 구성

More information

슬라이드 1

슬라이드 1 Pairwise Tool & Pairwise Test NuSRS 200511305 김성규 200511306 김성훈 200614164 김효석 200611124 유성배 200518036 곡진화 2 PICT Pairwise Tool - PICT Microsoft 의 Command-line 기반의 Free Software www.pairwise.org 에서다운로드후설치

More information

Ⅰ. Introduction 우리들을 둘러싸고 잇는 생활 환경속에는 무수히 많은 색들이 있습니다. 색은 구매의욕이나 기호, 식욕 등의 감각을 좌우하는 것은 물론 나뭇잎의 변색에서 초목의 건강상태를 알며 물질의 판단에 이르기까지 광범위하고도 큰 역할을 하고 있습니다. 하

Ⅰ. Introduction 우리들을 둘러싸고 잇는 생활 환경속에는 무수히 많은 색들이 있습니다. 색은 구매의욕이나 기호, 식욕 등의 감각을 좌우하는 것은 물론 나뭇잎의 변색에서 초목의 건강상태를 알며 물질의 판단에 이르기까지 광범위하고도 큰 역할을 하고 있습니다. 하 색 이론과 색채관리 Ⅰ. Introduction( 일반색채 이론) Ⅱ. 색의 표현 ⅰ) 색상 ⅱ) 명도 ⅲ) 채도 ⅳ) 색의 종류 ⅴ) 색의 삼원색 ⅵ) 색의 사원색 Ⅲ. 색의 전달 ⅰ) 변천과정 ⅱ) Color space Ⅳ. 색의 재현 ⅰ) 가법 혼합 ⅱ) 감법 혼합 ⅲ) C.C.M System Ⅴ. 색의 관리 ⅰ) 목적 ⅱ) 적용범위 ⅲ) 색차계 ⅳ)

More information

,,,,,, (41) ( e f f e c t ), ( c u r r e n t ) ( p o t e n t i a l difference),, ( r e s i s t a n c e ) 2,,,,,,,, (41), (42) (42) ( 41) (Ohm s law),

,,,,,, (41) ( e f f e c t ), ( c u r r e n t ) ( p o t e n t i a l difference),, ( r e s i s t a n c e ) 2,,,,,,,, (41), (42) (42) ( 41) (Ohm s law), 1, 2, 3, 4, 5, 6 7 8 PSpice EWB,, ,,,,,, (41) ( e f f e c t ), ( c u r r e n t ) ( p o t e n t i a l difference),, ( r e s i s t a n c e ) 2,,,,,,,, (41), (42) (42) ( 41) (Ohm s law), ( ),,,, (43) 94 (44)

More information

<4D F736F F F696E74202D F FB5BFBACEC7CFC0CCC5D820B1E8BFA9C8B22E BC8A3C8AF20B8F0B5E55D>

<4D F736F F F696E74202D F FB5BFBACEC7CFC0CCC5D820B1E8BFA9C8B22E BC8A3C8AF20B8F0B5E55D> Back Metal 면이 Drain 인 Vertical channel MOSFET 의 Wafer Test 에서 Chuck 을사용하지않는 RDSON 측정방법 동부하이텍검사팀김여황 I RDSON II Conventional Method III New Method IV Verification (Rdson) V Normal Test Item VI Conclusion

More information

182 동북아역사논총 42호 금융정책이 조선에 어떤 영향을 미쳤는지를 살펴보고자 한다. 일제 대외금융 정책의 기본원칙은 각 식민지와 점령지마다 별도의 발권은행을 수립하여 일본 은행권이 아닌 각 지역 통화를 발행케 한 점에 있다. 이들 통화는 일본은행권 과 等 價 로 연

182 동북아역사논총 42호 금융정책이 조선에 어떤 영향을 미쳤는지를 살펴보고자 한다. 일제 대외금융 정책의 기본원칙은 각 식민지와 점령지마다 별도의 발권은행을 수립하여 일본 은행권이 아닌 각 지역 통화를 발행케 한 점에 있다. 이들 통화는 일본은행권 과 等 價 로 연 越 境 하는 화폐, 분열되는 제국 - 滿 洲 國 幣 의 조선 유입 실태를 중심으로 181 越 境 하는 화폐, 분열되는 제국 - 滿 洲 國 幣 의 조선 유입 실태를 중심으로 - 조명근 고려대학교 BK21+ 한국사학 미래인재 양성사업단 연구교수 Ⅰ. 머리말 근대 국민국가는 대내적으로는 특정하게 구획된 영토에 대한 배타적 지배와 대외적 자주성을 본질로 하는데, 그

More information

서강대학교 기초과학연구소대학중점연구소 심포지엄기초과학연구소

서강대학교 기초과학연구소대학중점연구소 심포지엄기초과학연구소 2012 년도기초과학연구소 대학중점연구소심포지엄 마이크로파센서를이용한 혈당측정연구 일시 : 2012 년 3 월 20 일 ( 화 ) 14:00~17:30 장소 : 서강대학교과학관 1010 호 주최 : 서강대학교기초과학연구소 Contents Program of Symposium 2 Non-invasive in vitro sensing of D-glucose in

More information

SW_faq2000번역.PDF

SW_faq2000번역.PDF FREUENTLY ASKED UESTIONS ON SPEED2000 Table of Contents EDA signal integrity tool (vias) (via) /, SI, / SPEED2000 SPEED2000 EDA signal integrity tool, ( (via),, / ), EDA, 1,, / 2 FEM, PEEC, MOM, FDTD EM

More information

Product A4

Product A4 2 APTIV Film Versatility and Performance APTIV Film Versatility and Performance 3 4 APTIV Film Versatility and Performance APTIV Film Versatility and Performance 5 PI Increasing Performance PES PPSU PSU

More information

Microsoft PowerPoint - 26.pptx

Microsoft PowerPoint - 26.pptx 이산수학 () 관계와그특성 (Relations and Its Properties) 2011년봄학기 강원대학교컴퓨터과학전공문양세 Binary Relations ( 이진관계 ) Let A, B be any two sets. A binary relation R from A to B, written R:A B, is a subset of A B. (A 에서 B 로의이진관계

More information

Microsoft PowerPoint - 27.pptx

Microsoft PowerPoint - 27.pptx 이산수학 () n-항관계 (n-ary Relations) 2011년봄학기 강원대학교컴퓨터과학전공문양세 n-ary Relations (n-항관계 ) An n-ary relation R on sets A 1,,A n, written R:A 1,,A n, is a subset R A 1 A n. (A 1,,A n 에대한 n- 항관계 R 은 A 1 A n 의부분집합이다.)

More information

<313630313032C6AFC1FD28B1C7C7F5C1DF292E687770>

<313630313032C6AFC1FD28B1C7C7F5C1DF292E687770> 양성자가속기연구센터 양성자가속기 개발 및 운영현황 DOI: 10.3938/PhiT.25.001 권혁중 김한성 Development and Operational Status of the Proton Linear Accelerator at the KOMAC Hyeok-Jung KWON and Han-Sung KIM A 100-MeV proton linear accelerator

More information

Microsoft PowerPoint - analogic_kimys_ch10.ppt

Microsoft PowerPoint - analogic_kimys_ch10.ppt Stability and Frequency Compensation (Ch. 10) 김영석충북대학교전자정보대학 2010.3.1 Email: kimys@cbu.ac.kr 전자정보대학김영석 1 Basic Stability 10.1 General Considerations Y X (s) = H(s) 1+ βh(s) May oscillate at ω if βh(jω)

More information

6자료집최종(6.8))

6자료집최종(6.8)) Chapter 1 05 Chapter 2 51 Chapter 3 99 Chapter 4 151 Chapter 1 Chapter 6 7 Chapter 8 9 Chapter 10 11 Chapter 12 13 Chapter 14 15 Chapter 16 17 Chapter 18 Chapter 19 Chapter 20 21 Chapter 22 23 Chapter

More information

PowerPoint 프레젠테이션

PowerPoint 프레젠테이션 EBC (Equipment Behaviour Catalogue) - ISO TC 184/SC 5/SG 4 신규표준이슈 - 한국전자통신연구원김성혜 목차 Prologue: ISO TC 184/SC 5 그룹 SG: Study Group ( 표준이슈발굴 ) WG: Working Group ( 표준개발 ) 3 EBC 배경 제안자 JISC (Japanese Industrial

More information

DE1-SoC Board

DE1-SoC Board 실습 1 개발환경 DE1-SoC Board Design Tools - Installation Download & Install Quartus Prime Lite Edition http://www.altera.com/ Quartus Prime (includes Nios II EDS) Nios II Embedded Design Suite (EDS) is automatically

More information

solution map_....

solution map_.... SOLUTION BROCHURE RELIABLE STORAGE SOLUTIONS ETERNUS FOR RELIABILITY AND AVAILABILITY PROTECT YOUR DATA AND SUPPORT BUSINESS FLEXIBILITY WITH FUJITSU STORAGE SOLUTIONS kr.fujitsu.com INDEX 1. Storage System

More information

Page 2 of 5 아니다 means to not be, and is therefore the opposite of 이다. While English simply turns words like to be or to exist negative by adding not,

Page 2 of 5 아니다 means to not be, and is therefore the opposite of 이다. While English simply turns words like to be or to exist negative by adding not, Page 1 of 5 Learn Korean Ep. 4: To be and To exist Of course to be and to exist are different verbs, but they re often confused by beginning students when learning Korean. In English we sometimes use the

More information

82-01.fm

82-01.fm w y wz 8«( 2y) 57~61, 2005 J. of the Korean Society for Environmental Analysis p w w Á Á w w» y l Analysis of Influence Factors and Corrosion Characteristics of Water-pipe in Potable Water System Jae Seong

More information

Microsoft PowerPoint Relations.pptx

Microsoft PowerPoint Relations.pptx 이산수학 () 관계와그특성 (Relations and Its Properties) 2010년봄학기강원대학교컴퓨터과학전공문양세 Binary Relations ( 이진관계 ) Let A, B be any two sets. A binary relation R from A to B, written R:A B, is a subset of A B. (A 에서 B 로의이진관계

More information

Microsoft PowerPoint - dev6_TCAD.ppt [호환 모드]

Microsoft PowerPoint - dev6_TCAD.ppt [호환 모드] TCAD: SUPREM, PISCES 김영석 충북대학교전자정보대학 2012.9.1 Email: kimys@cbu.ac.kr k 전자정보대학김영석 1 TCAD TCAD(Technology Computer Aided Design, Technology CAD) Electronic design automation Process CAD Models process steps

More information

<BFACBDC0B9AEC1A6C7AEC0CC5F F E687770>

<BFACBDC0B9AEC1A6C7AEC0CC5F F E687770> IT OOKOOK 87 이론, 실습, 시뮬레이션 디지털논리회로 ( 개정 3 판 ) (Problem Solutions of hapter 7) . 반감산기와전감산기를설계 반감산기반감산기는한비트의 2진수 에서 를빼는회로이며, 두수의차 (difference, ) 와빌림수 (barrow, ) 를계산하는뺄셈회로이다. 에서 를뺄수없으면윗자리에서빌려와빼야하며, 이때빌려오는수는윗자리에서가져오므로

More information

(Exposure) Exposure (Exposure Assesment) EMF Unknown to mechanism Health Effect (Effect) Unknown to mechanism Behavior pattern (Micro- Environment) Re

(Exposure) Exposure (Exposure Assesment) EMF Unknown to mechanism Health Effect (Effect) Unknown to mechanism Behavior pattern (Micro- Environment) Re EMF Health Effect 2003 10 20 21-29 2-10 - - ( ) area spot measurement - - 1 (Exposure) Exposure (Exposure Assesment) EMF Unknown to mechanism Health Effect (Effect) Unknown to mechanism Behavior pattern

More information

Output file

Output file 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 An Application for Calculation and Visualization of Narrative Relevance of Films Using Keyword Tags Choi Jin-Won (KAIST) Film making

More information

<BACEBDBAC5CD20BAEAB7CEBCC52D A2DC3D6C1BE2D312D E6169>

<BACEBDBAC5CD20BAEAB7CEBCC52D A2DC3D6C1BE2D312D E6169> DOOCH PUMP Intelligent pressure boosting system 5Hz BOOSTER PUMP SYSTEM Water supply system Pressure boosting system Irrigation system Water treatment system Industrial plants 두크펌프 www.doochpump.com CONTENTS

More information

<313920C0CCB1E2BFF82E687770>

<313920C0CCB1E2BFF82E687770> 韓 國 電 磁 波 學 會 論 文 誌 第 19 卷 第 8 號 2008 年 8 月 論 文 2008-19-8-19 K 대역 브릭형 능동 송수신 모듈의 설계 및 제작 A Design and Fabrication of the Brick Transmit/Receive Module for K Band 이 기 원 문 주 영 윤 상 원 Ki-Won Lee Ju-Young Moon

More information

REVERSIBLE MOTOR 표지.gul

REVERSIBLE MOTOR 표지.gul REVERSIBLE MOTOR NEW H-SERIES REVERSIBLE MOTOR H-EX Series LEAD WIRE w RH 1PHASE 4 POLE PERFORMANCE DATA (DUTY : Min.) MOTOR OUTPUT VOLTAGE (V) FREQUENCY (Hz) INPUT CURRENT (ma) RATING SPEED (rpm) STARTING

More information

슬라이드 제목 없음

슬라이드 제목 없음 물리화학 1 문제풀이 130403 김대형교수님 Chapter 1 Exercise (#1) A sample of 255 mg of neon occupies 3.00 dm 3 at 122K. Use the perfect gas law to calculate the pressure of the gas. Solution 1) The perfect gas law p

More information

Buy one get one with discount promotional strategy

Buy one get one with discount promotional strategy Buy one get one with discount Promotional Strategy Kyong-Kuk Kim, Chi-Ghun Lee and Sunggyun Park ISysE Department, FEG 002079 Contents Introduction Literature Review Model Solution Further research 2 ISysE

More information

#KM-235(110222)

#KM-235(110222) PARTS BOOK KM-235A/B INFORMATION A. Parts Book Structure of Part Book Unique code by mechanism Unique name by mechanism Explode view Ref. No. : Unique identifcation number by part Parts No. : Unique Product

More information

서보교육자료배포용.ppt

서보교육자료배포용.ppt 1. 2. 3. 4. 1. ; + - & (22kW ) 1. ; 1975 1980 1985 1990 1995 2000 DC AC (Ferrite) (NdFeB; ) /, Hybrid Power Thyrister TR IGBT IPM Analog Digital 16 bit 32 bit DSP RISC Dip SMD(Surface Mount Device) P,

More information

Microsoft PowerPoint - 7-Work and Energy.ppt

Microsoft PowerPoint - 7-Work and Energy.ppt Chapter 7. Work and Energy 일과운동에너지 One of the most important concepts in physics Alternative approach to mechanics Many applications beyond mechanics Thermodynamics (movement of heat) Quantum mechanics...

More information

THE JOURNAL OF KOREAN INSTITUTE OF ELECTROMAGNETIC ENGINEERING AND SCIENCE Aug.; 30(8),

THE JOURNAL OF KOREAN INSTITUTE OF ELECTROMAGNETIC ENGINEERING AND SCIENCE Aug.; 30(8), THE JOURNAL OF KOREAN INSTITUTE OF ELECTROMAGNETIC ENGINEERING AND SCIENCE. 2019 Aug.; 30(8), 629639. http://dx.doi.org/10.5515/kjkiees.2019.30.8.629 ISSN 1226-3133 (Print)ISSN 2288-226X (Online) Analysis

More information

Microsoft Word - SRA-Series Manual.doc

Microsoft Word - SRA-Series Manual.doc 사 용 설 명 서 SRA Series Professional Power Amplifier MODEL No : SRA-500, SRA-900, SRA-1300 차 례 차 례 ---------------------------------------------------------------------- 2 안전지침 / 주의사항 -----------------------------------------------------------

More information

λx.x (λz.λx.x z) (λx.x)(λz.(λx.x)z) (λz.(λx.x) z) Call-by Name. Normal Order. (λz.z)

λx.x (λz.λx.x z) (λx.x)(λz.(λx.x)z) (λz.(λx.x) z) Call-by Name. Normal Order. (λz.z) λx.x (λz.λx.x z) (λx.x)(λz.(λx.x)z) (λz.(λx.x) z) Call-by Name. Normal Order. (λz.z) Simple Type System - - 1+malloc(), {x:=1,y:=2}+2,... (stuck) { } { } ADD σ,m e 1 n 1,M σ,m e 1 σ,m e 2 n 2,M + e 2 n

More information

<32382DC3BBB0A2C0E5BED6C0DA2E687770>

<32382DC3BBB0A2C0E5BED6C0DA2E687770> 논문접수일 : 2014.12.20 심사일 : 2015.01.06 게재확정일 : 2015.01.27 청각 장애자들을 위한 보급형 휴대폰 액세서리 디자인 프로토타입 개발 Development Prototype of Low-end Mobile Phone Accessory Design for Hearing-impaired Person 주저자 : 윤수인 서경대학교 예술대학

More information

11¹Ú´ö±Ô

11¹Ú´ö±Ô A Review on Promotion of Storytelling Local Cultures - 265 - 2-266 - 3-267 - 4-268 - 5-269 - 6 7-270 - 7-271 - 8-272 - 9-273 - 10-274 - 11-275 - 12-276 - 13-277 - 14-278 - 15-279 - 16 7-280 - 17-281 -

More information

DIB-100_K(90x120)

DIB-100_K(90x120) Operation Manual 사용설명서 Direct Box * 본 제품을 사용하기 전에 반드시 방송방식 및 전원접압을 확인하여 사용하시기 바랍니다. MADE IN KOREA 2009. 7 124447 사용하시기 전에 사용하시기 전에 본 기기의 성능을 충분히 발휘시키기 위해 본 설명서를 처음부터 끝까지 잘 읽으시고 올바른 사용법으로 오래도록 Inter-M 제품을

More information

Gray level 변환 및 Arithmetic 연산을 사용한 영상 개선

Gray level 변환 및 Arithmetic 연산을 사용한 영상 개선 Point Operation Histogram Modification 김성영교수 금오공과대학교 컴퓨터공학과 학습내용 HISTOGRAM HISTOGRAM MODIFICATION DETERMINING THRESHOLD IN THRESHOLDING 2 HISTOGRAM A simple datum that gives the number of pixels that a

More information

(specifications) 3 ~ 10 (introduction) 11 (storage bin) 11 (legs) 11 (important operating requirements) 11 (location selection) 12 (storage bin) 12 (i

(specifications) 3 ~ 10 (introduction) 11 (storage bin) 11 (legs) 11 (important operating requirements) 11 (location selection) 12 (storage bin) 12 (i SERVICE MANUAL N200M / N300M / N500M ( : R22) e-mail : jhyun00@koreacom homepage : http://wwwicematiccokr (specifications) 3 ~ 10 (introduction) 11 (storage bin) 11 (legs) 11 (important operating requirements)

More information

(Table of Contents) 2 (Specifications) 3 ~ 10 (Introduction) 11 (Storage Bins) 11 (Legs) 11 (Important Operating Requirements) 11 (Location Selection)

(Table of Contents) 2 (Specifications) 3 ~ 10 (Introduction) 11 (Storage Bins) 11 (Legs) 11 (Important Operating Requirements) 11 (Location Selection) SERVICE MANUAL (Table of Contents) 2 (Specifications) 3 ~ 10 (Introduction) 11 (Storage Bins) 11 (Legs) 11 (Important Operating Requirements) 11 (Location Selection) 12 (Storage Bins) 12 (Ice Machine)

More information

4. #include <stdio.h> #include <stdlib.h> int main() { functiona(); } void functiona() { printf("hihi\n"); } warning: conflicting types for functiona

4. #include <stdio.h> #include <stdlib.h> int main() { functiona(); } void functiona() { printf(hihi\n); } warning: conflicting types for functiona 이름 : 학번 : A. True or False: 각각항목마다 True 인지 False 인지적으세요. 1. (Python:) randint 함수를사용하려면, random 모듈을 import 해야한다. 2. (Python:) '' (single quote) 는한글자를표현할때, (double quote) 는문자열을표현할때사용한다. B. 다음에러를수정하는방법을적으세요.

More information

PJTROHMPCJPS.hwp

PJTROHMPCJPS.hwp 제 출 문 농림수산식품부장관 귀하 본 보고서를 트위스트 휠 방식 폐비닐 수거기 개발 과제의 최종보고서로 제출 합니다. 2008년 4월 24일 주관연구기관명: 경 북 대 학 교 총괄연구책임자: 김 태 욱 연 구 원: 조 창 래 연 구 원: 배 석 경 연 구 원: 김 승 현 연 구 원: 신 동 호 연 구 원: 유 기 형 위탁연구기관명: 삼 생 공 업 위탁연구책임자:

More information