Microsoft PowerPoint - dc_ch2 [호환 모드]
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1 Chapter 2 Boolean Algebra and Logic Circuits
2 Chapter 2 Boolean Algebra and Logic Circuits 2.1 Boolean Algebra Definition of Boolean Algebra Fundamental Theorems Switching Algebra Switching Operations and Gates 2.2 Switching Formulas and Functions Switching Formulas Manipulation of Switching Formula Propositions, Truth Tables and Switching Functions 2.3 Realization of Logic Functions Logic Families Wired Logic Gate Properties Problems
3 2.1 Boolean algebra 2.1 Definition of a Boolean Algebra * George Boole ( ) 1864) : 논리와수학적해석 : 사고법칙에대한고찰 (An Investigation of the Laws of Thoughts) : 미분방정식론 : 차분법론 * Boolean Algebra - Algebra for symbolically representing problems in complex logic statements involving propositions which are only true or false -2진변수와논리연산자를다루는대수를말함 * Claude E. Shannon - Application of a Boolean algebra to the design of relay networks in telephone systems * Switching circuit theory - The study of Boolean algebra as applied to logic design
4 2.1 Boolean Algebra 용어정리 * 논리 (Logic): Science of arguments which involve ascertaining the validity of a series of interdependent d t propositions (clearly l defined d statements), t t which h may be simple or compound *2 진논리 (Binary Logic): 오직 2 개의값 (0 과 1, 참 (T) 및거짓 (F), On 및 Off 등등 ) 만을갖는변수와이들변수에대한수학적연산에의한논리 * 2진변수 (Binary Variables): zero(0) 또는 one(1) 만을가지는변수 * 논리연산자 (Logical Operators): 논리연산을수행하는연산자 (AND, OR, NOT) * 논리함수 (Logic Functions): 입출력사이의관계를나타내는함수 * 진리표 (Truth Tables): 모든가능한경우의논리적입 / 출력사이의관계를나타낸표 * 부울대수 (Boolean Algebra): 논리연산자를사용하여논리적기능을처리하는수학 * 부울식 (Boolean Expressions or Formulas): 논리적기능을 Boolean constant, variables, 그리고 Boolean operations 을이용하여나타낸식
5 2.1 Boolean Algebra 명제 진리표디지털시스템논리회로 Logic map K-map 부울함수
6 2.1 Boolean Algebra Basic Logic Operations and Symbols * NOT: changes one logic level to the opposite logic level * AND: produces a HIGH output only if all the inputs are HIGH * OR: produces a HIGH output when any of the inputs is HIGH
7 2.1 Boolean Algebra 진리표 부울식 ( 부울함수 ) 으로의변환 출력값이 1 이되게하는입력변수의조합으로표현 [ 예 ] f is 1 if a b = 1 OR if ab = 1 OR if ab = 1 f = a b ab ab a b a b a b a b a b f
8 2.1 Boolean Algebra: 진리표 부울식 ( 부울함수 ) 으로변환 f is 1 if a=0 AND b = 1 OR if a = 1 AND b = 0 OR if a = 1 AND b = 1 f is 1 if a = 1 AND b = 1 OR if a = 1 AND b = 1 OR if a = 1 AND b = 1 f is 1 if a b = 1 OR if ab = 1 OR if ab = 1 f = a b ab ab
9 2.1 Boolean Algebra 진리표의간소화 (simplification) (1) 대수적인방법 * 부울대수의여러가지성질을이용하는방법 * 일의적인방법이아님 (2) 카노우도표방법 (Karnaugh map) * 진리표상의최소항의개수만큼의정사각형을 2차원의표로나타낸것 * K-map map, Veitch diagram * 진리표 2차원표 * 최소항, 최대항 정사각형 ; 진리표상의출력값이 1 인정사각형에 1 을대응시킴 * [ 예 ] n 변수: 2 n 개의최소항 ( 최대항 ) 2 n 개의정사각형
10 2.1 Definition of a Boolean Algebra * Definition of a Boolean algebra - A mathematical system B satisfying the following postulates:
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12 2.1 Definition of a Boolean Algebra * 부울함수 (Boolean functions) - 입력 (A, B,, Z 혹은 ab a,b,, z) 과출력 (F 혹은 Y) 을나타내는 2 진변수, 등호 (=), 상수 (0, 1), 괄호 ( ( ) ) 및논리연산기호,,, 등등을사용하여이루어진대수적표현을말함. - [ 예 ] F= X YZ, Y = ( a b )x( X Y ) - 부울함수의결과값은주어진입력변수가갖는모든값들의조합에대하여, 부울함수를구성하는항 (terms) 들각각에대한논리연산결과값을구한후, 이들을결합하는연산을수행하여구함.
13 2.1.2 Fundamental Theorems 쌍대성원리 (Principle of Duality) * 쌍대형태 (dual form): 어떤대수적표현의쌍대 (dual) 는 () 와 (.) 를서로교환하고, 0은 1 로 1 은 0 으로변환함으로써얻어짐. * < 주의 >: 일반적으로어떤대수적표현의쌍대진리값은그것의원래표현의진리값과는서로같지않으므로이를서로대치할수없음.
14 2.1.2 Fundamental Theorems
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16 2.1.2 Fundamental Theorems
17 2.1.2 Fundamental Theorems
18 2.1.2 Fundamental Theorems
19 2.1.2 Fundamental Theorems
20 2.1.2 Fundamental Theorems
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22 2.1.2 Fundamental Theorems * Redundancy Law - a x (a b) = a; a ( a b ) = a ab = a( b b ) ab = ab ab ab = a( b b ) = a 1 = a -a (a x b) = a; a ( a b ) = a( b b ) ab = ab ab ab = a( b b ) = a 1 = a * Nashelsky's theorem - ax(a c b)= axb; a ( a b ) = aa ab = ab -a (a c x b) = a b [ 예 1] F= X (Y Z ) = ( X Y ) Z G = X(YZ ) = ( XY )Z = XYZ = X Y Z [ 예 2] [ 예 3] F = ( A B )( A CD ) = A BCD X 1 X 2 X X N = X 1 X 2 X N = X 1 X 2 X N 1 X 2 X N
23 ABCD B A F = wxyz wxz wxyz wxz xyz f = ACD ABD ACD BC AB H wy xyz wxyz xyz wxy g = = AD BCD ABC ACD ABC G ACD ABD ACD BC AB H = = abd acd b cd abc h = xyz xyz xyz xyz xyz xyz p =
24 2.1.4 Switching Operations and Gates * Logic gates (1) 논리연산을수행하는전자회로혹은소자 (transistors, diodes, resistors, and capacitors) (2) 입력신호의 2진신호로의인식 (3) 2진출력신호를허용범위내의아날로그신호로전환출력 (4) [ 주의 ] 논리소자의입출력은아날로그신호 (5) 0 에서 1로혹은 1 에서 0으로의변화를 transition 이라함 (6) 0 에서 1로혹은 1에서 0으로변화하는비결정적영역을 transition region 이라함 (7) timing diagram : 시간의변화에따른신호의상태를나타내는것 (8) Integrated Circuits (IC) (9) Dual-in-line package (DIP)
25 2.1.4 Switching Operations and Gates * Logic families : manufacturing families (1) Transistor-transistor logic (TTL) based on the bipolar junction transistor(bjt) (2) 5Vdc power source (3) SN 74 LS 04 N manufacturer series subseries device type package where # SN : Semiconductor Network Program manufactured by Texas Instruments # 74 : standard TTL commercial device : 0 온도특성 70 (cf. 54 : high-reliability military : -55 온도특성 125 ) # LS : low power, high speed known as low-power Schottky # 04 : logic function (NOT) # N : plastic DIP device (4) Complementary metal-oxide semiconductor (CMOS) * designed around field effect transistor (FET) * 3Vdc ~ 18Vdc power source * consume much less power than TTL * slower than TTL * similar identification process to that of TTL
26 2.1.4 Switching Operations and Gates AND 와 NOT 기호로표현한 NAND 함수 x y s s = (xy) or s = xy NAND 게이트의논리기호 x y s x y z t w x y z u s = (xy) or s = xy t = (xyz) or t= xyz u = (wxyz) or u= wxyz (a) 2- 입력 NAND 게이트 (b) 3- 입력 NAND 게이트 (c) 4- 입력 NAND 게이트
27 2.1.4 Switching Operations and Gates OR 와 NOT 기호로표현한 NOR 함수 x y s = (x y) or s = x y NOR 게이트의논리기호 s x y s x y z s w x y z s S = (x y) or s = x y s = (x y z) or u = (w x y z) or s = x y z u = w x y z (a) 2- 입력 NOR 게이트 (b) 3- 입력 NOR 게이트 (c) 4- 입력 NOR 게이트
28 2.1.4 Switching Operations and Gates NAND 논리회로 NOR 논리회로
29 2.1.4 Switching Operations and Gates 2- 입력과 3- 입력 EX-OR 함수 x y z x y p y z y p y x z = z y x P = (a) 2- 입력 EX-OR 게이트 (b) 2- 입력 EX-OR 게이트를조합한 3 입력 EX-OR 게이트 y y
30 2.1.4 Switching Operations and Gates
31 2.1.4 Switching Operations and Gates 2- 입력과 3- 입력 EX-NOR 함수입력출력 x y s x y z x y p z z = x y P = x y z (a) 2- 입력 EX-NOR 게이트 (b) 2- 입력 EX-NOR 게이트를조합한 3 입력 EX-NOR 게이트
32 Universal Gates NAND 게이트를사용한 AND 와 OR 함수 x y ( xy)' (xy) (a) NAND 게이트를사용한 AND 함수 x x' y y' x y (b) NAND 게이트를사용한 OR 함수
33 Universal Gates NOR 게이트를사용한 AND 와 OR 함수 x x' y y' (x' y' ) = xy (a) NOR 게이트를사용한 AND 함수 x y (x y)' (x y) (b) NOR 게이트를사용한 OR 함수
34 Universal Gates V CC "1" x x' x (x 1) = x 그림 2-29 NAND 와 NOR 게이트를인버터로사용 x' (x x) = x (a) NAND 게이트인버터 x "0" x' x x' (x 0) = x (x x) = x (b) NOR 게이트인버터
35 2.2 Switching Formulas and Functions * 부울식 (Boolean Expressions or Formulas): 논리적기능을 Boolean constant, variables, 그리고 Boolean operations 을이용하여나타낸식 ( x y)z * 논리함수 (Logic Functions): 입출력사이의관계를나타내는함수 f f = ( x y)z * 진리표 (Truth Table): n 개의입력변수 2 n 개의조합
36 2.2 Switching Formulas and Functions * [Ex] 3 개의입력변수를가진함수 f 의진리표
37 2.2.1 Switching Formulas * 문자 (Literals): 부울변수자체또는보수화 ( ) 된부울변수 f = x wy w yz x,w,, y,w,, y,z * 곱항 (Product terms): 문자 / 다중문자의논리곱 (AND) f = x wy w yz x,wy,w w yz * 합항 (Sum terms): 문자 / 다중문자의논리합 (OR) f = z(x y)(w x y) z, x y, w x y * 최소항 (Minterms) - 곱항의특수한경우 ( 모든입력변수들을포함하는곱 ) - [ 예 ] XY, X Y, XY, X Y - n 개의변수에대하여 2 n 개의최소항 2개의변수에대한 4개의최소항 * 최대항 (Maxterm) - 합항의특수한경우 ( 모든입력변수들을포함하는합 ) - [ 예 ] XY, X Y, XY, X Y
38 2.2.1 Switching Formulas * m-notation - 최소항의간략화된표현 : m i - m i : 첨자 i 는진리표상에서변수가갖는값을십진수로변환한값 f = x yz xyz xy z = m m m = m(1,3,4 )
39 2.2.1 Switching Formulas * M-Notation - 최대항의간략화된표현 : M i - M i : 첨자 i i 는진리표상에서변수가갖는값을십진수로변환한값 f = (x y z)(x y z)(x y z)(x = M0M2M5M6M7 = M(0,2,5,6,7) y z)(x y z)
40 2.2.1 Switching Formulas [ 예 ] 최소항의 m- 표현
41 2.2.1 Switching Formulas 표 3 개의변수를가진최소항과최대항 입력변수최소항최대항 a b c 항 명칭 항 명칭 a'b'c' m 0 abc M a'b'c m 1 abc' a'bc' m 2 ab'c M 1 M a'bc ab'c' m 3 ab'c' a'bc M ab'c abc' abc m 4 m 5 m 6 m 7 a'bc' abc a'b'c a'b'c M 4 M 5 M 6 M 7
42 Map 2.1 Two-variable Karnaugh maps.
43 Map 2.3 Three-variable maps. Map 2.5 Product terms corresponding to groups of two.
44 Map 2.8 The four-variable map.
45 Map 2.12 x yz x yz xy z xy z xyz. Map 2.13 A better solution. Map 2.14 The minimum solutions.
46 2.2.1 Switching Formulas * 곱항의합 (SOP; Sum Of Product or disjunctive normal form) : 곱항들의논리합 f = x wy w yz * 합항의곱 (POS; Product Of Sum or conjunctive normal form) : 합항들의논리곱 f = z(x y)(w x y) * 최소곱항의합표현 (A minimum sum of products expression) - 곱항의수가최소인 SOP 표현 - 곱항의수가같은경우에는최소의문자를갖는 SOP 표현 - [ 예 ] 아래표현의경우 (3) 혹은 (4) (1) x yz x yz xy z xy z xyz 5 terms, 15 literals (2) x y xy xyz 3 terms, 7 literals (3) x y xy xz 3 terms, 6 literals (4) x y xy yz 3 terms, 6 literals
47 2.2.1 Switching Formulas * 표준곱항의합또는표준 SOP 형식 (Standard sum-of-products, Minterm canonical formulas, or Disjunctive canonical formulas) : 출력변수가논리적으로 1일때를정의하는최소항의완전한형태 ( 모든입력변수를포함하는최소항의합 ) f g 표준SOP SOP = x yz xyz = x yz xy z xy z * 표준합항의곱또는표준 POS 형식 (Standard product-of-sums): 출력변수가논리적으로 0 일때를정의하는최대항의완전한형태 ( 모든입력변수를포함하는최대항의곱 ) f 표준POS = ( x y z)( x y g POS = x ( y z )( x y z ) z)( x y z)
48 2.2.1 Switching Formulas 임플리컨트 (Implicant) * 어떤함수의임플리컨트는 임플리컨트가 1일때는언제든지함수가 1이되는곱항 를말함. * [ 예 ] 다음쪽의최소항 * 지도 (Map) 적관점에서설명하면, 4각형형태를지니면서내부에 1 만을포함하는 2 k 개 (1, 2, 4, 8,...) 의최소항으로구성된곱항 프라임임플리컨트 (Prime implicant of a function) * 임플리컨트중에서어느하나의다른임플리컨트에완전히포함되지않는것을말함 * [ 예 ] 지도 32 3,2 에타원으로표시된모든곱항 에센셜프라임임플리컨트 (Essential prime implicant) * 다른프라임임플리컨트에포함되지않는적어도하나의 1 을갖는프라임임플리컨트를말함. * [ 예 ] 지도 3,2에검은색타원으로표시된모든곱항
49 2.2.1 Switching Formulas The implicants of F are Minterms Groups of 2 Groups of 4 A B C D A CD CD A B CD BCD A BCD ACD ABC D B CD ABC D ABC ABCD ABD AB CD
50 2.2.2 Manipulation of Switching Formulas 1) 부울함수의대수적간소화 (1) 항결합 - XY XY = X (Y- Y ) = X 1 = X - X Y XYZ XYZ = XY ( X X )YZ = XY 1 YZ = XY YZ (2) 문자소거 - X XY = ( X X )( X Y ) = 1 ( X Y ) = X Y - X ( X Y ) = XX XY = 0 XY = XY (3) 중복항첨가 F = XYZ XYZ XYZ = XYZ XYZ XYZ XYZ = XZ(Y Y ) ( X X )YZ = XZ YZ = ( X Y )Z (4) 합의정리 (consensus theorem) XY XZ YZ = XY XZ
51 2.2.2 Manipulation of Switching Formulas 1) Algebraic manipulation X YZ XYZ XZ = XY XY XY = X(Y Y) = X 1 = X XY = X(1 Y) = X 1 = X XY = X(1 Y) = X 1 = X X XZ X (X Y) = XX XY = X XY = X(1 Y) = X 1 = X ( X Y)(X Y) = XX XY XY YY = X XY XY = X(1 Y Y) = X 1 = X (X Y) = XX XY = XY X X 2) Duality principle of Boolean algebra: F F It means that a Boolean equation remains valid if we take the dual of the expression on both sides of the equal sign (AND OR, X Xc) X Y - X Y ( X Y - )( X Z ) X Y XZ
52 Manipulation of Switching Formulas 3) Consensus theorem ( 흡수정리 ) - XY XZ YZ = XY (X Y)Z - = = = = = XY (X Y)(X X)Z XY (XY X XY)Z XY(1 Z) XZ(1 Y) by XY (XX XY X X XY)Z XY XZ (X Y)(X Z)(Y Z) = (X Y)(X Z)(Y Z) X X = 1 = (X Y)(XY XZ YZ Z) = (X Y) = (X Y) = (X Y) = (X Y) = (X Y) = (X Y) = (X Y)(X Z) - EX.: ( X Y )( X Z ) = XY XZ 4) Complement of a function c - (X YZ XYZ) = (X Y Z)(X Y Z) - c (X( Y Z YZ)) = X ( Y Z)(Y Z) X\YZ {(X(Y Z) Z(Y 1) } {(X(Y Z) Z} {(X(Y ( Z) Z XX } by XX = 0 { XY XZ Z XX} { X(X Y) Z(X 1) } { X(X Y) Z } 1 1 1
53 부울대수만을사용한부울식의간략화법 F = XY XZ YZ X\YZ XY, XZ, YZ 1) 곱항의합으로주어진부울식의각항 ( ) 을논리지도에오른쪽그림과같이표시 2) 첨가혹은분해하고자하는항 (YZ; 주로 Prime imlicant 임 ) 을발견하여간략화하고자하는항과결합 3) 더이상결합이불가능할때까지위의과정 2) 를반복 [ 예 ] XY XZ YZ = XY XZ ( X X ) YZ = XY XYZ XZ XYZ = XY (1 Z) XZ(1 Y ) = XY XZ 항의분해결합하고자하는항끼리정리 -
54 2.2.2 Manipulation of Switching Formulas * Theorems: Shannon s expansion theorem * [ 예 ]
55 2.2.2 Manipulation of Switching Formulas * [ 예 ] 부울식의간략화 (Simplification)
56 2.2.2 Manipulation of Switching Formulas * Theorems: Shannon s reduction theorems
57 2.2.2 Manipulation of Switching Formulas * [Ex]
58 2.2.2 Manipulation of Switching Formulas * Complementations of Canonical Formulas
59 2.2.2 Manipulation of Switching Formulas * [Ex] Complementation of the Boolean Expression
60 2.2.3 Propositions, Truth Tables and Switching Functions Minterm 을이용한 Switching Equation 구하기 1. 진리표로부터출력이논리적으로 1 이되는부분만을주목한다. 2. 위의변수들을 AND 연산을이용하여하나의항을만든다. 변수의값 :1 -> 그대로, 0 -> (not) ex) a b c K( 출력 ) > ab c 로출력이떨어지는항 (Term) 만을 OR 연산으로묶는다. ex) K= ab c abc ab c
61 2.2.3 Propositions, Truth Tables and Switching Functions * [ 예제 ] - For the given propositions : if a is 0 and b is 0 then z is 0 if a is 0 and b is 1 then z is 0 if a is 1 and b is 0 then z is 0 if a is 1 and b is 1 then z is 1 - Step 1 : inputs (a, b) output(z) - Step 2 : tabulate *2 변수의경우 Or a b z Z b a
62 2.2.3 Propositions, Truth Tables and Switching Functions * 3 변수의경우 Z a 0 1 bc * 4 변수의경우 Z ab cd S 3 i l i h i l l i f i AND - Step 3 : implement using the simple logic function AND - Step 4 : Combine the terms obtained from Step 3 : z = a x b
63 2.2.3 Propositions, Truth Tables and Switching Functions - [ 예 ] 부울함수의진리값을구하라 X Y Z F 1 = XY F 2 = YZ F 2 = F1 F = XY YZ
64 2.3.1 Logic Families 1) 디지털논리계열 (Logic families) * A set of logic gates using a single design technology * 종류 - RTL (Resistor-Transistor Logic) family - DTL (Diode-transistor logic) family - ECL (Emitter-Coupled Logic) family by Motorola - TTL (Transistor -Transistor Logic) family by Texas Instruments - MOS (Metal-oxide semiconductor) - CMOS (Complementary metal-oxide semiconductor) logic family - BiCMOS (Bipolar complementary metal-oxide semiconductor) * Transistor types: - ECL & TTL: utilize Bipolar transistors as the switching elements - CMOS utilizes MOSFET transistor t * Metrics for deciding what subfamily to use: - Product of speed and power consumption - Product of delay and power
65 2.3.1 Logic Families
66 2.5.1 Logic Families 4) Low-power TTL (74Lxx) - The same as standard TTL devices except that the resistor values are increased - Increased propagation delay 5) High-speed TTL (74Hxx) - The similar as standard TTL devices except that the resistor values are lower - Higher current flows required for faster switching operation 6) Schottky TTL (74Sxx) - The similar as standard TTL devices except that the transistors are replaced with Schottky-clamped transistors t - Approximately two times faster than H-series devices - The increased speed is accomplished by not allowing the transistors to go as deeply into saturation
67 집적회로 (ICs: Integrated Circuits) * 중요평가사항 (Some Characteristics of ICs) - Size and space - Reliability - Power Requirements -Cost -표준특성 * ASIC (Application-Specific ICs) * 집적도 (Levels of integration) 소규모집적 (Small-scale integrated : SSI) : 수십개이하의 gates 중규모집적 (Medium-scale integrated : MSI): 수백개의 gates 디코더, 계산기, 레지스터등 - 대규모집적 (Large-scale integrated : LSI) 수천개정도의 gates 프로세서, 기억장치칩, programmable module 등 - 초대규모집적 (Very large-scale integrated : VLSI) 만개이상의 gates 대규모기억장치, 마이크로칩
68 2.3.1 Logic Families TTL CMOS Description Hex inverter Hex inverter X x Four 2-input AND Three 3-input AND Two 4-input AND Four 2-input OR Three 3-input OR Two 4-input OR Four 2-input NAND Three 3-input NAND Two 4-input NAND One 8-input NAND x One 12-input NAND X x Four 2-input NOR Three 3-input NOR Two 4-input NOR Two 5-input NOR
69 2.3.1 Logic Families
70 2.3.1 Logic Families * Logic family comparison
71 2.3.2 Wired Logic: TTL circuits analysis * NOT gate utilizing a bipolar transistor
72 2.5.2 Wired Logic: Diode logic gates (1) AND 및 OR gates
73 2.5.2 Wired Logic: Diode logic gates
74 2.3.2 Wired Logic: Diode logic gates (2) NAND 및 NOR gates
75 2.3.2 Wired Logic 1) Tristate (High-Impedance or High-Z) Logic Gates * A state that the output has a very high impedance * When the additional enable input is active the gate behaves as a conventional gate, but when it is inactive the gate is in the high- impedance state 2) Open-Collector and Open-Drain Logic Gates * The collector or drain of the output transistor is an open circuit
76 2.3.2 Wired Logic: Diode logic gates 3) Open-collector TTL: useful when high current is necessary
77 2.3.3 Gate Properties * 표준특성 : 논리회로의평가기준 - 팬-인 (fan-in): the number of inputs available on a gate - 팬- 아웃 (fan-out): the number of standard d loads that t the output t of a typical gate can drive without impairing its performance; A standard load is usually defined as the amount of current needed by an input of another similar gate of the same family - 잡음여유 (noise margin): the maximum external noise voltage superimposed on a normal input value that will not cause an undesirable change in the output of the circuit - 전력소모량 (power dissipation): the power consumed by the gate and made available from the power supply - 전파지연시간 (propagation delay): the delay time for the change in value of a signal to propagate from input to output; t defined d as the maximum of tphl or tplh. high-to-low propagation time tphl : the delay measured from the reference voltage on the input voltage IN to the reference voltage on the output voltage OUT with the output voltage from H to L. low-to-high propagation time tplh : the delay measured from the reference voltage on the output voltage OUT to the reference voltage on the input voltage IN with the output voltage from L to H
78 2.3.3 Gate Properties
79 2.3.3 Gate Properties * Positive and negative logic - Positive logic Logic value Voltage level 0 L 1 H - Negative logic Logic value Voltage level 0 H 1 L
80 2.3.3 Gate Properties : IC Specifications IC Specifications 1) Summary: information describing the functional type and part number of the device - Operating temperature range - Truth or function table - Logic symbol or diagram - Boolean output equation - Packaging and pin configuration
81 2.3.3 Gate Properties : IC Specifications 2) Schematic diagram -Internal circuit diagram of the device - Absolute maximum ratings for VCC, input voltage, operating temperature, and storage temperatur
82 2.3.3 Gate Properties : IC Specifications 3) Electrical characteristics - Recommended operating conditions - Electrical characteristics - Switching characteristics
83 2.3.3 Gate Properties : IC Specifications
84 2.3.3 Gate Properties : Data sheet analysis 1) Power dissipation - Power consumed by the device P = V I D CC CC - Average power dissipation P D ( avg ) = VCC I CC( avg ) I CC ( avg ) = CCH 2) Noise immunity ( I I ) / 2 CCL - Measure of a circuit's ability to handle noise voltage on its inputs - Output voltages greater than V OH (min) are interpreted by the device as a logic 1 - Input voltages greater than V IH (min) are interpreted by the device as a logic 1
85 2.3.3 Gate Properties : Data sheet analysis - High-state noise margin V NMH = V OH (min) V IH (min) - For the 7400LS : VNMH = = 0.4 V - Output voltages less than V OL (min) are interpreted by the device as a logic 0 -Input voltages less than V IL( (min) will be interpreted by the device as a logic 0 - Low-state noise margin V NML = V OL(max) V IL(max) - For the 7400LS : VNMH = = 0.4 V
86 2.3.3 Gate Properties : Data sheet analysis
87 2.3.3 Gate Properties : Data sheet analysis 3) Fan-out - Maximum number of device inputs of the same logic family that a device output t can drive in parallel l - Calculation of fan-out Fan out = high Fan out = low - For the 74LS00 I I I I OH IH OL IL Fan I OH 0.4 ma out highh = = = 20 I 20 μa IH Fan out I 8 ma 0.4 ma OL low = = = I IL 20
88 2.3.3 Gate Properties : Data sheet analysis
89 2.3.3 Gate Properties : Data sheet analysis 4) Current sourcing and current sinking - Current sourcing: when the output of a gate is high and it is supplying current to the input of another gate or gates - Current sinking: when the output of a gate is low and current is flowing from the input of another gate or gates into the output
90 2.3.3 Gate Properties: CMOS circuit analysis CMOS circuit analysis - complementary metal-oxide semiconductor - slower propagation delays - far less power to operate than bipolar TTL devices - greater supply voltage range, higher fan-out capability, greater noise immunity than their TTL counterparts 1) Propagation delay - about 150 ns - 74HC high-speed CMOS series 2) Power dissipation - in the steady-state condition, a CMOS family device consumes virtually no power 3) Supply voltage - 3~18Vdc 4) Fan-out - ideally infinite due to its high input impedance(1012 ohms typical) - practically greater than 50 5) Noise immunity - for a supply voltage of 5 V, both the high noise margin and the low noise margin are approximately 1.5 V
91 2.3.3 Gate Properties : Interfacing logic families Interfacing logic families 1) Interfacing TTL devices to CMOS devices * typical solution is to connect the two logic families together using a pull-up resistor * typical value for the pull-up resistor when operating at 5 V is 2 kohm R R min max V = V = DD CC I I V OL max V IH min OL max IH min 2) Interfacing CMOS devices to TTL devices * the CMOS device output cannot sink enough current for the input of the TTL device in the logic 0 * the standard solution is to use a buffer
92 2.3.3 Gate Properties : Troubleshooting 1) Unused inputs to a TTL or CMOS device should always be connected to something. 2) An unused input on a TTL device will be perceived by the device as a logic 1 applied to its input. - Whereas unused TTL inputs that are left open become more susceptible to EMI and stray electronic interference, they generally can provide reliable operation. 3) Unused inputs of CMOS devices should be connected to either VDD or ground. - Open inputs on CMOS devices can lead to unpredictable operation and even oscillation. -increase the power consumption of the device and even destroy it 4) CMOS and TTL input-protection using input diodes 5) CMOS devices have a very high input impedance because MOS transistors are in effect an open circuit (1012 ohm). This makes CMOS devices highly susceptible to damage from static electricity. 6) Decoupling capacitors between the VCC and ground are used to eliminate unwanted transients, or spikes, on power supply lines of TTL devices to 1microF at the VCC input pin of an edge connector on a PCB - 001to F at the VCC input and ground for every one to three ICs. - install as close as possible to each IC, with the lead length of the capacitors being made as short as possible
93 Chapter 2 Boolean Algebra and Logic Gates Problems 2.1 What is logic? 2.2 What is a logic gate? 2.3 Identify and explain the three basic logic functions. 2.4 Identify and explain the two most common logic families. 2.5 Explain a DIP. 2.6 Describe a truth table. 2.7 Explain the active-state logic
94 Chapter 2 Boolean Algebra and Logic Gates 2.8 Give the logic symbol, truth table, and Boolean expression for the following: 1) AND gate 2) OR gate 3) Inverter 4) NAND gate 5) NOR gate 6) XOR gate 7) NXOR gate 29Designathree-input 2.9 input NAND gate and a three-input NOR gate using only AND gates, OR gates, and inverters In each of the following diagrams in Fig.(a) and (b), determine the output waveform Z using the input waveforms shown in Fig.(c).
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6 장부울함수의간소화 개요 모든입력과출력조건이동일한경우에는가능한한논리회로를간단하게구성 논리회로간소화혹은최적화 부울식의간소화 : term 을감소하거나 literal 를감소한다. term 은게이트의수, literal 은게이트의입력수를나타낸다. 논리회로의동작속도향상, 소비전력감소등효율적인논리회로구성가능 논리회로를간소화하는방법 논리회로자체를간소화하는방법 논리회로를부울함수로표현한후부울함수를간소화
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개요 l 모든입력과출력조건이동일한경우에는가능한한논리회로를간단하게구성 à 논리회로간소화혹은최적화 부울식의간소화 : term 을감소하거나 literal 를감소한다. term 은게이트의수, literal 은게이트의입력수를나타낸다. l 논리회로의동작속도향상, 소비전력감소등효율
6 장부울함수의간소화 개요 l 모든입력과출력조건이동일한경우에는가능한한논리회로를간단하게구성 à 논리회로간소화혹은최적화 부울식의간소화 : term 을감소하거나 literal 를감소한다. term 은게이트의수, literal 은게이트의입력수를나타낸다. l 논리회로의동작속도향상, 소비전력감소등효율적인논리회로구성가능 l 논리회로를간소화하는방법 논리회로자체를간소화하는방법
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6 장부울함수의간소화 l l l 개요 모든입력과출력조건이동일한경우에는가능한한논리회로를간단하게구성 à 논리회로간소화혹은최적화 부울식의간소화 : term 을감소하거나 literal 를감소한다. term 은게이트의수, literal 은게이트의입력수를나타낸다. 논리회로의동작속도향상, 소비전력감소등효율적인논리회로구성가능 논리회로를간소화하는방법 논리회로자체를간소화하는방법
개요 l 모든입력과출력조건이동일한경우에는가능한한논리회로를간단하게구성 à 논리회로간소화혹은최적화 부울식의간소화 : term 을감소하거나 literal 를감소한다. term 은게이트의수, literal 은게이트의입력수를나타낸다. l 논리회로의동작속도향상, 소비전력감소등효율
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