<4D F736F F F696E74202D F FB5BFBACEC7CFC0CCC5D820B1E8BFA9C8B22E BC8A3C8AF20B8F0B5E55D>

Size: px

Start display at page:

Download "<4D F736F F F696E74202D F FB5BFBACEC7CFC0CCC5D820B1E8BFA9C8B22E BC8A3C8AF20B8F0B5E55D>"

우은석 진
6 years ago
Views:

1 Back Metal 면이 Drain 인 Vertical channel MOSFET 의 Wafer Test 에서 Chuck 을사용하지않는 RDSON 측정방법 동부하이텍검사팀김여황

2 I RDSON II Conventional Method III New Method IV Verification (Rdson) V Normal Test Item VI Conclusion 1/ 18 동부하이텍검사팀

3 I. R DSON R DSON : MOSFET 의 Turn On 시 Drain 과 Source 사이의 Resistance?V Drain Current R DSON 그래프 온도 -R DSON 상관그래프 2/ 18 동부하이텍검사팀

4 II. Conventional Method Source (Needle) Rcon1 R Gate (Needle) Rcon2 Drain (Chuck) R DSON R = R n+ + R ch + R nepi + R sub = R con1 + R + R con2 =R con1 + (R n+ + R ch + R nepi + R sub ) + R con2 3/ 18 동부하이텍검사팀

5 II. Conventional Method 측정 Point (Vacuum line) 에따른 0.7 mohm 차이발생. 4/ 18 동부하이텍검사팀

6 III. New Method 40um 이상 5/ 18 동부하이텍검사팀

7 III. New Method Source1 (Needle) Source2 (Needle) Rcon Rcon Gate1 Gate2 Source1 Source2 R R Drain Gate1 Gate2 Full Turn On (10V) Source1 (Needle) Source2 (Needle) Rcon Rcon Source1 Source2 Gate R R Gate Drain 6/ 18 동부하이텍검사팀

8 IV. Verification( 구성 AO01) * Rchuck : Back Metal 이하의저항을총칭 1. Dual FET 2. Single FET 3. No-Chuck Source (Needle) Source (Needle) Source1 Source2 (Needle) (Needle) Rcon Gate Rcon Rcon Gate Rcon Gate R R R R R R Rchuck Rchuck Drain Drain (Chuck) Drain (Chuck) 7/ 18 동부하이텍검사팀

9 IV. Verification(Data 비교 ) Normal Test 와같은경향성을보이며, Repeat(10 회 )Test 시변화가없음 10V2A 4.5V2A 2.5V2A mω 10V 2A R DSON 17 (mω) Single Dual NoChuck Single Dual NoChuck Single Dual NoChuck Single Dual NoChuck / 18 동부하이텍검사팀

10 IV. Verification( 특성 Graph) Drain Current R DSON 관계 Graph : 동일양상 R DSON 4.5V 2.5V (mω) 2A 4A 5A 2A 4A 5A R DSON(mΩ) 30 V GS = 2.5V V GS = 4.5V I D (A) I D (A) AO01 측정 Data AO01 Package Data Sheet 9/ 18 동부하이텍검사팀

11 IV. Verification(Auto Test) ETS 1 Wafer Test 10 / 18 동부하이텍검사팀

12 V. Normal Test Item Device Test Condition & Die Sort Limit Test Item Limit Bias1 Bias2 Time Pass Fail 1 IGSS1 < 10uA VGS=10V IMAX=1mA 10ms SORT 2 IGSSR1 >- 10uA VGS=-10V IMAX=1mA 10ms SORT 3 IDSS1 < 100nA VDS=30V IMAX=1mA 20ms SORT 4 BVDSS >30.5V ID=250uA VMAX=45.0V 1ms SORT 5 VTH 0.7V<Vt<1.2V ID=250uA VGS=VDS 1ms SORT 6 RDSON <9mohm ID=5A VGS=10V 1ms SORT 7 RDSON <10mohm ID=4A VGS=4.5V 1ms SORT 8 RDSON <14mohm ID=2A VGS=2 2.5V 1ms SORT 9 VFSD 0.5<VF<0.7 IS=1A VGD=0 1ms SORT 10 IGSS2 < 10uA VGS=10V IMAX=1mA 10ms SORT 11 IGSSR2 >- 10uA VGS=-10V IMAX=1mA 10ms SORT 12 IDSS2 < 100nA VDS=30V IMAX=1mA 20ms SORT 11 / 18 동부하이텍검사팀

13 V. Normal Test Item IGSS : Check for leakage current between Gate and the Source & Drain terminals. R path Item Limit Bias1 Bias2 Time IGSS1 < 10uA VGS=10V IMAX=1mA 10ms IGSSR1 >- 10uA VGS=-10V IMAX=1mA 10ms Method : Connect Drain & Source to Ground. Force Gate Voltage(10V or -10V). Wait 10ms and Measure Gate Current. Lower Than 10uA = R gs // R gd > 1MOhm(=10V/10uA) Path Device Effect is ignored. (R path < 100 mohm) 12 / 18 동부하이텍검사팀

14 V. Normal Test Item IDSS : Checks for the leakage current between the Drain and Source terminals R path Item Limit Bias1 Bias2 Time IDSS1 < 100nA VDS=30V IMAX=1mA 20ms Method : Connect Gate & Source to Ground. Force Dain Voltage(30V). Wait 20ms and Measure Drain Current. Lower Than 100nA = R ds // R dg > 100MOhm(=10V/100nA) Path Device Effect is ignored. (R path < 100 mohm) 13 / 18 동부하이텍검사팀

15 V. Normal Test Item BVDSS : Checks for the breakdown voltage across the drain source junction of the device with an unbiased gate R path Item Limit Bias1 Bias2 Time BVDSS >30.5V ID=250uA VMAX=45.0V 1ms Method : Connect Gate & Source to Ground. Force Dain Current(250uA). Wait 20ms and Measure Voltage between Drain and source. R path < 100 mohm Delta V < 250uA * 100mOhm = 25uV Path Device Effect is ignored. 14 / 18 동부하이텍검사팀

16 V. Normal Test Item Vth : Checks for the voltage applied to the gate-source junction that will cause the DS junction to start conducting R path Item Limit Bias1 Bias2 Time VTH 0.7V < Vt < 1.2V ID=250uA VGS=VDS 1ms Method : Connect Source to GND, Gate & Drain shorted. Force Dain Current(250uA). Wait 1ms and Measure Voltage between Gate and Source. R path < 100 mohm Delta V < 250uA * 100mOhm = 25uV Path Device Effect is ignored. 15 / 18 동부하이텍검사팀

17 V. Normal Test Item RDSON : Parametric measurement of the DRAIN-to-SOURCE DC resistance while the FET is biased by a specified Vgs while Drain current is flowing. R path Item Limit Bias1 Bias2 Time RDSON1 <9mohm ID=5A VGS=10V 1ms RDSON2 <10mohm ID=4A VGS=4.5V 1ms Method : Connect Source to GND. Force V gs and I d. Wait 1ms and Measure Voltage between Drain and Source. V ds = Id * (R dson + R path ) R dson = (V ds / I d ) R path R dson1 R path 2R dson1 = V ds /I d R dson2 = V ds /I d R dons1 16 / 18 동부하이텍검사팀

18 V. Normal Test Item VFSD : Checks for the forward voltage drop of the body diode across the DS junction R path Item Limit Bias1 Bias2 Time VFSD 0.5<VF<0.7 IS=1A VGD=0 1ms Method : Connect Gate & Source to Ground. Force Source Current(1A). Wait 1ms and Measure Voltage between Source and Drain. Vsd = VFSD + R path * 1A VFSD = Vsd 1A * R dson1 ( R paht R dson1 ) Path Device Effect can not be ignored. (Rpath * 1A : 1mV~100mV) 17 / 18 동부하이텍검사팀

19 V. Conclusion 효과 - 정확성향상 (Rchuck, Contact 등의기생저항제거 ) - 장비호환성증가 (Probe Card 변경만으로측정가능 ) Future - 측정값내부의 Current Path Die 와 Measure Die 구분법 - Path Die 와 Measure Die 가동일하지않을때측정방법 18 / 18 동부하이텍검사팀

,,,,,, (41) ( e f f e c t ), ( c u r r e n t ) ( p o t e n t i a l difference),, ( r e s i s t a n c e ) 2,,,,,,,, (41), (42) (42) ( 41) (Ohm s law),

1, 2, 3, 4, 5, 6 7 8 PSpice EWB,, ,,,,,, (41) ( e f f e c t ), ( c u r r e n t ) ( p o t e n t i a l difference),, ( r e s i s t a n c e ) 2,,,,,,,, (41), (42) (42) ( 41) (Ohm s law), ( ),,,, (43) 94 (44)