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2 : Source code Assembly language code x = a + b; ld a, %r1 ld b, %r2 add %r1, %r2, %r3 st %r3, x (Assembler) (bit pattern) (machine code) CPU security (code generator).. (Instruction Format) opcode operand opcode () operand () 0, 1, 2, 3operand : opcode opcode dst opcode src dst opcode src1 src2 dst

3 (Instruction Execution) CPU : PC < while ( PC!= ) { execute ( MEM[PC]); ; fetch (fetch), PC decode (decode) operand fetch execute store 24 ( ),,,

4 (Instruction Set) load/store integer (jump ) (OS ) floating point vs (bit pattern) (symbolic representation) (assembler) : A 3,=F 1 RX 5A30B024(hex) 5A 3 B A 3 0 B : (11) (compiler): (statement) (1 ) (disassembler): AR AR R1,R2 AR 3,5 1A35 ; R3 = R3 + R5 SR 3,5 1B35 ; R3 = R3 R5 OR 7, ; R7 = R7 Or R4 R 7, ; R7 = R7 ad R4 XR 5, ; R5 = R5 Xor R6 LR 3, ; R3 = R6

5 L L R1,D2(X2,B2) L R1,D2(X2,B2) L 3,260(7,15) ; 5837F104 USIG *,15 ; (*) 15 ;. L 3,DATA1(7) ;DATA1 7 ; 4 ; 3. DATA1 DC F 10 ;DATA DC F 11 ;DATA DC F 12 ;DATA DC F 13 ;DATA DC F 14 ;DATA L 3,260(7,15) ST(STore) O(Or) A(Add) (ad) S(Subtract) X(Xor)

6 LM LM R1,R3,D2(B2) LM 4,7,FULL1 FULL1 DC F 1 ;R4 DC F 2 ;R5 DC F 3 ;R6 DC F 4 ;R7 I I D1(B1),I2 I KIMT+23,B I(ad Immediate) OI(Or Immediate) XI(eXclusiveor Immediate) MVC D1(L,B1),D2(B2) PATA DC CL5 TIGER ; 5 TIGER PATB DC CL8 ELEPHAT ; 8 ELEPHAT MVC PATA,PATB PATA T I G E R PATA E L E P H PATB E L E P H A T PATB E L E P H A T

7 PATA DC CL5 TIGER ; 5 TIGER PATB DC CL8 ELEPHAT ; 8 ELEPHAT MVC PATB,PATA PATA T I G E R PATA T I G E R PATB E L E P H A T PATB T I G E R T I G ZAP D1(L1,B1),D2(L2,B2) C D ZAP VALUEA,VALUEB..... VALUEA DC C 2413 F 2 F 4 F 1 F 3 VALUEB DC PL D D

8 RX BC mask,d2(x2,b2) RR BCR mask,r2 zero <zero >zero overflow A 3,=F 1 BC B 1000,ZERO BC 4,LTZERO BC B 0010,GTZERO OVERFLOW... BC B 1111,COT ZERO... BC 15,COT LTZERO... BC B 1111,COT GTZERO... COT B BR BP BPR BM BMR BZ BZR BAL 14,SUBRT ;R14... ; SUBRT... SUBRT BCR 15,14 ;R14 BALR 14,10 ;R14 ;R10 BALR 14,0 ;R14 ;

9 ITER L 5,UM(4) AR 5,3 ST 5,UM(4) L 7,ITER A 7,FOUR ST 7,ITER L 7,ITER+6 A 7,FOUR ST 7,ITER+6 S 2,OE BP ITER EXAMPLE CSECT BALR 15,0 USIG EXAMPLE+2,15 L 2,FIVE L 3,TWETY5 SR 4,4 ITER L 5,UM(4) AR 5,3 ST 5,UM(4) A 4,FOUR S 2,OE BP ITER BR 14 FIVE DC F 5 TWETY5 DC F 25 FOUR DC F 4 OE DC F 1 UM DC F 50 DC F 45 DC F 64 DC F 72 DC F 69 ED EXAMPLE CSECT BALR BASE,0 USIG EXAMPLE+2,BASE L 2,=F 5 L 3,=F 25 SR 4,4 ITER L 5,UM(4) AR 5,3 ST 5,UM(4) A 4,=F 4 S 2,=F 1 BP ITER BR 14 UM DC F 50 DC F 45 DC F 64 DC F 72 DC F 69 BASE EQU 15 ED 0 BALR 15,0 2 L 2,54(0,15) 6 L 3,58(0,15) 10 SR 4,4 12 L 5,34(4,15) 16 AR 5,3 18 ST 5,34(4,15) 22 A 4,62(0,15) 26 S 2,66(0,15) 30 BC 2,10(0,15) 34 BCR 15, F

10 EXAMPLE ITER UM BASE F 5 F 25 F 4 F USIG EXAMPLE+2, Y 2 DROP 15 USIG EXAMPLE+520, Y Y 2 (two pass) (pass) 1: (symbol definition) (pass) 2: (instruction assembly) (pass). 1, (type),, () (mapping). 2 (assemble). (lc: location counter).. <> < > pass1(st) pass2(st)

11 1 void pass1(st) { unsigned lc = 0; while (not EOF) { ; 2 ; if ( ) lc ST ; if ( POT ){ if (DS DC) {len = ; lc len ; if (EQU) ST ; if (ED) LT ; else { len = MOT ; LT ; lc += len; 2 1 void pass2(st) { unsigned lc = 0; while (not EOF) { ; if ( POT ){ if (DS DC) {len = ; lc len ; if (DC) { if (USIG) BT ; if (DROP) BT? ; if (ED) LT ; if (EQU START) ; else if ( MOT ){ len = MOT ; ; if (RX ) { ; += 3,4 if (RR ) { ; lc += len; ;

12 ADD32 CSECT ETRY DATA BEGI BALR BASE,0 USIG 2,BASE SR 4,4 L 3,FIVE LOOP L 2,DATA(4) A 2,THIRTY2 ST 2,DATA(4) A 4,FOUR S 3,OE BP LOOP BR 14 FIVE DC F 5 FOUR DC F 4 OE DC F 1 THIRTY2 DC F 32 DATA DS 5F BASE EQU 13 ED TEXT CARD 0 05D0 BALR 13,0 2 1B44 SR 4, D022 L 3,34(0,13) D032 L 2,50(4,13) 12 5A20 D02E A 2,46(0,13) D032 ST 2,50(4,13) 20 5A40 D026 A 4,38(0,13) 24 5B30 D02A S 3,42(0,13) D006 BC 2,6(0,13) 32 07FE BCR 15,

13 MAI CSECT EXTER ADD32 EXTER DATA BEGI BALR 15,0 USIG BEGI+2,15 L 3,=F 5 LOOP READ 3,ADATA L 4,AADD32 BALR 14,4 L 3,=F 5 WRITE 3,ADATA HALT ADATA DC A(DATA) AADD32 DC A(ADD32) ED TEXT CARD 0 05F0 BALR 15, F022 L 3,34(0,15) 6 F030 F01A READ 3,26(0,15) F01E L 4,30(0,15) 14 05E4 BALR 14, F022 L 3,34(0,15) 20 F130 F01A WRITE 3,26(0,15) 24 FF00 HALT ESD CARD ADD32 SD 0 72 DATA LD 52 1 TEXT CARD 0 05D0 BALR 13,0 2 1B44 SR 4, D022 L 3,34(0,13) D032 L 2,50(4,13) 12 5A20 D02E A 2,46(0,13) D032 ST 2,50(4,13) 20 5A40 D026 A 4,38(0,13) 24 5B30 D02A S 3,42(0,13) D006 BC 2,6(0,13) 32 07FE BCR 15, RLD CARD ED ESD CARD MAI SD 0 40 ADD32 ER 0 0 DATA ER 0 0 TEXT CARD 0 05F0 BALR 15, F022 L 3,34(0,15) 6 F030 F01A READ 3,26(0,15) F01E L 4,30(0,15) 14 05E4 BALR 14, F022 L 3,34(0,15) 20 F130 F01A WRITE 3,26(0,15) 24 FF00 HALT RLD CARD 3 1 A A 32 ED

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9 hamks@dongguk.ac.kr : Source code Assembly language code x = a + b; ld a, %r1 ld b, %r2 add %r1, %r2, %r3 st %r3, x (Assembler) (bit pattern) (machine code) CPU security (code generator).. (Instruction