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20 BE 8 BE 6 BE 4 BE 2 BE 0 y 17 y 16 y 15 y 14 y 13 y 12 y 11 y 10 y 9 y 8 y 7 y 6 y 5 y 4 y 3 y 2 y 1 y 0 0 BE 7 BE 5 BE 3 BE 1 BE 16 BE 14 BE 12 BE 10 y 32 y 31 y 30 y 29 y 28 y 27 y 26 y 25 y 24 y 23 y 22 y 21 y 20 y 19 y 18 BE 15 BE 13 BE 11 BE 9

21 (~ &~ &~ ) ( & & ) ~ & ( ^ ) ~ & & & ~ & ~ & ( ^ )

23 S 0 S 0 S 0 S 0 S 0 S 0 S 0 S 0 S 0 x x x x x x x S 1 S 1 S 1 S 1 S 1 S 1 S 1 x x x x x x x S 2 S 2 S 2 S 2 S 2 x x x x x x x S 3 S 3 S 3 x x x x x x x 1 1 -S 0 S 0 x x x x x x x 1 -S 1 S 1 x x x x x x x 1 -S 2 S 2 x x x x x x x 1 -S 3 S 3 x x x x x x x

24 pp_sel[4] pp_sel[2] pp_sel[0] pp_sel[3] pp_sel[1] Zero or sign generated input x i x i-1 x i x i-1 OR pp[i]

25 3 FA FA FA 3 4 FA FA FA FA 4 FA FA 3 FA FA FA 3 2 FA 2 FA FA FA 2 FA 2 C SUM FA C SUM

28 32 bits s e f msb lsb msb lsb (a) 단정도형식 (a) single format 64 bits s e f msb lsb msb lsb (b) 배정도형식 (b) double format

32 의보수

33 Exponent Sub tractor A lig n er Stiky Gen ST 1 (S/D) LOP LZC Fraction Adder Rnd Ctl ST 2 (S/D) 1bit shift Exponent Adder Norm Inc ST 3 (S/D) MUX

35 EX1 sign xor exponent adder fraction m ultiplier EX2 rnd ctrl Sticky bit gen EX3 exp adder shifter Inc

37 P i+1 /D 1 (8/3, 2/3) q i+1 =-2 q i+1 =-1 q i+1 =0 q i+1 =1 q i+1 = P i /D (-8/3, -2/3) -1

38 P=rP 1 (k+j+1)d (k+j)d y q=j+1 (-k+j+1)d x q=j (-k+j)d D min D 1 D 2 D max D

43 System DSP chip cont reg IU chip cont reg MAC ld / st memory AU exe ld / st FPU chip cont reg on-board bus FP AU ld / st FP Mult FP Div System IU / DSP/ FPU core cont decoder reg ld /st exe AU M A C FP AU FP M ult FP Div

44 MAC/MAS DSP Sub-Decoder AU (pack/unpack, extend/clam p, lzc, min/max) Mux XY Memory Address Gen DSP XY Memory

45 P L C Z S V R

47 IF ID EX MA WB IU inst address gen BUS inst memory inst decoder/ control inst folding branch target gen stack pointer SPR execution forward data memory system controller (TLB,MMU) register file access DSP prefetch queue GPR DSP address gen DSP XY memory DSP unit

53 C A B mux 64 3A generation Path 2 Booth selector R8 4 Booth encoder R Path Wallace tree Booth selector R4 3 Booth encoder R Wallace tree bit Final adder bit result

54 Yi+1 Yi Yi-1 output X X X X X X X X

55 Yi+2 Yi+1 Yi Yi-1 output X X X X X X X X X X X X X X X X R a d i x - 8 B o o t h 인코딩 0 0 Y 3 2 Y 3 1 Y 1 6 Y 1 5 Y 1 4 Y 1 3 Y 1 2 Y 1 1 Y 1 0 Y 9 Y 8 Y 7 Y 6 Y 5 Y 4 Y 3 Y 2 Y 1 Y 0 0 R a d i x - 4 B o o t h 인코딩

58 1 1 ~ ~ c 1 ~ c 1 ~ c c c 1 1 ~ c 1 1 ~ c 1 1 ~ c 1 1 ~ c 1 1 ~ 1 s complement 1 1 ~ c c 1 1 ~ correction carry-in 1 1 ~ c c 1 1 ~ 1 1 c Final adder ~ c ~ c ~ c ~ c ~ c c ~ c ~ c ~ c ~ c bit C

60 Signed extend (a) 8 -b it 부호확장 sign Signed extend sign data (b ) 1 6-bit 부호확장 data S i g n C o u n t S i g n C o u n t o u t p u t O v erfloe r f l o w check I n p u t C l a m p o u t p u t C l a m p

61 (dst + 1)[31:16] (dst + 1)[15:0] dst[31:16] dst[15:0] bit clamp 8-bit clamp 8-bit clamp 8-bit clamp dst[31:24] dst[23:16] dst[15:8] dst[7:0]

62 dst[31:24] dst[23:16] dst[15:8] dst[7:0] bit Sign extend 16-bit Sign extend 16-bit Sign extend 16-bit Sign extend dst[31:16] dst[15:0] (dst + 1)[31:16] (dst + 1)[15:0]

64 L-bit M-bit Memory Index(Address) Mask bits Generator ADDER Bits Reverse Logical shift(15-l) and and or or and Output

68 S E F ( a ) S E F ( b ) b0 1 F [22:0] (a) b0 1 F [51:32] F [31:0] H ig h e r b it d a ta Lower 32-bit data (b )

69 IU Core valid Instruction 16 load/store register Load data Store data FPU Sub-decoder IU 32-bit register file Source A Source B Forwarding FP-ALU FP-MUL FP-DIV 32 Result bus DSP MAC Unit busy Multiplier control

73 double_state opcode 32-bit reg 32-bit reg effective operation exp_diff_cout 4 s_s opcode_out 2 double_state_out 11-bit exp sub 11 exp_diff 32-bit comparator 11 2 significand_comparator_out compare_out effective_out bit sticky_gen_input 32 sign_final aligner compare_out exp_max 2 aligned_out 53 sticky_bit reg reg reg reg reg reg 53-bit reg 21-bit reg 53-bit reg 3-bit reg 4 opcode_out double_state sign_final reg reg reg reg 4 opcode_out double_state sign_final 2 11 compare_out 2 11 compare_out exp_max reg exp_max round selector effective_out reg 54-bit normalizer nor_rnd_sel bit significand adder complement mux swap 32 mux 2 increaser 27 mux 27 round control g _bit,r _bit, sticky _bit roundin rounding controller ST 1(Single Precision) / ST 1,2 (Double Precision) sticky gen g_bit,r_bit, 30-bit lzc sticky_bit 6 54-bit reg 6-bit reg 3-bit reg ST 2(Single Precision) / ST 3,4 (Double Precision) ST 3(Single Precision) / ST 5,6(Double Precision) reg reg reg reg reg reg 27-bit reg

75 ES,Comparator, Aligner,Sticky gen 1 1 ES,Comparator, Aligner,Sticky gen Significand Adder 4 Significand Adder Norm alization /Rounding Normalization /Rounding (a) 6 (b) 5 Inst EX1 EX2 EX3 Inst+1 EX1 EX2 EX3 Inst+2 EX1 EX2 EX3 1 cycle 3 cycles (a) Inst EX1 EX1 EX2 EX2 EX3 EX3 Inst+1 EX1 EX1 EX2 EX2 EX3 EX3 Inst+2 EX1 EX1 EX2 EX2 EX3 EX3 2 cycles 6 cycles (b)

77 2-to-1 MUX shft_cnta[0] shft_cntb[0] 2 0 = 1 shft_cnta[1] shft_cntb[1] 2 1 = 2 shft_cnta[2] shft_cntb[2] 2 2 = 4 shft_cnta[5:3] shft_cntb[5:3] Aligned out

79 shift_cnta[2:0] 5 bits M ask C ontrol G enerator 1 5 bits 1.f (53 bits) BS 1(0,1,2,3,4,5,6,7 shifts) 1.f GR OR bits Mask Control Gen. 2 shift_cnta[5:3] OR Sticky bit

80 A B C L A carry ou t 2 7 su m carry in reg reg

81 b 0 1 S U M [ 2 2 : 0 ] G R S (a ) C y c l e 1 : S U M [ 2 6 : 0 ] G R S C y c l e 2 : S U M [ 2 6 : 0 ] 3 b 0 (b )

82 G, R, S & C, I, K, L R o u n d m o d e R o u n d i n g In c re a se r C o n tro lle r M S B 1 -b it s h ift F i n a l s i g n i f i c a n d T o e x p o n e n t a d j u s t a d d e r R o u n d i n g v a l u e E x c e p t i o n m o d e

84 Single exponent 3 b0 (a) 11 0 Double exponent (b) shift b0 LZC when single 3 b0 (c) b0 Leading zero count (d)

86 21-bit X Y XH XL YH YL 32-bit 21-bit 32-bit 10-bit 32-bit XH YH 21-bit XH YL 32-bit 32-bit XL YL 32-bit 21-bit Incrementor 21-bit XL YH 32-bit 53-bit adder

87 r r r X Y opcode 3 multiply_state 2 Sign Selector round_mode 2 sign final Exponent Adder exp max 11 r r r r 11-bit reg 3X Gen Mult Booth Selector R Booth Booth Encoder R8 Selector R Multiplier Multiplier bit reg Mux 64-bit reg Booth Encoder R4 64-bit Multiply Final Adder opcode 3 multiply_state 2 round_mode 2 sign final bit Significand Adder exp max 21-bit Incrementor 11 sadder_cout 53 Mux Sticky0 32 r r r r 11-bit reg 53-bit reg 21-bit reg r exp max State_Machine Sticky1 double_state round_mode Exponent Adj Adder sign final 11 exp final r 11-bit reg r cout 32-bit Increaser 32 Shifter 32 significand final 32-bit reg roundin Round Controller

88 {8 b0,1,x[22:0]} {8 b0,1,y[22:0]} {11 b0,1,xh[19:0]} {11 b0,1,yh[19:0]} XL[31:0] YL[31:0] {11 b0,1,xh[19:0]} YL[31:0] XL[31:0] {11 b0,1,yh[19:0]}

91 Inst Inst+1 Inst+2 EX1 EX2 EX3 EX1 EX2 EX1 EX3 EX2 EX3 Higher 32-bits Inst Inst+1 Inst+2 Lower 32-bits 1 cycle 3 cycles (a) EX1 EX1 EX1 EX1 EX2 EX2 EX2 EX2 EX3 EX3 EX1 EX1 EX1 EX1 EX2 EX2 EX2 EX2 4 cycles 7 cycles (b) Lower 32-bits Higher 32-bits EX3 EX3 EX1 EX1 EX1 EX2 EX2 EX1 EX2

94 fadd F D EX1 EX2 EX3 fdiv fsub F D F EX1 D EX1 EX1 EX1 EX1 EX3 D D D D D EX1 dependency stall (a) fadd fdiv fsub F D EX1 F D F EX2 EX1 D EX3 EX1 EX1 EX1 EX1 EX3 EX1 EX2 EX3 (b)

95 X mux Y mux Sign Exponent Adder ROM Divisor Formation Significand Subtractor qpos qneg mux Partial+1 Partial quotuent mux Exponent Adj Adder Shifter Inc Shifter Sticky

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. 고성능마이크로프로세서 LU 와레지스터 파일의구조 (2.). 직접디지털주파수합성기 (FS) 의구조 3. 고성능마이크로프로세서부동소수점연산기 (Floating-Point Unit) 구조 (2) (2.) (2.) 2. 암호화를위한 VLSI 구조와설계의개요 (2.) 다음참

. 고성능마이크로프로세서 LU 와레지스터 파일의구조 (2.). 직접디지털주파수합성기 (FS) 의구조 3. 고성능마이크로프로세서부동소수점연산기 (Floating-Point Unit) 구조 (2) (2.) (2.) 2. 암호화를위한 VLSI 구조와설계의개요 (2.) 다음참 이비디오교재는정보통신부의 999년도정보통신학술진흥지원사업에의하여지원되어연세대학교전기전자공학과이용석교수연구실에서제작되었습니다 고성능마이크로프로세서 LU ( rithmetic Logic Unit) 와 Register File의구조 2. 연세대학교전기전자공학과이용석교수 Homepage: http://mpu.yonsei.ac.kr E-mail: yonglee@yonsei.ac.kr