wire [n-1:0] a, b, c, d, e, f, g, h; wire [n-1:0] x; // internal wires wire [n-1:0] tmp0, tmp1, tmp2, tmp3, tmp4, tmp5; mux_2to1 mux001 (.x(tmp0),.a(a

Size: px

Start display at page:

Download "wire [n-1:0] a, b, c, d, e, f, g, h; wire [n-1:0] x; // internal wires wire [n-1:0] tmp0, tmp1, tmp2, tmp3, tmp4, tmp5; mux_2to1 mux001 (.x(tmp0),.a(a"

정원 사공
5 years ago
Views:

1 [2010 년디지털시스템설계및실험중간고사 1 답안지 ] 출제 : 채수익 Verilog 문법채점기준 ( 따로문제의채점기준에명시되어있지않아도적용되어있음 ) (a) output이 always 문에서사용된경우, reg로선언하지않은경우 (-1 pts) (b) reg, wire를혼동하여사용한경우 (-1 pts) (c) ) 에서모든 input을 sensitivity list에집어넣지않은경우 (-1 pts) (d) instantiation 시에 instance 이름이없는경우 (-1 pts) (e) always 문밖에서 for loop을사용할때는 integer가아닌 genvar로 loop variable을선언해야한다. (-1 pts) (f) 그외에세미콜론, 오타등의사소한문법상실수 ( 여러개가있어도문제당 -1 pts) -> for loop에서 i++ 는 verilog에서사용되지않음 1. A. (5 pts) module mux_2to1(x, a, b, select); parameter n = 8; input select; input [n-1:0] a, b; output [n-1:0] x; wire [n-1:0] a, b; wire [n-1:0] x; assign x = (select == 1'b0)? a : b; module case 문, if/else 등으로맞게작성만하면 5점. case 문, if/else 사용시 always 문으로감싸지않은경우 (-1 pts) ) 에서모든 input을 sensitivity list에집어넣지않은경우 (-1 pts) 사소한문법오류 (-1 pts) B. (5 pts) module mux_8to1(x, a, b, c, d, e, f, g, h, select); parameter n = 8; input [2:0] select; input [n-1:0] a, b, c, d, e, f, g, h; output [n-1:0] x;

2 wire [n-1:0] a, b, c, d, e, f, g, h; wire [n-1:0] x; // internal wires wire [n-1:0] tmp0, tmp1, tmp2, tmp3, tmp4, tmp5; mux_2to1 mux001 (.x(tmp0),.a(a),.b(b),.select(select[0])); mux_2to1 mux002 (.x(tmp1),.a(c),.b(d),.select(select[0])); mux_2to1 mux003 (.x(tmp2),.a(e),.b(f),.select(select[0])); mux_2to1 mux004 (.x(tmp3),.a(g),.b(h),.select(select[0])); mux_2to1 mux010 (.x(tmp4),.a(tmp0),.b(tmp1),.select(select[1])); mux_2to1 mux020 (.x(tmp5),.a(tmp2),.b(tmp3),.select(select[1])); mux_2to1 mux100 (.x(x),.a(tmp4),.b(tmp5),.select(select[2])); module mux_2to1을사용하지않은경우 (-2 pts) case, if, always 등으로 mux_2to1 instantiation하는부분을감싼경우 (-1 pts) 연결 wire들을 [n-1:0] 로선언하지않은경우 (-1 pts) 사소한문법오류 (-1 pts) 2. 일반적으로 CLA에서 generate가 a&b에해당하고, propagate가 a^b에해당한다. 그러나만일모든부분문제에서일관성있게 g와 p를바꿔썼다면감점없음. 마찬가지로 g, p를 input a, b로착각한경우에도일관성있으면감점없음. A. (3 pts) module full_adder(sum, c_out, a, b, c_in); input a, b, c_in; output sum, c_out; wire sum, c_out, tmp1, tmp2, tmp3; assign sum = a ^ b ^ c_in; assign tmp1 = a & b; assign tmp2 = b & c_in; assign tmp3 = a & c_in; assign c_out = tmp1 tmp2 tmp3; module {c_out,s} = a+b+c_in; 를사용한경우 (2점) sum이나 c_out 중하나의결과가잘못되었을경우 (-1점)

3 사소한문법오류 (-1 pts) (assign 을해놓고 always 로둘러싼경우도포함 ) B. (3 pts) module carry_lookahead(c_out, g, p, c_in); parameter n = 4; output [n-1:0] c_out; input [n-1:0] g; input [n-1:0] p; input c_in; reg [n-1:0] c_out; integer i; c_out[0] = g[0] (c_in & p[0]); for (i=1; i<n; i=i+1) c_out[i] = g[i] (c_out[i-1] & p[i]); module 결과가잘못된경우 (0점) Parameterized module을작성하지않은경우 (-1 pts) c_out을 1-bit output으로생각하고마지막 carry out을넣은경우 (-1 pts) &, 대신에곱셈, 덧셈을썼는데, bit-width가 1이아닌경우 (-1 pts) 사소한문법오류 (-1 pts) C. (5 pts) module CLA_adder (S, c_out, A, B, c_in); parameter n = 4; input [n-1:0] A, B; input c_in; output [n-1:0] S; output c_out; wire [n-1:0] carry; wire [n-1:0] g, p;

4 integer i; carry_lookahead #(n) cla_logic0 (.c_out(carry),.g(g),.p(p),.c_in(c_in)); full_adder fa [n-1:0] (S,, A, B, {carry[n-2:0],c_in}); assign g = A & B; assign p = A ^ B; assign c_out = carry[n-1]; module full_adder instantiation을사용하지않고풀어썼을경우 (5점) Parameterized module로작성하지않은경우 (-2 pts) #(4) 로 parameterize한경우 (-1 pts) 사소한문법오류 (-1 pts) (#(n(n)), (#n) 도포함 ) D. (5 pts) module CLA_20bit_adder (S, c_out, A, B, c_in); input [19:0] A, B; input c_in; output [19:0] S; output c_out; wire [3:0] group_carry, group_g, group_p; reg [19:0] g,p; integer i; CLA_adder #(5) cadder_0 (S[19:15],c_out,A[19:15],B[19:15],group_carry[2]); CLA_adder #(5) cadder_1 (S[14:10],,A[14:10],B[14:10],group_carry[1]); CLA_adder #(5) cadder_2 (S[9:5],,A[9:5],B[9:5],group_carry[0]); CLA_adder #(5) cadder_3 (S[4:0],,A[4:0],B[4:0],c_in); carry_lookahead carry_look (.c_out(group_carry),.g(group_g),.p(group_p),.c_in(c_in)); p = A^B; g = A&B; assign group_p[0] = p[0]&p[1]&p[2]&p[3]&p[4]; assign group_p[1] = p[5]&p[6]&p[7]&p[8]&p[9];

5 assign group_p[2] = p[10]&p[11]&p[12]&p[13]&p[14]; assign group_p[3] = p[15]&p[16]&p[17]&p[18]&p[19]; assign group_g[0] = g[4] (g[3]&p[4]) (g[2]&p[3]&p[4]) (g[1]&p[2]&p[3]&p[4]) (g[0]&p[1]&p[2]&p[3]&p[4]); assign group_g[1] = g[9] (g[8]&p[9]) (g[7]&p[8]&p[9]) (g[6]&p[7]&p[8]&p[9]) (g[5]&p[6]&p[7]&p[8]&p[9]); assign group_g[2] = g[14] (g[13]&p[14]) (g[12]&p[13]&p[14]) (g[11]&p[12]&p[13]&p[14]) (g[10]&p[11]&p[12]&p[13]&p[14]); assign group_g[3] = g[19] (g[18]&p[19]) (g[17]&p[18]&p[19]) (g[16]&p[17]&p[18]&p[19]) (g[15]&p[16]&p[17]&p[18]&p[19]); module 5-bit CLA 간의 carry 전달이 carry-lookahead logic이아닌경우, 즉 group_p, group_g를사용하지않은경우 (-2 pts) 5개의 4-bit CLA adder를쓴경우, 혹은 instantiation 시에 parameter를바꾸지않은경우 (-2 pts) 사소한문법오류 (-1 pts) 3. (15 pts) 2ns 4ns 10ns 12ns 16ns a b c d e f 위에서 X 표시한부분은 undefined 에해당한다. 하나의 signal 에대해틀릴때마다 2 점씩감점. undefined 표기하지않았을경우 2 점감점.

6 모든 signal 에대해틀리고, undefined 표기하지않았을경우 0 점. 4. (5 pts + 5 pts) 두 module에대한설명및차이점비교 (2 pts + 2 pts) 모두있을경우 ( 기본 4 pts) 하나에대해서만설명한경우 ( 기본 2 pts) 아무런설명도없는경우 ( 기본 0 pts) 내용에오류가있는경우 (-1 pts) 회로 (3 pts + 3 pts) 아래의 block diagram대로그리거나혹은 gate level logic으로그리면 ( 기본 6 pts) 일부 signal이빠졌거나이름을잘못쓴경우 (-1 pts씩 ) reset이 active low임을고려하지않은경우 (-1 pts씩 ) Latch의 schematic을 or, and 형태로그린경우 (-1 pts) Latch의 block diagram이잘못된경우 (-1 pts) ( 세모꼴의표시는 clock input을의미 즉, flipflop) Flipflop의 block diagram이잘못된경우 (-1 pts) ( 세모꼴의표시는 clock input을의미한다 ) 기타오류 (-1 pts씩 ) 5. (3 pts + 3 pts + 5 pts) A. (3 pts) Simulation Cycle => Complete processing of all currently active events Inactive event => Events that occur at the current simulation time, but will be processed after all active events have been processed 위에 boldface 및밑줄로강조한부분에대한내용이있으면된다. ( 각 1.5 pts) 강조부분에대해명시하지는않았으나, 기타예시를제시하고설명하거나제대로된설명을한경우 ( 각 1 pts) B. (3 pts) active event, inactive event, non-blocking assignment event, monitor event 순서가하나라도틀리면 0 점.

7 C. (5 pts) while (there are events) if (no active events) if (there are inactive events) { activate all inactive events; } else if (there are non-blocking assign update events) { activate all non-blocking assign update events; } else if (there are monitor events) { activate all monitor events; } else { advance T to the next event time; activate all inactive events for time T; } } E = any active events; if (E is an update event) { update the modified object; add evaluation events for the sensitive processes to event queue; } else { // evaluation event evaluate the process; add all update events to the event queue; } } while loop이있음 : 1점 if (no active events) 문이있음 : 1점 inactive event, non-blocking assignment, monitor에관한 if 문이순서대로있음 : 1점 monitor 이후의 else에서다음 event time으로넘어간다는내용이있음 : 1점 update/evaluation event에관한 if 문이있음 : 1점 6. (10 pts) parameter인 n은항상 4의배수로주어지는것을가정한다. module BCD_counter(clk, start, qout); parameter n = 8; input clk, start; output reg [n-1:0] qout; wire [n-1:0] next_qout; wire [n/4:0] carry;

8 clk) if (start == 1'b1) qout <= {n{1'b0}}; else qout <= next_qout; genvar i; generate for (i=0; i<n/4; i=i+1) : sub_bcd if (i == 0) BCD_1digit bcd (qout[i*4+3:i*4],1'b1,next_qout[i*4+3:i*4],carry[i]); else BCD_1digit bcd (qout[i*4+3:i*4],carry[i-1],next_qout[i*4+3:i*4],carry[i]); generate module module BCD_1digit(curr_cnt, c_in, next_cnt, c_out); input c_in; input [3:0] curr_cnt; output c_out; output [3:0] next_cnt; reg c_out; reg [3:0] next_cnt; reg [3:0] tmp; tmp = curr_cnt + c_in; if (tmp > 4'd9) next_cnt = 4'h0; c_out = 1'b1; else next_cnt = tmp; c_out = 1'b0;

9 module Parameterized module로작성하지않은경우 (-3 pts) 0~9까지의 BCD counter만을구현한경우 (-3 pts) Output이 BCD 형태로바뀌지않은경우 (-3 pts) BCD(Binary Coded Decimal) counter가아닌다른 counter인경우 ( 기본 2 pts) 7. (10 pts) module Ring_counter(clk, start, qout); parameter n = 8; input clk, start; output reg [n-1:0] qout; clk or posedge start) if (start) qout <= {1'b1, {n-1{1'b0}}}; else qout <= {qout[0], qout[n-1:1]}; module Parameterized module로작성하지않은경우, 즉, 8-bit ring counter를작성한경우 (-3 pts) Start 시에 qout을 0으로한경우 (-1 pts) Rotational shift 형식으로순환되지않는경우 (-1 pts) 8. (10 pts) 이문제는 casex를제대로활용하기위해서는 n, log2n 등에대해추가적인가정이필요하므로, parameterized module이아닌 n=8인특정경우에대한해답을제시한다. module priority_en(y,valid,in); parameter n = 8; parameter log2n = 3; input [n-1:0] in; input valid; output reg [log2n-1:0] y; if (valid)

10 casex(in) 8'b1xxxxxxx: y=3'd7; 8'b01xxxxxx: y=3'd6; 8'b001xxxxx: y=3'd5; 8'b0001xxxx: y=3'd4; 8'b00001xxx: y=3'd3; 8'b000001xx: y=3'd2; 8'b x: y=3'd1; 8'b : y=3'd0; default: y=3'd0; case else y = 3'b000; module Parameterized module로작성한경우 (10점 +2점 : 추가점수 2점 ) casex를사용하지않고 parameterized module로작성한경우 ( 기본 10점 ) Priority가반대로된경우 (-1 pts) ( 즉, 8 b1xxxxxxx에 y=3 d0를한경우 ) 사소한문법실수 (-1 pts) 9. (10 pts) module universal(clk, reset_n, s0, s1, rsi, lsi, din, qout); parameter n = 4; input clk, reset_n; input s0, s1; // control input lsi, rsi; // left shift input, right shift input input [n-1:0] din; output reg [n-1:0] qout; reg [n-1:0] parallel_out; clk or negedge reset_n) if (!reset_n) qout <= {n{1'b0}}; else qout <= parallel_out;

11 case ( {s1, s0} ) 2'b00: parallel_out = qout; 2'b01: parallel_out = {rsi, qout[n-1:1]}; 2'b10: parallel_out = {qout[n-2:0], lsi}; 2'b11: parallel_out = din; case module Parameterized module로작성하지않은경우, 즉, 4-bit universal shift register를작성한경우 (-3 pts) rsi, lsi를고려하지않은경우 (-2 pts) 10. A. (10 pts) module single_cycle(clock, a, b, c, x); input [7:0] a, b, c; input clock; output [7:0] x; reg [7:0] x; (posedge clock) x <= a * (b c); module 사소한문법오류 (-1 pts) 계산이 single cycle에이루어지지않는경우 (-2 pts) 기타사소한실수 (-1 pts씩 ) B. (10 pts) module pipeline_3cycle(clock, a, b, c, x); input [7:0] a, b, c; input clock; output [7:0] x;

12 reg [7:0] x; reg [7:0] tmpa, tmpb, tmpc, tmpa2, tmp_sub, tmp_mul; clock) tmpa <= a; tmpb <= b; tmpc <= c; tmpa2 <= tmpa; tmp_sub <= tmpb tmpc; tmp_mul <= tmpa2 * tmp_sub; x <= tmp_mul; module pipeline이되어있지않은경우 (-2 pts) ( 예를들어, 를사용한경우 ) latency가 3 cycle이아닌경우 (-2 pts) ( 예를들어, blocking assignment를사용한경우 ) 3-stage pipeline을고려할때결과가잘못된값인경우 (-2 pts) ( 예를들어, tmpa2 없이 tmp_mul 계산에서 tmpa를그대로사용하는등 ) 기타사소한실수및문법오류 (-1 pts) 11. (10 pts) module parity(data, parity, even_odd, error); input [7:0] data; input parity; input even_odd; // 0 for even parity, 1 for odd parity output error; // 1 for parity error wire error; wire total_parity; assign total_parity = (^data) ^ parity; assign error = data_parity ^ even_odd; module 사소한실수및문법오류 (-1 pts) 12. (10 pts) 최초의순간에만 IDLE state에있으며, 이때입력된 data는무시한다. 이후에는 data 로필요한값이매 cycle마다입력된다고가정한다. module parity(clock, data, even_odd, error); input data, clock; input even_odd; // 0 for even parity, 1 for odd parity

13 output reg error; reg [3:0] curr_state; reg [3:0] next_state; reg curr_value; reg next_value; parameter IDLE = 4'd0, D1 = 4'd1, D2 = 4'd2, D3 = 4'd3, D4 = 4'd4, D5 = 4'd5, D6 = 4'd6, D7 = 4'd7, D8 = 4'd8, P1 = 4'd9; // parity initial next_state <= IDLE; next_value <= 1'b0; clock) curr_state <= next_state; curr_value <= next_value; error = 1'bx; case (curr_state) IDLE: next_state = D1; next_value = 1'b0; D1: next_state = D2; next_value = data; error <= curr_value; D2: next_state = D3; next_value = curr_value ^ data; D3: next_state = D4; next_value = curr_value ^ data;

14 D4: next_state = D5; next_value = curr_value ^ data; D5: next_state = D6; next_value = curr_value ^ data; D6: next_state = D7; next_value = curr_value ^ data; D7: next_state = D8; next_value = curr_value ^ data; D8: next_state = P1; next_value = curr_value ^ data; P1: next_state = D1; next_value = curr_value ^ data ^ even_odd; default: next_state = IDLE; next_value = 1'b0; case module 다른 state를추가적으로도입하는등의경우에도결과만정확하면기본 10pts. Moore machine이므로, error는 current state에만 depent하고 input에는 indepent해야한다. 이조건을어겼을경우 (-2 pts) 기타사소한실수및문법오류 (-1 pts) 13. (10 pts) module sequence0101(clock, data, z, reset_n); input data, clock, reset_n; output reg z; // 1 if detected reg [1:0] curr_state, next_state; parameter A = 2'b00, B = 2'b01, C = 2'b10, D = 2'b11;

15 clock) if (reset_n == 1'b0) curr_state <= A; else curr_state <= next_state; case (curr_state) A: if (data == 1'b1) next_state = A; else next_state = B; B: if (data == 1'b1) next_state = C; else next_state = B; C: if (data == 1'b1) next_state = A; else next_state = D; D: if (data == 1'b1) next_state = C; else next_state = B; case case (curr_state) A: z = 0; B: z = 0; C: z = 0; D: if (data == 1'b1) z = 1; else z = 0; case module Mealy machine이므로, z는 input과 current state에만 depent하다. 이를어겼을경우 (-2 pts) always 문이 3개가아닌경우 (-2 pts) Parameter 문을잘못사용한경우 (-8 pts)

PowerPoint 프레젠테이션

PowerPoint 프레젠테이션 Verilog: Finite State Machines CSED311 Lab03 Joonsung Kim, joonsung90@postech.ac.kr Finite State Machines Digital system design 시간에배운것과같습니다. Moore / Mealy machines Verilog 를이용해서어떻게구현할까? 2 Finite State