Microsoft PowerPoint - VHDL08.ppt [호환 모드]

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1 VHDL 프로그래밍 8. 조합논리회로설계 한동일 학습목표 테스트벤치의용도를알고작성할수있다. 간단한조합논리회로를설계할수있다. 하나의로직회로에대해서다양한설계방식을구사할수있다. 제네릭을활용할수있다. 로직설계를위한사양을이해할수있다. 주어진문제를하드웨어설계문제로변환할수있다. 설계된코드를테스트벤치를이용하여검증할수있다. 2/37

2 테스트벤치 (test bench) 테스트벤치 (test t bench) 란? 과거, 패턴발생기, 오실로스코우프, 멀티미터등을이용한검증환경 VHDL 환경내에서 VHDL 을이용하여모든검증가능 테스트벤치를이용한검증과정 로직설계 : 목표로하는하드웨어의 VHDL 설계 테스트벤치작성 VHDL 을이용하여하드웨어의검증환경작성 시뮬레이션및검증 VHDL 개발환경을이용한설계한로직의검증작업 3/37 로직설계예 AND 게이트 A B Y AND 게이트의 VHDL 표현 entity and_gate is port (A, B : in bit; Y : out bit); end; architecture and_gate of and_gate is Y <= A and B ; end; 4/37

3 로직의검증 AND 게이트의진리표및대응되는신호파형 A B Y=A and B A B ns 20 ns 30 ns 40 ns 신호파형의 VHDL 표현 A <= '0', '1' after 20 ns, '0' after 40 ns; B<='0', '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns; 5/37 테스트벤치의구성 테스트벤치의구성이유 생성된파형을설계한회로에인가 회로의출력값이기대값과일치하는지검증 로직설계 vs. 테스트벤치구성 로직설계 : 반드시논리합성이가능한코드로설계 VHDL 문법에서는하드웨어구현을위한다양한문법제공 테스트벤치구성 : 논리합성가능여부와는무관 VHDL 문법에서는테스트벤치구성을목적으로하는다양한문법구조제공 6/37

4 테스트벤치의구성 AND 게이트의테스트벤치구성예 entity tb_and_gate is port (Y : out bit) ; end tb_and_gate ; architecture simulation of tb_and_gate is component AND_gate port (A, B: in bit; Y : out bit); end component; signal a,b : bit; a <= '0', '1' after 20 ns, '0' after 40 ns; b <= '0', '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns; U0 : AND_gate port map (A=>a, B=>b, Y=>Y); end ; 7/37 테스트벤치의구성 시뮬레이션파형예 8/37

5 멀티플렉서설계 멀티플렉서 (multiplexer) l 9/37 멀티플렉서설계 멀티플렉서의 VHDL 표현 entity mux_4x1 is port( a, b, c, d: in bit; sel : in bit_vector(1 downto 0); q : out bit); end; architecture with_select of mux_4x1 is with sel select q<= a when "00", b when "01", c when "10", d when "11", a when others; end; 10/37

6 멀티플렉서설계 멀티플렉서의테스트벤치구성예 entity tb_mux_4x1 is end tb_mux_4x1 ; architecture simulation of tb_mux_4x1 is component mux_4x1 port ( a, b, c, d: in bit; sel : in bit_vector(1 downto 0); q : out bit); end component; ; signal a,b,c,d : bit; signal sel : bit_vector(1 downto 0); A<='0', '1' after 20 ns, '0' after 40 ns; B <= '0', '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns; C <= '0', '1' after 40 ns, '0' after 80 ns; D <= '0', '1' after 20 ns, '0' after 40 ns, '1' after 60 ns, '0' after 80 ns; SEL <= "00", "01" after 20 ns, "10" after 40 ns, "11" after 60 ns, "00" after 80 ns; U0 : mux_4x1 port map (A=>A,B=>B,C=>C, A,B B,C C, D=>D, D, SEL=> SEL, Q=>open); end ; 11/37 멀티플렉서설계 시뮬레이션파형예 12/37

7 멀티플렉서설계 멀티플렉서의테스트벤치구성예 entity tb_mux_4x1 is end tb_mux_4x1 ; architecture simulation of tb_mux_4x1 is component mux_4x1 port ( a, b, c, d: in bit; sel : in bit_vector(1 downto 0); q : out bit); end component; ; signal a,b,c,d : bit; signal sel : bit_vector(1 downto 0); A<='0', '1' after 5ns ns, '0' after 10 ns, '1' after 15 ns, '0' after 20 ns, '1' after 80 ns; B <= '0', '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns; C <= '0', '1' after 15 ns, '0' after 30 ns, '1' after 45 ns, '0' after 60 ns; D <= '0', '1' after 20 ns, '0' after 40 ns, '1' after 60 ns, '0' after 70 ns; SEL <= "00", "01" after 20 ns, "10" after 40 ns, "11" after 60 ns, "00" after 80 ns; U0 : mux_4x1 port map (A=>A,B=>B,C=>C, A,B B,C C, D=>D, D, SEL=> SEL, Q=>open); end ; 13/37 멀티플렉서설계 시뮬레이션파형예 14/37

8 비교기설계 비교기 (comparator) A B Y (A=B) A B Y /37 비교기설계 비교기의 VHDL 표현 entity comparator is port(a, B: in bit; Y : out bit); end comparator; architecture behavioral of comparator is process (A, B) if (A = B) then Y <= '1'; else Y <= '0'; end; end if; end process; 16/37

9 비교기설계 비교기의테스트벤치구성예 entity tb_comparator is end tb_comparator ; architecture simulation of tb_comparator is component comparator port (A, B: in bit; Y : out bit); end component; signal signal_a,signal_b i l : bit; end ; signal_a <= '0', '1' after 20 ns, '0' after 40 ns; signal_b <= '0', '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns; U0 : comparator port map (A=>signal_a, B=>signal_b, Y=>open); --U0 : comparator port map (signal_a, a signal_b, open); --U0 : comparator port map (Y=>open, A=>signal_a, B=>signal_b); --U0 : comparator port map (open, signal_a, signal_b); -- Not Good 17/37 비교기설계 일반화및제네릭의사용 4 bit 비교기의설계 entity comparator is port( A, B : in bit_vector(3 downto 0); end comparator; Y : out bit); N bit 비교기의설계 entity comparator is generic( N : integer); end comparator; port( A, B : in bit_vector(n-1 downto 0); Y : out bit); 18/37

10 비교기설계 제네릭의사용방법 제네릭선언시초기화 generic (N : integer := 4); 콤포넌트실체화문에서초기화 u0: comparator generic map (N => 4) port map (A=>signal_a,B=>signal_b,Y=>open); a 콤포넌트실체화문에서재정의 generic (N : integer := 2); -- 중략 u0: comparator generic map (N => 4) port map (A=>signal_a,B=>signal_b,Y=>open); 제네릭값은시뮬레이션시작이전에반드시값을정의 19/37 디코더설계 디코더 (decoder) d A(0) A(1) A(2) Y(0) Y(1) Y(2) Y(3) Y(4) Y(5) Y(6) Y(7) A(2) A(1) A(0) Y(7) Y(6) Y(5) Y(4) Y(3) Y(2) Y(1) Y(0) /37

11 디코더설계 디코더의 VHDL 표현 entity decoder3x8 is port (A : in bit_vector(2 downto 0); Y : out bit_vector(7 downto 0)); end decoder3x8; architecture behavioral of decoder3x8 is process(a) case A is when "000" => Y <= " "; when "001" => Y <= " "; -- 중략 when "111" => Y <= " "; when others=> Y <= " "; end case; end process; end behavioral; 21/37 디코더설계 디코더의테스트벤치구성예 entity tb_decoder3x8 is end tb_decoder3x8 ; architecture simulation of tb_decoder3x8 is component decoder3x8 port ( A : in bit_vector(2 downto 0); Y : out bit_vector(7 downto 0)); end component; signal signal_a : bit_vector(2 downto 0); signal_a a <= "000", "001" after 5ns ns, "010" after 10 ns, "011" after 15 ns, "100" after 20 ns, "101" after 25 ns, "110" after 30 ns, "111" after 35 ns, "000" after 40 ns, "001" after 45 ns, "010" after 50 ns, "011" after 55 ns, "100" after 60 ns, "101" after 65 ns, "110" after 70 ns, "111" after 75 ns, "000" after 80 ns; u0: decoder3x8 port map (A=>signal signal_a, a, Y=>open); end ; 22/37

12 디코더설계 시뮬레이션파형예 23/37 디코더설계 enable 기능이있는디코더 en A(2) A(1) A(0) Y(7) Y(6) Y(5) Y(4) Y(3) Y(2) Y(1) Y(0) /37

13 디코더설계 enable 기능이있는디코더의 VHDL 표현 entity decoder3x8_en is port ( A : in bit_vector(2 downto 0); EN : in bit; Y : out bit_vector(7 downto 0)); end decoder3x8_en; architecture behavioral of decoder3x8_en is process (A, EN) 25/37 디코더설계 enable 기능이있는디코더의 VHDL 표현 - 계속 end if; end process; end behavioral; if EN = '0' then Y<=" "; else case A is when "000" => Y <= " "; when "001" => Y <= " "; when "010" => Y <= " "; when "011" => Y <= " "; when "100" => Y <= " "; when "101" => Y <= " "; when "110" => Y <= " "; when "111" => Y <= " "; when others=> Y <= " "; end case; 26/37

14 디코더설계 enable 기능이있는디코더의테스트벤치구성예 architecture simulation of tb_decoder3x8_en is component decoder3x8_en en port ( A : in bit_vector(2 downto 0); EN : in bit; Y : out bit_vector(7 downto 0)); end component; signal signal_a : bit_vector(2 downto 0); signal en : bit; en <= '0', '1' after 40 ns, '0' after 80 ns; signal_a a <= "000", "001" after 5ns ns, "010" after 10 ns, "011" after 15 ns, "100" after 20 ns, "101" after 25 ns, "110" after 30 ns, "111" after 35 ns, "000" after 40 ns, "001" after 45 ns, "010" after 50 ns, "011" after 55 ns, "100" after 60 ns, "101" after 65 ns, "110" after 70 ns, "111" after 75 ns, "000" after 80 ns; u0: decoder3x8_en en port map (A=>signal signal_a, a, EN => en, Y=>open); end simulation; 27/37 디코더설계 시뮬레이션파형예 28/37

15 배럴쉬프터설계 배럴쉬프터 (barrel shifter) 입력데이터를원하는방향과크기만큼이동시켜출력 한멀티플렉서의출력이다른멀티플렉서입력으로인가되는구조반복 배럴쉬프터의용도 부동소수점연산의자리수고속이동 동영상복원과정의가변길이복호화 (variable length decoding) 베럴쉬프터의복잡도 입력비트수 n : 멀티플렉서의수 = n x log 2 (n) 고속동작이요구되는로직에서는배럴쉬프터의사용을자제 혹은효율적인구조의배럴쉬프터사용필요 29/37 배럴쉬프터설계 배럴쉬프터의입출력신호 4비트데이터입력 : shift_in (3 downto 0) 동작제어신호 : mode (1 downto 0) mode (1) : shift mode : 1 이면 rotate shift, 0 이면 logical shift mode (0) : shift direction: 1 이면 left shift, 0 이면 right shift 비트이동신호 : distance (1 downto 0) 0 부터 3 비트의이동신호발생 4 비트데이터출력 : shift_out (3 downto 0) 30/37

16 배럴쉬프터설계 배럴쉬프터의동작예 shift_in (3 downto 0) = 1101 mode (1 downto 0) = 10 (rotate right shift) distance (1 downto 0) = 01 Shift_in Shift_out /37 배럴쉬프터설계 배럴쉬프터의동작예 shift_in (3 downto 0) = 1101 mode (1 downto 0) = 01 (logical left shift) distance (1 downto 0) = 10 Shift_in Shift_out /37

17 배럴쉬프터설계 배럴쉬프터의동작예 logical right shift 의 VHDL 구현예 case distance is when "00" => shift_out(3 downto 0) <= shift_in(3 downto 0); when "01" => shift_out(3 t(3 downto 0) <= '0' & shift_in(3 i downto 1); when "10" => shift_out(3 downto 0) <= "00" & shift_in(3 downto 2); when "11" => shift_out(3 t(3 downto 0) <= "000" & shift_in(3); i when others => shift_out(3 downto 0) <= shift_in(3 downto 0); end case; 33/37 배럴쉬프터설계 배럴쉬프터의동작예 rotate left shift 의 VHDL 구현예 case distance is when "00" => shift_out(3 downto 0) <= shift_in(3 downto 0); when "01" => shift_out(3 downto 0) <= shift_in(2 in(2 downto 0) & shift_in(3); in(3); when "10" => shift_out(3 downto 0) <= shift_in(1 downto 0) & shift_in(3 downto 2); when "11" => shift_out(3 downto 0) <= shift_in(0) & shift_in(3 downto 1); when others => shift_out(3 downto 0) <= shift_in(3 downto 0); end case; 34/37

18 배럴쉬프터설계 배럴쉬프터의동작예 모드결정로직 -- mode(1) : shift mode : '1' 이면 rotate shift, '0' 이면 logical shift -- mode(0) : shift direction : '1' 이면 left shift, '0' 이면 right shift if mode(1) = '0' and mode(0) = '0' then -- description of logical shift right mode elsif mode(1) = '0' and mode(0) = '1' then -- description of logical shift left mode elsif mode(1) = '1' and mode(0) = '0' then -- description of rotate shift right mode else -- mode(1) = '1' and mode(0) = '1' -- description of rotate shift left mode end if; 35/37 배럴쉬프터설계 배럴쉬프터의동작예 가명선언을이용한모드결정로직 alias rotate : bit is mode(1); alias left : bit is mode(0); -- 중략 if rotate = '0' and left = '0' then -- description of logical shift right mode elsif rotate = '0' and left = '1' then -- description of flogical lshift hiftleft mode elsif rotate = '1' and left = '0' then -- description of rotate shift right mode else -- rotate = '1' and left = '1' -- description of rotate shift left mode end if; 36/37

19 배럴쉬프터설계 시뮬레이션파형예 37/37

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