Libero Overview and Design Flow

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1 Libero Overview and Design Flow <1>

2 Libero Integrated Orchestra Actel Macro Builder VDHL& VeriogHDL Editor ViewDraw Schematic Entry Synplicify for HDL Synthesis Synapticad Test Bench Generator ModelSim for Design Verification Actel Designer P&R Actel In-Circuit Probing Text Editor In Libero <2>

3 Libero Design Flow Text Editor SOURCE HDL PLACE & ROUTE NETLIST EDIF BITSTREAM PROBE Silicon Sculptor TESTBENCH GENERATION FUNCTION SIMULATION NETLIST HDL NETLIST HDL SDF FILE TESTBENCH HDL GATE SIMULATION TIME SIMULATION <3>

4 Software Install 1. Libero, Synplify, Waveformer install 2. Libero product : evaluation install <4>

5 Libero Software Feature <5>

$Language and products 선택 (Libero Evaluation) 4. C:\ vol 과 synplify 의 hostid 입력 => Synplify hostid 는설치후 synplify 를실행하면얻을수있음. 2 5.$

6 License Request 1. actel.com/.com/regserial.asp 접속 2. Evaluation 신청시 here click 3. Language and products 선택 (Libero Evaluation) 4. C:\ vol 과 synplify 의 hostid 입력 => Synplify hostid 는설치후 synplify 를실행하면얻을수있음 이후 customer 정보입력후 mail 로 license 받음. 3 4 <6>

7 License Setup 1. 로받은 license.dat 를 actel install directory 에 copy 2. Os 가 win2000 일경우 내컴퓨터등록정보 -> 고급 -> 환경변수변수 LM_LICENSE_FILE 값 C:\<INSTALL DIR>\license. license.dat 변수 SYNPLICITY_LICENSE_FILE 값 C:\<INSTALL DIR>\license. license.dat 위두항목을추가. 3. Os 가 win98 일경우 Autoexec.bat 파일에 SET LM_LICENSE_FILE = C:\< 라이센스위치 >\license. license.dat SET SYNPLICITY_LICENSE_FILE = C:\< 라이센스위치 >\license. license.dat SET SYNCAD_HOME = C:\<WaveFormer Install DIR>\synapticad 위세항목을추가. <7>

8 Demo Design Block Diagram TOP clk20 count_en reset clk20 COUNTER count 16 clk40 PLL clk80 enable shift_in shift_en clk80 PISO Shift Register data_out reset count Pll_block : 40Mhz input 을 20Mhz Mhz,, 80Mhz 의 clock 생성 2. Count_block : 20Mhz 의 clock 으로 16bit counter 3. Piso_block : counter 의 output 을 1bit serial 로출력 4. Top : 세개의 sub_block 을통합 <8>

Libero Project Manager Design Explorer Window 디자인의계층구조표시 : - Design hierarchy: source design 에대한계층구조표시 - File Manager : design 의구성및결과 file 관리창 HDL Editor Window Verilog 와

9 Libero Project Manager Design Explorer Window 디자인의계층구조표시 : - Design hierarchy: source design 에대한계층구조표시 - File Manager : design 의구성및결과 file 관리창 HDL Editor Window Verilog 와 VHDL93 text editor Process Window Design 을위한다른 tools 로연결 Log Window Software 연결상태및메세지창 Design Explorer Window Process Window Log Window HDL Editor Window Language and Family <9>

10 Create Project 2 1. Libero IDE V2.3 을실행 2. 메뉴에서 File -> > New Project 실행 3. Project Name, Location, Family, HDL 지정 4. OK. 3 Note : VHDL 과 Verilog 와의 mixed design 은지원하지않음. 한개의 HDL 과 Schematic 은가능 4 <10>

Design Entry Utilities HDL Editor : VHDL & Verilog editor 생성

11 Process Window 1. Design 방법및지원되는 S/W 를보여줌. 2. Design 단계별로사용가능한지를글씨체로확인가능하며다음단계로의이동을쉽게할수있음. Design Entry Utilities HDL Editor : VHDL & Verilog editor 생성 ViewDraw : Schematic editor 생성 ACTgen : Design Macro Builder NEW design 생성시 File -> > New Design Entry Utilities 에서선택 <11>

Create Design PLL Block 3 4 1. Process window 에서 actgen 을선택 2. 왼쪽 MACROS 메뉴에서 PLL 선택 3. Input clock 40Mhz. 4. Primary clock output 20Mhz 5.

12 Create Design PLL Block Process window 에서 actgen 을선택 2. 왼쪽 MACROS 메뉴에서 PLL 선택 3. Input clock 40Mhz. 4. Primary clock output 20Mhz 5. Secondary Clock output 80Mhz 6. Generate Pll_block. _block.vhd file <12>

13 Creat Design Count Block 1. 새로운 vhdl 생성시 -> New -> > VHDL Entity 2. cnt_block _block.vhd file 생성 3. HDL Editor Window 에서 cnt_block coding 4. 저장시 Design hierachy 에 cnt_block 추가됨 HDL Editor Window <13>

14 Creat Design Count Block -- cnt_block library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity cnt_block is port (count_en, reset, clk20 : in std_logic; count : out std_logic_vector(15 downto 0)); end cnt_block; architecture behave of cnt_block is signal tmp : std_logic_vector(15 downto 0); begin process(reset, clk20) begin if reset = '0' then tmp <= (others => '0'); elsif clk20'event and clk20='1' then if count_en = '1' then tmp <= tmp + '1'; end if; end if; end process; count <= tmp; end behave; 1. Library 선언구문 2. Entity 구문 cnt_block 의입출력 signal 선언구문 count_en reset clk20 cnt_block count Achitecture 구문 16bit counter with count enable and asynchronous reset <14>

15 Creat Design PISO Block New actgen file 생성 (new->actgen macro) 2. Macros 에서 Register 선택 3. Register 종류중에 Shift Register 선택 4. Variations => Parallel input to serial output register 5. Register condition 입력 6. Generate 5 2 <15>

16 Creat Design TOP BLOCK 1 1. 새로운 vhdl 생성시 -> New -> > VHDL Module 2. top.vhd file 생성및 HDL Editor Window coding 작업 3. Top design 을 root 로지정 4. Top design 을굵은글자체로전환 3 2 HDL Editor Window 4 <16>

17 -- top library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_.std_logic_arith.all; use ieee.std_logic_unsigned.all; Creat Design Top Design entity top is port (reset, clk40 : in std_logic; count_en, enable, shift_in, shift_en : in std_logic; count : out std_logic_vector(15 downto 0); data_out : out std_logic); end top; architecture behave of top is component pll_block is port(glb,gla,lock : out std_logic; CLK : in std_logic); end component; component cnt_block is port (count_en, reset, clk20 : in std_logic; count : out std_logic_vector(15 downto 0)); end component; component piso_block is port(data : in std_logic_vector(15 downto 0); Enable, Shiften, Shiftin, Aclr,, Clock : in std_logic; Shiftout : out std_logic) ; end component; signal tmp_cnt : std_logic_vector(15 downto 0); signal tmp_clk20, tmp_clk80 : std_logic; begin U1 : pll_block port map (tmp( tmp_clk20, tmp_clk80, open, clk40); U2 : cnt_block port map (count_en, reset, tmp_clk20, tmp_cnt cnt); U3 : piso_block port map (tmp( tmp_cnt,, enable, shift_en, shift_in, reset, tmp_clk80, data_out); count <= tmp_cnt cnt; end behave; 1. Library 선언구문 2. Entity 구문 top design 의입출력 signal 선언구문 reset clk40 count_en enable Shift_in Shift_en top 5. Component port map 구문 Sub block 간의 signal 연결 count 16 Data_out 3. Architecture 구문 4. Component 선언구문 Sub block pll_block, cnt_block, piso_block 선언 <17>

18 Synplify Synthesis 1 1. Top design 에서오른쪽마우스클릭또는 process window 에서 Synthesize 선택 2. Synthesize 실행 3. Design library & source file list 4. Synthesis implementation options 5. Target device change <18>

19 SYNPLICITY SYNTHESIS 1. Run 실행 2. RTL / Technology View 통해회로도검토 3. 출력은 edif (.edn edn) 으로출력됨 4. Libero 의 file manager 에서확인가능 <19>

<Bitstream> > program 하기위한 bit file 생성 * Sub menu <Netlist Viewer> gat level circuit 분석 <PinEdit> > pin assign

20 Designer Series Compile 1 1 < Place & Route 과정 > => actel designer series s/w 사용 1. Top design 에서오른쪽마우스클릭 2. Menu 중 Run Designer 실행 2 * Main menu <Compile> device 선택및 logic size 분석 <Layout> design place & route <Bitstream> > program 하기위한 bit file 생성 * Sub menu <Netlist Viewer> gat level circuit 분석 <PinEdit> > pin assign <ChipView> > layout 후내부 cell 의위치정보확인 <Timer> design timing 정보 <SmartPower> > power 소모량측정 <BackAnnotate> > Timing sim 을위한파일출력 <20>

21 Designer Series Compile 1 1. Device (gate,package,speed,voltage) 설정 2 Jteg pin 설정 3. Device (Operating Conditions) 설정 Temperature & Voltage : com, ind,, mil 4. 마침 2 3 <21>

22 Designer Series PinEdit 1. Compile 완료시녹색아이콘으로변함. 2. Device 사용량 Core cells : 124/3072 RAM/FIFO Cells : 0/12 Ios : 23/100 PLLs : 1/2 3. PinEdit => drag and drop 방식으로 pin assign <22>

23 Designer Series Layout 1. Layout options <Timing-Driven> constraint file(gcf gcf) 에명시된조건에따라 layout 을실행함. <Run Place> Incrementally : Select to use previous placement data as the initial placement for the next place run. Lock Existing Placement (fix) : Select to preserve previous placement data during the next incremental placement run. <Run Route> Incrementally : <Use Multiple Passes> layout 시시작시점 (Seed) 을다르게하여전혀다른 layout 결과를가져와성능향상에도움이됨 2. Ok <23>

24 1 Designer Series ChipEdit 2 1. ChipEdit 열기 2. Memory block APA 075/150 : 위에만 Memory 위치 APA 300 이상 : 위아래두곳에 Memory 위치 3. Core cell(tiles) Core cell 의위치좌표 L8 L6 L7 L L11 0 L9 L4 L5 L2L0L13 L3L1L15 L12 L14 <24>

25 1 Designer Series Timer 1. Timer 열기 2. Clk40 에대한 clock performance 3. Path 별 timer 분석 4. Register to Register delay 분석 <25>

26 Designer Series Timer 1 1. Bitstream 열기 2. File Type 선택 BitStream : silicon sculptor 를이용한 programming STAPL : flash pro and lite 를이용한 programming 3. FlashLock 입력시 program, erase 불가 4. Programming file 생성 <26>

27 1 Designer Series Backannotation 2 1. Backannotate 열기 2. SDF(Standard Delay Format) 출력 3. Timing simulation 을위한 netlist VHDL 파일출력 4. Pin file / Netlist 출력가능 5. Designer Place and Route 완료, top.adb 저장 3 4 <27>

28 Waveformer Lite 1. TOP design 에서 Create Stimulus 열기 2. Clk40 에 clock 속성부여 1 <note> signal list 에서진하게출력되는 signal 은 input 을나타내고엷게출력되는 signal 은 output 을나타낸다. Adjust signal levels 2 I/O signals <28>

29 Waveformer Lite Clock Properties Clock name Clock Frequency Clock Period Clock duty cycle <29>

30 Waveformer Lite Export files 1 1. Bit 입력은 high/low icon 을이용하여입력 2. Save fils Timing Project => top.tim tim Testbench VHDL=> top.vhd => VHDL Wait with Top Level TestBench 을선택 Adjust the transition times Edge 를 Click 하여 move 가능중간에 drag 하여 signal 값변경가능 <30>

31 Waveformer Lite Export files 2 Timing Project File Testbench VHDL File <31>

32 ModelSim Simulation 1 1. Simulation 하기위한 options 2. Tools -> > options 선택 3. Simulation tab 을선택 <Simulation Run> : Simulation 의끝점을선정. (ex: 2000ns : 결과를 2us 까지출력 ) <Compile VHDL Package Files> : simulation 할때마다 package file 을다시 compile 함. <Inculde wave.do> : user 가원하는 signal 을 wave.do 로저장하여다음 simulation 시적용됨. <Vsim Command> : Timing Simulation 시 Min(best)/Typ Typ(typical)/Max(worst) case 를선택하여 simulation 함. <Resolution> : simulation 결과출력시 sampling time 을의미함. 값이작을수록더정확한결과를얻을수있음. <32>

ModelSim Simulation 2 1. Modelsim Simulator 열기 2.

Post_Synthesis Simulation : Gate simulation Run

33 ModelSim Simulation 2 1. Modelsim Simulator 열기 2. 여러개의 stimulus 가있을경우한개를선택 3. ModelSim 이열리면서자동적으로 compile, load design, simulation 실행 Run Pre_Synthesis Simulation : Function simulation Run Post_Synthesis Simulation : Gate simulation Run Post_Layout Simulation : Timing simulation * 정확한 design 의검증을위해서는위세가지의모든경우에대해서 simulation 결과가일치해야함. <33>

34 ModelSim Simulation 3 Zoom in/out icon 가운데마우스키를이용하여 zoom area 가능 Input/output signal list <34>

35 ModelSim Simulation 4 < 내부 signal 을보기위한방법 > 1. View -> > Signals 과 Structure 창을 open 2. Structure 창에서내부 block 으로이동 3. Signals 창에서원하는 signal 을선택하여 add->wave 를한다. Input/output signal list <35>

36 ModelSim Simulation 4 1. Modelsim main windows 에서 vsim #> restart f vsim #> run 2 us 를실행 2. Wave 창에서결과확인 3. Wave 창에서 wave.do 로저장하게되면다음에이추가된 signal 이자동으로올라오게된다. <36>

37 Silicon Sculptor programming Silicon Sculptor 1. Silicon Sculptor Programmer 실행 2. Device 선택 3. Fusing file(bitstream 선택 ) Program 5. Program status <37>

38 Creat Design Schematic 1. New Schematic file 생성 (new->schematic) 1 Component Net Bus Schematic Editor <38>

39 Creat Design Schematic 1. Component 선택시두가지방법 i. Command line 에서원하는 component 를입력 => com and2 ii. Add component 에서원하는 component 를선택 <39>

40 Creat Design Schematic 1. Net 연결은 net icon 을이용하여 component 간의 pin 을연결한다. i. 단축키 <n> 를이용할수있다. 2. Block 의 in/out 은 component 에서 in 또는 out 을선택하여 net 끝에연결한다. 3. Net name 은 net properties 에 label 에이름을준다. i. In/out 의모든 net ii. 모든 bus 에는이름을주어야한다. <40>

41 Creat Design Schematic 1. Bus 연결은 bus icon 을이용하여 component 간의 pin 을연결한다. i. 단축키 <b> 를이용할수있다. 2. Bus name 은 Bus properties 에 label 에 name 을준다. 3. Index 를위하여 [7:0] 의형태를갖는다. 4. 배열을주기위해서 component properties 에서 array option 을이용한다. <41>

42 Creat Design Schematic 1. Bus 에서 bit 의분리는 bus 라인에서 net 바로연결하여사용한다. 2. Index 를 bus name 에바로붙여사용 <42>

43 Creat Design Schematic 1. Vhdl 로구성된 top design 을 schematic 의 sub block 으로만들기위해서 create symbol 2. Add component 에서 top design 을 import 하여 net 를연결한다. <43>

44 Creat Design Schematic 1. Vhdl top design 과 schematic 과의 2. Add component 에서 top design 을 import 하여 net 를연결한다. <44>

MAX+plus II Getting Started - 무작정따라하기

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