디지털 ASIC 설계 (1주차) MAXPLUS II 소개 및 사용법

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1 디지털 ASIC 설계 (1 주차 ) MAXPLUS II 소개및사용법 신흥대학전자통신과김정훈 jhkim@shc.ac.kr

2 차례 1. Why Digital 2. Combinational logic ( 조합회로 ) 소개 3. Sequential logic ( 순차회로 ) 소개 4. MAX+PLUSII 소개 5. MAX+PLUSII Tools 설계환경 6. 예제소개 2

3 Why Digital? The shape of waveform is affected by two basic mechanism Distorting effect Noise or interference Since binary circuits operate in one of two state, digital circuits are less subject to distortion and interference than are analog circuits. 3

4 Classification of Signals x(t) x(kt) Analog : x(t) is a continuous function of time Discrete : x(kt) is one that exists only at discrete times(kt) Digital : Sampling and Quantization t t 4

5 Combinational Logic 현재의입력값이아무때나출력되는 Logic NOT-, AND-, OR-gate와같은기본 logic 에의해서구성됨 Multiplexer, Encoder, Adder, Multiplier 등을구현할수있음 5

6 Sequential Logic Clock 의 rising edge 에입력된신호가출력 Flip-Flop(RS, JK, D) 으로구성됨 Flip-Flop 은 gate 에의하여구성됨 실제적으로주로 DFF 을이용함 Delay, Register, Shifter, Counter등을구현할수있음 복잡한 Logic을간단한 Logic으로분할하여 Pipe Line Processing 가능 6

7 State Machine 입력값과현재 State에따라서출력값과다음Sate 값이결정됨 Combinational Logic과 Sequential Logic 을함께이용하여구성됨 Controller등 Case가복잡한구현에적용하여간단한여러개의 Case로나누어구현할수있음 7

8 Review Advantage of Digital Systems Analog to Digital Conversion Quantization Noise Quantization Saturation Timing Jitter Goals of Digital Systems Logic Circuit의종류 8

9 MAX+PLUS II? 사용상의편리성과빠른컴파일속도 ALTERA PLD 전용디자인소프트웨어 단일시스템내에완벽히통합된설계과정을통해 PC 및 Unix 환경에서사용가능. VHDL, VerilogVHDL, Schemetic, LPM(Library of Parametrized Modules), AHDL(Altera Hardware Description Language) 그리고 Waveform Design 등주요한디자인기술을단일시스템상에서동시에지원하여개발기간을단축시켜줌. 일반 EDA 툴과간편하게데이타호환 9

10 PLD 의종류 10

11 Introduction to Altera Inventor of the EPLD in 1983 Seven Programmable Logic Families Product Term-based (EPROM, EEPROM) Classic FLASHLogic MAX 5000 MAX 7000E(S) MAX 9000 Look-Up Table-based (SRAM) FLEX 10K FLEX 8000A FLEX

12 Implement of Digital Systems Gate : 설계 ( 하 ), T/S( 하 ), 비용 ( 저 ), 유연성 ( 중 ) EPLD : 설계 ( 상 ), T/S( 상 ), 비용 ( 중 ), 유연성 ( 상 ) ASIC : 설계 ( 중 ), T/S( 중 ), 비용 ( 고 ), 유연성 ( 하 ) * 양산시는단가면에서 ASIC 이유리 12

13 Classification of Altera Chips Classic, 5000 series: Small size,low speed 7000, 9000 series (E-EPROM Type) logic cell : less then 550 speed : very high 8000, 10k series (SRAM Type) logic cell : less then 3500 speed : high 10k series include internal SRAM 13

14 Altera Chip 의종류 EPROM Type(EPM), SRAM Type(EPF) Series : 7000(7), 8000(8), 10k(10K) Logic Cell : 256, 1500 Speed Grade : 3(30), 2(20), 15, 10, 7 Package Type : GC(PGA), LC(PLCC) Number of Pin Ex) EPM7256EGC192-12, EPF10K100GC

15 MAXPLUS Tools 소개 Text Editor(.tdf,.rpt) Graphic Editor(.gdf) Waveform Editor(.scf) Compiler Timing Simulator Timing Analyzer Programmer(.pof) 15

16 MAX PLUS II 설계환경

17 Design Flow Debugging Waveform Editor Pin Assign & Recompile Design Compile Timing Simulation Programming AHDL, VHDL, Graphic Editor, (Verilog HDL, EDIF) Syntax Check, Synthesis, Partition, Fitting Waveform Editor 를이용하여 Input Signal 을정의하면 Node 및 Output Signal 의출력 Design 이확정되었을때실제 Altera Chip 에 Programming 을함 17

18 Design Entry There are serveral methods of design entry in MAX+PLUS II Graphic design (Schematic Capture) AHDL (Altera Hardware Description Language) VHDL Waveform design EDIF (Synopsys, Viewlogic, Mentor, Cadence, etc.) Proprietary (ABEL, PALASM, OrCAD.sch, Xilinx.xnf) 18

19 컴파일수행과정과생성파일

20 Compile Process Compiler Netlist Extractor : 각디자인파일에서 netlist 파일 (.cnf) 생성 Database Builder : 전기적인연결상태점검 Logic Synthesizer : 로직점검하여연결되지않은노드삭제 Partitioner : 하나의 Device에할당하고불가능시여러 Device로나눔 Fitter : 나누어진회로를최상의 ; Logic Cell에할당하고배선을함 Timing SNF Extractor : 최적화된데이터에 timing data를포함하는 Timing Simulation File 생성 Assembler : Fitter의로직셀이나 pin등을해당 Device에대한 Programmer Object File(.pof) 나 SRAM Object File(.sof),.hex File 등을생성한다. 20

21 프로그래밍

22 GDF(Graphic Design File 예 ) 22

23 Simulation 결과예 23

24 TDF (Text Design File) 사용예 24

25 VHDL 사용예 library ieee; use ieee.std_logic_1164.all; entity test1 is port( a,b,c1,c0: in std_logic; and_out,or_out,xor_out : out std_logic); end test1; architecture sample of test1 is signal an : std_logic; signal cn : std_logic; begin an <= a and b; cn <= c1 or c0; and_out <= an; or_out <= cn; xor_out <= an xor cn; end sample; 25

MAX+plus II Getting Started - 무작정따라하기

MAX+plus II Getting Started - 무작정따라하기 무작정 따라하기 2001 10 4 / Version 20-2 0 MAX+plus II Digital, Schematic Capture MAX+plus II, IC, CPLD FPGA (Logic) ALTERA PLD FLEX10K Series EPF10K10QC208-4 MAX+plus II Project, Schematic, Design Compilation,