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1 Programmable Logic Device 설계특성 이재흥한밭대학교정보통신컴퓨터공학부

2 발표순서 1. PLD의개요및구조 2. CPLD/FPGA의구조 3. CPLD/FPGA 설계및검증방법 4. Embedded SW와 FPGA Design 질의 & 응답 2

3 ASIC vs PLD Standard ICs General-purpose processors, memory chips and other standard components ASIC(Application Specific IC) Semi-custom chip design Dedicated to single function, or limited range of functions A typical ASIC is a circuit, where functions are designed by the customer and layout and the fabrication is done by the silicon vendor Personalized at the factory PLD(Programmable Logic Device) Personalized at the client site (EE)PROM, PLA, PAL, CPLD/FPGA 3

4 What's the PLDs? CAD S/W를이용하여설계한회로를다운로드하여칩으로즉시제작가능한소자 PLD의구성요소 Configurable Logic Block Programmable Routing Switch Block Configurable Memory Block Input/Output Block PLD의장점 Fast Prototyping PLD PLD PLD Re-Programmable In-System Programmable Easy Transfer of Design Results HDL Text File Format Design Security in Chips 4

5 Classifications of PLDs SPLD(Simple PLD) PLA (Programmable Logic Array) PLA is a relatively small FPD that contains two levels of logic, an AND-plane and an OR-plane, where both levels are programmable PAL (Programmable Array Logic) PAL is a relatively small FPD that has a programmable AND-plane followed by a fixed OR-plane CPLD(Complex PLD) a more Complex PLD that consists of an arrangement of multiple SPLD-like blocks on a single chip. FPGA(Field-Programmable Gate Array) FPGA is an FPD featuring a general structure that allows very high logic capacity. 5

6 Basic Configuration of PLDs(I) 6

7 Basic Configuration of PLDs(II) PROM PLA PAL 7

8 Logic Allocation: PLA PAL: Requires 4 pt s! PLA: Requires only 3 pt s! A B C A B C Can NOT share common logic X Y X = A & B + C Y = A & B +!C X Y Indicates used junction Indicates unused junction Indicates fixed junction Common logic may be shared in CoolRunner-II 8

9 CPLD A CPLD comprises multiple PAL-like blocks on a single chip with programmable interconnect to connect the blocks. CPLD Architecture I/O block I/O block PAL-like block PAL-like block PAL-like block Programmable interconnect PAL-like block I/O block I/O block 9

10 FPGA FPGA consists of an array of programmable basic logic cells surrounded by programmable interconnect. FPGA Structure 10

11 FPGA Chip Architecture 프로그램회로 논리모듈 프로그램회로 I/O 패드스위치매트릭스 배선채널 프로그램회로 A1 A2 A3 A4 B1 B2 B3 B4 Look-Up Table Look-Up Table Look-Up Table clk clk F/F F/F O2 O1 O3 프로그램회로 FPGA 구조 SRAM 스위치소자 SRAM 5X5 배선스위치매트릭스 11

12 CPLD/FPGA Design Process Design Flow Design Specification Define I/O I/O Design Entry Functional Simulation Map, Place, Route Timing Simulation Download Debug 12

13 Mentor VHDL Simulator 13

14 Documentation for FPGA Design Design Specification Functional Spec., I/O Signal Spec., Test plan Define I/O 신호별세부기능에관한기술문서 Design Entry HDL(VHDL/VerilogHDL) design files Schematic diagram Functional Simulation Test vector 에대한기술문서 Simulation waveform 및분석결과문서 Map, Place, Route Timing Simulation 중간출력파일 - User constraints file Test vector 에대한기술문서 Timing simulation 분석결과문서 Report file 문서 Download JTAG file Board-level Test 보드레벨검증문서 14

15 CPLD/FPGA 설계문서화 CPLD/FPGA 설계및검증에관한문서화내용 CPLD/FPGA 설계방법및설계과정 설계환경 (HW, SW), 구체적인설계과정 CPLD/FPGA 디바이스및내부구조 디바이스선택의타당성검토문서 CPLD/FPGA 설계에대한검증방법론 설계에대한 Functional/Timing Simulation Simulation Waveform 및결과분석서 설계단계별중간생성자료 ( 파일 ) 분석서 User Constraints Files 검증에필요한테스트시나리오및테스트벡터집합 보드레벨검증문서 검증환경, 실측입출력신호파형, 검증결과분석서 15

16 ASIC/FPGA 구현을위한 CAD Tool 흐름도 RTL 회로설계 회로도추출및효율적 VHDL 표현 Functional Simulation 에의한회로검증 Gate Level 회로설계 면적, 속도,Power 를고려한 Design Constraints 설정 Design Library 의설정 FPGA, ASIC Component Delay 를고려한기능및 Timing Simulation 에의한회로검증 Physical Design 을위한 EDIF 파일생성 16

17 ASIC/FPGA 구현을위한 CAD Tool 흐름도 FPGA 를이용한 Physical Design FPGA Tool 에의한 Compile 수행 사용할 Device 및 Option 의설정 Layout Data 를이용한 Simulation Target Board 의구성과 Emulation 을통한검증 ASIC 으로의변환여부에따른대응 ASIC 설계를위한 Physical Design Design House 와연계및 EDIF 전달 Wire Delay 를함께고려한 Simulation Sign-off 와 ASIC 에대한기다림 Test Board 구성, 검증및평가 17

18 Logic Synthesis ( 논리합성 ) Synthesis = Translation+Optimization+Mapping module fa(sum,c_out,a,b); output sum,c_out; input c_in,a,b; Translate into Boolean Representation wire S0,S1,S2; xor(s0,a,b); and(s1,a,b); xor(sum,s0,c_in)... HDL Source code Optimize+Map Generic Boolean (GTECH) Synthesis Target Technology 18

19 Why HDL? HDL is for writing models of a system Growing complexity of designs Reasons for modeling Requirements specification Documentation Testing using simulation Formal verification Synthesis Goal Most reliable design process, with minimum cost and time Avoid design errors before fabrication 19

20 Verilog and VHDL Two Major HDLs Both are programming languages Text-based, easier to create a design over schematic entry/capture Verilog is Similar to C VHDL is closer to ADA Differences to regular programming languages Regular programming is inherently sequential HDLs have concurrency (parallel execution) and timing HDLs have constructs to describe hardware 20

21 GPL vs HDL Type of Input Tools Target (Output) General Programming Language Text file (.c,.cpp. cpp,,.java,.cs. cs) Compiler, Debugger Executable code (Binary) Hardware Description Language Text file (.vhd,.v,.sv. sv) Synthesizer(Silicon Compiler), Emulator, Logic analyzer Bit-Stream (Binary) Execution Sequential execution Parallel execution Reviewed material Verification methodology Source code Debugging No consideration for HW Source code, Waveform Simulation, Emulation, Probing, Co-Verification Controlled by Clock, Always think synthesized HW 21

22 Embedded SW vs FPGA Design Flow MicroBlaze code in off-chip memory Standard Embedded SW Development Flow C Code Compiler/Linker (Simulator) Object Code Debugger MicroBlaze code in Spartan-3 onchip memory Download to Board & FPGA? Embedded Development Kit Data2BlockRAM Bitstream Download to FPGA OPB GPIO OPB Arbiter OPB UART Standard FPGA HW Development Flow VHDL/Verilog Synthesizer Simulator Place & Route? 22

23 Hardware and Software Co-Design Approach to develop Traditional Systems Generic Hardware Software with Relaxed Resource HW and SW are separated designed. Approach to develop Embedded Systems SOFTWARE which is planned to run with resource constraints. HARDWARE which is optimized and specialized to run the software HW and SW are co-designed. Unified Design Process 23

성능향상 SoC (System On Chip) design 프로세서가포함된시스템보드를하나의칩으로구현

24 디지털시스템설계 TTL-based System design 여러종류의 TTL IC를이용한시스템보드설계 System design with FPGA/CPLD TTL IC 들을하나의 FPGA로집적화 면적, 성능향상 SoC (System On Chip) design 프로세서가포함된시스템보드를하나의칩으로구현 SoC 설계를위한 HW/SW Codesign, Cosimulation 및 Coverification 개념도입 24

25 SoC(System On Chip) Design Core Platform Memory Options Peripheral Options Design-Driven Auto- Generated Verification Environments HW Test Env SW Test Env CPU Core(s) DSP Core(s) USB & RS232 Multimedia Decryption Engine RTOS Kernel Flash Drivers Bluetooth USB SRAM MPEG4 Core Apps DRAM System Bluetooth MPEG4 Decoder User Designed HW/SW Coverification SW Programmers Model Emulation Live Target RTOS & Application Options Others... 25

26 질의 & 응답

MAX+plus II Getting Started - 무작정따라하기

MAX+plus II Getting Started - 무작정따라하기 무작정 따라하기 2001 10 4 / Version 20-2 0 MAX+plus II Digital, Schematic Capture MAX+plus II, IC, CPLD FPGA (Logic) ALTERA PLD FLEX10K Series EPF10K10QC208-4 MAX+plus II Project, Schematic, Design Compilation,