Microsoft PowerPoint - ICCAD_Digital_lec03.ppt [호환 모드]

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1 IC-CAD CAD 실험 Lecture 3 장재원

2 주문형반도체 (ASIC * ) 설계흐름도개요 Lecture 2 REVIEW ASIC Spec. Front-end design Logic design Logic synthesis Behavioral-level design Structural-level design Schematic editor *Analog 회로설계시 Transistor-level design Netlist FPGA 구현검증 Auto P&R layout Full-custom layout Back-end design Layout verification (LVS, DRC, ERC) Post-simulation Layout 설계 GDS file Fabrication & testing *ASIC(Application Specific Integrated Circuit)

3 Verilog HDL 코드예 : 4 비트카운터 module counter(rst, clk, load, enb, din, dout) ; input rst, clk, load, enb; input[3:0] din; output[3:0] dout; reg[3:0] tmp; always@(posedge clk or negedge rst) begin if (~rst) tmp <= 0; else if (load) tmp <= din; else if (~enb) tmp <= tmp + 1; end assign dout = tmp; endmodule Lecture 2 REVIEW

4 Verilog HDL 코드예 : 8 비트카운터 module counter(rst, clk, clr, direct, load, enb, din, dout) ; input rst, clk, load, enb, clr, direct; input[7:0] din; output[7:0] dout; reg[7:0] tmp; always@(posedge clk or negedge rst) begin if (~clr) tmp <= 0; if (~rst) tmp <= 0; else if (load) tmp <= din; else if (~enb) if(~direct) tmp <= tmp + 1; else tmp <= tmp - 1; end assign dout = tmp; endmodule Lecture 2 REVIEW

5 Synchronous & Asynchronous Synchronous Clock의동작에맞추어, positive clock일경우해당값에따라동작 clk) begin if (~rst) clk rst val tmp <= 0; reset reset Asynchronous Clock 에상관없이값이변하면바로동작 clk or negedge rst) begin if (~rst) tmp <= 0; rst) begin tmp <= 0;

6 Verilog HDL 코드예 : 테스트벤치 Lecture 2 REVIEW `timescale 1 ns/1 ns module tb_cnt ; reg rst, clk, load, enb; reg[3:0] din; wire[3:0] dout; counter cnt(rst, clk, load, enb, din, dout); initial begin clk = 0; forever #50 clk = ~clk; end #5000 load = 1; din = 4'b1101; #500 load = 0; #500 enb = 1; #500 enb = 0; end endmodule initial begin rst = 0; load = 0; din = 4'b0; 4b0; enb = 1; #1001 rst = 1; #1000 enb = 0;

7 Verilog HDL 코드예 : 테스트벤치 Lecture 2 REVIEW `timescale 1 ns/1 ns module tb_cnt ; reg rst, clk, load, enb, clk, direct; reg[7:0] din; wire[7:0] dout; counter cnt(rst, clk, clr, direct, load, enb, din, dout); initial begin clk = 0; forever #50 clk = ~clk; end initial begin rst = 0; load = 0; din = 8'b0; 8b0; enb = 1; direct = 0; clr = 1; #1001 rst = 1; #1000 enb = 0; #5000 load = 1; din = 8'b ; #500 load = 0; #500 enb = 1; direct = 1; #500 enb = 0; #1050 clr = 0; end endmodule

8 do 파일 vlog.do vlog ~/hdl_design/source/counter.v design/source/counter vlog ~/hdl_design/source/tb_cnt.v Testbench Counter vsim -c tb_cnt -wlf /home2/commasic/asic_course/train20/hdl_design/results/sim/tbwav e.wlf log -r * run ns quit wav.do vsim -view /home2/commasic/asic_course/train20/hdl_design/results/sim/tbwave. wlf add wave * add wave /cnt/tmp

9 HDL 시뮬레이터 (Modelsim) 사용 Lecture 2 REVIEW vlib : 라이브러리디렉토리의생성 vlib 경로 / 작업디렉토리명 vmap : 작업디렉토리에대한환경설정 vmap 라이브러리명경로 / 작업디렉토리명 log[-r] * : 시뮬레이션결과파형에지정된신호의파형을실어주는역할 [-r] 옵션을사용하면테스트벤치 & 내부모듈의신호까지포함됨 log 인스턴스명 / 신호명 log /T1/S1/test vlog : Verilog HDL 파일의컴파일 vlog [-work 라이브러리명 ] 경로 /verilog 파일 run [ 시뮬레이션시간 ] : 기록한시간동안시뮬레이션실행 vsim : HDL 시뮬레이터의명령수행 옵션 : -c, -do do 파일, -L 라이브러리명, - sdf{min typ max}, -wlf 경로 /wave 파일, -view 경로 /wave파일 add wave * : 테스트벤치에있는모든신호의파형을보여주는명령 add wave /T1/* vsim c do sim.do quit : 시뮬레이터의종료

10 논리회로합성 Synthesis 상위수준코드로부터게이트수준네트리스트를생성하는절차 Oti Optimizei 기능, 속도, 면적요건을만족하기위해라이브러리셀을이용하여최적의회로를만드는합성과정상의한단계 Compile 최적화를수행하는명령으로이를수행하기위해서는일단디자인을읽어들인후필요한작업들을처리한후컴파일러명령을수행한다. 그러면게이트수준네트리스트 (netlist) 가생성된다

11 Design Compiler 를이용한 synthesis 과정 < 참고자료 > Design Compiler User Guide

12 디자인읽기 analyze Reads an HDL source file Checks it for errors (without building generic logic for the design) Creates HDL library objects in an HDL-independent intermediate format Stores the intermediate files in a location you define elaborate Translates the design into a technology-independent design (GTECH) from the intermediate files produced during analysis Allows changing of parameter values defined in the source code Allows VHDL architecture selection Replaces the HDL arithmetic operators in the code with DesignWare components Automatically executes the link command, which resolves design references read Reads several different formats Performs the same operations as analyze and elaborate in a single step Creates.mr and.st intermediate files for VHDL Does not execute the link command automatically Does not create any intermediate files for Verilog (However, you can have the read_file command create intermediate files by setting the hdlin_auto_save_templates templates variable to true)

13 설계제약조건설정 operating conditions wire loads I/O port requirements timing constraints area constraints design rule constraints set_drive set_operating_conditions set_load set_driving_cell set_wire_load set_fanout_load

14 Operating Conditions set_operating_conditions dc_shell> set_operating_conditions WCCOM -lib class dc_shell> report_lib class

15 Wire Loads top (default 설정 ) top 레벨에서정의된 wire load 모델을모두사용 enclosed 배선을완전히포함하는가장작은디자인의 wire load 모델사용 segmented 세그먼트를둘러싸는디자인의 wire load 모델사용 50X50 20X20 mode = enclosed 30X30 20X20 50X50 30X30 50X50 mode = top 50X50 mode = segmented 20X20 30X30 20X20 30X30 50X50 20X20 50X50 30X30

16 I/O port Requirements set_drive 공정라이브러리의셀로입력포트구동능력이기술될수없을때최상위레벨포트의구동저항을정해준다 set_driving_cell 공정라이브러리의셀로만들어진포트의구동특성을나타내기위해사용한다 set_load 입력과출력포트에서의캐패시턴스값을정한다 set_fanout_load 출력포트의팬아웃을결정 set_driving_cell top_level_design set_drive U1 U2 External System PAD PAD I1 I2 logic IV AN2 I3 I4 sub_design sub_design

17 Timing Constraints create_clock dc_shell> create_clock clock -period 50 -waveform {0 30} CLK set_clock_skew dc_shell> set_clock_skew -plus_uncertainty 0.2 -minus_uncertainty 0.2 {CLK} set_input_delay dc_shell>set_input_delay 20 -clock CLK {DATA_IN} set_output_delay dc_shell> set_output_delay 15 -clock CLK {DATA_OUT}

18 Area Constraints set_max_area dc_shell> set_max_area 100 타이밍과면적제약조건을모두설정되어있으면컴파일할때타이밍이우 선적으로고려

19 Design Rule Constraints set_max_transition 명시된포트에연결되어있는배선이나디자인의모든배선의최대천이시간을설정 set_max_fanout 허용가능한최대의팬아웃 (fanout) 을설정 set_max_capacitance set_max_transition ii 은실제적인배선의캐패시턴스를제한하지는않으므로, 이를위해서 max_capacitance 설정

20 Multiple Instance 의 Resolve uniquify 각각의 instance 를복사한다 uniquify 를하면중복되어사용되는 instance 가복사되어생성 각각을특성화할경우사용 ungroup 계층구조를없애고하나의이름으로모든셀에대해최적화를한다 각각을특성화하지않을경우 ungroup 명령을실행후컴파일 set_dont_touch 각서브디자인을재합성할때변경하지않으려면각서브디자인을컴파일한후 set_dont_touch 명령사용

21 디자인옵션 map effort : medium verify design : low allow boundary optimization : yes TOP LEVEL TOP LEVEL Block1 Block2 Block1 Block2 X A B L O G I C X A B L O G I C

22 실험내용 Page 53~63

23 리포트및공지사항 리포트제출 P63~64 의실험과제및프로젝트 수정사항 : P64 모듈 1 의클럭주파수 : 100 Mhz(10ns) 2 장에서작성한 verilog 코드가합성이안되면코드를수정할것 옵션조절로주어진 spec. 을만족시키지못하면 verilog 코드를수정하여 spec. 을맞추도록노력할것 코드를수정했다면, 수정한코드를첨부하고수정사항및개선사항에대한고찰을작성할것 리포트의종이인쇄본을제출할것 제출기한 : 다음수업시작전까지 조교 ( 장재원 ) 주소 jaera82@soc.yonsei.ac.kr