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1 Verilog: Finite State Machines CSED311 Lab03 Joonsung Kim,

2 Finite State Machines Digital system design 시간에배운것과같습니다. Moore / Mealy machines Verilog 를이용해서어떻게구현할까? 2

3 Finite State Machines Moore machine Output: function of Current state Larger # of states Safe (= synchronous) Current state가변할때만 output이바뀐다. == 즉! Clock이변할때만 (triggered) output이바뀐다. Input Previous state Output Next state logic (combinational) Current state Output logic (combinational) 3

4 Finite State Machines Mealy machine Input Output: function of Current state & input Smaller # of states Unsafe (= asynchronous) Input 값이변하게되면 (asynchronous) => 즉시 ouput 의값이바뀐다. Previous state Output Next state logic (combinational) Current state Output logic (combinational) 4

5 Finite State Machine: example Example: Reduce 1 s 주어진 0,1 로이루어진일련의숫자에대해서, 연속된 1 들중첫번째 1 을 0 으로바꿔준다. Examples: > > > Verilog 를이용해서구현해봅시다! 5

6 Finite State Machine: example Designing a FSM Moore Mealy If in 0s -> output: 0 If first 1 encounter -> output: 0 If in 1s -> output: 1 6 If input 0, current 0 -> output: 0 If input 1, current 0 -> output: 0 If input 0, current 1 -> output: 0 If input 1, current 1 -> output: 1

7 Finite State Machine: example Setup template Moore // pre-define states Parameter zero=0, one1=1, two1s=2; Think of it as enum in C Const 선언하는것과비슷 Mealy // pre-define states Parameter zero=0, one=1; // start of my module module reducer (clk, reset, in, out); // start of my module module reducer (clk, reset, in, out); Input clk, reset, in; // input Input clk, reset, in; // input Reg out; // output Reg [1:0] state // currentstate Reg [1:0] state_next; // nextstate Reg out; // output Reg state // currentstate Reg state_next; // nextstate state 3 개 => 2bits register State 2 개 => 1bit register 7

8 Finite State Machine: example always 블락을이용해서 state 변화를표현한다. Moore Mealy clk) if (reset) state <= zero; else state <= state_next; clk) if (reset) state <= zero; else state <= state_next; Reset 되면, state 를 zero 로셋팅한다. 이 block 은 clock 의 Positive edge 에서 trigger 된다. 다른경우에는 next state 로옮긴다. 8

9 Finite State Machine: example always 블락을이용해서 state 변화를표현한다. Moore or state) case (state) zero: out = 0; if (in == 1) state_next = one1; else one1: out = 0; if (in == 1) state_next = two1s; else out" and in 는다름 default: out = 0; Default case case in 이나 state 이변할때, trigger 9 or state) case (state) zero: out = 0; Mealy if (in == 1) state_next = one; else one: if (in == 1) state_next = one; out = 1; else case

10 Finite State Machine: example Mealy machine 의 asynchronous 문제해결방법 Output buffering!!! Output 이 posedge clk 때까지바뀌지않는다. Buffer 된 output 을 synchronous 하게변화시킨다! clk) if (reset) state <= zero; out <= 0; else state <= state_next; out <= out_next; 10 or state) case (state) zero: out_next = 0; if (in == 1) state_next = one; else one: if (in == 1) state_next = one; out_next = 1; else case

11 Finite State Machine: tips Always block 을목적에따라서잘분할하세요 하나의 always block 에전부때려박는건. 안됩니다. // Always block for everything! clk) // if state is ~ and input is ~ do sth // else if state is ~ and input is ~ do sth Too complex to understand and debug! (next output,state,logic ) 11

12 Finite State Machine: tips Always block 을목적에따라서잘분할하세요 쓰이는목적에맞게잘나누세요 // Always block for synchronous state update clk) // State <= Next state // Always block for next state logic or input change) // If (state & input) next state <= something // else if(state & input) next state <= something else // Always block for synchronous output update clk) // output <= Next output // Always block for next output logic (moore) // If (state) next output <= something // else if(state) next output <= something else Easier to track output, state, etc 12

13 Finite State Machine: tips Always block 을목적에따라서잘분할하세요 하나의 register 를다른 always block 에서 update 하시면안됩니다. 1) // my register <= blah blah blah 2) // my register <= blah blah blah 2 ILLEGAL 1 or condition 2) // if(1) my register <= blah blah blah // elif(2) my register <= blah blah blah 2 OK 13

Microsoft PowerPoint - hw4.ppt [호환 모드]

Microsoft PowerPoint - hw4.ppt [호환 모드] 4.1 initial 과 always Chapter 4 Verilog의특징 보통의 programming언어와같은 procedural statement을제공 추상적인 behavioral model 기술에사용 순차적으로수행하는보통의 programming 언어와는다르게병렬적으로수행하는언어임 module Behavioral Model 논리설계 병렬수행 module