PowerPoint 프레젠테이션

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1 1 파워 IC 설계기술 박시홍 단국대학교전자전기공학부

2 목차 2 - 파워 IC 설계주의사항. 동부하이텍 BD350 BCD 공정기준 - Power IC Design Examples. 24V/3A Synchronous Buck Converter. 40V/1A Antenna Driver

Power IC Core Technology 3 핵심기술 집적회로설계기술

18um 고전압 BCDMOS 공정최적화 Low RDS(ON) 정전기보호및래치업방지

3 Power IC Core Technology 3 핵심기술 집적회로설계기술 Analog/Digital/Power 혼성모드설계 High Speed OP Amps 고전압 / 고전류구동기술 AD/DA, MCU BCD 공정기술 Clock Control Logic Vin 파워 IC 0.35/0.18um 고전압 BCDMOS 공정최적화 Low RDS(ON) 정전기보호및래치업방지 파워컨버터설계기술 고효율 Buck, Boost, Charge Pump 고주파수구동컨버터 New Topology 시스템응용및평가기술 파워 IC 응용기술 모바일 / 디스플레이 / 자동차시스템응용기술 실장적용및평가기술

4 파워 IC 설계주의사항 4

5 5 고전압공정의난제들 소자별 / 단자별내압에대한자동체크기능이없다. 고전압공정은 Epi 층이두껍고농도가낮아기생소자가동작하기쉽다. 기생소자에대한모델링이없다. 일부소자는모델링이없거나정확하지않다. 출력단고전류스위칭노이즈의영향이크다. 공정이해를통한최적의 Layout이반드시필요하다. (Latch-up/Noise/ 효율감소 ) SOI Process - 기생소자의영향이없다. - 생산원가가높다. - 열방출능력이낮다.

6 대표적인 Power IC 용 BCD 공정 6 동부 BD350BA 0.35um 공정 - P-Epi process - 3.3V, 8V CMOS and Isolated CMOS - 12V ~ 60V DECMOS - 8V ~ 60V High-side and Low-side NLDMOS with low Vgs option - 6V ~ 36V PLDMOS with low Vgs option - Bipolar NPNs & lateral PNPs - well & poly resistors (optional high sheet poly resistor) - well-poly/poly-metal/mim/pip capacitors - zener diode & HV diode - SCR for ESD - Optional Poly fuse

7 BCD 공정소자별주의사항 7 적합한소자의선택및사용 - 소자의내압 - Vds, Vgs, Vbs 내압 Diode - Zener Diode - Power Diode LDMOS & 기생소자 - Parasitic NPN, PNP - Parasitic Diode - Parasitic Capacitor - PDK 에서제공되지않는메뉴얼확인사항임 - 경험에의존한설계

8 적합한소자의선택및사용 8 LDO Example 사용가능한소자의종류 Vin = V - Low voltage CMOS - High voltage DE-CMOS (Low Vgs) Vbg Q5 Q3 Q6 Q4 Q8 Q9 Q10 Q11 R1 Vreg (5.0V) - PLDMOS, NLDMOS - Isolated CMOS - Zener Diode Manual Check Point VB R2 - VGS (voltage limit) - VDS (proper component) Q1 Q2 Q7 - VBS (different layout) - Zener 내압 - Capacitor 내압

9 Zener Diode 9 Vin = V P+ R N-BL Vz (5.9V) Internal Blocks Buried Zener P+ Voltage Reference Input Voltage Clamp VGS Clamp Zener Diode 용도 - Simple Voltage Reference - Voltage Clamp - Automotive IC에많이사용됨 Surface Zener Integrated Zener Diode - Surface zener (Low current capability, Zener Voltage Drift) - Buried zener (High current capability, 1 option layer +)

10 Power Diode 10 L Vin Vin Vout Vout D N-Well P+ P+ P+ N-WELL N-BL HV Power Diode Power Diode - 고내압 / 저전류용으로사용 - 대전류컨버터용으로는사용불가 ( 효율감소및 Latch-up 발생 ) - 정전기보호다이오드로사용

11 Parasitic structure of Low-side NLDMOS High-Side VDC P+ LOW Low-Side Iout Turn-off Adjacent N- well Iout Iout Adjacent N- well 0.3V Rds,on 기생 Diode 모델 기생 NPN 모델 - Forward 동작에는기생소자동작없음 - Dead time 동안기생 NPN 에의한 Noise 및 Latch-up 위험 - Reverse 동작시기생 NPN 동작억제조건 : Rds,on Iout < 0.3V - Dead time 최소화설계필요 (Shoot-through 방지를위한최소 Dead time 필요 )

12 Parasitic structure of Low-side NLDMOS WB (Base Width) P+ P+ DEEP-P DEEP-P N-WELL 기생 NPN 동작억제를위한 Layout Base 농도 - 기생 NPN 동작억제를위한충분한거리확보가필요 (WB 증가에따른 β 감소, 거리별 β 값 Foundry 제공필요 ) - P-Well Guard Ring 도제한적효과있음 (Base 농도증가에따른 β 감소 )

13 Parasitic structure of High-side NLDMOS 13 VDD P+ Repi N-BL Iout L GND GND P+ P+ P+ - Forward 동작시에는기생소자동작없음 - Dead time 구간 Reverse 동작시기생 PNP 동작 Latch-up 방지를위한 Layout - 기생동작억제를위한조건 : Rds,on Iout < 0.3 V - Power Diode 와같은기생 PNP 형성 (N-BL Layer 반드시필요 ) - 기생 PNP에의한 Noise 및 Latch-up 위험 - SUB 전압상승을방지하는 GND Guard Ring 필요 N-BL

14 High-side vs. Low-side NLDMOS 14 VDD P+ P+ P+ Repi N-BL Iout L Iout Adjacent N-well DEEP-P P+ P+ DEEP-P N-WELL - High-side LDMOS는기생 PNP를억제하는 N-BL 필요 (Base 농도 ) - Low-side LDMOS를 High-side에사용할경우 : Reverse 동작시 Latch-up 발생가능성매우높음 (N-BL이없는공정 ) - High-side LDMOS를 Low-side에사용할경우 Reverse 동작시 N-BL에의해서기생 NPN β가증가함 (Emitter Injection Efficiency )

15 Parasitic structure of PLDMOS 15 VDD P+ P+ P+ P+ Repi N-WELL DEEP-P N-BL L Iout P+ P+ P+ P+ P+ P+ N-WELL DEEP-P N-BL Latch-up 방지를위한 Layout - Forward 동작시기생동작은없으며모든기생동작은 Reverse 동작시발생 - 보통의경우 을 Source 에연결하여사용 - Power Diode 와같은기생 PNP 형성 (Noise 및 Latch-up 위험 ) - SUB 전압상승을방지하는 GND Guard Ring 필요 - 을 Source 보다높은전위에연결할경우기생 NPN 동작

16 Parasitic structure of ISO-DENMOS 16 VIN P+ N-WELL N-BL ISO-DECMOS - Forward 동작시기생동작은없으며모든기생동작은 Reverse 동작시발생 - 기생동작억제설계조건 : Rds,on Iout < 0.3 V - 보통의경우 을가장높은전위에연결 ( 기생 NPN 동작 ) - 을 N-WELL(Drain) 에연결할경우 High-side LDMOS와동일기생동작 ( 기생 PNP에의한 Noise 및 Latch-up 위험 GND Guard Ring 필요 )

17 Synchronous Buck Converter 17 DB 40V P+ INH Level Shift CB SH N-BL L High-side LDMOS (SH) 5V INL SL C P+ Low-side LDMOS (SL) - Dead time 동안인덕터전류방향에따라기생 NPN/PNP 동작 : Dead time 최소화필요 - Bootstrap Diode 도기생 PNP 동작 - 기생동작을고려한 Layout 반드시요구됨 (Noise/Latch-up 발생위험, 효율감소 )

18 Synchronous Boost Converter 18 L SH VIN SL C P+ P+ N-BL Low-side LDMOS (SL) High-side LDMOS (SH) - SH 항상 Forward 동작 기생동작없음 - Dead time 동안 SH 기생 PNP 동작 : Dead time 최소화필요 - SH의기생동작을고려한 Layout 반드시요구됨 (High-side LDMOS와동일조건 ) - 기생 PNP 동작에따른 Noise/Latch-up 발생위험및효율감소 - SH용 Bootstrap Diode도기생 PNP 동작

19 Synchronous Buck-Boost Converter with LDMOS 19 SH SL VIN L C VOUT P+ P+ P+ P+ P+ N-WELL DEEP-P N-BL N-BL PLDMOS (SH) High-side LDMOS (SL) - SH 항상 Forward 동작 기생동작없음 - Dead time 동안 SL 기생 PNP 동작 : Dead time 최소화필요 - 기생동작에의해서인덕터전류의출력전달률감소 ( 최대구동전류감소 ) - 기생동작을고려한 Layout 반드시요구됨 (Noise/Latch-up 발생위험, 효율감소 )

20 Synchronous Buck-Boost Converter with ISO-DECMOS 20 VIN SH SL VIN L C VOUT P+ N-WELL N-BL ISO-DECMOS (SL) - SH 항상 Forward 동작 기생동작없음 - Dead time 동안 SL 기생 NPN 동작 : Dead time 최소화필요 - 기생동작에의해서인덕터전류의출력전달률감소 ( 최대구동전류감소 / 효율감소 ) - 기생동작에의한효율은감소하나 Latch-up 은없음

21 Parasitic Diode Junction Capacitor of LDMOS 21 Vbst = Vin + 5V Vin = 40V out Cj*dv/dt qb Idrv Idrv q - Idrv is a small current to reduce Pd - Retrigger problem due to diode junction capacitor - Careful design of level shift circuit required

22 Synchronous Rectification (Active Rectification) 22 VDC VDC VDC VAC VAC VAC Low voltage CMOS (VDC < 8) Medium voltage PLDMOS + NLDMOS (VDC < 12-20V) High voltage NLDMOS (VDC > 20V) - All transistors operate under a reverse mode (minimum dead time control and proper layout required) - Poor performance and severe parasitic effect of integrated diodes - Hard to make an integrated bridge diode rectifier without using SOI process - Synchronous rectification increases the efficiency but hard to realize when VDC is high

23 23 파워 IC 설계예

24 24. 24V/3A Synchronous Buck Converter. 40V/1A Antenna Driver

LDMOS - No active devices near low-side LDMOS - GND guard ring for

25 24V/3A Synchronous Buck Converter 25 DB 40V INH Level Shift CB SH L 5V INL SL C DB - High-side LDMOS prevents the parasitic NPN operation of low-side LDMOS - No active devices near low-side LDMOS - GND guard ring for high-side LDMOS and Bootstrap diode High-side LDMOS Low-side LDMOS No active devices

Sense Driver RS - 40V/1A antenna driver (6 channels) - 125Khz

26 40V/1A Antenna Driver 26 Boost Converter Sine Wave Generator Class AB Driver Antenna Current Command Control Peak Current Sense Driver RS - 40V/1A antenna driver (6 channels) - 125Khz sine wave driver for low EMI - Adaptive boost voltage control for low Pd

27 40V/1A Antenna Driver 27 Boost Converter Sine Wave Generator Class AB Driver LDMOS Antenna Current Command Control Peak Current Sense Driver RS - 3V Additional distance & P+ guard ring - - 3V minimum return driver output (severe parasitic NPN operation) - Additional distance and P+ guard ring to minimize parasitic NPN action

28 40V/1A Antenna Driver 28 P+ P+ P+ SINK SINK Isolated LDMOS N-BL Isolated LDMOS Thick epi BCD Process - NO parasitic NPN action with isolated LDMOS - Chip size reduced but thicker epi and 2 more optional masks required - Both ICs work fine. Standard BCD Process + additional distance

Microsoft PowerPoint - ch03ysk2012.ppt [호환 모드]

Microsoft PowerPoint - ch03ysk2012.ppt [호환 모드] 전자회로 Ch3 iode Models and Circuits 김영석 충북대학교전자정보대학 2012.3.1 Email: kimys@cbu.ac.kr k Ch3-1 Ch3 iode Models and Circuits 3.1 Ideal iode 3.2 PN Junction as a iode 3.4 Large Signal and Small-Signal Operation