17(3)-1(10-35)p.1-9.fm

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1 Journal of the Microelectronics & Packaging Society Vol. 17, No. 3, p 특집 : 무연솔더의신뢰성평가표준화 플립칩패키지 BGA 의전단강도시험법표준화 안지혁 김광석 이영철 김용일 정승부 Regulation in Shear Test Method for BGA of Flip-chip Packages Jee-Hyuk Ahn, Kwang-Seok Kim, Young-Chul Lee, Yongil Kim and Seung-Boo Jung Abstract: We reported the methodology for the shear test which is one of the evaluation procedure for mechanical reliability of flip-chip package. The shear speed and the tip height are found to be two significant experimental parameters in the shear test. We investigated how these two parameters have an influence on the results, the shear strength and failure mode. In order to prove these experimental inconsistency, simulation using finite element analysis was also conducted to calculate the shear strength and to figure out the distribution of plastic energy inside of the solder ball. The shear strength decreased while the tip height increased or the shear speed decreased. A variation in shear strength due to inconsistent shear conditions made confusion on analyzing experimental results. As a result, it was strongly needed to standardize the shear test method. 1. 서론 IT 산업이발전하면서컴퓨터, 핸드폰, PDA, 노트북등여러가지전자제품의빠른신호처리를위한반도체칩의개발과동시에칩과칩, 그리고칩과기판간의빠른신호전달을위한전자패키징기술들이개발되고있다. 1-5) 그중대표적인전자패키징시스템구성기술인 SiP (System in Package), PoP(Package on Package) 와같은 3D 패키지기술은 Embedding 및 TSV(Through Silicon Via) 와같은요소기술로서미세패턴제작의물리적한계와실장되는소자의수가많아지면서생기는신호의지연을부분적으로극복할수있게해주었다. 1-7) 또한플립칩패키지기술은 low inductance 및 area array 가가능하므로경 박 단 소를지향하는전자제품의핵심적인패키징기술로인식되고있다. 플립칩패키지는칩에형성된 I/O 단자가기판을서로마주보게하고단자와기판을솔더범프로접합한패키징방식을말하는데, 기존의와이어본딩법에비해패키지의크기를훨씬줄일수있고전기적특성이더우수하며, 신뢰성측면에서도매우견고하다고알려져있어 3D 패키지기술에많이적용되고있다. 8) 그러나다양한수동및능동부품들이사용된다기능패키지제작시각부품들의생산비용의증가는물론테스트및 rework 에대한비용또한증가하므로, 차단계생산공정진행여부를결정하기위한각부품에대하여더욱높은신뢰성이요구되고있는실정이다. 한편대표적인솔더범프용재료인 Sn-Pb 계솔더는가격이싸고, 우수한 solderability 를가지고있기때문에산 업전반에널리사용되어왔다. 그러나유해물질제한지침 (RoHS : Restriction of Hazardous Substances Directive) 이 2006년 7월 EU에서발효되면서, 모든전기 전자제품을사용할수없게되었다. 이에따라 Sn-Pb계솔더의대안으로 Sn-Ag계솔더, Sn-Ag-Cu계솔더, Sn-Bi계솔더등여러종류의무연솔더들이개발되어생산현장에서사용되고있다. 3) 이에따라무연솔더합금에대하여기계적인특성평가는물론 EM(Electro-migration) 이나 ECM (Electro-chemical Migration) 등과같은다양한특성평가가진행되고있다. 특히기계적인특성평가방법의경우, 전자패키지의구조상 IC칩과기판간의열팽창계수차이로인하여계면에서발생하는전단응력이발생한다. 따라서일반적인재료의대표적인기계적인특성평가방법인인장강도 (tensile strength) 특성과는다르게전자부품에서는전단강도 (shear strength) 가강조되고있고, 전자부품에서는 ball shear test 법으로정의되고있다. 8,12) Table 1은 ( 사 ) 한국마이크로전자및패키징학회에서 2009년에제시한전자패키지기술의 Road map자료이다. 여기서알수있듯이플립칩패키지전극의 pitch는감소하므로 interconnection 으로사용되는 ball size도종래의 750 µm-200 µm까지의크기로부터약 20 µm정도까지감소할것을예측할수있다. 동시에전자패키지가더욱고밀도화되면서면적당방출되는패키지로부터의열방출은더욱증가되므로더욱신뢰성이높은다양한물성의 DB가필요하다. 전자부품의 BGA Ball평가에자주이용되는전단시험법은미국재료시험학회 (ASTM : American Society for Corresponding author sbjung@skku.ac.kr 1

2 2 안지혁 김광석 이영철 김용일 정승부 Table 1. Flip-chip bonding technology roadmap.1) Max. pad number Min. Pad Pitch [µm] Min. Chip thickness [µm] Min. Bump diameter [µm] Min. Bump height [µm] Pad Fig. 1. A schematic view of shear test. Testing Council)에 의해 처음 규격이 발표되었고, 2001년 국제 반도체기구 표준 협의기구(JEDEC : Joint Electron Device Engineering Council)에 의해 규격이 더욱 보완되 어 제정되었다. 그 중 JESD22-B117A 에서는 solder ball shear test의 규격에 대해 설명하고 있다. Fig. 1에 JEDEC 규격의 전단시험 모식도를 나타내었다. 그 이후 Table 2 에서 알 수 있듯이 2006년에 평가법의 일부가 개정되어 전단속도와 전단높이에 대한 새로운 항목의 규정이 추가 되었다. 2006년 이전에는 전단속도에 대한 규정 항목이 없었으나, 현재는 Table 2와 같이 low speed shear test 와 high speed shear test 로 구분하여 그 속도의 범위를 규정 하고 있다. 그리고 전단높이의 경우에는 Table 2에서 알 수 있듯이 솔더볼 높이의 25 % 이하, 50 µm높이 이상에서 전단시험을 하도록 규정되어 있었으나, 이와 같이 실험 할 경우 크기 200 µm이하의 솔더볼의 전단시험은 어려웠다. 따라서 2006년 이후에 전체 솔더볼 크기의 25%미만, 10% 권장으로 측정 방법의 항목이 개정 되었다. Fig. 2와 3에 몇 종류의 전문 국제학술지(ScienceDirect, IEEE, SpringerLink 등)에서 2006년부터 현재까지 발표 된 연구논문을 조사하여, 전단강도의 시험평가 기준의 통 계분포도를 전단속도와 전단높이로 구분하여 나타내었 다. 위 결과로 2006년에 ball shear test 규격이 정해졌음에 마이크로전자 및 패키징학회지 제17권 제3호 (2010) Fig. 2. Statistics of the shear speed in recent researches from ScienceDirect & IEEE & SpringerLink ( ): (a) low speed shear test, (b) high speed shear test.14-92) 도 불구하고, 전단시험의 일관성 없는 연구가 최근까지 계속 진행되어 왔다는 것을 알 수 있다. 정확한 규칙과 시험표준화 없이 구해진 전단강도 특성 평가의 신뢰도는 매우 낮고, 이런 결과 들은 마이크로 패 키지 된 전자부품에 많은 문제를 발생시킬 수 있다. 그리 고 표준화된 규칙과 평가방법으로 전단강도 값을 구해야

3 플립칩패키지 BGA 의전단강도시험법표준화 3 Fig. 3. Statistics of the shear height in recent researches from ScienceDirect & IEEE & SpringerLink ( ) ) Fig. 4. Shear force distributions with increasing shear speed. 4) Table 2. The regulation for shear test in JEDEC standard. 9) Before 2006 The edge of the probe nearest the module surface should be no further from the surface than 1/4 the ball height, which equals 1/2 the solder ball center line to substrate distance. The probe should not contact the module surface and should be no closer to the module surface than 0.05 mm. After 2006 The shear tool standoff should be no greater than 25 % (10 % preferred) of the solder ball height, and ensure that the shear tool does not contact the device surface throughout the monitored shear tool travel distance. The same shear speed should be used for all comparative testing because shear force and failure modes are sensitivity to shear speed. Shear speed divides into two classes; low speed shear testing is typically conducted at speeds ranging from 100~ 0 µm/s, and hight speed shear testing is usually performed at speeds ranging from 10 mm/s ~ 1 m/s. 만타연구자의연구결과와정확한비교가가능하다. 따라서본고에서는이러한전단시험의평가기준에따라서발생할수있는문제를직접실험과유한요소해석 (finite element analysis) 을이용한전산모사의간접적인결과를통해비교 검토하고새로운전단시험의표준화규격의필요성에대해서보고하고자한다. 2. 전단속도에따른전단강도의영향 2.1. Low speed shear test JEDEC 규격에서는 shear speed 조건을 low speed shear test 와 high speed shear test 로분류해서구별하고있다. 그중 low speed shear test 는대개 100~0 µm/s 의속도로전단시험을시행하는것을말한다. 일반적으로 ball shear test 에서전단속도가빠를수록전단강도값이증가하게되는데, 이러한전단강도의변화는전단시험중에솔더의 Fig. 5. Shear force-displacement curves with various shear speed. 5) 가공경화와크립특성에기인한것으로알려져있다. 4) Fig. 4 는 Sn-3.5Ag 조성의 500 µm 솔더볼과 ENIG 처리된 Cu 패드를리플로우공정을 1 회진행하여접합한후, 10~700 µm/s 의전단속도로전단시험을한결과와유한요소해석을이용한전산모사결과를나타냈다. 그래프에서알수있듯이전단속도가빨라질수록전단강도값은실험값과전산모사값모두증가하는것을확인할수있다. 전단속도가 70 배증가할때전단강도는 35% 가까이증가한다. Fig. 5 는 Cu/Ti 층에 Cu UBM 층을형성하고, 그위에전해도금과리플로우공정을통해지름 50 µm 크기의 Sn-2.5Ag 조성의솔더볼을형성한후, 각각 10, 100, 1000 µm/s 의전단속도로전단시험을한결과이다. 이결과로전단속도가빨라질수록전단강도값이최대 33% 가까이증가함을알수있다. 500 µm 크기의비교적큰솔더볼과 50 µm 크기의비교적작은솔더볼이전단속도에따라 30% 이상의전단강도차이를보일수있다는결과는, 솔더볼의크기와상관없이전단속도가시험결과에큰영향을미친다는것을알려준다. 즉, 1 회리플로우한뒤전단시험을할때, 전단 J. Microelectron. Packag. Soc. Vol. 17, No. 3 (2010)

4 4 안지혁 김광석 이영철 김용일 정승부 전단강도가 증가하지만, 전단속도가 빨라지면 충격량이 더 커지기 때문에 솔더 내부에서 발생하는 연성파괴 보 다 솔더 접합부에서 일어나는 취성파괴가 더 많이 발생 하게 됨에 따라 전단강도가 증가하게 된다.5) 결과적으로 High speed shear test에서도 low speed shear test와 마찬가 지로 전단속도에 따라 전단강도가 크게 변할 수 있으므 로, 전단속도를 명확히 규격화 하여 전단시험 결과의 신 뢰도를 높여야한다 유한요소 해석을 통해 전단강도 값의 검토 Fig. 6. Shear force variation with shear speed ranged from 0.01 to 1 m/s.6) 속도에 따라서 30%이상 전단강도 값의 차이는 열충격시 험(thermal shock) 및 고온방치실험(high temperature storage test)과 같은 신뢰성 시험 이후에는 더욱 큰 오차 가 발생 할 것으로 예측해 볼 수 있다 High speed shear test High speed shear test는 10 ~ 1000 mm/s의 속도로 전단 시험을 진행하는 것으로, 그 이상의 속도에서 실시하여 도 무관하다고 JEDEC 규격에 명시되어 있다. 위 시험법 은 low speed shear test에 비해 매우 빠른 속도로 전단시 험을 진행하기 때문에 솔더볼에 큰 충격을 가하므로, drop test를 보완할 수 있는 시험법이라고 알려져 있다.6,13) Fig. 6는 Sn-3.0Ag-0.5Cu 조성의 500 µm 솔더볼과 ENIG처리한 Cu패드를 리플로우 공정을 1회 진행하여 접 합한 후 0.01, 0.1, 1 m/s의 속도로 전단시험을 진행한 결 과이다. 이 결과에서 전단속도가 100배 상승할 때, 30% 가까이 전단속도가 증가하는 것을 알 수 있다. 전단속도 가 낮을 때는 솔더볼의 소성변형에 대한 저항성 때문에 앞의 Table 1에서 보여주듯이 패키지의 밀도 증가와 더 불어 솔더볼의 사이즈는 더욱 감소하여 수십 µm에 지나 지 않는다. 그리고 Table 2와 같이 전단강도 실험에서 수 µm를 일정하게 유지시키기란 매우 어렵다. 실험자, 시편 및 실험환경에서 발생된 오차가 포함된 전단강도 값으로 나타날 가능성이 매우 높고, 이는 실험 결과를 정확히 규 명하는데 큰 영향을 미칠 수도 있다. 이와 같은 이유 때 문에 다양한 연구 분야에서 유한요소 해석을 이용한 전 산모사가 실제 실험 결과를 보완하고, 그 메커니즘을 분 석하는데 많이 이용되고 있다. 무연솔더의 기계적 신뢰성 연구에서도 유한요소 해석 을 이용하면 전단속도에 따른 전단강도 값의 변화를 전 산모사 소프트웨어 상에서 계산하여 실제 실험 결과와 비 교하고, 전단시험 시 발생하는 솔더 내부 균열과 파괴 메 커니즘을 분석할 수 있어 유용하다. Fig. 4에서는 low speed shear test 방법을 이용하여, 실 제 실험값과 유한요소해석을 이용한 전산모사 결과 값을 비교하였고, 전산모사 결과 값 역시 전단속도가 증가할 수록 전단강도 값이 증가함을 확인 할 수 있다. Fig. 7은 스텐실 프린팅 법으로 형성한 Sn-3.0Ag-0.5Cu 조성의 솔더 범프와 Cu 패드를 리플로우 공정을 1회 진 행하여 접합한 후 전단시험을 진행하였을 때 그 단면사 진과 전산모사 후 소성변형 에너지밀도 분포를 보여준다. 전단시험의 조건은 전단속도 200 µm/s, 전단높이 20 µm로 Fig. 7. Averaged incremental equuvalent plastic strain distribution of the solder joint (a) and croos-sectional view of the fractured specimen (b) after shear test.7) 마이크로전자 및 패키징학회지 제17권 제3호 (2010)

5 플립칩패키지 BGA 의전단강도시험법표준화 5 Fig. 8. Force-displacement graph of Sn-3.5Ag at 200 µm/s. 3) Fig. 9. Shear force variations with shear height. 10) 하였다. 가장높은에너지밀도변형구역은전단툴과솔더볼이접촉하는구역에존재하였고, 높은소성변형에너지가기판과솔더볼의접합부를따라평행하게분포하고있다. 실제전단시험후의시편을살펴보면소성변형에너지밀도가높은곳과파단이일어난부위가일치함을알수있다. 전산모사는실제실험과거의동일한파괴거동을보여주며, 이를통해유한요소법을이용한전산모사결과는실제실험을충분히보충할수있음을알수있었다. 8,10,12) Fig. 8은 Sn-3.5Ag 조성의 500 µm 솔더볼과 ENIG 처리된 Cu 패드를리플로우공정을 1회진행하여접합한후전단시험을진행하였을때전단거리에따른전단응력값과동일한조건에서진행한전산모사결과값을나타낸그래프이다. 실선으로나타낸것이실제실험값, 점선으로나타낸값이전산모사값으로, 실제실험값이전산모사값과약간의차이가있고, 오차가조금씩발생했음을알수있다. 이와같은전단강도값의차이는실제실험시전단툴의재료가가지는고유한물성의영향과 JEDEC 규격에서도언급한툴의손상이나변형에의해전단강도값이변하기때문이다. 따라서전단시험시시험규격에따라서시험을진행하는것은물론최적의툴재료선택및시험평가에사용될패키지시편의준비에도각별한주의가필요하다. 결과이다. 전단높이가 12 배높아졌을때, 전단강도값이 23% 가까이감소하는것을실제실험과전산모사의결과를통해알수있다. 이러한경향은다음과같은식으로해석할수있다. 11) F x A H 위식에서 F 는전단력 (shear force), A 는전단면적, x 는전단거리, H 는전단높이를의미한다. 식을통해전단높이가증가하면전단강도값이감소하는것을간단하게알수있다. Table 2 에서언급했듯이 JEDEC 규격이나 JIS(Japanese Industrial Standard) 규격에서는기판에서솔더볼까지의높이중 25% (10% 권장 ) 미만인지점에서전단시험을할것을규정하고있다. Fig. 9 에서알수있듯이전단높이가증가할수록실험오차가커지게된다. 전단높이가커지게되면솔더볼과전단툴이접촉하는면적이작아지므로솔더볼의기계적신뢰성을평가하고파괴메커니즘을분석하는데있어서정확하지않을수있다. 반면에너무낮은높이에서전단시험을진행하게되면, 기판에전단툴이닿아변형이올수있다. 9) 따라서적절한전단높이를규정하고이를바탕으로실험을한다면신뢰할수있는실험결과를얻을수있을것이다. 4. 요약 3. 전단높이에따른전단강도의영향 앞서 Fig. 3 에서보여주는타연구자의통계표에서알수있듯이, 전단높이또한일관성없이진행되고있다. 따라서전단높이의변화가전단강도에어떠한영향을미치는지그차이를비교검토하였다. Fig. 9 는 In-48Sn 조성의 500 µm 솔더볼과 ENIG 처리된 Cu 패드를리플로우공정을 1 회진행하여접합한후 200 µm/s 의전단속도에서전단높이를변화하여실험한 본고에서는마이크로접합을위한솔더볼또는범프의기계적신뢰성평가에사용되는전단시험의표준화규격에대해고찰해보았다. 전단시험에서중요한실험조건중하나인전단속도는 low speed shear test 와 high speed shear test 로구분된다. 전단속도가빨라질수록솔더볼에가해지는충격이커지기때문에, 소성변형에대한저항성이커지게되고, 전단강도가커지게된다. 그리고이결과는전산모사를통하여확인할수있다. 또하나의중요한실험조건으로전단툴의높이가있 J. Microelectron. Packag. Soc. Vol. 17, No. 3 (2010)

6 6 안지혁 김광석 이영철 김용일 정승부 다. 일반적으로전단툴의높이가높을수록전단강도값은낮아지게되는데, 여러국제규격에서제시한솔더볼높이의 25% 지점을초과한높이에서전단시험을진행했을때에는전단시험이진행되는접합계면의면적이줄어들어실험결과의신뢰도가떨어지게된다. 이와같이전단속도와툴의높이등의실험조건들이구체적으로규격화되어있지않은채진행되면, 실험결과의신뢰도가떨어지고, 각계에서진행된연구결과를상호비교하기가어렵다. 따라서효율성을고려한간접시험법개발및최신패키징기술을반영된특성평가시험법의규격, 그리고다양한시험표준화는결국마이크로전자패키지의고신뢰성으로나타날것이라생각된다. 감사의글 본연구의일부는산업자원부차세대신기술개발사업 ( 과제번호 : ) 으로지원된연구임. 참고문헌 1. S. Y. Oh, Electronic Packaging Technology Roadmap, pp. 5-, Korea Microelectronics and Packaging Society (2009). 2. K. S. Kim, Y. C. Lee, J. H. Ahn, Effect of Process Parameters on TSV Formation Using Deep Reactive Ion Etching, J. Kor. Inst. Met.& Mater., (in press). 3. J. H. Lee, N. H. Kang, C. W. Lee, J. H. Kim, Necessity of Low Melting Temperature Pb-free Solder Alloy and Characteristics of Representative Alloys, Int. J. of KWS, 24, 2 (2006). 4. J. W. Kim, S. B. Jung, Experimental and finite element analysis of the shear speed effects on the Sn-Ag and Sn-Ag-Cu BGA solder joints, Materials Science and Engineering A, 371 (1-2), 267 (2004). 5. S. S. Ha, J. K. Jang, S. O. Ha, J. W. Yoon, H. J. Lee, J. H. Joo, Y. H. Kim, S. B. Jung, Effect of multiple reflows on interfacial reaction and shear strength of Sn-Ag electroplated solder bumps for flip chip package, Microelectronic Engineering, 87 (3), 517 (2010). 6. J. W. Kim, Y. C. Lee, S. S. Ha, S. B. Jung, Failure behaviors of BGA solder joints under various loading conditions of high-speed shear test, J. Mater. Sci. : Materials in electronics, 20(1), 17 (2009). 7. E. Kaulfersch, S. Rzepka, V. Ganeshan, A. Muller, B. Michel, Dynamic mechanical behavior of SnAgCu BGA solder joints determined by fast shear tests and FEM simulations, proc. 8th Thermal, Mechanical and Multi-Physics Simulation Experiments in Microelectronics and Micro-Systems (Euro- SimE), London, 1-4, IEEE Components, Packaging and Manufacturing Technology Society (CPMT) (2007). 8. J. W. Kim, S. B. Jung, Optimization of shear test for flip chip solder bump using 3-dimensional computer simulation, Microelectronic Engineering, 82 (3-4), 554 (2005). 9. JEDEC Standard JESD22-B117A, Solder ball shear, (2006). 10. J. W. Kim, S. B. Jung, Characterization of the shear test method with low melting point In-48Sn solder joints, Materials Science and Engineering A, 397(1-2), 145 (2005). 11. J. W. Kim, S. B. Jung, Optimization of the shear test method for flip chip solder bump, Spring Conference of KWS, Samcheok, 18, Journal of KWS, (2006). 12. J. W. Joo, D. H. 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