10 서석용(69~79)_수정.hwp

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1 병행설계를이용한 H.264/AVC 의 DCT 및 CAVLC 하드웨어구현 왕덕상 *, 서석용 **, 고형화 **0 Duck-Sang Wang *, Seok-Yong Seo ** and Hyung-Hwa Ko **0 요약 H.264/AVC DCT(Discrete Cosine Transform) CAVLC(Context-Adaptive Variable Length Coding) IP (Co-Design). DCT Hadamard Shift table 16(%). IP Xilinx ML410 Virtex-4 FX60 FPGA MicroBlaze CPU H.264/AVC JM13.2. IP ModelSim. FPGA. MicroBlaze S/W H/W DCT 16, CAVLC 10. H.264 H/W S/W,. Abstract In this paper, DCT(Discrete Cosine Transform) and CAVLC(Context Adaptive Variable Length Coding) are co-designed as hardware IP with software operation of the other modules in H.264/AVC codec. In order to increase the operation speed, a new method using SHIFT table is proposed. As a result, enhancement of about 16(%) in the operation speed is obtained. Designed Hardware IPs are downloaded into Virtex-4 FX60 FPGA in the ML-410 development board and H.264/AVC encoding is performed with Microblaze CPU implemented in FPGA. Software modules are developed from JM13.2 to make C code. In order to verify the designed Hardware IPs, Modelsim program is used for functional simulation. As a result that all Hardware IPs and software modules are downloaded into the FPGA, improvement of processing speed about multiples of 16 in case of DCT hardware IP and multiples of 10 in case of CAVLC compared with software-only processing. Although this paper deals with co-design of H/W and S/W for H.264, it can be utilized for the other embedded system design. Key words : H.264/AVC, DCT, CAVLC I. 서론 2003 H.264/AVC ITU-T VCEG(Video Coding Expert Group) ISO/IEC MPEG(Moving Picture Expert Group) JVT(Joint Video Team) * (LG Electronics. co. Ltd.) ** (Dept. of Electronics and Communication Eng., Kwang-Woon University) 1 (First Author) : (Duck-Sang Wang) 0 (Corresponding Author) : (Hyung-Hwa Ko, tel: , hhkoh@kw.ac.kr) : ( ) : ( : ) :

2 70 [1][2]. ISO/IEC ITU-T MPEG-4 part 10 Advanced Video Coding (ISO/IEC ) ITU-T H.264 H.264/AVC. H.264/AVC (MPEG-2, H.264, MPEG-4 ) (Intra Prediction),, 4x4 DCT,, [3].,,,, HD-DVD [4]. H.264/AVC 5 32 MPEG-2 45~65(%), 25~45(%) [5].. PC.,. H.264/AVC IP,, SoC/IP., ASIC,.,, ASIC.. H.264/AVC ASIC DSP.,,.. ImpulseC CoDeveloper H.264/ AVC DCT/Hadamard, CAVLC. 2 H.264/AVC IP, 3 IP. 4, 5. Ⅱ. H.264/AVC의기술적내용 2-1 주파수영역에서의보간 H.264/AVC,, (DCT). MPEG 4 4 DCT/Hadamard, DCT Deblocking. DCT,. H.264/AVC,. 2-2 DCT 부호화와양자화

3 ,, ; H.264/AVC DCT CAVLC 71 H.264/AVC DCT 4 4, ,, H.264/AVC DCT,,, DCT. H.264/AVC DCT. H.264/AVC DCT DCT. DCT (1). (1),,,. H.264/AVC HDTV 8 8 FRExt(Fidelity Range Extensions). H.264/AVC DCT Hadamard. Hadamard. DCT. (2), DCT, F offset. H.264/AVC DCT MF. (3) SHIFT1, SHIFT2, SHIFT3. SHIFT (4). (3) (4) 1 MF SHIFT. SHIFT DCT MF. (4) 3, 2. 표 1. SHIFT Table 생성 Table 1. Generation of SHIFT Table 2-3 개선된정수형 DCT 알고리즘제안 H.264/AVC Table Shift. (2) H.264/AVC DCT. DCT MF 2-4 CAVLC 엔트로피부호화 H.264/AVC (Context-based Adaptive Variable Length Coding, CAVLC)

4 72 (Context-based Adaptive Binary Arithmetic Coding, CABAC). CAVLC CABAC, CAVLC. CAVLC DCT. 1,, 0. CAVLC 0 Run-level. 2 0 ±1 CAVLC ± look-up look-up (DC ). CAVLC VLC look-up. 2 CAVLC, 1 CAVLC DCT Zigzag Scan 표 2. CAVCL 의부호화요소 Table 2. Encoding elements of CAVLC. CAVLC. 1 TrailingOnes(±1) Coeff_token. 2 TrailingOnes sign(±). 3 0 Level_prefix Level_subfix Level Total zero Run_before.

,, ; H.264/AVC DCT CAVLC 73 그림 1. CAVLC 부호화 Fig. 1. CAVLC Encoding. Ⅲ. DCT 변환부및 CAVLC 부호화부 3-1 병행설계기법 하드웨어설계 (Co-Design). ImpulseC CoDeveloper. ImpulseC S/W H/W (Co-Design),,,. C VHDL, Verilog..,,,,.

5 ,, ; H.264/AVC DCT CAVLC 73 그림 1. CAVLC 부호화 Fig. 1. CAVLC Encoding. Ⅲ. DCT 변환부및 CAVLC 부호화부 3-1 병행설계기법 하드웨어설계 (Co-Design). ImpulseC CoDeveloper. ImpulseC S/W H/W (Co-Design),,,. C VHDL, Verilog..,,,,.., (Overhead)., FIFO, Handshaking [6][7]. H.264/AVC DCT/ Hadamard CAVLC, MicroBlaze. 2 IP FPGA. DCT CAVLC H/W H.264/AVC MicroBlaze S/W. H/W IP Modelsim Xilinx ISE/XPS H/W IP, Synthesis Implementation. XPS Bit Xilinx ML410 Virtex-4 FX60 FPGA. 그림 2 구현된시스템의구조 Fig. 2. Structure of Implemented System. 3-2 변환부호부 H/W 모듈설계 H.264/AVC 4 4 DCT (FRExt) 8 8 DCT. DCT H/W 4 4 DCT 8 8 DCT, Hadamard.

6 , 4 4 DCT DCT Hadamard H/W. 4 4 DCT 8 8 DCT Hadamard 8 8 DCT. S/W H/W 32. H/W 32, 4 4 DCT. 4 4 DCT 32 S/W, Hadamard. Shift 8 look-up. H/W DCT Hadamard 32 S/W. H.264/AVC. 4 4 DCT 1 Coeff_token,, level, totalzero, runbefore. 4 CAVLC H/W DCT Coeff_token table. 1 Sign(±) 0 Level table. 0 0 Total zero table 0 Run_before table CAVLC. 그림 DCT H/W 의내부구조 Fig. 3. Internal Structure of 4 4 DCT H/W. 3-3 CAVLC H/W 모듈설계 CAVLC 4 4 DCT CABAC 그림 4. CAVLC H/W 의내부구조 Fig. 4. Internal Structure of CAVLC H/W.

7 ,, ; H.264/AVC DCT CAVLC 75 Ⅳ. 실험및결과. 4-1 실험방법 (1) DCT IP Modelsim, Xilinx ISE 8.2 EDK 8.2 Tool H/W MicroBlaze, S/W H/W. H/W Xilinx ML410 Virtex-4 FX60 FPGA. FPGA MicroBlaze Core 75MHz. JM13.2 MicroBlaze 3 Xilinx ML410 Virtex-4 FX60 FPGA 8 8 DCT (%). 표 3. DCT 연산시간비교 Table 3. Comparison of processing time for DCT. MicroBlaze Core OPB-Timer. OPB-Timer IP ticks, ticks [8]. 표 4. S/W 모듈과 H/W 모듈의연산시간비교 Table 4. Comparison of processing time with S/W and H/W module.( 단위 :Tick) 실험결과 H/W 4 4 DCT, CAVLC H/W. 8 8 DCT H/W H.264/AVC 8 8 DCT. JM13.2 CAVLC CABAC PSNR 4 H/W. ML410. DCT 10.4( ), CAVLC 15.5( ). (2) PSNR 5 H.264/AVC DCT Shift DCT PSNR. JM13.2 PC

8 76 표 5. 제안한 DCT 에따른 CAVLC 엔트로피부호화시평균 PSNR 과비트율 Table 5. Average PSNR and Bit Rate using CAVLC entropy coding for proposed DCT. 10 QCIF( ) (Bus, City, Soccer, Crew, Footboll, Foreman, Harbour, Ice, Mobile, Akiyo) 58 CAVLC. JM13.2. Shift 3. Shift 2 PSNR trade-off CAVLC CABAC. Shift 3 CAVLC PSNR 0.17(%). CABAC PSNR 0.24(%). Shift 2 CAVLC PSNR 0.15(dB) 2.17(%). CABAC PSNR 0.1(dB) 1.9(%). 3 16(%)., [8][9] PSNR 0.066(dB) 2.31(bps) 61.2(%). DED(Domain Edge Direction) [10] PSNR 0.17(dB) 4.23(bps) 73.78(%). PSNR Shift 3 PSNR DCT 16(%). Shift 2 표 6. 엔트로피부호화에따른평균 PSNR 과비트율비교 Table 6. Comparison of average PSNR and Total Bit according to entropy coding

,, ; H.264/AVC DCT CAVLC 77 그림 5. 16 16 DCT 시뮬레이션결과 Fig. 5. 16 16 DCT Simulation result. 그림 6.

4 4 DCT H/W 4 4 DCT H/W [11]. 4 4 DCT H/W PCI 30K. 4 4 DCT 21. 4 4 DCT H/W, 158K 4 4 DCT 198.

9 ,, ; H.264/AVC DCT CAVLC 77 그림 DCT 시뮬레이션결과 Fig DCT Simulation result. 그림 DCT 시뮬레이션결과 Fig DCT Simulation result. PSNR 0.1~0.15(dB) 2(%). (3) H/W. 4 4 DCT H/W 4 4 DCT H/W [11]. 4 4 DCT H/W PCI 30K. 4 4 DCT DCT H/W, 158K 4 4 DCT 198. Impulse C (FSM: Finite State Machine),., ASIC., 4 4 DCT 183K 121. CLVLC H/W 583K Codeword 100~

10 DCT ModelSim. 100(ps). Visual Studio 2008, DCT 122.2(ns). 6 FRExt 8 8 DCT ModelSim. 8 8 DCT 72(ns)..,., IP H.264/AVC. Ⅴ. 결론 (Co-Design) H.264/AVC DCT CAVLC. DCT H.264/AVC DCT Shift DCT. H/W H.264/AVC DCT 16(%) FPGA. 3 Shift DCT PSNR Shift 2 PSNR 0.1~0.15(dB) 2(%). ML410 FPGA DCT IP MicroBlaze 10.4( ), CAVLC IP 15.5( )., Impuse C FSM( ) 감사의글 Reference [1] JVT G050r1, "Draft ITU-T Recommendation and Final Draf t International Standard of Joint Video Specification(ITU- T Rec, H.264/ISO/IEC AVC)," May 2003 [2] Thomas Wiegand, Gary J. Sullivan, Gisle Bjontegaard, and Ajay Luthra, Overview of the H.264/AVC Video Coding Standard, IEEE Trans. on Circuits and System for Video Technology, Vol. 13, No.7, pp , July [3] Iain E.G. Richardson, H.264 and MPEG-4 Video Compression, The Robert Gordon University, Aderdeen, [4] Je-Chang Jeong, H.264/AVC TextBook, HongRung Publishing Co [5] Thomas Wiegand, Heiko Schwarz, Anthony Joch, and Faouzi Kossentini, Rate-Constrained Coder Control and Comparison of Video Coding Standard, IEEE Transactions on Circuits and Systems for Video Technology, Vol.13, pp , July 2003 [6] Jun-Mo Jeong, HW/SW co-design of H.264/AVC Decoder using ARM-Excalibur, J. KAIS, Vol.10, No.7, pp , [7] Seong-Mo Park, Sukho Lee, Kyoungseon Shin, Jea-Jin Lee, Moo-Kyong Caung, Jun-Young Lee, and Nak-Woong Eum, "A Low Power Design of H.264 Codec Based on Hardware and Software Co-design," J. KICS, vol.25, No.12, pp.10-18, 2008

,, ; H.264/AVC DCT CAVLC 79 [8] Jhing-Fa Wang, Jia-Ching Wang, Jang-Ting Chen, An-Chao Tsai, and Anand Paul, "A Novel Fast Algorithm for Intra Mode Decision in H.

[9] Seong-Whan Lee, Young-Min Kim, and Sung Woo Choi, "Fast Scen Charnge Detection using Direct Feature extraction from MPEG Compressed Videos," IEEE Trans. On Multimedia Vol.

On SP, Vol.44, No.3, pp.23 32, May 2007. [11] Young-Hun Lim and Yong-Jin Jeong, Hardware Implementation of Integer Transform and Quantization for H.264, J. KICS, Vol.28, No.

11 ,, ; H.264/AVC DCT CAVLC 79 [8] Jhing-Fa Wang, Jia-Ching Wang, Jang-Ting Chen, An-Chao Tsai, and Anand Paul, "A Novel Fast Algorithm for Intra Mode Decision in H.264/AVC Encoders," ISCAS2006, pp , July [9] Seong-Whan Lee, Young-Min Kim, and Sung Woo Choi, "Fast Scen Charnge Detection using Direct Feature extraction from MPEG Compressed Videos," IEEE Trans. On Multimedia Vol.2, No. 4. pp Dec 2000 [10] Byeongdu La, Minyoung Eom, and Yoonsik Choe, Fast Intra Mode Decision for H.264/AVC by Using the Approximation of DCT Coefficient," IEEK Trans. On SP, Vol.44, No.3, pp.23 32, May [11] Young-Hun Lim and Yong-Jin Jeong, Hardware Implementation of Integer Transform and Quantization for H.264, J. KICS, Vol.28, No.12C, 고형화 (Hyung-Hwa Ko) : ( ) : () : () ~ : : H.264, JBIG2, H/W-S/W co-desing, HEVC, Watermarking, 왕덕상 (Duck-Sang Wang) : ( ) : () ~ : LG Car : H.264, H/W-S/W co-desing, 서석용 (Seok-Yong Seo) : ( ) : () : () : JBIG2, H.264, H/W-S/W co-desing, Watermarking

그림 2. 최근 출시된 스마트폰의 최대 확장 가능한 내장 및 외장 메모리 용량 원한다. 예전의 피쳐폰에 비해 대용량 메모리를 채택하고 있지 만, 아직 데스크톱 컴퓨터 에 비하면 턱없이 부족한 용량이다. 또한, 대용량 외장 메모리는 그 비용이 비싼 편이다. 그러므로 기존

그림 2. 최근 출시된 스마트폰의 최대 확장 가능한 내장 및 외장 메모리 용량 원한다. 예전의 피쳐폰에 비해 대용량 메모리를 채택하고 있지 만, 아직 데스크톱 컴퓨터 에 비하면 턱없이 부족한 용량이다. 또한, 대용량 외장 메모리는 그 비용이 비싼 편이다. 그러므로 기존 스마트폰을 위한 A/V 신호처리기술 편집위원 : 김홍국 (광주과학기술원) 스마트폰을 위한 동영상 압축 기술 호요성, 최정아 광주과학기술원 요 약 스마트폰이 대중화되면서 이동통신 시장은 일대 혁신을 맞이 했다. 최근 출시되는 스마트폰이 크고 선명한 화면과 빠른 프로 세서를 잇따라 탑재하면서 고해상도 및 고품질 영상에 대한 사 용자들의 수요가 급증하고 있다. 하지만