(JBE Vol. 20, No. 2, March 2015) (Special Paper) 20 2, (JBE Vol. 20, No. 2, March 2015) ISSN
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1 (JBE Vol. 20, No. 2, March 2015) (Special Paper) 20 2, (JBE Vol. 20, No. 2, March 2015) ISSN (Online) ISSN (Print) SIMD HEVC RExt a), a), a), a) SIMD Instruction-based Fast HEVC RExt Decoder Jung-Soo Mok a), Yong-Jo Ahn a), Hochan Ryu a), and Donggyu Sim a) HEVC RExt (High Efficiency Video Coding Range Extension) SIMD (Single Instruction Multiple Data). RExt,, -, -, SIMD. RExt,, -, -, SSE (Streaming SIMD Extension)., 256 AVX2 (Advanced Vector extension 2), -,. SIMD HEVC HM 16.0 HEVC RExt 12%. Abstract In this paper, we introduce the fast decoding method with the SIMD (Single Instruction Multiple Data) instructions for HEVC RExt (High Efficiency Video Coding Range Extensions). Several tools of HEVC RExt such as intra prediction, interpolation, inverse-quantization, inverse-transform, and clipping modules can be classified as the proper modules for applying the SIMD instructions. In consideration of bit-depth increasement of RExt, intra prediction, interpolation, inverse-quantization, inversetransform, and clipping modules are accelerated by SSE (Streaming SIMD Extension) instructions. In addition, we propose effective implementations for interpolation filter, inverse-quantization, and clipping modules by utilizing a set of AVX2 (Advanced Vector extension 2) instructions that can use 256 bits register. The evaluation of the proposed methods were performed on the private HEVC RExt decoder developed based on HM The experimental results show that the developed RExt decoder reduces 12% average decoding time, compared with the conventional sequential method. Keyword : HEVC, RExt, HEVC Range extensions, SIMD, Parallelization a) (Dept. of Computer Engineering, Kwangwoon University) Corresponding Author : (Donggyu Sim) dgsim@kw.ac.kr Tel: ORCID: ( ) (NRF-2014R1A2A1A ) 2014 ( ) ( ) Manuscript received January 21, 2015; revised March 24, 2015; accepted March 24, 2015.
2 3 : SIMD HEVC RExt (Jung-Soo Mok et al.: SIMD Instruction-based Fast HEVC RExt Decoder)., ISO/IEC MPEG (Moving Picture Experts Group) JCT-VC (Joint Collaboration Team on Video Coding) H.264/AVC 2 HEVC (High Efficiency Video Coding) [1][2]. HEVC,, YUV 4:2: [3]. HEVC 1 HEVC SHVC(Scalable HEVC), MV-HEVC (Multi-view HEVC), HEVC-RExt (HEVC Range Extension). HEVC RExt 16 YUV 4:0:0/ 4:2:0/4:2:2/4:4:4 [4]. HEVC RExt HEVC 1 RExt [5]. HEVC 1 [6] [7][8][9] HEVC 1 RExt., SIMD (Single Instruction Multiple Data) CPU GPU (multi threading). HEVC 2 RExt SIMD. HEVC RExt SIMD MMX (MultiMedia extension) SSE(Streaming SIMD Extension) AVX2 (Advanced Vector extension 2).. 2 MMX SSE HEVC RExt. 3 AVX2 AVX2 4 MMX SSE AVX MMX SSE SIMD HEVC RExt SIMD MMX SSE. SIMD HEVC RExt (Intra prediction), (Interpo- lation), - (Inverse quantization), - (Inverse transform). 1. HEVC DC, PLANAR 33 Angular. SIMD.
3 (JBE Vol. 20, No. 2, March 2015) 1. PLANAR Fig. 1. Intra PLANAR mode prediction method DC SIMD movdqu. PLANAR 1 (1). TU (Transform Unit). (1) 2 PLANAR 4 4 SIMD. punpcklwd punpckhwd pack pmullw. (S4) (S9). paddw pshw. 33 Angular. HEVC 2. SSE PLANAR Fig. 2. Intra PLANAR prediction using SSE instruction set
4 3 : SIMD HEVC RExt (Jung-Soo Mok et al.: SIMD Instruction-based Fast HEVC RExt Decoder) (2). (3) (4).. (3) & (4) Angular 3 Angular 2. (3) (4) pshuflw, pshufhw, pshufd 3. (2) 2. HEVC. 8, 4 DCT (Discrete Cosine Transform) 1. SIMD [10] pmaddwd pack phaddd SSE Angular 2 Fig. 3. Mode 2 of Intra Angular prediction using SSE instruction set
5 (JBE Vol. 20, No. 2, March 2015) 4. SSE Fig. 4. Horizontal interpolation using SSE instruction set 5. SSE Fig. 5. Vertical interpolation using SSE instruction set 5 8.
6 3 : SIMD HEVC RExt (Jung-Soo Mok et al.: SIMD Instruction-based Fast HEVC RExt Decoder) punpcklwd punpckhwd pack. packssdw 16. (6) 0~ (7). (6) 3. - (7) HEVC RExt (Uniform reconstruction quantizer) (5) (C ) (Qstep). (5) (16). shift. - SIMD 6 SIMD SSE Fig Inverse quantization using SSE instruction set
![(JBE Vol. 20, No. 2, March 2015) SSE 4 pmulld paddd psrad. packssdw pack - 16. 4. - Chen [11]. SIMD butterfly [12], 1D, 7. pmaddwd phaddd.](/docs-images/101/149046047/images/7-0.jpg "HEVC 4 4 ~ 32 32 TU (DCT : Discrete Cosine Transform) (DST : Discrete Sine Transform). IDCT (Inverse Discrete Cosine Transform) IDST (Inverse Discrete Sine Transform) - -. HEVC partial butterfly.")
7 (JBE Vol. 20, No. 2, March 2015) SSE 4 pmulld paddd psrad. packssdw pack Chen [11]. SIMD butterfly [12], 1D, 7. pmaddwd phaddd. HEVC 4 4 ~ TU (DCT : Discrete Cosine Transform) (DST : Discrete Sine Transform). IDCT (Inverse Discrete Cosine Transform) IDST (Inverse Discrete Sine Transform) - -. HEVC partial butterfly. AVX2 SIMD AVX2 SIMD. HEVC RExt 8 16 MMX SSE 7. SSE Fig Inverse transform using SSE instruction set
![3 : SIMD HEVC RExt (Jung-Soo Mok et al.: SIMD Instruction-based Fast HEVC RExt Decoder). AVX2 x86 MMX SSE 128 256 / SIMD SSE 2 [13]. HEVC RExt -,, (clipping) AVX2, AVX2. HEVC RExt AVX2, AVX2 SSE.](/docs-images/101/149046047/images/8-0.jpg "SSE 128,, pack HEVC. AVX2,, pack. AVX2 256 128 0~127 128~255. 8 SSE AVX2 pack. SSE pack 64 64. AVX2 pack 128 256 64 64. Pack SSE AVX2 pack 128. AVX2 AVX2.. AVX2 pack SSE, AVX2 pack. SSE 8.")
8 3 : SIMD HEVC RExt (Jung-Soo Mok et al.: SIMD Instruction-based Fast HEVC RExt Decoder). AVX2 x86 MMX SSE / SIMD SSE 2 [13]. HEVC RExt -,, (clipping) AVX2, AVX2. HEVC RExt AVX2, AVX2 SSE. SSE 128,, pack HEVC. AVX2,, pack. AVX ~ ~ SSE AVX2 pack. SSE pack AVX2 pack Pack SSE AVX2 pack 128. AVX2 AVX2.. AVX2 pack SSE, AVX2 pack. SSE 8. AVX2 SSE pack Fig. 8. Pack and unpack of AVX2 and SSE instruction set
9 (JBE Vol. 20, No. 2, March 2015) AVX2 SSE AVX2 19%. AVX vpmaddwd 9. AVX2 Fig. 9. Horizontal interpolation using AVX2 instruction set 10. AVX2 Fig. 10. Vertical interpolation using AVX2 instruction set
10 3 : SIMD HEVC RExt (Jung-Soo Mok et al.: SIMD Instruction-based Fast HEVC RExt Decoder). vphaddd 8 32, 16 pack vperm2i SSE AVX AVX TU -. AVX2 11 vpmulld, vpaddd, vpsrad - vpackssdw pack AVX2 12. vpaddw vpminsw vpmaxsw. SSE AVX2 8 8 TU - Fig TU inverse quantization using AVX2 instruction set
![(JBE Vol. 20, No. 2, March 2015) 12. AVX2 Fig. 12. Clipping using AVX2 instruction set. SIMD HEVC RExt. HM 16.0 ANSI C HEVC RExt 1. HEVC RExt 10 YUV 4:2:2 [14]. (8) (Average Time Saving) SIMD, SIMD.](/docs-images/101/149046047/images/11-0.jpg "1. SIMD Table 1. Test environment for SIMD instruction-based decoding Component CPU Clock speed Memory OS Description Intel Core i7 4770K 3.5GHz (Haswell) 3.")
11 (JBE Vol. 20, No. 2, March 2015) 12. AVX2 Fig. 12. Clipping using AVX2 instruction set. SIMD HEVC RExt. HM 16.0 ANSI C HEVC RExt 1. HEVC RExt 10 YUV 4:2:2 [14]. (8) (Average Time Saving) SIMD, SIMD. 1. SIMD Table 1. Test environment for SIMD instruction-based decoding Component CPU Clock speed Memory OS Description Intel Core i7 4770K 3.5GHz (Haswell) 3.5GHz 32GB MS Window 7 64 bits Compiler Intel C AVX2 SSE HEVC RExt. SIMD 10. SSE - 38% 47%, AVX2, -, 19%, 80%, 44%. 12%, AVX2, -, -. 3 SSE AVX2 SSE.
12 3 : SIMD HEVC RExt (Jung-Soo Mok et al.: SIMD Instruction-based Fast HEVC RExt Decoder) 2. SSE AVX2 Table 2. Experiments result using SSE and AVX2 instruction set Sequence EBUHorse EBUKids Soccer Kimono Seeking Total Average QP Intra prediction decoding (SSE) ATS (%) Avg. Interpolation decoding (AVX2) ATS (%) Avg. Inverse transform decoding (SSE) ATS (%) Avg. Inverse quantization decoding (AVX2) ATS (%) Avg. ATS (%) Clipping (AVX2) Avg. Total decoding ATS (%) Avg SSE AVX2 Table 3. Time reduction ratio AVX2 instruction set compared SSE instruction set ATS (%) interpolation horizontal interpolation vertical Uni Bi Uni Bi inverse quantization clipping SSE AVX2 12%. AVX2, -,,, -, -.. HEVC RExt SIMD HEVC RExt. SIMD. HEVC RExt,, -, - SIMD (References) [1] B. Bross, W. Han, G. Sullivan, J. Ohm, and T. Wiegand, High Efficiency Video Coding (HEVC) Text Specification Draft 10, document JCTVC-L1003_v34, Geneva, CH, Jan [2] B. Li, G. and G. Sullivan, Comparison of Compression Performance of HEVC Draft 10 with AVC High Profile, JCTVC-M0329, Incheon, Korea, April [3] G. J. Sullivan, J. Ohm, W. Han, and T. Wiegand, Overview of the High Efficiency Video Coding ( HEVC ) Standard, IEEE Trans. on CSVT., vol. 22, no. 12, pp , Dec [4] J. Boyce, J. Chen, Y. Chen, D. Flynn, M. M. Hannuksela, M. Naccari, C. Rosewarne, K. Sharman, J. Sole, G. J. Sullivan, T. Suzuki, G. Tech,
13 (JBE Vol. 20, No. 2, March 2015) Y.-K. Wang, K. Wegner, Y. Ye, Draft high efficiency video coding (HEVC) version 2, combined format range extensions (RExt), scalability (SHVC), and multi-view (MV-HEVC) extensions, JCTVC-R1013, Sapporo, JP, July, 2014 [5] C. Rosewarne, K. Sharman, M. Naccari, G. Sullivan, HEVC Range extensions test model 6 encoder description, JCTVC-P1013, San Jose, US, Jan [6] Y.J. Ahn, W.J. Han, and D.G. Sim, Study of decoder complexity for HEVC and AVC standards based on tool-by-tool comparison, SPIE Applications of Digital Image Processing XXXV, Proceedings of SPIE, vol. 8499, pp , San Diego, USA, Aug [7] C. Chi, M. Alvarez-Mesa, J. Lucas, B. Juurlink, and T. Schierl, Parallel HEVC decoding on multi- and many-core architectures, Journal of Signal Processing Systems, vol. 71, no. 3, pp , June, [8] H. Jo, D. Sim, Hybrid Parallelization for HEVC Decoder, Image and Signal Processing (CISP)., vol. 1, pp , Dec [9] Chi, C. C., Alvarez-Mesa, M., Bross, B., Juurlink, B., and Schierl, T, SIMD acceleration for HEVC decoding, IEEE Trans. on CSVT., no. 99, Oct [10] T. Hwang, Y. Ahn, J. Ryu, D. Sim, Optimized Implementation of Interpolation Filter for HEVC Encoder, Journal of The Institute of Electronics Engineers of Korea, vol. 50, no. 10, pp , October, 2013 [11] W-H. Chen, C. H. Smith, and S. C. Fralick, A fast computational algorithm for the discrete cosine transform, IEEE Trans. on Commun., vol. 25, no. 9, pp , Sep [12] T. Hwang, Y. Ahn, D. Sim, SIMD instruction-based HEVC encoder optimization, IPIU, Feb [13] Intel, Intel Advanced Vector Extensions Programming Reference, Technical Report , Intel, June, [14] D.Flynn, C.Rosewarnem Common test condition and software reference configurations for HEVC range extensions, document JCTVC-L1006_v2, Geneva, Jan : ~ : - ORCID : - :, : : ~ : - ORCID : - :, : : - ORCID : - :,
14 3 : SIMD HEVC RExt (Jung-Soo Mok et al.: SIMD Instruction-based Fast HEVC RExt Decoder) : : : ~ : ~ : ~ : University of Washington Senior research engineer ~ : - ORCID : - :,,
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