Integrated Circuits SSI(Small Scale IC) 10 / ( ) MSI(Medium Scale IC) / (, ) LSI(Large Scale IC) / (LU) VLSI(Very Large Scale IC) - / (CPU, Memory) ULSI(Ultra Large Scale IC) - / ( ) GSI(Giant Large Scale IC)
Commonly used 7400-Series SSI ICs 14 13 12 11 10 9 8 V cc 14 13 12 11 10 9 8 V cc 14 13 12 11 10 9 8 V cc 7400 7402 7486 GND 1 2 3 4 5 6 7 GND 1 2 3 4 5 6 7 GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 V cc 14 13 12 11 10 9 8 V cc 14 13 12 11 10 9 8 V cc 7408 7404 7420 GND 1 2 3 4 5 6 7 GND 1 2 3 4 5 6 7 GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 V cc 14 13 12 11 10 9 8 V cc 14 13 12 11 10 9 8 V cc 7432 7410 7427 GND 1 2 3 4 5 6 7 GND 1 2 3 4 5 6 7 GND 1 2 3 4 5 6 7
Positive Logic and Negative Logic Positive logic Negative logic Logic Value Signal Value Logic Value Signal Value 1 H 0 L 0 H 1 L Positive logic Positive logic Negative logic Negative logic ND OR ND OR Positive logic ND = Negative logic OR Positive logic OR = Negative logic ND
Characteristics of IC Logic Family Fanout, Power dissipation Propagation delay Noise margin Degree of integration Component cost
IC Digital Logic Family RTL (Resistor Traansistor Logic) DTL (Diode Transistor Logic) TTL (Transistor Transistor Logic) : ECL (Emitter Coupled Logic) : MOS (Metal Oxide Semiconductor) : CMOS (Complementary Metal Oxide Semiconductor) :, I 2 L (Integrated Injection Logic) : icmos
Diode Logic Y=+ +5V Y=
ipolar Transistor I C R C I [m] I C [m] R C I = 0.6m 0.5 I V o 0.4 V i R 0.3 I E 0.6 0.7 0.8 V E [V] 0.2 V CE [V] Region V E [V] V CE [V] Current Relationship Cutoff < 0.6 Open circuit I =I C =0 ctive 0.6-0.7 > 0.8 I C =h FE I Saturation 0.7-0.8 0.2 I >> I CS /h FE
RTL(Resistor Transistor Logic) L:0.2V, H:1.0-3.6V Power dissipation:12mw Propagation delay: 25ns Noise Margin: 0.4V Fanout= 5 =3.6V 640 =3.6V 640 Y= C Y= ++C 450 450 450 C C
DTL(Diode Transistor Logic) L:0.2V, H:4-5V Power dissipation:12mw Propagation delay: 30ns Noise margin: 1V Fanout: 8 =5V,,C L 5K 2K Y= C P=0.2+0.7= 0.9V Q1 ON P P= 0.7+0.7+0.7= 2.1V C P D1 D2 5K Q1 Q1 is OFF Y=5V,,C H Q1 is ON Y= 0.2V
DTL =5V 1.6K 2K 2K Y= C P Q1 D2 Q2 C 5K
TTL(Transistor Transistor Logic) TTL series name Prefix Fanout Power dissipation [mw] Propagation delay [ns] Speed-Power product [pj] Standard 74 10 10 9 90 Low-power 74L 20 1 33 33 High speed 74H 10 22 6 132 Schottky 74S 10 19 3 57 Low-power Schottky 74LS 20 2 9.5 19 dvanced Shottky 74S 40 10 1.5 15 dvanced low-power Schottky 74LS 20 1 4 4 TTL output 1) Open-collector output 2) Totem-pole output 3) Tristate output
=5V =5V 4K 1.6K R L C Q1 Q2 1K Q3 Y= C
Open Collector TTL C D OC OC Y I 1 I 2 I 3 0 0 0 OC1 OC2 OC3 1 1 1 us line OC5 Y C D OC OC Y I 4 1 0 OC4 0 1
Totem-Pole Output TTL =5V 4K 1.6K 130 Q4 C Q1 Q2 Q3 D1 Y= C 1K
Schottky TTL =5V 2.8K 900 50 Q5 Q4 Q1 Q2 3.5K Q3 500 250 Q6
3-State TTL Gate Q5 Q4 C Y= if C=high Y=high impedance if C=low Q1 Q2 Q3 Y Y= if C=low Y=high impedance if C=high C D1 C Q6 Q7 Q8
ECL(Emitter Coupled Logic) 2 =GND 1 =GND R C1 220 R C2 245 907 Q8 OR output Q7 Q1 Q2 Q3 Q4 Q5 V = -1.3V Q6 NOR output Rp 50K Rp 50K Rp 50K Rp 50K R E 779 6.1K 4.98K C D V EE = -5.2V
ECL gates (+) : NOR (+) : OR (+) +(C+D) =[(+)(C+D)] (+)(C+D)
CMOS Logic Gates
CMOS
CMOS Logic Gate
Transmission Gates