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1 K2E-PAT Page 1 대한민국특허청 (KR) Korea patent office (KR) 특허공보 (B1) Gazette (B1) 1993 년 10 월 09 일 1993 year October 09. International Patent Classification Edition 5 G06F 9/44 G06F 9/44 Unexamined Publication Number 특 KR 년 10 월 09 일 1993 year October 09. Application Number 특 KR Application Date 1985 년 09 월 24 일 09 month, 1985 year 24. 특 KR Publication Date 1986 년 06 월 20 일 06 month, 1986 year 년 11 월 30 일 1984 year November 30. EPO(EP) EPO(EP) Applicant 인모스리미티드 InMoSeu RiMiTiDeu 제임스씨. 시몬스 James C. Simons. 영국 United Kingdom. 영국브리스틀루인스미드화이트프리아 United Kingdom bristle fistula ins mid white beep Lias. 스 Inventor 마이클데이비드메이 MaIKeul DeIBiDeu MeI 영국 United Kingdom. 영국브리스틀클리프튼펨브로크로드 124 United Kingdom bristle *** pem broke load 124. Inventor 로저마크세퍼드 RoJeo MaKeu SePeoDeu 영국 United Kingdom. 영국브리스틀코담코담베일 21 The nose wall veil 21 the United Kingdom bristle nose sweets. Agent 이병호 Byeong-Ho Lee

2 K2E-PAT Page 2 김연호 ( 책자공보제 3431 호 ) GimYeonHo (ChaekJaGongBo Je3431Ho) KR KR Title 시간의존처리용마이크로컴퓨터 Time dependent *** microcomputer. Abstract Abstract 내용없음. Content none. Selected Drawing: Figure 1 Description [ 발명의명칭 ] [Title of invention] 시간의존처리용마이크로컴퓨터 Time dependent *** microcomputer. [ 도면의간단한설명 ] [The simple description of the drawing] 제 1 도는본발명을구성하는마이크로컴퓨터의주특성을도시하는블록도. 제 2 도는편의상제 2a 도및 2b 도로분리된마이크로컴퓨터부분의블록도로써, 특히중앙처리장치및메모리그리고통신링크간의인터페이스는물론레지스터, 데이타통로및중앙처리장치의산술논리장치의도시도. 제 3 도는제 2b 도의부분을형성하는타이머논리회로의도시도. 제 4 도는마이크로컴퓨터에의한실행용고우선권처리의스케쥴 (schedule) 된리스트의작업공간과프로세서레지스터간의관계도. 제 5 도는고우선권처리가실행되는동안저우선권처리의스케쥴된리스트의도시도. 제 6 도는재스케줄되기이전에예정된시간을대기하는저우선권처리의타이머리스트의도시도. 제 7 도는재스케쥴되기이전에예정되시간을대기하는고우선권처리의타이머리스트의도시도. 제 8 도는본발명에따라서서로다른워드길이를가지는회로망내의마이크로컴퓨터인, 통신마이크로컴퓨터회로망의도시도. 제 9a 도내지제 9d 도는 " 타이머입력 " 작동을실행하는처리용동작순차의도시 Figure 1 is a block diagram showing the principal characteristic of the microcomputer comprising the present invention. Figure 2 is a block diagram, especially, the register as well as an interface between the central processing unit and the memory and communications link, and the illustration drawing of the arithmetic logic unit of data path and central processing unit of the microcomputer part back separated with for convenience the 2a drawing and 2b. Figure 3 is an illustration drawing of the timer logic circuit forming the part of Figure 2b. Figure 4 is a relationship diagram between the work space of the list which becomes with the schedule (schedule) and the process register of the high priority processing for an execution by a microcomputer. Figure 5 is an illustration drawing of the scheduled list of the base priority processing the high priority processing is performed. Figure 6 is an illustration drawing of the timer list of the base priority processing queuing the time which is scheduled before being small and scheduled. Figure 7 is an illustration drawing of the timer list of the high priority Keown processing which queues *** time before being small and scheduled. Figure 8 is an illustration drawing of the microcomputer phosphorus within C network C having the according to the present inventioneach other dissimilar word length, and the communications micro computer circuit network. Through Figure 9a. And figure 9d is an illustration drawing of

3 K2E-PAT Page 3 도. 제 10a 도내지 10e 도는타이머리스트내로처리를삽입하기위한순차의도시도. 제 11a 내지 11c 도는시간교대 (alternative) 처리를위한동작순차의도시도로써, 특히처리가어떻게더이른교대시간을결정하는가의도시도. 제 12a 도내지 12c 도는다수의교대시간들중의하나사이의처리선택을위한동작순차의도시도로써, 이들중의하나는이미도착되어있는도시도. 제 13a 내지 13f 도는다수의교대시간들사이의처리선택을위한동작순차의도시도로써, 이들중의어느하나도처리가처음선택을시도할시에도착되지않고있는도시도. 제 14a 내지 14d 도는특정시간의발생혹은, 처리가선택을개시하는시간에서통신할준비가되어있는메세지채널로부터의입력의양자택일간의처리선택을위한동작순차의도시도. 제 15a 도내지제 15f 도는처리가양자중의어느하나를택일적으로선택하고자시도할시에발생되는시간을가지지도않거나메세지를입력할준비도되어있지않는특정시간의발생혹은, 메세지채널을통한입력의양자택일간의처리선택을위한동작순차의도시도. *** operation consecutive enforcing "timer input" operation. The illustration drawing of Figure 10a or the consecutive where 10e drawing inserts a processing within the timer list. The illustration drawing of *** the changing time writing the 11a or 11c drawing with the city road of the operation consecutive for the time alternation (alternative) processing, and when especially, a processing how more tells. The illustration drawing using with the city road of the operation consecutive for the processing selection between Figure 12a or one of 12c drawing is lots of the changing times, and one of these middles already arrives. The illustration drawing writing the 13a or 13f drawing with the city road of the operation consecutive for the processing selection between lots of the changing time, and does not arrive when a ones a processing attempts a selection for the first time. The 14a or 14d drawing is the illustration drawing of the operation consecutive for the processing selection between the alternative of an input from the generation of the specific duration or the message channel in which it becomes the preparation communicating in the time when a processing discloses a selection. Through Figure 15a. And figure 15f is an illustration drawing of the operation consecutive for the processing selection between the alternative of the input through a generation, or the message channel of the specific duration which does not become the preparation which does not have the time to be generated when a processing attempts in order to alternatively select one among both sides out or inputs a message. * 도면의주요부분에대한부호의설명 * The description of reference numerals of the main elements in drawings. 10 : 동기논리장치 11 : 단일실리콘칩 10: the synchronized logic apparatus 11: single silicon chip. 12 : 중앙처리장치 (CPU) 13 : RAM 12: central processing unit (CPU) 13: RAM. 14 : 메모리인테페이스 15 : 인터페이스제 14: memory interface 15: interface control logic device. 어논리장치 16 : 버스 17 : 서비스시스템 16: bus 17: service system. 18 : 입력핀 19 : RAM 18: input pin 19: RAM. 20 : ROM 23 : 외부메모리인터페이스 20: ROM 23: external memory interface. 24 : 핀 25 : 일련링크 24: pin 25: series link. 26 내지 27 : 핀 Through 26 27: pin. 30 : 산술논리유니트 (ALU) 31 : 양방향성데 30: arithmetic logic unit (ALU) 31: bidirectional data bus. 이타버스 32 : 버스제어스위치회로의레지스터 34 : 32: the register of the bus control switching circuit 34:

4 K2E-PAT Page 4 명령어버퍼 instruction buffer. 35 : 디코더 36 : 상태멀티플렉서 35: decoder 36: state multiplexer. 37 : 마이크로명령어레지스터 (MIR) 38 : 우선권 1레지스터뱅크 39 : 우선권 0 레지스터뱅크 40 : 콘스탄트박스 37: micro instruction register (MIR) 38: priority 1 register bank. 39: priority 0 register bank 40: constant box. 41 : 레지스터뱅크선택기 41: register bank selector. 42 : 메모리어드레스레지스터 (MA DDR) 42:memory address register(ma DDR) 43 : 데이타출력 44 : 일시레지스터 43: data out 44: temporary register. 45 : 처리포인터레지스터 46 : 처리설명기레지스터 47 : 우선권표시프래그 48 : 처리우선권프래그 45: processing pointer register 46: processing descriptor register. 47: priority display flag 48: processing priority flag. 49 : 일시레지스터 50 : IPTR 레지스터 49: temporary register 50: IPTR register. 51 : WPTR 레지스터 52 : BPTR 레지스터 51: WPTR register 52: BPTR register. 53 : FPTR 레지스터 54 : A 레지스터 53: FPTR register 54: a register. 55 : B 레지스터 56 : C 레지스터 55: b register 56: c register. 57 : O 레지스터 58 : SNP 프래그 57: o register 58: SNP flag. 59 : 카피프래그 81 : 클록레지스터 59: copy flag 81: clock register. 84 : 유효시간프래그 85 : 차순시간프래그 84: effective time flag 85: order time flag. 86 : 타이머논리 87 : 처리기클록 86: timer logic 87: processor clock. 88 : 감산기 90 : 라인 88: subtracter 90: line. 91 : 라인 92 : 인버터 91: line 92: inverter. 93 : 라인 94 : 논리 AND 게이트 93: line 94: logic AND gate. 95 : 라인 96 : 라인 95: line 96: line. [ 발명의상세한설명 ] [The detail description of an invention] 본발명은마이크로컴퓨터를포함하는컴퓨터에관한것으로, 특히시간의존처리를실행할수있는마이크로컴퓨터에응용할수있는것에관한것이다. 마이크로컴퓨터는처리기가다수의동시에발생하는처리간의그처리시간을할당하도록허용하는스케쥴링 (scheduling) 장치를포함하는유럽특허명세서 내에기술된다. 스케쥴된처리대기실행의링크된리스트가형성될수있다. 현재실행중인처리는디스케쥴되어처리는요구될시에스케쥴된리스트에부가함에의해스케쥴되게된다. 예를들어이는 2 개의처리간의메세지전송을초래하여야기하며여기 The present invention relates to the computer including a microcomputer, and it relates to adapt the microcomputer practicing especially, the time dependent processing. A microcomputer is described within EP A including the scheduling apparatus which it allows so that a processor assign the processing time between lots of the processings which at the same time, are generated. The linked list of the scheduled processing wait execution can be formed. Presently, as to the processing enforced, by adding the list which is scheduled when it is scheduled with di and a processing is requested, it is scheduled. For example, as to this, while causing the message transport between the processing of 2 and causing, here when the amount processing

5 K2E-PAT Page 5 에서양처리는메세지전송이발생할시에그들프로그램순차내의대응단에있게되는것이요구된다. 그러나그특허명세서에는처리의스케쥴링이처리를위한특정화된시간에따라야기될수있는시간의존처리를기술하고있지않다. 본발명의목적은시간의존처리를실행하는데사용하기위한개량된마이크로컴퓨터를제공하는데에있다. 본발명의또다른목적은처리기가다수의처리들간의그처리시간을할당할뿐만아니라장치가하나이상의처리에대하여시간의존파라메터에응답하게하도록, 다수의동시에발생하는처리들을스케쥴링하기위한장치를가진개량된마이크로컴퓨터를제공하는데에있다. 터엄 (tenm) 마이크로컴퓨터가일반적으로집적회로방식을기초로한작은크기의컴퓨터에관한것이지만여기에는컴퓨터가얼마나작아야하는어떠한제한은없다. 본발명은메모리를포함하는마이크로컴퓨터와동시에일어나는다수의처리를실행하도록배열된처리기가제공되며, 각각의처리는처리기에의해순차적실행을위한다수의명령어로구성된프로그램을가지며, 상기처리기는 1) 다수의레지스터들과이레지스터들과상호데이타를전달하는데사용하기위한데이타전달장치와, 2) 각각의명령어를입수하고명령어와연관된값을처리기레지스터중의하나에로딩 (loading) 하기위한장치와, 3) 처리기가명령어에따라작동하도록수신된각각의명령어에응답하는레지스터와상기데이타전달장치를제어하기위한제어장치를구비하며, 어기에서마이크로컴퓨터는, a) 다수의동시에일어나는처리들간의처리기의처리시간을할당하기위한스케쥴링장치를포함하되, 상기스케쥴링장치는처리가처리기에의해실행을위해준비할때를지시하는장치를포함하고있으며, b) 처리시간제어장치를포함하며이장치는 1) 처리들이처리기에의해실행하기의해준비되기전에예정된시간을대기하는처리들의적어도하나이상의타이머콜렉션을형성하는하나이상의처리들을식별하기위한장치와, 2) 상기타이머콜렉션내의그처리혹은각각의처리가실용준비로되는스케쥴링시간을가리키기위한장치와, 3) 상기타이머콜렉션에하나이상의처리들을부가하기위한장치와, 4) 상기타이머콜렉션으 the message transport is generated, is required what has in the corresponding edge within they program consecutive. But in the patent specification, the scheduling of a processing does not describe the time dependent processing which can be caused according to the specified time for a processing. The object of the present invention has in the stem providing the improved microcomputer for using to practice the time dependent processing. As to the purpose of anothering of the present invention, in order that a processor assigns the processing time between a plurality of processings the apparatus answers to the time dependent parameter about one or more processings, the apparatus has in the stem providing the improved microcomputer having the apparatus for scheduling lots of the processings which at the same time, are generated. It relates to the term (tenm) microcomputer, generally, the computer of the small size based on the integrated circuit type, but any limit in which a computer has to be here in small does not have. The present invention is to be equipped with the apparatus, respected in one of processor register data delivery apparatus, for using a processor delivers the registers of 1) multiple and E registers and mutual data each processing has the program comprised of the command of the multiple for the sequential execution with a processor the processor which is arranged it practices lots of the processings which at the same time, occur with the microcomputer including the memory is provided and the value obtaining 2) each command and is related to a command with the loading (loading) below and the apparatus, for distinguishing one or more processings forming one or more timer collections at least of the processings queuing the time which is scheduled this apparatus is prepared 1) processings are according to it practices with a processor it includes the b) processing time control device the scheduling apparatus includes the apparatus for indicating the time which a processing prepares with a processor for an execution a microcomputer includes the scheduling apparatus for assigning the processing time of a processor between the processings which at the same time, occur of the a) multiple in a place for angling it includes the register responding to each command which is received 3) processor operates according to command and the control device for controlling data transfer device and the apparatus, for meaning the processing within 2) timer collection or the scheduling time when each processing consists of the utility preparation and the apparatus, for adding one or more processings to 3) timer collection and the apparatus for removing a processing from 4) timer collection.

6 K2E-PAT Page 6 로부터처리를제거하기위한장치를포함한다. 양호하게는콜렉션내에서의그처리혹은각처리의스케쥴링시간에의존하여시간정렬된순차를형성하도록상기타이머콜렉션내의처리를정렬하는데장치가배열된다. 양호하게는콜렉션내의가장빠른스케쥴링시간을가져그로인하여콜렉션내의제 1 의처리를형성하는상기타이머콜렉션내의처리를가리키기위하여장치가제공되며이장치는어드레스가능한메모리위치를구비할수있다. 양호하게는상기메모리는처리와연관된변수를기록하기위한위치를포함하는다수의어드레스가능한위치를가지는작업공간을각각의처리가제공되며, 여기에서상기처리기레지스터중의하나는현재처리의작업공간의어드레스를식별하는작업공간포인터값을보유하도록배열된다. 양호하게는각각의처리에대한작업공간은타이머콜렉션내의연속처리에대한포인터값을보유하기위한링크장치를포함하되, 이링크장치는처리가콜렉션내의다음처리를가리키도록타이머콜렉션내에있을경우사용되어지게되어그로인하여처리들의링크된타이머리스트를형성한다. 양호하게는각각의처리작업공간의상기링크장치는처리가현재타이머리스트상의최종스케쥴링시간을가진처리임을가리키는특정값을보유하도록배열된다. 양호하게는각각의처리에대한작업공간은처리의스케쥴링시간을가라키기위한어드레스가능한위치를포함한다. 양호한실시예에서, 마이크로컴퓨터는다수의우선권중의하나를각각의처리로할당하기위한장치를포함하며상기시간제어장치는하나이상의상기타이머콜렉션을형성하기위한장치를포함하되, 각각의타이머콜렉션은또다른타이머콜렉션내의처리의것과는다른공통우선권의처리를가진다. 양호하게스케쥴링장치는 ; 1) 처리기에의해실행되어지는현재처리를가리키기위한장치와, 2) 처리기에의해실행을대기하는스케쥴된콜렉션을형성하는하나이상의처리들을식별하기위한장치와, 3) 상기스케쥴된콜렉션에하나이상의또다른처리들을 In order to form the consecutive which is good, depends on the scheduling time of the processing within a collection or each processing and is time-arranged the processing within the timer collection is arranged but the apparatus is arranged. This apparatus in order to indicate the processing within the timer collection which is good, has the most fast scheduling time within a collection and forms the first processing within a collection due to that, the apparatus is provided provide the memory location canning be addressed. In order to hold the workspace pointer value distinguishing the address of the work space of a processing one of processor register each processing is the work space had provideds are the plurality of location canning be addresseds including the location for recording the variable related to a processing arranged. The work space about each processing is good comprises the linkage for holding the point value about the consecutive processing within the timer collection. In case of having within the timer collection a processing is used and so that a processing indicate the next processing within a collection it forms the linked timer list of the processings this linkage due to that. The linkage of each processing work space is good is arranged the linkage of each processing work space is good holds the definite value in which a processing indicates a processing having the final scheduling time on the timer list. The work space about each processing is good provides the location which takes good care of the scheduling time of a processing with the edge rocky canning be addressed. In the good embodiment, while including the apparatus for assigning one of microcomputer is lots of the prioritieses to each processing, a timer includes the apparatus for forming one or more timer collections. Each timer collection has the processing of the common priority different from the thing of the processing within the another timer collection. The scheduling apparatus it is good includes the apparatus for indicating the performed present processing, the apparatus for distinguishing one or more processings forming the scheduled collection queuing an execution with 2) processor, the apparatus, and the order treatment basin time apparatus for indicating the next processing within the scheduled collection

7 K2E-PAT Page 7 부가하기의한장치와, 4) 처리기에의해실행되어질상기스케쥴된콜렉션내의다음처리를가리키는차순처리지시기장치를포함하되, 처리기는, 처리기에의해상기현재처리의실행을종결하도록선택된명령에응답하고처리가지시된현재처리로되도록상기차순처리기지시기장치에응답하도록배열되어, 이로인하여처리기가다수의동시에발행하는처리들간의그처리시간을할당하도록작동된다. 양호하게는스케쥴된콜렉션을역시링크된리스트이다. 본발명은또한전술한바와같이다수의상호접속된마이크로컴퓨터를가진회로망이며, 이들각각은다른장치상의비슷한링크에로의접속에의해접속된하나이상의통신링크로제공된통신채널을갖게되어이로인하여메세지전송이다른마이크로컴퓨터상의동시에발생하는처리들간의동기화로되도록허용한다. 양호하게는마이크로컴퓨터는다수의교호시간관계된성분을가진처리를실행하도록배열되는데, 상기마이크로컴퓨터는각각의성분과연관된시간을지시하는장치와각각의성분과연관된시간을테스트하는장치및어떤성분과연관된가장이른시간이현재발생되었는가를결정하는장치로제공된다. 양호하게는, 처리기를시간주기의만료후에현재처리를실행하는것을정지하게하고스케쥴된콜렉션에처리를부가시킴에의해처리를재스케쥴하는상기시간주기에응답하는장치및처리의실행을위한시간주기를열거하기위하여제공된다. 본발명의실시예는첨부된도면을참조하여실시예를통하여더욱명료히기술될것이다. 이실예에기술된마이크로컴퓨터는외부통신을허용하는링크와마찬가지로 RAM 의형태로프로세서와메모리양자를가지는단일실리콘칩형태의집적회로방식을포함한다. 마이크로컴퓨터의주소자는 P 형의잘보상된 MOS 기법 (P-well complementary MOS technology) 을사용한제 1 도에도시된단일실리콘칩 (11) 이다. 중앙처리장치 ( 이하 CPU 라칭함, 12) 는약간의판독전용메모리 ( 이하 RAM 이라칭함 13) as described above performed by 4) processor with : 1) processor. In order to respond to the command which is selected in order to conclude the execution of a processing with a processor and a processor answers to the order processor indicator apparatus to the processing in which a processing is indicated it is arranged. Due to this, a processor is in operation in order to assign the processing time between lots of the processings which at the same time, it publishes. The apparatus is according to add one or more another processings to the collection scheduled with 3) above statement. It is the list which also is the collection which is good, is scheduled linked. As described in the above, it has the communications channel provided to one or more communications links connected with the connection of the similar link on the dissimilar apparatus and C network C, theses which the present invention has moreover allow lots of the interconnected microcomputers for a synchronization between the processings which at the same time, are generated on the microcomputer in which due to this, the message transport is different as as possible. In order to practice the process having the component connected with a plurality of alternating times it is arranged. A microcomputer is provided to the apparatus, for indicating the time related to each component the apparatus for testing the time related to each component and the apparatus for determining whether the name time related to any kind of component was occurred present or not. Processing are provided the time period for the execution of the apparatus for answering to the time period which reschedules a processing it adds a processing to the collection which is a processor scheduled the apparatus stop the apparatus practice the process after the expiration of the time period thing is good and processing are listed. The embodiment of the present invention will be more *** described through the attached embodiment. The microcomputer described in the bilocular example provides the integrated circuit type having a processor and bilateral memory like the link allowing the wide area network in the form of RAM of the single silicon chip-type. The addresser of a microcomputer is the single silicon chip (11) shown in Figure 1 using the well compensated MOS technique (P-well complementary MOS technology) of P-type. The central processing unit (12 it is below CPU) is connected to the memory interface (14) which is controlled with the interface control logic (15) while the read only

8 K2E-PAT Page 8 도제공되며인터페이스제어논리 (15) 에의해제어된메모리인터페이스 (14) 에접속된다. CPU(12) 는산술논리유니트 ( 이하 ALU 로칭함 ), 레지스터및제 2 도에좀더자세히도시된데이타경로와조합되어있다. CPU(12) 와메모리인터페이스 (14) 는칩 (11) 상의소자들간에상호접속하는버스 (16) 에접속된다. 마이크로컴퓨터는랜덤억세스메모리 ( 이하 RAM 으로칭함, 19) 나 ROM(20) 이제공되며칩상의다량의메모리는 1K 바이트보다작지않아서처리기 (12) 가외부메모리없이도동작할수있다. 양호하게는칩상의메모리로적어도 4K 바이트이다. 외부메모리인터페이스 (23) 는임의의외부메모리에접속하기위한다수의핀 (24) 에접속되도록제공된다. 마이크로컴퓨터라회로망을형성하는다른컴퓨터에링크되어지도록하기위하여다수의일련링크 (25) 가각각입력과출력관들 (26 및 27) 로제공된다. 일련링크의입출력핀은자체의단일선에의해제 2 도에도시된바와같은또다른마이크로컴퓨터상의일련링크의대응입출력핀에분할되지않는단일방향으로각각접속되어있다. 각각의일련링크는처리스케쥴논리를구비한동기논리유니트 (10) 에접속된다. 본실시예는유럽특허출원서제 호와계류중인 PCT 특허출원제 PCTGB 84/00379 호에기술된마이크로컴퓨더의개량이다. 설명이반복되는것을피하기위하여, 그마이크로컴퓨터의구조및동작에대한상세한설명은생략되겠지만상술한특허출원서들내의설명은본원발명을설명하는데참조하여기술된다. 본실시예는개량된형태의트랜스퓨터 (Transputer 상표 INMOS 국제 PIC) 마이크로컴퓨터가제공된다. 이는타이머제어가제공되어, 처리들은실행이형성되기전에특정화된시간을대기하는처리들의타이머리스트와타이머데이타에의존하여실행하게된다. 마이크로컴퓨터에전체배열은일반적으로상술한특허출원서들에기재된것과비슷하다. 아래주어지는설명에는상술한특허출원서내의실시예에상응하는부분에는유사한명칭으로주어진다. 메모리는포인터에의해지시될수있는어드레스가능한위치를가지는다수의처리작업공간이제공된다. 메세지통신은동일마이크로컴퓨더상의통신을처리하는처리의경우에있어서 memory (13 it calls because of being below RAM) of a little is provided. The CPU (12) is combined with data path shown in the arithmetic logic unit (it calls below ALU), and the register and Figure 2 in detail. The CPU (12) and memory interface (14) are connected to the bus (16) interconnected between the devices on the chip (11). As to a microcomputer, the processor (12) can operate without the external memory the memory of the large amount of on chip is not smaller than 1K byte the RAM (19 it calls below RAM) or the ROM (20) is provided. It is at least, 4K byte to the memory of on chip is good. The external memory interface (23) is provided the external memory interface (23) is connected to lots of the pin (24) for connecting to the arbitrary external memory. Lots of the series link (25) is provided to the respective input and power tube (26 and 27) it is linked to the dissimilar computer forming C network C it is a microcomputer. The input output pin of the series link is connected to the correspondence input output pin of the series link on another microcomputer like being illustrated with the single-filar of an itself in Figure 2 to the one-way which is not divided. Each series link is connected to the motive logical unit (10) equipped with the processing schedule logic. This embodiment is the reorganization of the microcomputer which it moors and which is described in the PCT PCTGB 84/00379 A and application EP A. In order that it avoids that a description is recapitulated, the detail description about the structure of the microcomputer and operation be skipped but the above-described description of the Patent Application smell of preilla illustrates the present invention but it refers and it is described. Provided is the transputer (transputer trademark INMOS international PIC) microcomputer which this embodiment is improved of a form. As to this, the timer control is provided. It depends on the timer list and timer data of the processings queuing the time which is specified before an execution is formed and processings enforce. The total array is similar in a microcomputer to the thing which is written in above-described Patent Applications generally. In the given with lower part description, it is given in the part corresponding to the embodiment within the above-described Patent Application to the similar name. Provided is lots of the processing work space having the location which can be indicated with a pointer canning be addressed the memory. The message communications can become through the channel having in case of the processing

9 K2E-PAT Page 9 어드레스가능한메모리위치를구비한채널을통하여될수있다. 서로다른마이크로컴퓨터들간의통신을처리하는처리를하기위해입, 출력채널은일련링크내에제공되며, 이러한채널들은메모리내에제공된소프트채널에비슷한방식으로어드레스될수있다. 상술한개량을수행하기위하여, 마이크로컴퓨터의구조및동작에있어다양한변형이필수적이며, 후술되는설명은그러한견지에서상기변형이그러한개량을이루어지게하기위하여상술한특허출원서에실예에서와같이, 기술된실예의특정워드길이는 16 비트이지만 8, 16, 24, 32 와같은다른워드길이가사용될수있다는것을인지하게될것이다. 더우기본원의경우에있어서, 다른워드길이마이크로컴퓨터는제 8 도에도시된바와같은동일회로망내에접속될수있어이는그들은독립적인워드길이를무시하고서로통신될수있다. 각각의포인터는단일워드이며 2 개의보충신호의값으로취급된다. 이뜻은단일포인터의 MSB 가 1 인경우 MSB 는양성의수를표시하는모든잔여비트로써음성을취하게된다. 만일 MSB 가인경우포인터의모든비트는양성값을나타내는바와같이취해진다. 이는그들의수치상에사용되는방식으로표준비교기능을포인터의값에사용되어지도록한다. 확실한값은소정의특이한작용이통신채널의상태에특별히요구되는것을가리키도록보존되는포인터와같이사용되지는않는다. 아래주어지는설명에서의명칭들은이러한값이나다른값들을설명하는데사용된다. 즉 Most Neg : 거의음성인값 (MSB 가 1 이고모든다른비트는 0) Most Pos : 거의양성인값 (MSB 가 0이고모든다른비트는 1) processing a communications on the identical microcomputer and includes the memory location canning be addressed. Below harm mouth, and the output channel are the processing processing a communications between the each other dissimilar microcomputer provided within the series link. And this channels can be addressed to the similar one room type in the soft channel provided to memory. In order that the above-described reorganization is performed, the deformation which is various as to a structure and operation of a microcomputer an essential, the description which will be described later recognizes that the room etiquette special word length described in that point of view in the Patent Application which describes in detail so that the deformation be such reorganization made an instantiation is 16 bit but the other word length like 8, 16, 24, 32 can be used. Besides, it has in case of the present application. The other word length microcomputer can be connected within the identical C network C like being illustrated in Figure 8 and it can ignore the independent word length and this they can be communicated. Each pointer is the single word and it is treated as the value of the supplement signal of 2. The voice is become as all remaining bits indicating the number of MSB is a positivity this meaning MSB of the single pointer is 1s with the withdrawal crab. In case MSB is, as shown the positive value, all bit of a pointers are taken against. This is the standard comparison function used as the mode used for their numericals for the value of a pointer. The certain value is not used like the pointer which is preserved in order to indicate that the predetermined peculiar action is specially required from the state of the communications channel. The names at the given with lower part description illustrate this value or the dissimilar values but the names at the given with lower part description are used. That is Most Neg:nearly, the value which is the voice(dissimilar bits is 0 MSB is 1) 장치 TRUE : 1 Apparatus TRUE: 1. 장치 PALSE : 0 Apparatus PALSE: 0. 비처리 P : Most Neg Nonprocessing P : Most Neg. 구동 P : Most Neg+1 Drive P : Most Neg+1. 대기 P : Most Neg+2 Atmosphere P : Most Neg+2. Most Pos:nearly, bisexual person value(other bits is 1 MSB is 0)

10 K2E-PAT Page 10 준비 P : Most Neg+3 시간세트 P : Most Neg+1 시간비세트 P : Most Neg+2 시간세트 P 및시간비세트 P 에대한특정값은구동 P 혹은대기 P 와같은위치내에결코사용될수없으므로 Most Neg+1 및 Most+2 의이중사용으로인한혼란을피할수있다. 전술한특허출원서의실예에서와같이, 각각의처리는처리에의해수동조작된국부변수와일시적인값을유지하는데사용된메모리내의백터워드로구성된작업공간을가지게된다. 작업공간포인터 ( 이하, WPTR 이라칭함 ) 는처리작업공간에대한셀위치를지시하는데사용된다. 각각의처리는 LSB 가처리의우선권을지시하고 MS15B 가처리작업공간을식별하는메모리내의워드를지시하는 " 처리설명기 " 에의하여식별될수있다. 이러한경우에있어서, 각각의처리는제 6 도에도시된형태의 " 처리설명 " 에의해동일시될수있다. LSB 는처리의우선권을지시하고 MSB 15 비트는처리작업공간을동일시하는메모리의워드를지시한다. 본실예에있어서, 마이크로컴퓨터는각각의처리에대하여 2 개의가능우선권중의하나를배당한다. 고우선권처리는지정 Pri(designation Pri)=0 이주어지며저우선권처리는지정 Pri=1 을가진다. 그러므로각각의처리설명기는작업공간포인터 WPTR 의 " 비트와이즈 OR"(bit wise OR) 와처리우선권 Pri 를취하므로써형성되는단일워드를포함한다. 유사하게작업공간포인터 WPTR 은 NOT 1 과처리설명기의 " 비트와이스 AND" 를형성함에의해처리설명기로부터얻어진다. 처리의우선권은 1 과처리설명기의 " 비트와이즈 AND" 를형성함에의해얻어진다. [CPU 데이타경로및레지스터 ] 중앙처리장치 (12) 및그작동은제 2 도를참조하여더욱상세히설명될것이다. 편의상이는제 2a 및제 2b 도로분리되었지만각각은레지스터세트및데이타경로를형성하도록같이결합된다는것을주지하라. CPU(12) 는산술논리유니트 (ALU ; 30) 과 X 버스, Y 버스, Z 버스및양방향성데이타버스 (31) 에접속된다수의데이타레지스터를가진다. 레지스터들의작동과버스들에로의그들의상호접속은 (32) 에서도식적으로나 Preparation P : Most Neg+3. Time set P : Most Neg+1. Time ratio set P : Most Neg+2. The definite value for the time Bissett P/6 and time set P/6 can avoid a disruption due to the double-spending of the Most Neg+1 and Most+2 since being ever used within a location such as the drive P/6 and atmosphere P/6. Each processing has the work space consisting of the vector word of in memory maintaining the local variable which is manually operated and the temporary value with a processing but is used the instantiation of the above-described Patent Application. Workspace pointer (hereinafter, the WPTR Lee RaChing box) are used when the cell position about the processing task space is indicated. Each processing can be discriminated with "the processing descriptor" indicating the word of in memory in which LSB indicates the priority of a processing and MS15B distinguishes the processing task space. It is like that. In that case, each processing can be regarded with "the processing description" shown in Figure 6 of a form. LSB indicates the priority of a processing and the MSB 15 bit indicates the word of the memory of regarding in the same light with the processing task space. One of microcomputer as to this instantiation, is the available priority of 2 about each processings are assigned. As to the high priority Keown processing, the base priority processing has the designation Pri=1 while the designation Pri =0 is given. Therefore, each processing descriptor provides the single word formed with "the bitwise OR" (bit wise OR) and processing priority Pri of the workspace pointer WPTR as the as ***. Similarly, the workspace pointer WPTR is obtained from the processing descriptor by forming "the bit wide area information service/server AND" of the NOT 1 and processing descriptor. The priority of a processing is obtained by forming "the bitwise AND" of 1 and processing descriptor. [The CPU data path and register] The central processing unit (12) and operation will be more circumstantially explained with reference to Figure 2. The offset dissimilarity was back separated with the 2a and 2b but each is well-known that each is together combined in order to form the register set and data path. The CPU (12) has the arithmetic logic unit (ALU : 30) and X bus, Y bus, and data register connected to the bidirectional data bus (31) of the multiple and Z bus. Their interconnections (32) of the operation of the registers and buses are controlled with lots of the switches which it

11 K2E-PAT Page 11 타낸다수의스위치들에의해제어되어 ROM(13) 내에함유된마이크로명령어프로그램으로부터취출된신호들에의해제어된다. CPU 와메모리간의통신은데이타버스 (31) 과마찬가지로메모리인터페이스 (14) 로안내하는단일방향성어드레스경로 (33) 를통하여이루어진다. 상술한특허출원서들에서와같이, 각각의명령어는 8 비트로구성되어있다. 4 비트는명령어의요구된기능을나타내고 4 비트는데이타에대하여할당된다. 처리를위한프로그램순차로부터취출된각각의명령어는명령어버퍼 (34) 로인가되어 2 명령어는디코더 (35) 에의해디코드된다. 디코더 (35) 의출력은상태멀티플렉서 (36) 를통하여마이크로명령어 ROM(13) 을어드레스하기위하여사용된마이크로명령어레지스터 (37) 에인가된다. 명령어버퍼 (34), 디코더 (35), 상태멀티플렉서 (36), MIR(37), 마이크로명령어 ROM(13) 및스위치들 (32) 의동작은일반적으로상술한특허출원서및유럽특허출원서제 호내에기술되어있다. 본실시예가 2 세트의처리들로취급하는데배열되므로써, 그러한우선권 0 과그러한우선권 1,2 개의레지스터뱅크가제공된다. 레지스터뱅크 (38) 는우선권 1 처리에대하여제공되며비슷한레지스터뱅크 (39) 는고우선권 0 처리에대하여제공된다. 양자의레지스터뱅크는 X, Y, Z 및데이타버스에유사하게접속된비슷한세트의레지스터를갖는다. 간단히하기위하여, 레지스터및그들에의접속은오직레지스터뱅크 (38) 에대하여만자세히도시되어있다. 특정우선권들에게로할당된 2 개의레지스터뱅크에부가하여, CPU 는콘스탄트박스 (40), 레지스터뱅크선택기 (41) 및우선권 0 및 1 처리의양자에공통인제 2a 및 2b 도에지시된다수의다른레지스터를포함한다. 그제리스터들은아래와같다. Image 1 not available 우선권 0 처리들에대한레지스터 (39) 의뱅크는우선권 1 처리들에대하여전술하였던것과같다. 설명에있어서써픽스 (suffix)[1] 은우선권 1 뱅크에관한레지스터를지시하고써픽스 [0] 는레지스터가우선권 0 뱅크에관한것을지시한다. 우선권이알려지지않는곳에서, 써픽스 [Pri] 는적절한우선권처리의레지스터가사용된다. 레지스터들은이경우에있어서통상 1 비트프래그 (47, schematically shows and it is controlled with signals taken out from the micro instruction program contained within the ROM (13). A communications between the memory and CPU are made through the unidirectional route of address (33) guiding to the memory interface (14) like data bus (31). Each command is comprised of 8-bit above-described Patent Applications. Four bits is allocated about data four bits expresses the required function of a command. 2 command is decoded with the decoder (35) each command taken out from the program consecutive for a processing is applied to the instruction buffer (34). The output of the decoder (35) is applied in the micro instruction register (37) which is used the output of the decoder (35) addresses the micro instruction ROM (13) through the state multiplexer (36). Generally the operation of the switch (32) and instruction buffer (34), the decoder (35), the state multiplexer (36), the MIR (37), the micro instruction ROM (13) is described within the Patent Application and application EP A. Provided is such register bank of that priority 0 and 1,2 priorities it is arranged this embodiment handles as the processings of 2 set. As to the register bank (38), while being provided, the similar register bank (39) is provided about the register bank (39). The register bank of both sides has the register of the similar set which similarly is connected to X, Y, and Z and data bus. In order that it simplifies, the register and their connections are only in detail illustrated about the register bank (38). CPU in addition to the register bank allocated to specific priorities of 2 provides the dissimilar register which is indicated in 2b drawing of the multiple and the 2a which is the common in the constant box (40), and both sides of the register bank selector (41) and priority 0 and 1 processing. The Jerry stirs are as follows:. The bank of the register (39) about priority 0 processings are the same in what it described in the above about priority 1 processings. As to a description, the PICS (suffix) [1] indicates the register about the priority 1 bank and the register the PICS [0] gives the thing about the priority 0 bank an indication. In the place which the priority does not inform, the register of the proper priority processing the PICS [Pri] is employed. In this case, generally, registers are the word length which is 16 bits which become distant from single bit

12 K2E-PAT Page 12 48, 58 및 59) 로부터멀어진 16 비트들인워드길이이다. A, B 및 C 레지스터들 (54, 55 및 56) 은가장산술적이고논리적인동작에대한소스와목적지이다. 그들은겹쳐지게된다. 더우기, 뱅크 (38 및 39) 의각각의레지스터및프래그는유효시간프래그 (84), 차순시간레지스터 (85) 및클록레지스터 (81) 로부터입력을수신하도록배열된타이머논리 (86) 를포함한다. 타이머논리 (86) 는제 3 도를참조하여더욱상세히설명될것이다. 클록레지스터 (81) 는처리기클록 (87) 으로부터입력을수신한다. 레지스터뱅크각각에대한타이머논리 (86) 는제 1 도의타이머 (9) 를구성한다. 레지스터뱅크 (38 및 39) 양자의 0 레지스터 (57) 는디코더 (35) 에접속되어양자의우선권처리들에대하여 0 레지스터내로인가되는명령어부분은디코더가적절한마이크로명령어를발생하는데사용되게한다. SNP 프래그 (58) 및양자의우선권뱅크의 COPY 프래그 (59) 는상태멀티플렉서 (36) 에또한접속되어마이크로명령어는언제든지프로세서에의해발생될수있는다음작용을결정하는데양자의우선권처리에대한이러한프래그의셋팅을고려할수있게된다. 작업공간포인터 (WPTR) 의처리가기초로서사용되어그것으로부터처리의국부변수가어드레스될수있으므로써, 때때로작업공간포인터에의해지시되는위치로부터의오프셋값을계산하는데이처리가필수적으로된다. 콘스탄트박스 (40) 는 Y 버스에접속되어마이크로명령어 ROM(13) 의제어하에 2 버스상에일정한값이주어지게해준다. 이들은처리작업공간내의위치를오프셀하도록지시하는데사용될수있다. 레지스터뱅크들 (38 혹은 39) 의하나혹은다른하나의선택을하기위하여, 레지스터뱅크선택기 (41) 는 PRI 프래그 (47), 처리우선권프래그 (48) 및마이크로명령어 ROM(13) 으로부터의입력들을가진다. 레지스터뱅크선택기로부터의출력은상태멀티플렉서 (36), 디코더 (35) 및스위치 (32) 에접속된다. 마이크로명령어 ROM(13) 의출력에따르면, 선택기는 PRI 프래그 (47) 혹은처리우선권프래그 (48) 에의해지시된레지스터뱅크를선택할것이다. flags (47, 48, 58 and 59). As to A, and B and C registers (54, 55 and 56), most and it is a source and destination location about the logical operation. They are overlapped. Besides, each register and flag of bank (38 and 39) provide the timer logic (86) which is arranged in order to receive an input from the effective time flag (84), and the order time register (85) and clock register (81). The timer logic (86) will be more circumstantially explained with reference to Figure 3. The clock register (81) receives an input from the processor clock (87). The timer logic (86) about the register bank comprises the timer (9) of Figure 1. 0 register (57) of register bank (38 and 39) both sides are connected to the decoder (35) and it is generated the micro instruction in which a decoder is fit but the command part applied about the priority processings of both sides within 0 register is used. The micro instruction considers the setting of this flag about the priority processing of both sides the COPY flag (59) of the priority bank of the SNP flag (58) and both sides determine an action the COPY flag (59) of the priority bank of the SNP flag (58) and both sides can be any time generated with a processor the COPY flag (59) of the priority bank of the SNP flag (58) and both sides are moreover connected to the state multiplexer (36). The processing of the workspace pointer (WPTR) is used as the basis and the local variable of a processing can be addressed from that. In that way the offset value from the location from time to time indicated with the workspace pointer is calculated but it becomes obligatorily this processing. The constant box (40) is connected to Y bus and the fixed value is given the micro instruction ROM (13) on 2 bus. These indicate the location of the processing task Gong GanNae with the off-cell river channel lock but the location can be used. It respects to do one of the register bank (38 or 39) or dissimilar one selection. The register bank selector (41) has the PRI flag (47), and an input from the processing priority flag (48) and micro instruction ROM (13). An output from the register bank selector is connected to the state multiplexer (36), and the decoder (35) and switch (32). According to the output of the micro instruction ROM (13), a selector will select the PRI flag (47) or the register bank indicated with the processing priority flag (48).

13 K2E-PAT Page 13 타이머논리 (86) 는레지스터뱅크의각각에대하여비슷하며제 3 도에더욱상세히도시된다. 논리유니트 (86) 는차순시간레지스터로부터라인 (89) 상에서입력을수신하도록배열된감산기 (88) 를구비하며이시간값은클록레지스터 (81) 로부터라인 (90) 상에공급된시간값으로부터감산기 (88) 내에서감산된다. 다른 MSB 는논리 AND 게이트 (94) 에로라인 (93) 상에서신호를공급하는인버터 (92) 에도라인 (91) 상에서의출력상에제공된다. 게이트 (94) 는또한유효시간프래그 (84) 로부터라인 (95) 상에서입력을수신한다. AND 게이트 (94) 는상태멀티플렉서 (36) 에인가되는라인 (96) 상의출력을제공한다. 라인 (96) 상의신호는 " 타이머요청 " 신호라불려지며처리기를타이머리스트의상부로부터처리가제거되게하도록배열되어이는실행을준비하게된다. 제 3 도에도시된논리도는 2 개의상태가동시에만날때라인 (96) 상의 " 타이머요청 " 신호가오직출력되도록배열된다는것이인지될것이다. 첫째로, 유효시간프래그 (84) 는값 1 에세트되어야만하고클록레지스터 (81) 에의해지시된시간은차순시간레지스터 (85) 에의해지시된시간과같거나그이후에중의어느한경우이어야만한다. 감산기 (88) 는클록레지스터 (81) 에보유된값으로부터차순시간레지스터 (85) 내에포함된값을감산하는데사용되며만일그러한감산의결과가음성 (-) 의수일경우 MSB 는상기에서참조된바와같은 2 개의보충표시된값의사용에기인하여 1 이될것이다. 이러한이유때문에, 라인 (91) 은감산으로부러기인한 MSB 를출력하는데배열되며, 감산의결과가양성의결과치를제공하여그로인하여라인 (91) 상에 0 비트를초래하는경우, AND 게이트 (94) 가오직 " 시간요청 " 을제공하도록인버터 (92) 가요구된다. The timer logic (86) is more circumstantially illustrated about each of the register bank in Figure 3 the timer logic (86) is similar. This temporal value is reduced from the temporal value supplied from the clock register (81) on the line (90) in the subtracter (88) the logical unit (86) includes the subtracter (88) which is arranged the logical unit (86) receives an input from the order time register on the line (89). Dissimilar MSB is provided to the inverter (92) supplying a signal to the logic AND gate (94) on the line (93) on an output on the line (91). The gate (94) moreover receives an input from the effective time flag (84) on the line (95). [ 처리작업공간에대한메모리할당 ] [The memory allocation about the processing task space] 전술한특허출원서들내에서기술한실시예에서와같이, 마이크로컴퓨터는다수의처리들간의그시간을다같이분할하는다수의처리들을수행한다. 다같이수행되는처리들은동시에발생하는처리로불려지며어떠한시간에서나실행되어지는처리는전류처리로불려진다. 각각의동시에발생되는처리는처리에의해수동조작되는국부변수및일시적인값을보유하기위한작업공간으로불려지는메모리의영역을가진 A microcomputer performs a plurality of processings which altogether divides the time between a plurality of processings the embodiment described in the above-described Patent Application smell of preilla. As to altogether performed processings, at the same time, the processing which is performed in any time while being called as the generated processing is called as the current process. The processing which at the same time, is generated has the domain of the memory of being called as the work space for possessing the local variable which is manually operated and the temporary

14 K2E-PAT Page 14 다. 작업공간의제 1국부변수의어드레스는작업공간포인터 (WPTR) 에의해지시된다. 이는제 3 도에서 4 개의동시에발생되는처리들인처리 L, M, N 및 O 가작업공간 (60, 61, 62 및 63) 을가진다. 작업공간 (60) 은더욱상세히도시되어있으며, WPTR 레지스터 (51) 로유지된작업공간포인터는이예에서 으로써지시된어드레스를가지는단일워드위치인 O 위치에로지시된다. 이처리에대한다른국부변수는작업공간포인터에의해지시된워드로부러양성오프셋어드레스로어드레스된다. O 위치로부터작은음성오프셋을가지는약간의작업공간위치는스케쥴하기위하고통신목적을위하여사용된다. 이러한실예에있어서, 3 개의부가워드위치들 (65, 66, 67, 68 및 69) 은 WPTR 에의해지시된 O위치들이하로각각 1, 2, 3, 4 및 3 의음성의오프셋을가지고도시되어있다. 이러한 5개의위치는아래와같다 : value with a processing. The address of the first local variable of the work space is indicated with the workspace pointer (WPTR). As to this, in Figure 3, the processing L/6, which is the processings which at the same time, are generated of 4 M, and N and O have work spaces (60, 61, 62 and 63). The work space (60) is more circumstantially illustrated. And the workspace pointer maintained by the WPTR register (51) is indicated in O location which is the single word location having the address which in this example, is indicated as As to the other local variable about this processing, to swell with the word furnace, indicated with the workspace pointer it is addressed to the positivity offset address. It respects to schedule and the work space location of the little having the small voice offset from O location is used for the communications purpose. As to this instantiation, in word locations (65, 66, 67, 68 and 69), the part of 3 is illustrated having the offset of the voice of the respective 1, 2, 3, 4 and 3 less than O locations indicated with WPTR. A location of 5 these is same as those of the lower part : Image 2 not available 위치 (65) 는, 처리가현재처리될시에처리에의해실행되어진다음명령어도포인터 (IPTR) 를보유하도록, 처리가현재처리가아닐경우사용된다. 위치 (66) 는실행을대기하는처리들의열혹은링크-리스트상의다음처리의작업공간포인터를저장하는데사용된다. 위치 (67) 는데이타블록을카피하기위한포인터로서혹은교호입력동작을수행하는처리의상태지시를포함하는데통상사용된다. 위치 (68) 는실행을위해스케줄되어지기전에예정된시간을대기하는처리들의링크된타이머리스트상에다음처리의작업공간포인터를기억하는데사용되며이는또한교호의타이머입력작동을수행하는처리의상태를지시하는데사용된다. 위치 (69) 는시간을지시하는데사용되며이후에처리가실행하게된다. 메모리는또한통신을처리하는처리용의워드위치를제공해주며, 제 3 도는소프트채널 (70) 과같이지시된다. [ 주해 (Notation)] [Annotation] 마이크로컴퓨터가특히그기능, 작동및진행순서를참조하여작동하는방식의주어지는설명에있어서, 주해가 OCCAM( 상표 INMOS 국제 P1C) 에언어에의해사용되었다. 이언어는 1983 년영국의 INMOS 사에의해발행되어분류된편량명칭 " 프로그레 As to the location (65), in order that command hold the pointer (IPTR) after a processing is performed by a processing in the present processing, a processing is used in case of being not present processing. The location (66) stores the workspace pointer of the next processing on the heat of the processings queuing an execution or the link-list but the heat is used. The location (67) is commonly used to imply the state indication of the processing which or performs the alternating input action as the pointer for copying data block. As to the location (68), while being used to memorize the workspace pointer of the next processing on the linked timer list of the processings queuing the time which is scheduled before being scheduled for an execution, it indicates the state of the processing performing moreover, the timer input operation of an alternating but this is used. While the location (69) indicates the time but the time is used, thereafter a processing practices. The memory moreover provides the word location of *** processing a communication. And figure the third is indicated like the soft channel (70). As to the given description of the mode in which a microcomputer operates with reference to especially, the function, and an operation and progress sequence, an annotation was used for the OCCAM (trademark INMOS international P1C) by the language. This language is settled in the piece amount name "the programming manual -OCCAM"

15 K2E-PAT Page 15 밍매뉴얼 -OCCAM" 에정립되어있다. 더우기사용된주해는영국특허출원서 에충분히기술되어있으며, 본원의설명을간편히하기위하여본명세서에서는반복설명않기로한다. 그러나유럽특허출원서 내에기술되어있는사용된주해는여기에서참조하여조합하기로한다. 상술한주해에부가하여, 주어진설명은소정의메모리엑세스진행순서에참조한것으로아레와같이정의된다. At 워드 ( 베이스, N, A) A 를 N번째워드패스트 (past) 베이스에서지적하도록셋트 At 바이트 ( 베이스, N, A) A 를 N번째바이트패스트베이스에서지적하도록셋트 R 인덱스워드 ( 베이스, N, X) X 를 N번째워드패스트베이스값으로셋트 R 인덱스바이트 ( 베이스, N, X) X 를 N번째바이트패스트베이스값으로셋트 W 인덱스워드 ( 베이스, N, X) N 번째워드패스트베이스값을 X로셋트 W 인덱스바이트 ( 베이스, N, X) N 번째바이트패스트베이스값을 X로셋트워드 O 오프셋 ( 베이스, X, N) N 을 X와베이스간의워드수로셋트. in which the INMOS corp. of 1983 year United Kingdom issues and which is classified. The used to be hot annotation is enough described in the application GB A. And it decides to be not in the specification which it respects to conveniently explain the description of the present application the repeted comment. But the used annotation which is described within the application EP A refers and here it decides to assemble. As to the description that is given in addition to the above-described annotation, with referring in the predetermined memory access progress sequence it is defined like ***. It sets At word (the base, N, and A) A/6 are pointed out in N number word fast (past) base. It sets in order to point out At byte (the base, N, and A) A/6 in N number byte fast base. The set with N number word fast base value R index word (the base, N, and X) X/6. The set with N number byte fast base value R index byte (the base, N, and X) X/6. The set with X W index word (the base, N, and X) N number word fast base value. The set with X W index byte (the base, N, and X) N number byte fast base value. The set with the word number between X and the base word O offset (the base, X, and N) N/6. [ 마이크로컴퓨터에의해사용된절차 ] [The procedure which a microcomputer takes] 아래설명에있어서, 다양한다른진행순서 (PROCEDURE) 가참조된다. 아래의 6 개진행순서는처리기의작동설명에사용된다. Dequeue 진행 (RUN) 다음처리개시진행요청조작준비요청조작타이머요청조작블록카피단계삽입단계삭제단계진행순서 " 진행요청조작 " 과 " 준비요청조작 " 그리고블록카피단계는현재계류중인 PCT 를특허출원서제 PCT GB 84/00379 호와유 As to the lower part description, the various and dissimilar progress sequence (PROCEDURE) is referred to. The following 6 the progress sequence is used for the operation description of a processor. Dequeue Progressing (RUN) Next processing initiation. The progressing request manipulation. The preparation request manipulation. The timer request manipulation. Block copy step. Inserting step. Erase step. The progress sequence "the progressing request manipulation", "the preparation request manipulation" and block copy step are circumstantially PCT moored described

16 K2E-PAT Page 16 럽특허출원서제 호내에상세히기술되어있다. 이러한진행순서의정의는본발명에대하여변화되지않으며, 그들이타이머제어에관련되지않기때문에본특허출원서상에서는반복되지않을것이다. 진행순서, "Dequeue" 는현재처리를나열한우선권 "Pri" 스케줄된처리의전단부상에처리를만든다. 만일 Pri=1 이면, 처리가다른처리들이실행되어지도록허용하도록일시적으로정지되어져야만하는시간으로시간슬라이스레지스터 (80) 를세트시킨다. 시간슬라이스의길이는콘스탄트박스 (40) 내의내용중의하나와같게기억된일정시간주기에의해결정된다. within the PCT GB 84/00379 A and application EP A. The definition of this progress sequence is not changed about the present invention. And it has no choice but to be repeated on the Patent Application which they see because of not relating to the timer control. The progress sequence, and "Dequeue" try to produce a processing on the front-end of the processing scheduled with the priority "Pri" enumerates a processing using. If it is Pri=1. It is determined by the predetermined time cycle which is memorized it is the same as that of one of length of the time slice is the content within the constant boxes (40). 1. PROC Dequeue= 1. PROC Dequeue= 2. 순차 2. Consecutive. 3. Wptr 레지스더 [Pri] : =Fptr 레지스터 [Pri] 3. wptr *** [Pri]: =Fptr register [Pri]. 4. 만일 4. If. 5. Fptr 레지스터 [Pri] =Bptr 레지스터 5. Fptr register [Pri] =Bptr register. 6. Fptr 레지스터 [Pri] : =Not 처리.P 6. fptr register [Pri]: the =Not processing. P 7. 참 (true) 7.Truth(true) 8. R 인덱스워드 (Fptr 레지스터 [Pri], 링크.S, Fptr 레지스터 [Pri] 9. R 인덱스워드 (Wptr 레지스터 [Pri], Iptr.S, Iptr 레지스터 [Pri]) : 10. 만일 10. If. 11. Pri = Pri = 시간슬라이스레지스터 : = 클록레지스터 + 시간슬라이스의길이 13. Pri = Pri = 도약 14. Curvet. 진행순서, " 진행 " 은설명기가처리설명기레지스터내에포함된처리를스케줄한다. 이는우선권, 처리를즉시진행을개시하도록한다. 아래에서, 모든라인시작은단순히설명에의한것이며정의의부분을형성하지는않는다. 1. PROC 진행 = 1. PROC progressing =. 2. 순차 2. Consecutive. 3. 처리우선권프래그 : - 처리설명기레지스터 / \ 1 8. R index word (Fptr register [Pri], and a link. S, and the Fptr register [Pri]. 9.R index word (the Wptr register [Pri], the Iptr S, and the Iptr register [Pri]): 12. time slice register: the length of the = clock register + time slice. The progress sequence, and "progressing" schedule the processing in which a descriptor is included within the processing descriptor register. Immediately this discloses a progressing the priority, and a processing. In the lower part, it is a thing by a description and all line beginnings just does not form the part of the definition. 3. processing priority flag: - processing descriptor register / \ 1.

17 K2E-PAT Page Proc Ptr 레지스터 : = 처리설명기레지스터 / \(1 이아님 ) 5. 만일 5. If. 6. (Pri-0) 혹은 (( 처리우선권프래그 =Pri) 그리고 (Wptr 레지스터 [Pri] 비처리.P)) 4. proc Ptr register:the = processing descriptor register / \(it is not 1) 6. (Pri-0) Or ((processing priority flag =Pri) and (Wptr register [Pri] <> nonprocessing. P)) 7. 순차-- 처리를열 (queue) 로더한다. 7. The consecutive -- processing is added to the heat (queue). 8. 만일 8. If. 9. Fptr 레지스터처리우선권프래그 = 비처 9. Fptr register processing priority flag = nonprocessing. P 리.P 10. Fptr 레지스터처리우선권프래그 =Proc 10. Fptr register processing priority flag =Proc Ptr register. Ptr 레지스터 11. 참 11. Truth. 12. W 인덱스워드 (Bptr 레지스터 [ 처리우선권프래그 ], 링크.S Proc Ptr 레지스터 ) 13. Bptr 레지스터처리우선권프래그 : =Ptr 레지스터 14. 참 14. Truth. 15. 순차 -- Pri 1 을방해하는 Pri 0 나혹은 Pri 1 그리고휴지 m/c 12. W index word (Bptr register [processing priority flag], and a link. S Proc Ptr register). 13. bptr register processing priority flag: =Ptr register. 15. The Pri 0, obstructing the consecutive -- Pri 1 or, the Pri 1 and pause m / c/ Pri=Proc Pri 레지스터 16. Pri=Proc Pri register. 17. Wptr 레지스터 [Pri] : =Proc Ptr 레지스터 17. wptr register [Pri]: =Proc Ptr register. 18. R 인덱스워드 (Wptr 레지스터 [Pri], Iptr.S, Iptr 레지스터 [Pri] 19. O 레지스터 [Pri] : =0 : 19. o register [Pri]:=0: 진행순서 " 다음처리개시 " 는현재처리를디스케줄하는데만일거기에또다른진행가능한처리가있을경우, 다음의진행가능한처리를선택한다. 이는만일진행하는또다른우선권 0 처리들이없을경우차단된우선권 1처리가재개시되게한다. 절차 " 다음처리개시 " 는항상셋트되어진프래그의결과로써실행된다. 그러므로이러한처리의제 1 의작용은그프래그를크리어 (clear) 하는데있다. 18. R index word (Wptr register [Pri], the Iptr S, and the Iptr register [Pri]. When the progress sequence "next processing initiation" handles the present processing with the di schedule but it has another processing can progress in addition, it selects the processing excelling with the following proceed price. This makes resumed is blocked this does not have another priority 0 processings progressed. The procedure "next processing initiation" is performed as the result of the always set flag. The first action of such processing the flag the clear. 1. PROC 다음처리개시 = 1. PROC next processing initiation =. 2. 순차 2. Consecutive. 3. SNP 프래그 [Pri] : =0--SNP 프래그를크리 3. SNP flag [Pri]: a clear the =0--SNP flag. 어 4. 만일 4. If. 5. Fptr 레지스터 [Pri] 비처리. P 5. Fptr register [Pri] <> nonprocessing. P

18 K2E-PAT Page Dequeue 6. Dequeue 7. Pri = 0 7. Pri = 0 8. 순차 8. Consecutive. 9. Pri : =1 9. Pri : =1 10. 만일 10. If. 11. (Wptr 레지스터 [Pri]= 비처리. P) 그리고 11.( Wptr register [Pri] = nonprocessing. P) And. 12. (Fptr 레지스터 [Pri] 비처리.P) 12.( Fptr register [Pri] <> nonprocessing. P) 13. Dequeue 13. Dequeue 14. 참 14. Truth. 15. 도약 (SKIP) 15.Curvet(SKIP) 16. Pri=1 16. Pri=1 17. Wptr 레지스터 [Pri] : = 비처리. P : 17. wptr register [Pri]: = nonprocessing. P : 진행순서 " 진행요청조작 " 은프로세서에대해 " 진행요청 " 을만드는링크의결과로써실행된다. 진행순서 " 타이머요청조작 " 은타이머논리유니트 (86) 중의하나로부터라인 (96) 상의타이머요청의결과로써실행된다. 요청이우선권 0 처리에대하여있다면, 타이머요청 0 신호는발생될것이며처리기는처리우선권레지스터를 1 로세트할것이다. 진행순서는적절한 TPTR 워드의성분으로부터준비하게되는처리를식별한다. 진행순서는적절한경우처리를스케줄하고 TPTR 워드, 차순시간레지스터및관련우선권레벨에대한유효시간프래그를새롭게한다. The progress sequence "the progressing request manipulation" is performed about a processor as the result of the link making "progressing request". It is performed from one of progress sequence "the timer request manipulation" is the timer logical units (86) as the result of the timer request on the line (96). It has a request about the priority 0 processing. A processor will set the processing priority register to 1 while the timer request 0 signal will be generated. The progress sequence distinguishes the processing prepared from the component of the proper TPTR word. As to the progress sequence, in case of being appropriate, it schedules a processing and it makes the TPTR word, and the effective time flag for the related priority level and order time register new. PROC 타이머요청조작 = The PROC timer request manipulation =. 1. 순차 1. Consecutive. 2.--Procptr 레지스터를리스트상의제 1 의처리에세트 3. R 인덱스워드 (Tptr Loc0, 처리우선권, 일시레지스터 ) 2.-- The set in the first processing on a list the Procptr register. 3.R index word(the Tptr Loc0, the processing priority, and the temporary register) 4. Proc Ptr 레지스터 : = 일시레지스터 4. proc Ptr register: = temporary register 일시레지스터를제 1 의처리의 T 링크위치에세트 6. R 인덱스워드 (Proc Ptr 레지스터, T 링크. S, 일시레지스터 ) 7. W 인덱스워드 (Proc Ptr 레지스터, T 링크.S, 시간세트. P) 5.-- The set in T link position of the first processing the temporary register. 6. R index word (Proc Ptr register, and T link. S, and the temporary register). 7. W index word (Proc Ptr register, and T link. S, and the time set. P)

19 K2E-PAT Page 타이머포인터워드를새롭게한다 It makes the timer pointer word new. 9. W 인덱스워드 (Tptr Loc0, 처리우선권, 일시레지스터 ) 9.W index word(the Tptr Loc0, the processing priority, and the temporary register) 리스트가현재공백인가? A list is the blank. 11. 만일 11. If. 12. 일시레지스터 = 비처리. P 12. Temporary register = nonprocessing. P 예 Example. 14. 유효시간프래그 [ 처리우선권 ] : =0 14. the effective time flag [processing priority]: = 일시레지스터 비처리.P 15. Temporary register <> nonprocessing. P 16. -아니오 : 차순시간레지스터를세트 16.- it is not: the set the order time register. 17. R 인덱스워드 ( 일시레지스터, 시간.S, 차순시간레지스터 [ 처리우선권 ]) 17. R index word (temporary register, and the time. S, and the order time register [processing priority]) 처리의상태위치를검사 An inspection the status position of a processing. 19. R 인덱스워드 (Proc Ptr 레지스터, 상태.S, 일시레지스터 ) 19. R index word (Proc Ptr register, and the state. S, and the temporary register). 20. 만일 20. If. 21. 일시레지스터 = 준비.P 21. Temporary register = preparation. P 22. 도약 22. Curvet. 23. 일시레지스터 = 대기. P 23. The temporary register = atmosphere. P 24. 순차 24. Consecutive. 25. W 인덱스워드 (Proc Ptr 레지스터, 상태.S, 준비.P) 26. 처리설명기레지스터 : =Proc Ptr 레지스터처리우선권 27. 진행 : 27.Progressing: 상기정의에있어서, Tptr Loc0 에참조된다. 여기에는 2 개의 Tptr 위치가있는데, 하나는우선권 1 에대한것이고다른하나는우선권 0 에관한것이라는것이인지될것이다. 그들은인접메모리위치를사용하며우선권 0 에대한위치는어드레스 Tptr Loc0 를가진다. 이러한방법에있어서, 위치들의어느하나는관련우선권에의존한 Tptr Loc0 로부터 0 혹은 1의오프셋에의해어드레스될수있다. " 삽입단계 " 과정은삽입프래그 [Pri] 가고정되고난후에수행된다. 이러한과정의반복된실행은올바른위치안에전류우선권레벨을위하여전류처리를타이머리스트안으로삽입한다. B 레지스터 [Pri] 및 C 레지스터 [Pri] 는올바른위치를위한추적이지금까지도달된점이 25. W index word (Proc Ptr register, and the state. S, and a preparation. P) 26. processing descriptor register: =Proc Ptr register processing priority. As to the definition, it is referred to the Tptr Loc0, it here in has the Tptr location of 2. It will be recognized to one be the priority 1 a thing and the other one be the thing about the priority 0. As to they, the priority 0 a location has the address Tptr Loc0 while using the adjaceny memory location. As to this method, one of the locations can be addressed from the Tptr Loc0 depending on the related priority with the offset of 0 or 1. "The inserting step" The process is performed after the insertion flag [Pri] is fixed. The repeated execution of this process inserts the current process into the right inside of position for the current priority level to the timer list inside. B register [Pri] and C register [Pri] are the same the hunting for the right location so far reaches that.

20 K2E-PAT Page 20 같다. 삽입이행해질때, 과정은삽입프래그 [Pri] When an insertion is performed, the process removes the 을제거하며, 타이머레지스터를적당히정 insertion flag [Pri]. 정하고다음처리가수행되도록한다. 처리삽입단계 = The processing inserting step =. --A 레지스터 [Pri] 는이처리와연관된시간 -- A register [Pri] provides the time related to this processing. 을포함한다. --B 레지스터 [Pri] 는포인터에서다음처리의포인터까지사용된다. --C 레지스터 [Pri] 는포인터에서다음처리까지사용된다. -- In a pointer, B register [Pri] is used to the pointer of the next processing. -- In a pointer, C register [Pri] is used to the next processing. 1. 순차 1. Consecutive. 2. 만약 2. If. 3. C 레지스터 [Pri] 비처리.P 3. C register [Pri] <> nonprocessing. P 4. --다음처리와연관된시간을포착하라 The time related to the next processing is seized. 5. R 인덱스워드 (C 레지스터 [Pri], 시간.S,T 레지스터 [Pri]) 5. R index word (C register [Pri], and the time. S,T register [Pri]). 6. C 레지스터 [Pri] -비처리.P 6. C register [Pri] - nonprocessing. P 7. 도약 7. Curvet. 8. 만약 8. If. 9. (C 레지스터 [Pri] 비처리.P) 그리고 (T 레지스터 [Pri] 초과 A 레지스터 [Pri]) 9.( C register [Pri] <> nonprocessing. P)And(t register [Pri] Amomi tsao-ko Fructus A register [Pri]) 10. 순차 10. Consecutive 하나의처리상으로이동 A movement on one processing. 12. 워드에서 (C 레지스터 [Pri].T 링크,S,B 레지스터 [Pri]) 13. R 인덱스워드 (B 레지스터 [Pri],O,C 레지스터 [Pri]) 12.In the word(c register [Pri] T. link S, B, and the register [Pri]) 13.R index word(b register [Pri],O,C register [Pri]) 14. 참 14. Truth. 15. 순차 15. Consecutive 삽입할장소발견 The place discovery inserted. 17. 삽입프래그 [Pri] =0 17. Insertion flag [Pri] = 이처리안에링크 The link in this treatment method. 19. W 인덱스워드 (B 레지스터 [Pri],O,Wptr 19.W index word(b register [Pri],O,Wptr register [Pri]) 레지스터 [Pri]) 20. W 인덱스워드 (Wptr 레지스터 [Pri],T 링크.S,C 레지스터 [Pri]) 20. W index word (Wptr register [Pri],T link. S,C register [Pri]) 다음시간레지스터를고정 A fixing the next second register.

21 K2E-PAT Page R 인덱스워드 (Tptr Loc0,Pri,T 레지스터 [Pri]) 23. R 인덱스워드 (T 레지스터 [Pri], 시간.S, 다음시간레지스터 [Pri]) 22.R index word(tptr Loc0,Pri,T register [Pri]) 23. R index word (T register [Pri], and the time. S, and the next second register [Pri]). 24. 유효시간프래그 [Pri]=1 24. Effective time flag [Pri] = W 인덱스워드 Wptr 레지스터 [Pri],Iptr.S,Iptr 레지스터 [Pri]) 26. SNP 프레그 [Pri]=1 26. SNP flag [Pri] =1. " 삭제단계 " 과정은삭제프래그 [Pri] 고정되고난후에수행된다. 이러한과정의실행의반복은전류우선권레벨을위하어타이머리스트로부터전류처리를삭제한다. B 레지스터 [Pri] 및 C 레지스터 [Pri] 는전류처리를위한추적이지금까지도달한점을동일시한다. 삭제가행해지게된때, 과정은삭제프레그 [Pri] 를제거하고, 타이머레지스터를적당하게정정한다. 25. W index word Wptr register [Pri],Iptr S. Iptr, and the register [Pri]). "Erase step" The process is performed after being fixed with the deletion flag [Pri]. The repetition of the execution of this process respects the current priority level and it deletes the current process from the timer list. B register [Pri] and C register [Pri] regard in the same light that the hunting for the current process so far reaches. When the deletion is performed, the process removes the deletion flag [Pri]. The timer register is befittingly corrected. [ 처리삭제단계 ] [Processing erase step] 1. 만약 1. If. 2. C 레지스터 Wptr 레지스터 [Pri] 2. C register <> Wptr register [Pri]. 3. 순차 3. Consecutive 현재처리가아직발견되지않았다 : 단 4.-- presently, a processing was not yet discovered: on a step. 계상에서 5. 워드에서 (C 레지스터 [Pri],T 링크.S,B 레지 5. The C( register [Pri],T link in the word. S,B register [Pri]). 스터 [Pri]) 6. R 인덱스워드 (B 레지스터 [Pri],O,C 레지 6.R index word(b register [Pri],O,C register [Pri]) 스터 [Pri]) 7. C 레지스터 [Pri] =Wptr 레지스터 [Pri] 7. C register [Pri] =Wptr register [Pri]. 8. 순차 -- 처리가발견됐다 : 리스트로부터삭제 9. 삭제프래그 [Pri] =0 9. Deletion flag [Pri] = R 인덱스워드 (Wptr 레지스터 [Pri],T 링크.S,C 레지스터 [Pri]) 11. W 인덱스워드 (B 레지스터 [Pri],O,C 레지스터 [Pri]) 만약 queue 상에어떤처리가남아있다면체크. 13. R 인덱스워드 (Tptr Loc0,Pri,B 레지스터 [Pri]) 14. 만약 14. If. 8. the consecutive -- processing was discovered: the deletion from a list. 10. R index word (Wptr register [Pri],T link. S,C register [Pri]). 11.W index word(b register [Pri],O,C register [Pri]) A check any kind of processing remains on a queue. 13.R index word(tptr Loc0,Pri,B register [Pri])

22 K2E-PAT Page B 레지스터 [Pri]= 비처리.P 15. B register [Pri] = nonprocessing. P 처리가남아있지않았다 A processing did not remain. 17. 유효시간프래그 [Pri]=0 17. Effective time flag [Pri] = B 레지스터 [Pri] 비처리.P 18. B register [Pri] <> nonprocessing. P 제 1처리로부터시간을얻는다 The time is obtained from the first processing. 20. R 인덱스워드 (B 레지스터 [Pri], 시간.S, 다음시간레지스터 [Pri]) 21. W 인덱스워드 (Wptr 레지스터 [Pri],T 링크.S, 시간비처리.P) : 연속링크를대신하여처리기에의해실행되는동작은 " 조정수행요청 " 과 " 조정준비요청 " 이며, 이것들은앞서언급된계류중인특허출원에모두설명되어있다. 타이머 (9) 를대신하여처리기에의해실행되는동작은앞에서정의된것처럼, " 조정타이머요청 " 과정에서설명된다. 각각이이러한동작은순차적인미소명령어를수반한다. 이러한동작을구성하는순차중에서마지막미소명령어는 " 다음동작 " 이다. 이것은처리로하여금실행되는다음동작을선택하게한다. " 다음동작 " 미소명령어가수행될시간다음에동작이실행되는것을처리기가결정하는방법은다음과같다. 동기제어논리 (10) 는언제나기껏해야하나의 " 수행요청 " 혹은 " 준비요청 " 에서처리기로나아간다. 만약우선권 0요청이있다면우선권 1요청으로나아가지않는다. 이것은상태멀티플렉서 (36) 로입력되는두개의신호를가져오며하나는요청의존재를지시하고, 또하나는그요청의우선권을지시한다. 두개의신호 " 타이머요청 0" 및 " 타이머요청 1" 은현재선택된 SNP 프래그 (58), 삭제프래그 (83), 삽입프래그 (82) 및카피프래그 (59) 로부터신호와연결된상태멀티플렉서 (36) 로연결된다. 그러므로아래서설명된것처럼선택될수있다. 처리기는만약 SNP 프래그 [Pri] 가세트된다면 " 시작후처리 " 과정을실행한다. 반면에실행될수있는것이하나있다면처리기는우선권 1동작을선택한다. 반면에처리될수있는것이하나있다면우선권 0 동작을선택한다. 반면에, 타이머혹은통신채널로부터요청이있을때까지처리기는대기한다. 20. R index word (B register [Pri], and the time. S, and the next second register [Pri]). 21. W index word (Wptr register [Pri],T link. S, and the time nonprocessing. P) : "control performance request" and "control preparation request" these are altogether explained in the patent application which is before mentioned and which the operation of being performed instead of the continuous link with a processor moors. As the operation of being performed instead of the timer (9) with a processor is defined in the front. The operation of being performed instead of the timer (9) with a processor is explained in "the control timer request" process. The operation in which each is like that accompanies the successive micro command. The final micro command is "the next operation" among the consecutive comprising this operation. This selects an operation after being performed to a processing. "Next operation" The method in which a processor determines that an operation is performed in the time next in which the micro command is performed is the next department equal. The synchronization control logic (10) always moves to a processor in one "performance request" or "preparation request" at most. It does not move to the priority 1 request if it has the priority 0 request. One indicates the presence of a request while bringing about the signal of a cranium inputted with this is the state multiplexer (36). And one indicates the priority of the request. Two signal "the timer request 0"s and "the timer request 1" are connected to the state multiplexer (36) connected to a signal from the SNP flag (58), which is currently selected the deletion flag (83), and the insertion flag (82) and copy flag (59). Therefore, it can be selected as it is explained in the lower part. As to a processor, it performs the process if the SNP flag [Pri] is set "A processing after a beginning". On the other hand, if it has with one to be performed, the priority 1 operation is selected a processor. On the other hand, if it has with one, the priority 0 operation is selected to be processed. On the other hand, a processor queues until it has a request from the timer or the communications channel.

23 K2E-PAT Page 23 처리기는다음에규칙에의하여특별한우선권레벨 Pri 에서동작을선택한다. 처리기는만약삭제프레그 [Pri] 가고정된다면 " 삭제단계 " 를실행한다. 반면에처리기는만약삽입프래그 [Pri] 가고정된다면 " 삽입단계 " 가실행된다. 반면에처리기는어떠한우선권 Pri 채널요청을조정한다. 반면에처리기는어떠한우선권 Pri 타이머요청을조정한다. 반면에카피프래그 [Pri] 가고정된다면, 처리기는 " 블록카피단계 " 과정을실행한다. 반면에만약우선권 Pri 의현재처리가있다면, 처리기는명령어를끌어내고해독하며실행한다. 유럽특허제 호에기재된것처럼명령어는취출되고, 해독되며, 실행된다. 이어지는기능의기술은추가되는네개의과정에대해언급한다. 시간슬라이스타이머리스트내삽입타이머리스트로부터삭제선택된처리인가이러한과정에대한다음정의에서참조는상대시간을행한다. 클록레지스터 (81) 는규칙적으로 1에의해증가하고, 가장작은음의값으로부터증가하는연속싸이클을통과하여가장큰양의값까지지나간다. 가장큰양성의값을초과한다음의증가는가장큰음의값보다뒤에있는레지스터를갖는다. 다음의기술에서표현 (Y 초과 X) 수단 (X) 은시간 (Y) 보다더늦다. (X+1) 과 (X+ 가장큰양의값 ) 사이의모든시간을 X 초과가되도록규정된다.( 클록레지스터 +1) 과 ( 클록레지스터 + 가장큰양의값 ) 사이의모든시간은점차인식되며,( 클록레지수터와 (-1)) 및 ( 클록레지스터 + 가장적은음의값 ) 사이의모든시간은과거에인식된다. Next a processor selects an operation in the special priority level Pri than with a regulation. As to a processor, it enforces "the erase step" the deletion flag [Pri] is fixed. On the other hand, as to a processor, "the inserting step" is performed the insertion flag [Pri] is fixed. On the other hand, a processor controls any priority Pri channel request. On the other hand, a processor controls any priority Pri timer request. On the other hand, the copy flag [Pri] is fixed. If it is the case, a processor performs "the block copy step" process. On the other hand, it has the present processing of the priority Pri. A command is taken out as it is written in EP A command is decoded. And a command is performed. The technology of the function of being connected mentions to four processes of being added. Time slice. Timer list my insertion. The deletion from the timer list. It is the selected processing. In the next definition about this process, a reference performs the relative time. The clock register (81) regulary increases with 1. It passes through the series cycle increasing from the most small negative value and it passes to the most big positive value. The following increment which is over the value of the most big positivity has the register who is in a behind with the most big negative value. In the following technology, the expression (Y Amomi tsao-ko Fructus X/6) means (X) is more late than the time (Y). (X+1) It is prescribed so that X Amomi tsao-ko Fructus become every the times between (the most big with X+ positive value). (The clock register +1) Every the times between (the positive value which the clock register + is most big) are gradually acknowleged. And every the time between (the negative value which the clock register + most writes) and (the clock ledge Sutter and (-1)) are acknowleged in a past. 그이외의과정에대한정의는다음과같 The definition toward the process of the except is as follows. 다. 1. PROC 시간슬라이스 = 1. PROC time slice =. 2. 만약 2. If. 3. (Pri=1) 그리고 (( 시간슬라이스레지스터초과클록레지스터 ) 혹은 ( 클록레지스터 = 시간슬라이스 )) 4. 순차 4. Consecutive. 3. (Pri=1)And((Time slice register Amomi tsao-ko Fructus clock register)or(clock register = time slice))

24 K2E-PAT Page 처리설명레지스터 : =Wptr\ /Pri 5. processing description register: =Wptr\ /Pri. 6. 런 SNP[Pri] : =1 7. SNP[Pri] : =1 8. 참 8. Truth. 9. 도약 9. Curvet. 1. PROC 타이머리스트내삽입 = 1. The insertion = within the PROC timer list 이것은레지스터와삽입프래그가세트업하므로삽입 Sep 의반복수행은 A레지스터 [Pri] 안에규정된시간에서시간리스트안으로삽입되는이러한처리를가져오며, 그다음에디스케쥴된다. --B 레지스터 [Pri] 는포인터에서다음처리의포인터까지사용된다. --C 레지스터 [Pri] 는포인터에서다음처리까지사용된다. 2. 순차 2. Consecutive. 3. W 인덱스워드 (Wptr 레지스터 [Pri], 시간, S, A 레지스터 [Pri]) 2.-- As to this, since the register and insertion flag set up, the repeating performance of the insertion Sep brings this processing inserted by the time list from the prescribed time in A register [Pri]. And it is and then de-scheduled. -- In a pointer, B register [Pri] is used to the pointer of the next processing. -- In a pointer, C register [Pri] is used to the next processing. 3.W index word(the wptr register [Pri], time, S, a register [Pri]) 4. 삽입프래그 [Pri] : =1 4. insertion flag [Pri]: =1. 5. 워드에서 (Tptr Loc O, Pri, B 레지스터 [Pri]) 5.In the word(the Tptr Loc O/6, Pri, and B register [Pri]) 6. R 인덱스워드 (B 레지스터 [Pri], O, C 레지스 6.R index word (B register [Pri], O, and C register [Pri]): 터 [Pri]) : 1. PROC 타이머리스트로부터삭제 1. The deletion from the PROC timer list 이것은현재처리가적당한타이머리스트로부터삭제되게하며, 시간비세트가 T 링크위치에기록되게한다. 이것은레지스터의회복에의해관성되며, 그다음에삭제단계가반복되어실행한다. --A 레지스터는사용되지않는다. --B 레지스터는포인터에서다음처리의포인터까지사용된다. --C 레지스터는포인터에서다음처리까지사용된다 This is deleted from the timer list in which a processing is appropriate. And the time ratio set is recorded in T link position. As to this, and then, the erase step is repeated the inertia measure and it enforces with the recover of the register. -- A register is not used. -- In a pointer, B register is used to the pointer of the next processing. -- In a pointer, C register is used to the next processing. 2. 순차 2. Consecutive. 3. 삭제프래그 [Pri] : =1 3. deletion flag [Pri]: =1. 4. 워드에서 (Tptr Loc O, Pri, B 레지스터 [Pri]) 4.In the word(the Tptr Loc O/6, Pri, and B register [Pri]) 5. R 인덱스워드 (B 레지스터 [Pri], O, C 레지스 5.R index word(b register [Pri], O, and C register [Pri]) 터 [Pri]) 1. PROC 선택된처리인가 = 1. The chosen with PROC processing approval =.

25 K2E-PAT Page 이것은모든비구동명령어에의해사 2.-- This is used with all deactivate commands. 용된다. 3. 순차 3. Consecutive. 4. R 인덱스워드 (Wptr 레지스터 [Pri], O, O 레지스터 [Pri]) 5. 만약 5. If. 6. O 레지스터 [Pri] =(-1) 6.O register [Pri] =(-1) 7. 순차 7. Consecutive. 8. W 인덱스워드 (Wptr 레지스터 [Pri], O, A 레지스터 [Pri]) 4.R index word(the Wptr register [Pri], O, and O register [Pri]) 8.W index word(the Wptr register [Pri], O, and A register [Pri]) 9. A 레지스터 [Pri] : = 장치참 9. a register [Pri]: the = apparatus, truth. 10. O 레지스터 [Pri] (-1) 10.O register [Pri] < >(-1) 11. A 레지스터 [Pri] : = 장치거짓 11. a register [Pri]: = apparatus false. [ 기능셋트 ] [Function set] 유럽특허명세서 에기재된바와같이, 마이크로컴퓨터에대한각각의명령어는기능셋트로부터선택된기능소자를포함한다. 마이크로컴퓨더에의해실행되는기능을직접기능, 프리픽싱 (prefixing) 기능 pfix 및 nfix, 그리고오퍼란드레지스터인 O 레지스터를사용하여한셋트의동작중하나를선택하는간접기능 opr 을포함한다. 상술한특허명세서에서와같이, O 레지스터 [Pri] 는 PFIX 및 NFIX 를제외한모든명령어를실행후에크리어된다. 직접가능의개량된셋트와본원의작동은아래와같다. As described in EP A, each command about a microcomputer provides the functional device selected from the function set. The direct function the function of being performed, and the indirect function opr are included with a microcomputer. The indirect function opr selects one out of the operation of one set by using O register who is the prefixing function pfix, a nfix and *** register. O register [Pri] is cleared PFIX and NFIX all commands the above-described patent specification after an execution. The operation of the present application and the improved set of the direct available are same as those of the lower part. [ 직접기능 ] [Direct function] 코드번호약어명칭 Code number abbreviation name. 0 Idl 국부부하 0 Idl part load. 1 stl 국부기억 1 stl local storage. 2 ldlp 국부포인터부하 2 ldlp part pointer load. 3 ldnl 비-국부부하 3 ldnl specific- part load. 4 stnl 비-국부기억 4 stnl specific- local storage. 5 ldnlp 비-국부포인터부하 5 ldnlp specific- part pointer load. 6 egc 상수 (constant) 일정 6 egc constant constant. 7 ldc 상수부하 7 ldc constant load. 8 adc 상수부가 8 adc equilibrium part. 9 j 점프 9 j jump.

26 K2E-PAT Page cj 조건적점프 10 cj facultative jump. 11 call 호출 11 call call. 12 ajw 작업공간조절 12 ajw work space adjustment. 13 opr 작동 13 opr operation. 14 pfix 프리픽스 (prefix) 14 pfix prefix (prefix) 15 nfix 네가티브프리픽스 15 nfix negative prefix. (Negative prefix) (Negative prefix) [ 동작 ] [Operation] 코드번호 No. 약어명칭 Code number No. abbreviation name. 0 rev 역전 0 rev inversion. 1 ret 복귀 1 ret return. 2 gcall 일반호출 2 gcall general call. 3 gajw 일반조절작업공간 3 gajw general control work space. 4 ldpi 포인터를명령어에부하 The load in a command 4 ldpi pointer. 5 bsud 바이트가입 (subscript) 5 bsud byte subscription (subscript) 6 wsub 워드가입 6 wsub word subscription. 7 bcnt 바이트계수 7 bcnt byte count. 8 wcnt 워드계수 8 wcnt word system number. 9 lend 루프종결 9 lend loop termination. 10 lb 바이트부하 10 lb byte load. 11 sb 바이트기억 11 sb byte memory. 12 copy 메세지카피 12 copy message copy. 13 gt 보다큰 13 gt ***. 14 add 부가 14 add part. 15 sub 감산 15 sub subtraction. 16 mint 최저정수 16 mint lowest fixed number. 17 startp 처리개시 17 startp processing initiation. 18 endp 처리종결 18 endp processing termination. 19 runp 처리진행 19 runp process progress. 20 stopp 처리정지 20 stopp processing pause. 21 ldpri 우선권부하 21 ldpri priority load. 22 in 메세지입력 22 in message input. 23 out 메세지출력 23 out message output. 24 alt 개시 24 alt initiation.

27 K2E-PAT Page alwt 대기 25 alwt atmosphere. 26 altend 종결 26 altend termination. 27 enbs 구동도약 27 enbs drive curvet. 28 diss 비구동도약 28 diss deactivate curvet. 29 enbc 구동채널 29 enbc drive channel. 30 disc 비구동채널 30 disc deactivate channel. 31 ld 타이머부하타이머 31 ld timer load timer. 32 tin 타이머입력 32 tin timer input. 33 talt 타이머교대시작 33 talt timer alternation beginning. 34 taltwt 타이머교대대기 34 taltwt timer alternation atmosphere. 35 enbt 구동타이머 35 enbt drive timer. 36 dist 비구동타이머 36 dist deactivate timer. 코드번호 (31 내지 36) 의작용을제외한앞서기록된모든기능과작용은앞서언급된계류중인특허출원에서이미명백히나타나있어이명세서에서는재언급되지않는다. 그러나 " 점프 " 기능과 " 루프끝 " 작용은타이머 (9) 를사용하게하도록재규정되었고, 이것은다음과같이규정된다. [ 점프 ] [Jump] 정의 : 순차 Definition: consecutive. 바이트에서 (Iptr 레지스터 [Pri], O 레지스터 [Pri], Iptr 레지스터 [Pri]) [ 시간슬라이스 ] [Time slice] 목적 : 역방향혹은순방향제어가루프로부터루프와출구를준비하기위해전송되고, 만약할당된시간슬라이스가경과한다면, 처리가재스캐줄되도록하기위해서 The action of the code number (31 through 36) all the functions and the before recorded action already clearly show up in the patent application which is before mentioned mooring and it measures in this specification and it is not mentioned. But "A jump" function and "the loop end" action were re-regulated in order to use the timer (9). This is prescribed like a next. In a byte (the Iptr register [Pri], O register [Pri], and the Iptr register [Pri]) Purpose: it is transmitted so that the reverse direction or the forword control prepare for a loop and exit from a loop. The allocated time slice passes. If it is the case, it becomes a processing with *** line. [ 루프끝 ] [Loop end] 정의 : 순차 Definition: consecutive. R 인덱스워드 (B 레지스터 [Pri],1, C 레지스터 R index word (b register [Pri],1, and C register [Pri]) [Pri]) C 레지스터 [Pri] : =C 레지스터 [Pri] -1 C register [Pri]: =C register [Pri] -1. W 인덱스워드 (B 레지스터 [Pri],1, C 레지스터 W index word (b register [Pri],1, and C register [Pri]) [Pri]) 만약 If. C 레지스터 [Pri] O C register [Pri] >O. [ 순차 ] [Consecutive]

28 K2E-PAT Page 28 R 인덱스워드 (B 레지스터 [Pri],0, C 레지스터 R index word (b register [Pri],0, and C register [Pri]) [Pri]) C 레지스터 [Pri] : =C 레지스터 [Pri] +1 C register [Pri]: =C register [Pri] +1. W 인덱스워드 (B 레지스터 [Pri], O, C 레지스터 W index word (b register [Pri], O, and C register [Pri]) [Pri]) 바이트에서 (Iptr 레지스터 [Pri], -A 레지스터 [Pri], Iptr 레지스터 [Pri] ) 참도악 In a byte (the Iptr register [Pri], -A register [Pri], and the Iptr register [Pri]) Truth. Cultellus. [ 시간슬라이스 ] [Time slice] 목적 : 응답에도움을주며, 만약할당된시간슬라이스가경과한다면, 처리를재스케쥴되게하기위해서이이외의작동및 "altend" 는다음과같다. Purpose: an operation and "altend" of this except it makes a processing rescheduled a dome is decreased in a response, and the allocated time slice passes are as follows. [ 타이머입력용작동 ] [The operation for the timer input] 부하타이머 Load timer. 정의 : 순차 Definition: consecutive. C 레지스터 [Pri] : =B 레지스터 [Pri] C register [Pri]: =B register [Pri]. B 레지스터 [Pri] : =A 레지스터 [Pri] B register [Pri]: =A register [Pri]. A 레지스터 [Pri] : = 클록레지스터 A register [Pri]: = clock register. 목적 : 타이머의전류값을 A 레지스터안으로부하하기위해 Purpose: the current value of a timer is carried a load of by A register. [ 타이어입력 ] [Tire input] 정의 : Definition : 1. 만약 1. If. 2. A 레지스터 [Pri] 경과클록레지스터 2. A register [Pri] stalk and clock register. 3. 도약 3. Curvet. 4. 참 4. Truth. 5. 순차 5. Consecutive. 6. W 인덱스워드 (Wptr 레지스터 [Pri], 상태, S, 6. W index word (Wptr register [Pri], state, S, atmosphere. P) 대기.P) 7. A 레지스터 [Pri] : =A 레지스터 [Pri] a register [Pri]: =A register [Pri] 타이머리스트내에삽입 8. The insertion within the timer list. 목적 : 일정한시간이경화한후처리를스 Purpose: a processing is scheduled the fixed time hardens. 케쥴하기위해 [ 교대타이머입력용작동 ] [The operation for the alternation timer input] 타이머교대입력 Timer alternation input.

29 K2E-PAT Page 29 정의 : Definition : 1. 순차 1. Consecutive. 2. W 인덱스워드 (Wptr 레지스터 [Pri], 상대.S, 구동.P) 3. W 인덱스워드 (Wptr 레지스터 [Pri], T 링크.S, 시간비세트.P) 목적 : 구동교대입력및타이머에앞서처리상태및타이머상태를개시화하기위해 2. W index word (Wptr register [Pri], and the opposite side. S, and a drive. P) 3. W index word (Wptr register [Pri], and T link. S, and the time ratio set. P) Purpose: the process state and timer state are respected before the drive alternation input and timer with the initiation below. [ 타이머교대대기 ] [Timer alternation atmosphere] 정의 : Definition : 1. 순차 1. Consecutive. 2. W 인덱스워드 (Wptr 레지스터 [Pri],O-1) 2.W index word(wptr register [Pri],O-1) 3. R 인덱스워드 (Wptr 레지스터, T 링크.S, B 레지스터 [Pri]) 4. R 인덱스워드 (Wptr 레지스터 [Pri], 시간.S, A 레지스터 [Pri]) 5. 만약 5. If. 6. (B 레지스터 [Pri] = 시간세트 ) AND(A 레지스터 [Pri] 초과클록레지스터 ) 3. R index word (Wptr register, and T link. S, and B register [Pri]). 4. R index word (Wptr register [Pri], and the time. S, and A register [Pri]). 6. (B register [Pri] = time set)and(a register [Pri] Amomi tsao-ko Fructus clock register) 7. 순차 -- 클록은처리시작을만든다. 7. The consecutive -- clock makes the processing start. 8. W 인덱스워드 (Wptr 레지스터 [Pri] 상대.S, 시작.P) 9. W 인덱스워드 (Wptr 레지스터 [Pri], 시간.S, 클록레지스터 ) 10. 참 10. Truth. 11. 순차--클록은처리시작을만들지않는다. 12. R 인덱스워드 (Wptr 레지스터 [Pri], 상태.S, C 레지스터 [Pri]) 8. W index word (Wptr register [Pri] opposite side. S, and a beginning. P) 9. W index word (Wptr register [Pri], and the time. S, and the clock register). 11. The consecutive -- clock does not make the processing start. 12. R index word (Wptr register [Pri], and the state. S, and C register [Pri]). 13. 만약 13. If. 14. C 레지스터 [Pri] = 시작. P 14. C register [Pri] = beginning. P 15. W 인덱스워드 (Wrtr 레지스터 [Pri], 시간.S, 클록레지스터 ) 16. C 레지스터 [Pri] = 구동.P 16. C register [Pri] = drive. P 17. 순차 17. Consecutive. 18. W 인덱스워드 (Wptr 레지스터 [Pri], 상태.S, 대기.P) 19. 만약 19. If. 15. W index word (Wrtr register [Pri], and the time. S, and the clock register). 18. W index word (Wptr register [Pri], and the state. S, and an atmosphere. P)

30 K2E-PAT Page B 레지스터 [Pri] = 시간세트. P 20. B register [Pri] = time set. P 21. 순차 21. Consecutive. 22. A 레지스터 [Pri] : =A 레지스터 [Pri] a register [Pri]: =A register [Pri] 타이머리스트내삽입 23. The insertion within the timer list. 24. B 레지스터 [Pri]= 시간비세트.P 24. B register [Pri] = time ratio set. P 25. 순차 25. Consecutive. 26. W 인덱스워드 (Wptr 레지스터 [Pri], Iptr.S,Iptr 레지스터 [Pri]) 27. SNP 프래그 [Pri] SNP flag [Pri] +1. 목적 : 구동된다수의입력중하나와타이머입력되는몇개를대기하기위해 26.W index word(the Wptr register [Pri], the Iptr S. Iptr, and the register [Pri]) Purpose: a several is queued inputted to one and timer among a plurality of inputs runing. [ 구동타이머 ] [Drive timer] 정의 : Definition : 1. 순차 1. Consecutive. 2. 만약 2. If. 3. A 레지스터 [Pri]= 처리기거짓 3. A register [Pri] = processor false. 4. 도약 4. Curvet. 5. A 레지스터 [Pri] 처리기거짓 5. A register [Pri] processor false. 6. 순차 6. Consecutive. 7. R 인덱스워드 (Wptr 레지스터 [Pri], T 링크.S,O 레지스터 [Pri]) 7. R index word (Wptr register [Pri], and T link. S,O register [Pri]). 8. 만약 8. If. 9. O 레지스터 [Pri]= 시간비세트.P 9. O register [Pri] = time ratio set. P 10. 순차 10. Consecutive. 11. W 인덱스워드 (Wptr 레지스터 [Pri], T 링크.S, 시간세트.P) 12. W 인덱스워드 (Wptr 레지스터 [Pri], 시간.S, B 레지스터 [Pri]) 11. W index word (Wptr register [Pri], and T link. S, and the time set. P) 12. W index word (Wptr register [Pri], and the time. S, and B register [Pri]). 13. O 레지스터 [Pri] = 시간세트. P 13. O register [Pri] = time set. P 14. 순차 14. Consecutive. 15. R 인덱스워드 (Wptr 레지스터 [Pri], 시간 : S, O 레지스터 [Pri]) 15.R index word(the Wptr register [Pri], and the time: s, and O register [Pri]) 16. 만약 16. If. 17. B 레지스터 [Pri] 초과 O레지스터 [Pri] 17. B register [Pri] Amomi tsao-ko Fructus O register [Pri]. 18. W 인덱스워드 (Wptr 레지스터 [Pri], 시간.S, B 레지스터 [Pri]) 19. 참 19. Truth. 18. W index word (Wptr register [Pri], and the time. S, and B register [Pri]).

31 K2E-PAT Page 도약 20. Curvet. 21. B 레지스터 [Pri] : =C 레지스터 [Pri] 21. b register [Pri]: =C register [Pri]. 목적 : 타이머입력을구동하기위해 Purpose: the timer input is operated. [ 비구동타이머 ] [Deactivate timer] 용법 : 입구상에서 : A 레지스터 = 코드오프셋, B 레지스터 =Boolean 감시, C 레지스터 = 시간 출구상에서 : A 레지스터 = 만약이것이성분을선택솬다면처리기참 Usage: on an entrance: a register = code offset, B register =Boolean monitoring, and C register = time. On an exit: a register =, if, this is *** many sides processor a component, truth. A 레지스터 = 그외에는처리기거짓 The processor false in A register = ***. 정의 : Definition : 1. 만약 1. If. 2. B 레지스터 [Pri]= 처리기거짓 2. B register [Pri] = processor false. 3. A 레지스터 [Pri] : = 처리기거짓 3. a register [Pri]: = processor false. 4. B 레지스터 [Pri] 처리기거짓 4. B register [Pri] < > processor false. 5. 순차 5. Consecutive. 6. R 인덱스워드 (Wptr 레지스터 [Pri], T 링크.S, 0 레지스터 [Pri]) 6. R index word (Wptr register [Pri], and T link. S, and 0 register [Pri]). 7. 만약 7. If 레지스터 [Pri]= 시간비세트. P 8. 0 register [Pri] = time Bissett. P 9. A 레지스터 [Pri]= 처리기거짓 9. A register [Pri] = processor false 레지스터 [Pri]= 시간세트. P register [Pri] = time set. P 11. 순차 11. Consecutive. 12. R 인덱스워드 (Wptr 레지스터 [Pri], 시간.S, 0 레지스터 [Pri]) 12. R index word (Wptr register [Pri], and the time. S, and 0 register [Pri]). 13. 만약 13. If. 14. C 레지스터 [Pri] 초과 0 레지스터 [Pri] 14. C register [Pri] Amomi tsao-ko Fructus 0 register [Pri]. 15. 선택된처리인가 15. It is the selected processing. 16. 참 16. Truth. 17. A 레지스터 [Pri] : = 처리기거짓 17. a register [Pri]: = processor false. 18. 참 18. Truth. 19. 순차 19. Consecutive. 20. A 레지스터 [Pri] : = 처리기거짓 20. a register [Pri]: = processor false. 21. 타이머리스트로부터삭제 21. The deletion from the timer list. 목적 : 다수의교대타이머입력중하나를 Purpose: the timer input runing for selecting one out is

32 K2E-PAT Page 32 선택하기위한구동된타이머입력을비구동하기위해 respected among lots of the alternation timer input with the deactivate below. [ 교대끝 ] [Alternation end] 정의 : 순차 Definition: consecutive. 1. R 인덱스워드 (Wptr 레지스터 [Pri], 0, 0 레 1.R index word(the Wptr register [Pri], 0, and 0 register [Pri]) 지스터 [Pri]) 2. 바이트에서 (Iptr 레지스터 [Pri], 0 레지스터 [Pri], Iptr 레지스터 [Pri]) 목적 : 교대처리의선택된성분의수행을시작하기위하여처리기가 ROM13 에서유출된미소명령의결과로서상기어느작용이라도수행됨으로써, 미소명령 ROM13 은상기모든기록된기능과작용과일치하는미소명령을포함하는것으로이해된다. [ 스케쥴링 ] [Scheduling] 처리기는두개의상이한우선권레벨 (0 및 1) 에서실행하는다수의병행처리들사이의시간을공유한다. 만일양쪽다실행할수있다면, 우선권 0 처리는항상우선권 1 처리에우선하여실행된다. 언제든지처리들중의오직하나만이실제로처리되며, 현재처리되는이러한처리는 WPTR 레지스터 (51) 안에작업공간포인터를갖고있으며, IPTR 레지스터 (51) 안의명령포인터는특수한처리에관계있는프로그램에서명령어순차로부터실행되는다음의명령어를지시한다. 현재처리되지도않고실행을기다리지도않는처리는디스케쥴된다. 처리가스케쥴될때, 현재처리가되거나, 리스트에가해지거나, 혹은실행을기다리는처리 queue 된다. 그러한작성된리스트는작업공간의링크위치 (66) 안에포인터를갖고있는리스트상에서상기리스트의다음처리의작업공간까지각각의처리를갖는링크된리스트처럼구성된다. 리스트상의어느처리의명령어포인터는제 4 도에도시된바와같이작업공간의 IPTR 위치 (65) 안에기억된다. 이러한경우에, 처리기는각각의우선권레벨중의하나를실행하기위하여, 기다리는작성된처리들중의두개의리스트들을유지한다. 게다가, 각각의우선권에준비되어있는하나의타이머리스트를작성하기전에특별한시간들을기다리는작성되지않은처리들중의두개의타이머리스트를유지한다. 제 5 도가우선권 0 처리가제 4 도에 2.In a byte(the Iptr register [Pri], 0 register [Pri], and the Iptr register [Pri]) Purpose: the performance of the selected component of a stagger is started. For the result of the micro command in which a processor is flowed out of ROM13 a action is performed. In that way. A processor shares the time between a plurality of overlap processings practiced in two different priority levels (0 and 1). It both sides all can practice. The priority 0 processing is always performed the priority 1 processing. Alpha-antitrypsin, it is only processed among processings only one in fact. And processed this processing has the workspace pointer in the WPTR register (51). And the command pointer in the IPTR register (51) indicates the performed following command in the program ***ing in the special processing from the command consecutive. Presently, it becomes the processing which processed does not wait for an execution with the di schedule. When a processing is scheduled, a processing is processed, or it is applied in a list, or it is the processing queue. Or waits for an execution. The prepared list is comprised like the linked list having each processing on the list having a pointer in the link position (66) of the work space to the work space of the next processing of a list. As shown in the instruction pointer of a processing on a list is Figure 4, it is memorized in the IPTR location (65) of the work space. In order that one of processor is each priority level it is like thats are enforced, two lists among the prepared processing waited is maintained. Moreover, two timer lists among the prepared processing waiting for special times before preparing prepared one timer list in each priority is maintained. Figure 5 shows the list in which the low priority Keown 1 the priority 0 processing is prepared in Figure 4 of the time when being processed like being illustrated, on the

33 K2E-PAT Page 33 서도시된바와같은현재처리될때의시간에저우선권 1 작성된리스트를도시하는반면에제 4 도는고우선권 0 작성된리스트를나타낸다. 이러한경우현재처리고우선권 0 처리일때, 레지스터뱅크선택기 (41) 는처리기에의하여사용하기위한뱅크 (39) 내에레지스터를선택한다. 따라서 WPTR 레지스터 [0] 는제 4 도에서도시된바와같이현재처리 (L) 의작업공간의 0 의위치상에서포인터를보유한다. IPTR 레지스터 0 메모리에기억된프로그램순서에서다음명령까지포인터를포함한다. 제 4 도에도시된레지스터 (54, 55, 56 및 57) 는현재처리 (L) 가실행되는동안사용된다른값을포함한다. 실행을기다리는우선권 0 처리들의작성된리스트는작업공간이 61, 62 및 63 에도시적으로표시된세개의처리들 (M, N 및 0) 에의해제 4 도에표시된다. 각각의이러한공간들은일반적으로처리 (L) 에표시된것과비슷하다. 53 에기록된 FPTR 레지스터 0 는이러한리스트의앞에서처리되고있는처리 (M) 의작업공간에서포인터를포함한다. 처리 (M) 의작업공간은처리 (M) 이현재처리될때실행되어질프로그램연속내의다음명령에대한포인터를 IPTR 위치 (65) 안에포함한다. 처리 (M) 의링크위치 (66) 는리스트상의다음처리가있는처리 (N) 의작업공간에포인터를포함한다. 지시된리스트상의마지막처리는 63 에서지된작업공간을갖는처리 (0) 이다. 52 에기록된 BPTR 레지스터 [0] 는이러한마지막처리 (0) 의작업공간에포인터를포함한다. 이러한처리 0 의작업공간 (63) 은이전의처리 (N) 의링크위치 (66) 에의해지시되지만, 처리 (0) 의링크위치와차례로처리 (0) 의링크처리 (M) 의경우에는이러한것이리스트상의마지막리스트상의마지막처리같이어떤포인터에포함되지않는다. 또다른처리가또다른처리의작업공간에대해포인터를리스트에가해질때 BPTR 레지스터 (52) 에배치되며, 처리 (0) 의링크위치는리스트에가해지는또다른처리의작업공간에대해포인터를포함한다. 리스트에작성된우선권 (1) 은일반적으로유사하며, 이것은제 5 도에도시되어있다. 이러한경우에, 작성되어있고수행을기다리는우선권 1 처리의리스트는처리 (P,Q 및 R) 로구성된다. S 로기록된또다른우선권 1 처리는도시되어있지만, 이것은현재비작성상태이고링크된리스트의일부분으로구성되어있지않다. FPTR 레지스터 [1] 는수 other hands, figure the fourth shows the list which the high priority Keown 0 is made. In case of being like that, the register bank selector (41) selects the register upon the processing high priority Keown 0 processing date within the bank (39) for using with a processor. Therefore, in Figure 4, as shown in the figure, the WPTR register [0] holds a pointer on the location of 0 of the work space of the processing (L). In the program order memorized in the IPTR register 0 memory, a pointer is included to the next command. Registers (54, 55, 56 and 57) shown in Figure 4 provide the dissimilar value which is used the processing (L) is performed. The prepared list of priority 0 processings waiting for an execution are indicated with three processing (M, and N and 0) in which the work space is indicated on 61, 62 and 63 as an illustration on Figure 4. Generally each this spaces are similar to the thing indicated on the processing (L). The FPTR register 0 recorded in 53 provides the pointer in the work space of the processing (M) processed at the front of such list. The work space of the processing (M) includes the pointer about the next command within the program series which is performed when the processing (M) is handled in the IPTR location (65). The link position (66) of the processing (M) provides the pointer in the work space of the processing (N) having with the next processing edge on a list. In 63, the last processing on the indicated list is the processing (0) having *** work space. The BPTR register (0) recorded in 52 provides the pointer in the work space of such last processing (0). The work space (63) of this processing 0 is indicated with the link position (66) of the processing (N) of the previous. However, is not successively included in any kind of pointer with the link position of the processing (0) in case of the link processing (M) of the processing (0) like the last processing on the tail list on a list. What Lees ReoHa. And the link position of the processing (0) the dissimilar processing is a pointer imposed about the work space of another processing in a list provides the pointer about the work space of another processing applied in a list. Generally the priority (1) prepared of a list is similar. And this is illustrated in Figure 5. In case it is like that, it is comprised of the list of the priority 1 processing which prepared is in wait for a performance of processing (P,Q and R). *** priority 1 processing recorded in S is illustrated. However, it is the ratio preparation state and this is not comprised of a portion of the linked list. The FPTR register [1] provides the pointer about the work space of the processing (P) comprising the first processing on the list which is in wait for a performance. Next

34 K2E-PAT Page 34 행을기다리는리스트상에서제 1 처리를구성하는처리 (P) 의작업공간에대해포인터를포함한다. 각각이처리 (P,Q 및 R) 는상기처리가현재처리될때에다음에명령이들어오게될때부터프로그램단계에대해지시하는 IPTR 위치내에 IPTR 을갖는다. 스케쥴된리스트상의마지막처리와는별개의각각의처리중의링크위치는리스트상에있는다음처리의작업공간에대해포인터를포함한다. 처리는이미확정된 " 디큐 (dequeue)" 과정에의해실행을위한리스트상부로부터행해진다. 현재처리는이미확정된 " 처리후시작 " 과정에의해디스케쥴된다. 제 4 도및도에서도시된바와같이두개의스케쥴된처리리스트를작동하는방식은앞서언급된출원에서설명되었고더이상되풀이하지않겠다. 그러나현재실시예는타임슬라이싱설비를준비하므로, 만약현재처리가저우선권처리이라면현재처리는 " 타임슬라이스 " 라명명된주기후에정지되며, 실행되는스케쥴된리스트상에서다른처리를위한기회를주기위하여제 5 도에서도시된마지막 queue 에서재스케쥴된다. 저우선권처리가제 5 도에서도시된형태의스케쥴된리스트의상부를약하게했을때, 처리기는 dequeue 과정을실행하며, 상기과정의정의에서의라인 (11, 12) 에서볼수있을때, 만약처리가라인 (12) 에따라 ( 저우선권처리를위한경우에서 ) 우선권 1 처리이라면시간슬라이스레지스터 (80) 는 " 시간슬라이스의길이 " 가요구된시간과함께클록레지스터 (81) 에의해지시된현재총시간의값을가지고부하된다. 타임슬라이스길이는적당한시간간격에적합하도록선택되며, 이같은경우에 1000 명령이실행하는데필요한시간을가질수있다. 이러한시간슬라이스는콘스탄트박스 (40) 에기억된다. 저우선권처리가 " 점프 " 기능혹은 " 루프끝 " 작동을실행할때, 처리기는점프기능과루프끝작동의정의의단부로부터볼수있는것처럼 " 시간슬라이스 " 과정을실행한다. 앞에서정의된 " 시간슬라이스 " 과정에따라서처리기는현재처리의우선권 1 이고, 클록레지스터에의해지시된시간이시간슬라이스레지스터 (80) 에의해지시된시간과같거나경과하는경우에그순차는실행되는데그순차내에서현재처리의작업공 since command come to one's ears when a processing is handled, each processing (P,Q and R) has IPTR within the IPTR location indicated on the program phase. The link position of the last processing on the scheduled list and distinct each in-process provide the pointer about the work space of a processing it has on a list. A processing is performed with the process of being already settled "dequeue" from the list top for an execution. Presently, a processing is de-scheduled with the process of being already settled "post treatment beginning". In Figure 4 and drawing, as shown in the figure, the mode will operating two scheduled processing lists any more will notrepeat the mode was explained in the before mentioned application. But presently, the embodiment prepares for the time slicing facility. Therefore, if a processing is the low priority Keown processing, a processing is stopped in after period of time named at "time slice". And it respects to give the opportunity for the other processing on the performed and scheduled list and it is rescheduled in the final queue illustrated in Figure 5. When the low priority Keown processing made the top of the illustrated and scheduled list of a form weak in Figure 5, a processor performs the dequeue process. And when it can look in lines (11, 12) at the definition of process, if a processing is the priority 1 processing according to the line (12) (in the case for the low priority Keown processing), the time slice register (80) is loaded having the value of the total duration indicated with the clock register (81) with the time when "the length of the time slice" is required. The time slice length is selected in order to be suitable for the appropriate the time interval. And 1000 command practices in this case but the time slice length can have the necessary time. This time slice is memorized in the constant box (40). When the low priority Keown processing enforces "A jump" function or "the loop end" operation, a processor performs the process as it can look from the end part of the definition of the jump function and loop end operation "the time slice". A processor is the priority 1 of a processing according to the process of being defined "the time slice" in front of. In case the indicated with the clock register time is the same as that of the time indicated with the time slice register (80) or the time passes, the consecutive is performed but the workspace pointer and priority of the present processing are loaded in the consecutive by the processing descriptor register (46). And "***" process is performed. It inspects that a processing is

35 K2E-PAT Page 35 간포인터및우선권이처리설명기레지스터 (46) 안으로부하되며, " 런 " 과정이실행되어, 리스트가작성된우선권 1 의단부에처리를부가함으로써처리가재스케쥴되도록실행되는것을검사한다. 또한과정이 SNP 프래그 (58) 를값 1 로고정시켜처리기가현재처리의실행을멈추고처리기에의해작동을원하는어떤처리나고우선권의요구가있지않는한리스트가스케쥴된우신권 1 의상부로부터또다른처리를실행하기시작한다. 또한현재실시예는제 6 및 7 도에도시된형태의타이머리스트를위한설비를작성한다. 제 6 도가우선권 0 처리의링크된타이머리스트를도시한것에비해제 7 도는고우선권 1 처리의유사한링크된리스트를도시한다. 제 6 도에서저우선권처리가문자 T, U 및 V 로표시한데비해제 7 도에서는고우선권처리를 W, X 및 Y 로표시한다. 두개의리스트는거의유사하여, 제 6 도의리스트만을상세히설명했다. 리스트내에각각의처리를위한작업공간 (60) 은제 6 도에도시되어있다. 타이머리스트의정면은 TPTR 이라명명된포인터값을갖는단일워드기억위치 (90) 에의해지속된다. 특별한우선권의타이머리스트상에처리들이없을때, 우선권을위한 TPTR 은특수치 " 비처리.P" 에고정된다. 반면에, TPTR 은기억위치 90 점내에타이머리트스상에제 1 처리의작업공간 (60) 의 " 변수 0" 위치 ( 또한, 0 위치라명명 ) 로가진다. 이것은제 6 도에도시되어있다. 타이머리스트내의처리는시간순서된방식안에모두링크된다. 각각의처리작업공간은처리가스케쥴된시간을지시하는시간위치 (69) 내에한값을포함한다. 각각의처리작업공간의 T 링크위치 (68) 는타이머리스트상에다음처리의작업공간의 0 위치로포인터를포함한다. 리스트상에각각의처리작업공간의위치 (65) 는처리가스케쥴되고현재처리가될때사용을위하여프로그램순차 (181) 에서다음의명령으로포인터를기억한다. 유효시간프래그 (84) 는타이머리스트상에처리가있고, 타이머리스트상에처리가없을시 0 값으로될때 1 값으로고정된다. 차순시간레지스터 (85) 는타이머리스트전면에서처리의위치 (69) 로부터받는시간을포함한다. 이러한면에서, 레지스터 (85) 는연관된타이머상에어떠한처리가스케쥴되어야하는가장빠른시간의지시를포함한다. 어떤레지스터이든지간에리 performed so that a processing be rescheduled by adding a processing to the end part in which a list is prepared of the priority 1. Moreover, as long as it does not have the demand of any kind of processing in which the process fixes the SNP flag (58) with the value 1 and in which a processor stops the execution of a processing and desiring an operation with a processor or the high priority Keown, the another process begins to be practiced from the top in which a list is scheduled of the usin Keown 1. Moreover, presently, the embodiment prepares the facility shown in the sixth and figure 7 for the timer list of a form. Figure 6 shows the linked timer list of the priority 0 processing. And figure 7 shows the similar and linked list of the high priority Keown 1 processing. In Figure 6, the high priority Keown processing is indicated in Figure 7 by W, and X and Y the low priority Keown processing indicates by the character T/6, and U and V. Two lists was nearly similar. It circumstantially illustrated only the list of Figure 6. The work space (60) for each processing is illustrated within a list in Figure 6. The front side of the timer list is continued by the single word storage position (90) having the point value which is named the front side of the timer list is TPTR. TPTR for the priority is the speciality value " nonprocessing it does not have processings on the timer list of the special priority. It is fixed to P". On the other hand, TPTR has within the storage position 90 point on the timer *** to "the variable 0" location (it moreover names it is 0 location) of the work space (60) of the first processing. This is illustrated in Figure 6. The processing within the timer list is altogether linked in *** mode. Each processing task space provides the single-value within the temporal position (69) indicating the time when a processing is scheduled. T link position (68) of each processing work space provides a pointer with 0 location of the work space of the next processing on the timer list. The location (65) of each processing work space memorizes a pointer on a list for use in the program consecutive (181) as the following command a processing is processed a processing is scheduled. The effective time flag (84) has a processing on the timer list. The order time register (85) provides the time to receive from the location (69) of a processing in the timer list front side. The register (85) in this side provides the indication of the most fast time in which any processing has to be scheduled on the timer related with. It is prepared for the timer list indicated in the backplane of a list it is any kind of register. The work space of the last processing on the timer list is the speciality value " nonprocessing in the bit link position (68) of the work space. It has P". Rather the front side of a list is indicated with the use of the memory location (90) than the register. The front side of a list is

36 K2E-PAT Page 36 스트의후면에지시된타이머리스트를위하여준비된다. 타이머리스트상에마지막처리의작업공간은작업공간의트링크위치 (68) 안에특수치 " 비처리.P" 를갖는다. 리스트의전면은레지스터보다오히려메모리위치 (90) 의사용에의해지시된다. 이러한식으로리스트의전면은리스트상의모든중간엔트리가동일시되는것같이메모리위치의사용에의해동일시되며, 이것은순차적인시간순서된방식에서타이머리스트상에또다른처리를삽입하거나삭제하는데필요한작용을간소화한다. 처리는타이머리스트상에서제 1 처리가나타나기전에처리를삽입시키는데필요하게되거나, 삽입될처리가스케쥴되는시간에의존하는리스트를지나처리를부분통로로삽입시키는데필요하게됨으로써동일시된다. 제 3 도에서도시된타이머논리의상기서술에서볼수있는것처럼, 유효시간프래그 (84) 중의하나가적당한우선권타이머리스트상에처리가있다는것을지시하는값 1 로고정된다면, 제 3 도에서도시된타이머논리는클록레지스터 (81) 에의해지시된시간을갖는차순시간레지스터 (85)( 리스트상에서어떤처리를스케쥴하기위한제 1 시간을지시하는 ) 에서도시된시간들을비교하며, 제 1 처리를스케쥴하기위한시간이도달했다면, 타이머논리는적당한요청신호를상태멀티플렉서 (36) 로준비한다. 처리기는적당한타이머리스트로부터제 1 처리를제거하고, 적당한유효시간프래그, 차순시간레지스터및 TPTR 위치 (90) 를새롭게함으로써그러한요청신호를응답한다. 그다음에이것은타이머리스트의새로운상태에영향을미친다. " 시간세트.P" 값은처리가더이상타이머리스트상에있지않다는것을지시할목적으로처리작업공간을위하여 T 링크위치 (68) 안으로기록된다. 처리가현재처리를아직안하거나, 스케쥴된리스트상에벌써했다면, 처리는제 4 혹은 5 도에서보여준형태의스케쥴된리스트에가해지게되거나, 혹은현재처리가스케쥴리스트없는것이된다. 타이머리스트의상부에서처리를제거하는데의처리기작용은앞서정의한 " 타이머요청조작 " 에설명된다. [ 타이머입력명령어 ] [Timer input command] 처리가 A 레지스터 (54) 안으로재스케쥴되고, " 타이머입력 " 작동을실행하는시간후에부하함으로써처리는 " 타이머입력 " 을 together regarded to this type with the use of the memory location with thing. And all in-between entries on a list are regarded. As to a processing, before the first processing shows up on the timer list, it inserts a processing but it is necessary to have, or. In Figure 3, it was fixed to the value 1 which indicated that it had a processing on the priority timer list in which one of effective time flag (84) like the thing, can look in the narration of the timer logic of being illustrateds were appropriate. If it is the case, the timer logic of being illustrated in Figure 3 compared illustrated times in the order time register (85) (the period for scheduling any kind of processing is indicated on a list) having the time indicated with the clock register (81). And the time for scheduling the first processing reached. The timer logic prepares for the fit request signal in the state multiplexer (36). A processor removes the first processing from the fit timer list. It answers that request signal by making the fit effective time flag, and the order time register and TPTR location (90) new. And then, this has an effect on the new state of the timer list. " The time set. The P" value is recorded as the purpose of indicating that it any more does not have a processing on the timer list for the processing task space as T link position (68) inside. A processing yet did not processing, or it already did on the scheduled list. A processing is imposed in the scheduled list shown in the fourth or figure 5 of a form, or or a processing do not have the present processing with the schedule list. In the top of the timer list, the processor action of the stem removing a processing is explained in "the timer request manipulation" which it before defines. A processing is rescheduled by A register (54). By carrying a load after the time to enforce "timer input" operation a processing executes the command including "timer input".

37 K2E-PAT Page 37 포함한명령어를실행한다. 제일먼저처리기는, 클록레지스터에의해지시된현재시간이 A 레지스터에의해지시된시간이후에나타나는지의여부를검사하고, 만약나타난다면어떠한작용도발생하지않도록처리는스케쥴된상태로남아있다. 그러나만약이러한상태에직면하지않는다면, " 타이머입력 " 의정의에규정된순차는특수치 " 대기.P" 가처리작업공간의상태위치 (67) 안에기록되면서발생한다. 처리가재스케쥴되는시간은 A 레지스터안에도시된시간후에존재하며, 따라서 A 레지스터에지시된시간은처리가재스케쥴되는시간을지시하기위한 1 에의해증가한다. 처리기는처리가재스케쥴되는시간에처리작업공간의시간위치안으로기록되는 " 타이머리스트내부삽입 " 과정을실행하며, 처리기는처리가시간순서된순차에따르게하기위해처리를리스트내의한위치에서적당한타이머리스트안에꼭맞게한다. 또한처리기는 SNP 프래그를처리기가다른처리를실행하게시작할수있도록 1 값에고정한다. " 타이머입력 " 명령어로실행된처리는적당한시간이지나갔을때재스케쥴된다. First of all, a processor inspects whether or not of the paper in which the current time indicated with the clock register shows up after the time indicated with A register. A processing remains as the scheduled state so that any action be generated if it shows up. But the consecutive which is not confronted with such state, and if it is the case, is prescribed in the definition of "the timer input". Is the speciality value " atmosphere. It is generated while P" is recorded in the status position (67) of the processing work space. The time when a processing is rescheduled exists after the time illustrated in A register. And therefore the time indicated in A register increases the time when a processing is rescheduled with 1 for indicating. A processor performs the process of being recorded as the time inside of position of the processing work space "the timer list interpolation" in the time when a processing is rescheduled. And in order to a processing makes follow the time *** consecutive the time surely fits a processing a processor in one location within a list in the appropriate the timer list. Moreover, as to a processor, in order to start the SNP flag so that a processor enforce the other processing it fixes on 1 value. "The timer input" As to the processing performed to a command, it is rescheduled when the appropriate the time passed. [ 교대타이머입력명령어 ] [Alternation timer input command] 위에서언급된현안인특허출원에서, 교대처리가설명되어있다. 그러한교대처리는실행을위한다수의교대성분의하나를선택한다. 교대식의각각의성분은입력이나, 유사한처리에의해뒤따르는도약구성한다. 본예는실행을위해다수의교대성분중의하나를선택하는타이머교대처리를실행할수있다. 교대타이머의각각이성분은메세지채널입력 ( 내부혹은외부채널중하나로부터 ), 도약혹은유사한처리에의해뒤따르는타이머압력을구성한다. 만약채널이준비되며, 상기언급된현안의특허출원에서설명된것처럼도약성분이항상선택된다면, 메세지채널입력성분은선택된다. 타이머입력성분은클록레지스터내의값이타이머입력에규정된시간을초과할때선택되어진다. 본예는이미언급된현안의특허출원에서설명되며, 이명세서에서는되풀이하지않는것과같은방식으로정확하게타이머입력에종속하지않는교대처리를실행한다. 현재처리가다수의교대성분을가질때, 각각의성분은만약하나이상의성분이선택될수있다면, 결정하도록심사된다. 만약어떠한성분도선택될수없다면, 처리는성분중하나가선 위에서언급된현안인특허출원에서, 교대처리가설명되어있다. 그러한교대처리는실행을위한다수의교대성분의하나를선택한다. 교대식의각각의성분은입력이나, 유사한처리에의해뒤따르는도약구성한다. 본예는실행을위해다수의교대성분중의하나를선택하는타이머교대처리를실행할수있다. 교대타이머의각각이성분은메세지채널입력 ( 내부혹은외부채널중하나로부터 ), 도약혹은유사한처리에의해뒤따르는타이머압력을구성한다. 만약채널이준비되며, 상기언급된현안의특허출원에서설명된것처럼도약성분이항상선택된다면, 메세지채널입력성분은선택된다. 타이머입력성분은클록레지스터내의값이타이머입력에규정된시간을초과할때선택되어진다. 본예는이미언급된현안의특허출원에서설명되며, 이명세서에서는되풀이하지않는것과같은방식으로정확하게타이머입력에종속하지않는교대처리를실행한다. 현재처리가다수의교대성분을가질때, 각각의성분은만약하나이상의성분이선택될수있다면, 결정하도록심사된다. 만약어떠한성분도선택될수없다면, 처리는성분중하나가선택될수있을때까지재스케쥴된다. 그다음에처리는재스케쥴되고, 성분은재심사되며, 그들중의하나는선택된다. 메세지채널입력성분과도약성분의심사는앞서언급한바와같이실행된다. 모든성분이심사됐을때, 처리작업공간의상태위치 (67) 는두개의

38 K2E-PAT Page 38 택될수있을때까지재스케쥴된다. 그다음에처리는재스케쥴되고, 성분은재심사되며, 그들중의하나는선택된다. 메세지채널입력성분과도약성분의심사는앞서언급한바와같이실행된다. 모든성분이심사됐을때, 처리작업공간의상태위치 (67) 는두개의특수치 " 구동.P" 나 " 준비.P" 중하나를포함한다. 만약상태위치 (67) 이 " 준비.P" 만을포함한다면이성분처리중의하나는선택될수있다. 타이머입력성분의심사가진행되는동안, T 링크 S(68) 및시간위치 (69) 는제각기특수목적으로사용된다. T 링크위치 (68) 는두개의특수치 " 시간세트.P" 혹은 " 시간비세트.P" 중하나를갖는다. 아직어떤타이머입력도심사되지않았고, 제 1 타이머입력이심사될때, " 시간세트.P" 로변한다는것을지시하는 " 시간비세트.P" 로초기화된다. 제 1 타이머입력이심사될때, 타이머위치 (69) 는규정된시간으로초기화된다. 다음에, 각각의타이머입력이심사될때, 시간위치는, 만약시간위치 (69) 에기록된시간보다더빠르다면, 규정된시간으로갱신된다. 따라서모든성분이심사됐을때, 시간위치 (69) 는어떤타이머입력에의해규정된가장빠른시간을갖는다. 교대처리는만약 T 링크위치 (68) 가 " 시간세트.P" 값과클록레지스터의값만을포함한다면시간위치 (69) 에서시간을초과한다. 모든성분이심사됐을때, 타이머교대처리는, 만약어떤성분이상태 (67) 와 T 링크 (68) 및시간위치 (69) 를사용해선택될수있다면, 결정된다. 만약어떤성분도선택될수없다면, 처리는디스케쥴되며, 어떤타이머입력성분이심사됐을때, 처리는적당한타이머리스트상에위치한다. 적어도하나의성분이선택될수있을때, 각각의성분은재심사되며제 1 선택성분은선택된다. 앞서언급된현안의특허출원에서설명된것처럼, 처리작업공간 (60) 의 0 위치는만약어떤성분이선택되었을때의기록으로사용된다. 채널입력성분과도약성분의재심사는앞서언급된현안의특허출원처럼실행된다. 다음과같이타이머입력성분의재심사는 T 링크 (68) 및시간위치 (69) 를사용한다. 만약, 제 1 타이머입력성분이재심사될때, 타이머교대처리가타이머상에없다면처리중의하나는타이머리스트상에위치해있었고다음에처리는제거되었으며, 전혀타이머리스트상에는존재하지않았다. 전자경우에시간위치 (69) 는매우빠 특수치 " 구동.P" 나 " 준비.P" 중하나를포함한다. 만약상태위치 (67) 이 " 준비.P" 만을포함한다면이성분처리중의하나는선택될수있다. 타이머입력성분의심사가진행되는동안, T 링크 S(68) 및시간위치 (69) 는제각기특수목적으로사용된다. T 링크위치 (68) 는두개의특수치 " 시간세트.P" 혹은 " 시간비세트.P" 중하나를갖는다. 아직어떤타이머입력도심사되지않았고, 제 1 타이머입력이심사될때, " 시간세트.P" 로변한다는것을지시하는 " 시간비세트.P" 로초기화된다. 제 1 타이머입력이심사될때, 타이머위치 (69) 는규정된시간으로초기화된다. 다음에, 각각의타이머입력이심사될때, 시간위치는, 만약시간위치 (69) 에기록된시간보다더빠르다면, 규정된시간으로갱신된다. 따라서모든성분이심사됐을때, 시간위치 (69) 는어떤타이머입력에의해규정된가장빠른시간을갖는다. 교대처리는만약 T 링크위치 (68) 가 " 시간세트.P" 값과클록레지스터의값만을포함한다면시간위치 (69) 에서시간을초과한다. When all components were examined, the timer stagger any kind of component can be selected by using the state (67), T link (68) and temporal position (69). It is determined. Any kind of component could not be selected. A processing was de-scheduled. And when any kind of timer input component was examined, a processing is located on surface the fit timer list. At least, when one component can be selected, each component is reexamined and the first selection component is selected. As it is explained in the patent application of the before mentioned pending problem. 0 location of the processing work space (60) is used as the register when any kind of component was selected. The re-examination of the curvet component and channel entry component is performed like the patent application of the before mentioned pending problem. T link (68) and temporal position (69) are used the re-examination of the timer input component like a next. When the first timer input component was if reexamined, if it did not have the timer stagger on a timer, one of the in-process was positioned on the timer list and next a processing was removed. And it did not exist in the timer list at all. The temporal position (69) in the electronics case provides the time when the very fast timer input component

39 K2E-PAT Page 39 른타이머입력성분이선택하게될때의시간을포함한다. 후자경우에시간위치 (69) 는성분처리의심사후즉시 " 클록레지스터 " 값을포함한다. 시간위치는동일한타이머입력성분의모든재심사값을보유한다. 타이머입력성분은만약시간위치 (69) 의내용이규정된시간일때에만선택된다. 제 1 타이머입력성분이재심사될때, 타이머교대처리가아직타이머상에있다면, 선택타이머입력성분은없어지나, 선택채널입력성분은있게된다. 이러한경우에타이머입력성분의제 1 재심사는타이머리스트로부터처리를제거하며, 어떤타이머입력성분의선택을방지하는 " 시간비세트.P" 값으로 T 링크위치 (68) 를설정한다. 이러한경우에무엇을사용하여도시간위치 (69) 를만들수없다. 이행타이머교대처리가 " 타이머교대시작 " 인명령어는각각의타이머성분을위하여 " 구동타이머 " 에의해뒤따른다. 만약처리기가교대명령어에결합된다면, 처리기는또한각각의모든메세지채널을위하여 " 구동채널 " 을실행할것이다. 그다음 " 타이머교대대기 " 와각각의타이머압력을위한 " 비구동타이머 " 및채널입력을위한 " 구동채널 " 이계속하여뒤따른다. 뒤이어 " 교대끝 " 작용이뒤따른다. 타이머교대처리에의해실행된제 1 명령어는 " 타이머교대시작 " 동작이며, 이작용의정의에서볼수있었던것처럼, 라인 (2) 에따라특수치 " 구동 P" 는처리를위하여상태위치 (67) 에기록되고, 라인 (3) 에따라특수치 " 시간비처리.P" 는처리작업공간을위하여 T 링크위치 (68) 에기록된다. 어떠한채널입력성분및도약성분은앞서언급된현안의특허출원에서처럼 " 구동채널 " 및 " 구동도약 " 에의해심사된다. 어떠한타이머입력성분은 A 레지스터안으로감시값을부하하고, B 레지스터안으로타이머성분을위하여규정된시간을부하하며, " 구동타이머 " 동작을실행함으로서성사된다. 이작용의정의에따라, 라인 (2,3) 은 A 레지스터안의감사기차거짓인지아닌지를검사한다. 만약거짓이라면, 타이머입력성분은무시되며, 명령어는다른영향을받지않는다. 감사치가거짓이아니라면, 정의의라인 (5) 에따라, 처리기는정의의라인 (7) 에서시작하는순차를수행한다. 이것은 T 링크위치 (68) 로부터얻은값을 0 레지스터로부하하고, 라인 (8) 의값이라인 (9) 에 selects. The temporal position (69) in the latter case provides the examination of the component processing, realtime, "the clock register" value. The temporal position holds all re-examination values of the same timer input component. The timer input component is selected in the time task time when the content of the temporal position (69) is prescribed. When the first timer input component is reexamined, it yet has the timer stagger on a timer. The selection timer input component is removed. But it has the selector channel input component. " time Bissett which the first re-examination of the timer input component removes a processing from the timer list in case of being like that, and prevents the selection of any kind of timer input component. T link position (68) is set up as the P" value. Even if a what is used in case of being like that, the temporal position (69) cannot be made. The command in which the transition timer stagger is "timer alternation beginning" is followed for each timer component with "drive timer". A processor is combined in the alternation command. If it is the case, a processor will enforce "the drive channel" for moreover, each all message channels. Next, and then, "the drive channel" for "the deactivate timer" for "the timer alternation atmosphere" and each timer pressure and channel entry are followed. ***, "the alternation end" action is followed. The speciality value " time nonprocessing according to the line (3) the first command performed by the timer stagger the speciality value "drive P/6" is recorded in the status position (67) could look in the definition of "timer alternation beginning" operation, this action according to the line (2) for a processing. P" is recorded in T link position (68) for the processing work space. The channel entry component and any curvet component are examined like the patent application of the before mentioned pending problem with "the drive channel" and "drive curvet". Any timer input component carries a load of the monitoring value by A register. It carries a load of the time prescribed by B register for the timer component. According to the definition of this action, lines (2,3) inspect it is not it is the inspection article difference false in A register. It is the false. If it is the case, the timer input component is ignored. And a command is not influenced. Dissimilar. It is not inspection value the false. If it is the case, a processor performs the consecutive started in the line (7) of the definition according to the line (5) of the definition. The value of the line (8) is " time Bissett according to the line (9) this carries a load of the obtained value with 0 register from T link position (68). P "according to the line (9)" time set. The examination which

40 K2E-PAT Page 40 따라 " 시간비세트.P" 인지, 라인 (9) 에따라 " 시간세트.P" 인지를테스트하기위한심사를가져온다. 만약값이 " 시간비세트.P" 인것이발견된다면, " 시간세트.P" 값은라인 (11) 에따라 T 링크위치안에기록되며, B 레지스터내에지시된시간은정의의라인 (12) 에의해요구된것처럼처리작업공간을위하여시간위치 (69) 안에기록된다. 이것은처리에의해심사된제 1 타이머입력성분을위하여발생한다. 라인 (13) 의조건이심사되는연속타이머입력은라인 (14) 을뒤따르는순차가발생할경우와부합된다. 라인 (15) 는처리를위하여시간위치 (69) 안에기록된시간값 0 레지스터 (57) 안으로부하되며, 이러한시간값은이것의정의의라인 (17) 의조건과부합되는지를보기위해테스트된다. 만약상기시간이 B 레지스터내에지시된시간이후이라면, B 레지스터내에시간은처리를위하여시간위치 (69) 안으로기륵된다. 라인 (19,20) 은, 만약 0 레지스터에지시된시간이 B 레지스터에지시된시간이후가아니라면어떠한작동도일어나지않는다는것을지시한다. 마지막으로 B 레지스터는정의의라인 (21) 에의해요구된것처럼 C 레지스터로부터의값으로부하된다. 이러한면에서처리는각각의가능성이있는타이머입력을심사하며, 처리의시간위치 (69) 는새롭게하여, 심사후에가장빠른타이머성분의시간을포함한다. 이때문에각각의타이머성분을위하여연속된 " 구동타이머 " 동작은효과적으로가장빠른시간성분을결정하고, 심사된성분의가장빠른시간을가진시간위치 (69) 는더욱더새롭게하는것을볼수있다. 그다음에처리는 " 타이머교대대기 " 동작을설행한다. 규정의라인 (2) 에따라, 이것은처리작업공간의 0 위치를 -1 값으로초기화하며, 만약교대처리의어떤성분이이미선택되었다면, 결정하기위해테스트한다. 정의의라인 (3, 4) 에따라, 그것은 T 링크위치 (68) 로부터의값을 B 레지스터안으로판독하며, 시간위치 (69) 로부터의값을 A 레지스터안으로판독한다. 라인 (5, 6) 은, 만약처리가 " 시간세트.P" 값을가졌고, 클록레지스터가처리의시간위치 (69) 내에지시된시간이후의시간을나타낸다면, 라인 (8, 9) 에정의된순차는발생한다는것을보여준다. 특수치 " 준비.P" 는처리를위하여상태위치 (67) 안으로기록되며, 클록레지스터에의해지시된현재시간은처리를위하여시간위치 (69) 안으로기록된다. 처리는 respects it does with test it is P" is brought about. If, a value is " time Bissett. P "the thing is discovered" time set. According to the line (11), the P" value is recorded in T link position. This is generated for the first timer input component examined with a processing. The series timer input in which the condition of the line (13) is examined corresponds with the case that the consecutive following the line (14) around is generated. The line (15) is loaded by the temporal value 0 register (57) recorded for a processing in the temporal position (69). It is the time next in which the time is indicated within B register. If it is the case, the time is *** within B register for a processing to the temporal position (69) inside. Lines (19,20) indicates that the time indicated in 0 register the operation *** if it is not time next indicated in B register does not occur. Finally, B register is loaded in a value from C register B register is required with the line (21) of the definition. The processing in this side provides the time of the timer component examining the timer input in which it has each possibility, and makes new, and is most fast after an examination. For this reason, the operation continued for each timer component "the drive timer" determines the effectually,effectivelymost fast time factor. And then, a processing tells "timer alternation atmosphere" operation about the theory row. According to the line (2) of the rules, this initialized 0 location of the processing work space as -1 value. And any kind of component of a stagger was already selected. It tests in order to determine. According to lines (3, 4) of the definition, that reads a value from T link position (68) by B register. And a value from the temporal position (69) is read by A register. Lines (5, 6), if, a processing is " time set. It had the P" value. The clock register shows the time of the indicated time next within the temporal position (69) of a processing. If it is the case, the consecutive defined in lines (8, 9) shows being generated. The speciality value " preparation. P" is recorded for a processing by the status position (67). And the current time indicated with the clock register is recorded for a processing by the temporal position (69). It is not de-scheduled and a processing moves the next command. But it is not condition of the line (6) of the

41 K2E-PAT Page 41 디스케쥴되지않고다음명령어를이동한다. 그러나만약정의의라인 (6) 의조건이참이아니라면, 처리는정의라인 (12) 으로이동한다. 처리를 C 레지스터로부하함으로써처리를위하여상태위치 (67) 의내용을테스트하며, 라인 (14) 은처리가 " 준비.P" 값을포함하였는지를테스트한다. 만약그렇다면, 라인 (16) 에따라클록레지스터에의해지시된현재시간이처리를위하여시간위치 (69) 안으로기록되고, 처리는디스케쥴되지않는다. 그것은또다른교대입력때문에준비되며, 처리는다음명령어로이동한다. 그러나만약정의의라인 (16) 에따라특수치 " 구동.P" 가처리의상태위치로부터발견되었다면, 이것은어떠한교대성분도아직준비하지않았고, 라인 (17) 에서시작하는순차가발생하는것을지시할것이다. 특수치 " 대기.P" 는처리를위하여상태위치 (67) 안으로기록되며, 라인 (19, 20) 은만약처리가타이머성분을기다린다면테스트한다. 만약라인 (20) 에의해처리가 " 시간세트.P" 값을갖는다면, A 레지스터의내용은처리가스케줄됐을때시간을지시할목적으로 1 에의해증가되며라인 (23) 에의해 " 타이머리스트내삽입 " 과정이실행된다. 이것은적당한우선권타이머리스트상으로처리가위치하는효과를가지게하기위해처리가재스케쥴되지만, 이때의시간의지시를포함한다. 정의의라인 (24) 에따라 B 레지스터는만약처리가어떠한타이머성분을기다리지않는다면, B 레지스터는 " 시간비세트.P" 값을갖고, 이것은처리가아직타이머입력보다오히려채널입력을기다리는곳에서나타난다. 이런상황에서라인 (25) 을뒤따르는순차는발생하고, 처리를위한명령어포인터는처리의 IPTR 위치 (5) 내에기억되어있으며, SNP 프래그는값 1 로설정되므로처리는디스케쥴된다. 정의에서라인 (6 내지 9) 은처리가타이머입력때문에준비되는지테스트한다. 라인 (13,14) 는, 만약처리가비타이머입력, 예를들어채널입력때문에시작한다면, 테스트한다. 상향성의라인 (16) 은처리가준비하지않는곳에서사용된다. 만약디스케쥴되지않고, 다음에재스케쥴될때, 처리에의해실행된다음명령어는각각의타이머성분을위한 " 비구동타이머 " 와, 어떠한도약성분을위한 " 비구동도약 " 및어떠한채널성분을위한 " 비구동채널 " 작동어효과가있다. 채널입력성분및도약성분은위에서언급된현안의특허출 definition a truth. If it is the case, a processing moves to the definition line (12). In the line (14), a processing " preparation a processing is carried a load of C register. It tests whether the P" value was included or not. Then the current time indicated with the clock register is recorded in the temporal position (69) inside according to the line (16) for a processing. A processing is not de-scheduled. That is prepared due to the another alternation input. And a processing moves to the next command. But if, the speciality value " drive according to the line (16) of the definition. A thing generated around the consecutive in which P" was discovered from the status position of a processing, and in which this any alternation component yet did not prepare, and starting in the line (17) will be indicated. The speciality value " atmosphere. P" is recorded for a processing by the status position (67). And lines (19, 20) test if a processing waits for the timer component. If, a processing by the line (20) is " time set. The insertion " process is performed within P "using the line (23) it has a price the content of A register is increased to the purpose of indicating the time with 1" timer list. This provides the indication of the time at this time it has the effect that a processing is positioned to the appropriate the priority timer list phase. B register is " time Bissett the timer component in which a processing is is not waited B register according to the line (24) of the definition. It has the P" value. This shows up in the place rather where a processing yet waits for the channel entry than the timer input. In such situation, the consecutive following the line (25) around is generated. The instruction pointer for a processing is memorized within the IPTR location (5) of a processing. And a processing is de-scheduled since the SNP flag is set up as the value 1. In the definition, whether a processing is prepared due to the timer input or not the line (6 through 9) tests. As to lines (13,14), a processing therefore starts with the ratio timer input, for example, the channel entry. If it is the case, it tests. The line (16) of the upper direction is used in the place which a processing does not prepare. Is not if de-scheduled. Next when it is rescheduled, "the deactivate channel" operation effect for "deactivate curvet" for "deactivate timer" for each timer component and any curvet component and any channel element have as to a command, after being performed by a processing. As the channel entry component and curvet component are explained in the patent application of the pending problem mentioned by

42 K2E-PAT Page 42 원에서설명된것처럼, " 비구동채널 " 및 " 비구동도약 " 동작에의해재심사된다. 타이머교대처리는 " 비구동타이머 " 동작의정의에따라타이머입력성분을재심사한다. 처음에 A 레지스터는교대성분이처리에의해선택되어야하는연속프로그램명령어를위치할수있도록하기위해프로그램순차에서필요한오프셋지시하는코드오프셋을가지고부하된다. 감시값은 B 레지스터안으로부하되고, C 레지스터는처리가스케쥴되는시간과함께부하된다. 정의의라인 (2) 은감시값이거짓인지와, 그렇다면이성분은선택될수없는지, 또한 A 레지스터가선택기거짓값을가지고부하되는지를검사한다. 감시가거짓이아니라면, 처리는처리를위한 T 링크위치 (68) 의내용을심사한다. 세가지생각을할수있다. 첫째로, T 링크위치는, 만약시간위치 (69) 내의시간이 C 레지스터내에규정된시간을초과한다면, 성분이선택될이러한경우에정의의라인 (10) 에따라서 " 시간세트.P" 값을포함한다. 이것은정의의라인 (14) 에서조건이며, 만약부합된다면, 처리는 " 선택된처리인가 " 과정을실행한다. 상기과정의정의에대한라인 (5, 6) 에따라, 처리작업공간의 0 위치가 -1 값을포함하는지안하는지를검사한다. 만약포함한다면이성분은선택되며, 정의의라인 (8) 에따라작업공간의 0 위치는 A 레지스터로부터의코드오프셋을가지고부하된다. 만약작업공간의 0 위치가과정이정의된라인 (10) 에따라 -1 값을갖기않는다면, 성분처리는이미선택되어, 현재는선택될수없다. 만약 " 비구동타이머 " 동작이, 처리의 T 링크위치 (68) 가 " 시간세트.P" 혹은 " 시간비세트.P" 과는다른값을포함한것을발견한다면, 이것은 " 비구동타이머 " 정의의라인 (18) 내의상황을수반한다. 이것은처리가아직타이머리스트상에있어 T 링그위치 (68) 가리스트상의또다른처리로포인터를포함할때나타난다. 그러므로처리가아직타이머리스트상에대기하고, 처리가 " 타이머리스트상의제거 " 과정에의해타이머리스트로부터제거될때, 타이머성분은선택되지않는다. 이것은 " 시간비세트.P" 값을처리를위하여 T 링크위치 (68) 안으로기록되게한다. " 비구동타이머 " 동작은 T 링크위치가정의의라인 (8) 에따라 " 시간비세트.P" 값을포함하는것을발견한다. 이러한경우에 T 링크위치 (68) 는이값을처리가타이머리스트상이있었을동안실행되었던이전의 the upper part. It is reexamined with "the deactivate channel" and "deactivate curvet" operation. According to the definition of "the deactivate timer" operation, the timer stagger reexamines the timer input component. First, a register is loaded in order to be the series program instruction in which the alternation component has to be selected with a processing positioned, having the code offset indicated in the program consecutive with offset necessary. The monitoring value is loaded by B register. C register is loaded with the time when a processing is scheduled. As to the line (2) of the definition, the monitoring value is the false, then a binary cannot be selected, whether it inspects whether moreover, A register has the selector false value and it is loaded. It is not monitoring the false. If it is the case, a processing screens the content of T link position (68) for a processing. It can think of the man of influence paper. Firstly, " time set according to the line (10) of the definition T link position the time within the temporal position (69) exceeds the time prescribed within C register, and if it is the case, that a component is selected. The P" value is included. In the line (14) of the definition, this corresponds a condition. If it is the case, a processing performs "the selected processing approval" process. According to lines (5, 6) about the definition of process, it inspects whether whether 0 location of the processing work space includes -1 value or not does not perform or not. A binary is selected if it includes. And 0 location of the work space is loaded according to the line (8) of the definition having the code offset from A register. Is not to have -1 value according to the line (10) in which the process of 0 location of the work space is defined. If it is the case, the component processing is already selected. Presently -1 value cannot be selected. If, "the deactivate timer" operation, T link position (68) of a processing is " time set. P "or" time Bissett. The situation within the line (18) of P "this the it includes the other value thing is discovered" deactivate timer " definition is accompanied. A processing yet shows up as to the timer list phase when T link location (68) includes a pointer to a list, and, the other processing. Therefore, a processing yet queues on the timer list. When a processing is removed using "A removal on the timer list" process from the timer list, the timer component is not selected. This is " time Bissett. It is the P" value recorded for a processing as T link position (68) inside. "Deactivate timer" In an operation, T link position " time Bissett according to the line (8) of the definition. It discovers to include the P" value. In case of being like that, it was set up by "deactivate timer" operation of the previous which was this value performed while the timer list phase had a processing

43 K2E-PAT Page 43 " 비구동타이머 " 동작에의해설정되고이전의 " 비구동타이머 " 동작에의해설정되었고, 그렇게해서이성분은선택되지않는다. 따라서, A 레지스터는정의의라인 (9) 에따라선택기거짓값이설정된다. 모든교대성분이재심사되었을때, 처리는 " 교대끝 " 동작을실행하며, 상기정의에따라처리작업공간의 0 위치내에기억되었던코드오프셋을처음에 0 레지스터안으로부하하며, 0 레지스터에지시된오프셋에의해 IPTR 레지스터안으로포인터값을조정한다. 이것은처리로하여금선택된교대처리에적합한오프셋을가진프로그램순서내의다음명령어를선택하게된다. 처리에대한여러실시예가설명될것이다. [ 실시예 1] [Embodiment 1] 제일먼저처리가디스케쥴없는상황에서 " 타이머입력 " 명령어를우선권 1 처리가실행하도록고찰한다. 예를들어, A 레지스터는클록레지스터가 14 이후의값을포함할때처리가계속되기를바라는것을지시하는실시예 14 를의한값을갖고부하된다. 클록레지스터가값 20 을포함할때, 만약명령어가실행된다면, 처리기는클록레지스터내의값이 A 레지스터에서지시된값을초과할때에 " 타이머입력 " 체크의정의에대한제 1 두개의라인에따른다. 이러한실시예에서상기조건은적용되고, 그래서처리는처리의디스케쥴없이계속된다. [ 실시예 2] [Embodiment 2] 이것은디스케쥴되는처리에의해 " 타이머입력 " 의동작이며제 9a 내지 9d 도에도시되어있다. 이것들은처리 (X) 의작업공간을위한여러워드위치변화를나타낸다. 제 9a 도는 " 타이머입력 " 명령어의실행비로이전의위치를보여준다. A 레지스터는처리가클록레지스터 (81) 내의시간이 30 을초과할때만스케쥴되길원하는것을지시하는값 (30) 을포함한다. 일반적으로클록레지스터는신간값 (20) 을포함하며, 유효시간프래그 (84) 는우선권 1 타이머리스트상에처리가없는것을지시하는 0 이설정된다. " 타이머입력 " 동작이실행될때, 클록레지스터의내용은 A 레지스터의내용과비교한다. 클록레지스터내의값이 A 레지스터내의값을초과하지않을때, 처리는디스케쥴된다. 정의된 " 타이머입력 " 의상향으로라인 5 로부터시작될때처럼, 특수치 " 대기.P" 는처리 (X) 의상태위치 (67) 안으로 and T link position (68) was set up by "deactivate timer" operation of the previous. It makes so and a binary is not selected. Therefore, as to a register, according to the line (9) of the definition, the selector false value is set up. When all alternation components were reexamined, a processing enforces "alternation end" operation. And the code offset memorized according to the definition within 0 location of the processing work space is carried a load of by 0 register at first time. And the point value is controlled with the offset indicated in 0 register by the IPTR register. This selects the next command within the program order having the offset which is suitable for the selected stagger to a processing. The different embodiment about a processing will be explained. First of all, in the situation where it does not have a processing with the di schedule, it inquires so that the priority 1 processing execute "timer input" command, it has the price which is the embodiment 14 which indicates that it hopes in their heart that a processing is continued when the clock register includes the value of 14 next according to and for example, A register is loaded. When the clock register includes the value 20, a command is executed. If it is the case, when the value within the clock register exceeds the price "the timer input" indicated in A register, it follows a processor into the line of the first cranium about the definition of a check. In this embodiment, a condition is applied to. So a processing is continued without the di schedule of a processing. This is illustrated with the de-scheduled processing in the operation of "timer input" the 9a or 9d drawing. These show the different word location change for the work space of the processing (X). Figure 9a shows the location of a before with the execution ratio of "the timer input" command. A register provides the value (30) which indicates that a processing desires to be scheduled only when the time within the clock register (81) exceeds 30. Generally, the clock register includes the stature value (20). "The timer input" When an operation is performed, it compares the content of the clock register with the content of A register. When the value within the clock register does not exceed the value within A register, a processing is de-scheduled. The speciality value " atmosphere like the time upwards initiated from the line 5 of defined "the timer input". P" provides the time when it is recorded as the status position (67) inside of the processing (X), and the value within A register is increased and a processing is scheduled. And then, a processing inserts by the timer list. And the location is illustrated in Figure 9b. The effective time flag

44 K2E-PAT Page 44 기록되며, A 레지스터내의값은증가되어처리가스케쥴되는시간을포함하도록한다. 그다음에처리는타이머리스트안으로삽입시키며, 그위치는제 9b 도에도시된다. 유효시간프래그 (84) 는지금타이머리스트상에적어도하나의처리가있는것을지시하는값 1 을설정한다. 다음시간레지스터 (85) 는타이머상의제 1 처리가스케쥴되는시간이있는값 (31) 을포함하며, TPTR 위치 (9) 은제 1 이되는처리 (X) 와타이머리스트상에처리뿐인작업공간포인터를포함한다. 처리 (X) 의작업공간은위치 (65) 내의명령포인터 (IPTR) 와, 위치 (67) 내에특수치 " 대기 P" 와, 타이머리스트상에서마지막처리인것을지시하는위치 (68) 내의특수치 " 비처리.P" 및, 처리가재스케쥴될수있는시간을지시하는위치 (69) 내의값 (31) 을포함한다. 충분한시간이지나가고, 클록레지스터가값 (31) 을증가할때, 위치는제 9c 도에도시된바와같다. 클록레지스터의값이지금다음시간레지스터의값과동일하고, 유효시간프래그가값 1 을설정할때, 타이머논리는처리기에서시간요청을발생시킨다. 이것은처리기를값 1 을갖는처리우선권레지스터를부하하게하고, " 시간조작요청 " 과정을실행하게한다. 이것은처리 (X) 를스케쥴되게하고, 유효시간프래그를아무것도없게하며, TPTR 위치 (90) 를 " 비처리.P" 로설정되게하며, 이것은제 9d 도에도시된위치이다. [ 실시예 3] [Embodiment 3] 이러한실시예는삽입프래그 (82) 가시간순서된순차의올바른위치에서처리를어떻게타이머리스트안으로삽입되는데익숙한가를보여준다. 처리 (P) 는처리가디스케쥴되게하는타이머입력동작을실행한다. 처리 (P) 는우선권 1 처리이고오직실행하는처리뿐이라는것이추측된다. 우선권 1 타이머리스트상에대기하는세개의다른처리들이있다고추측될수있는데, 이들은타이머 (25) 를위해대기하는처리 (X) 와, 타이머 (26) 를위해대기하는처리 (Y) 및, 타이머 (29) 를위해대기하는처리 (Z) 들이다. 제 10a 도는타이머입력명령어가실행되기바로전의위치를도시한것이다. 처리 (P) 는실행하고있고, A 레지스터는시간 (27) 을포함한다. 클록레지스터는시간 (20) 을포함한다. 유효시간프래그는타이머리스트가사용중인것을지시하는값 1 에설정되고, 다 (84) now sets up the value 1 which indicates the thing has one processing thing on the timer list at least. The next time register (85) provides the processing (X) in which in the TPTR location (9), the first is it includes the value (31) in which it has the time when the first processing on a timer is scheduled and the workspace pointer which is on the timer list a processing. The work space of the processing (X) is the speciality value " nonprocessing within the command pointer (IPTR), within the location (65) and the location (68) which indicates the speciality value "the atmosphere P/6", and the to be the last processing on the timer list thing within the location (67). P", and the value (31) within the location (69) indicating the time when a processing can be rescheduled are included. The enough time is passed. When the clock register increases the value (31), a location is similar like the bar shown in Figure 9c. The value of the clock register is now identical with the value of the next time register. When the effective time flag sets up the value 1, the timer logic generates the time request in a processor. This carries a load of the processing priority register having the value 1 a processor. It performs "time manipulation request" process. " nonprocessing the TPTR location (90) the effective time flag is done not have nothing it makes the processing (X) this scheduled. It is set up as P". And this is the location shown in Figure 9d. In the insertion flag (82) is the right location of the time *** consecutive, this embodiment shows whether it is familiar to be how a processing inserted to the timer list inside or not, the processing (P) enforces the timer input operation in which a processing is de-scheduled, a thing called the processing in which the processing (P) is the priority 1 processing and which it only enforces is presummed. Because it has three other processings queued on the priority 1 timer list, it can be presummed. It employs these with the processing (X), and the processing (Y), and the processing (Z). It queues for the timer (29) it queues for the timer (26) it queues for the timer (25). Figure 10a shows the location of the immediately former the timer input command is executed. The processing (P) provides a register is the time (27) it practices. The clock register provides the time (20). The effective time flag provides the value 25 which is set up in the value 1 which indicates that the timer list is a busy, and the next time register the time related to the processing which is most fast

45 K2E-PAT Page 45 음시간레지스터는타이머리스트상에서가장빠른처리와연관된시간은 25 인것을지시하는값 25 를포함한다. 타이머리스트상에는세개의처리가있다는것을볼수있게된다. TPTR 위치 (90) 는처리 (X) 가있는첫번째처리에포인터를포함한다. 처리 (X) 의 T 링크위치 (68) 은두번째처리 (Y) 에포인터를포함하고, 잇달아세번째처리 (Z) 에포인터를포함한다. 처리 (Z) 의 T 링크위치 (68) 은처리 (Z) 가타이머리스트상에서마지막처리인것을지시하는특수값 " 비구동.P" 를포함한다. 타이머리스트는가장빠른제 1 처리와제일늦은마지막처리로배열된것을볼수있다. 처리 P 가타이머입력명령어를실행할때, 클록레지스터및 A 레지스터는비교되어, 클록레지스터가아직 A 레지스터를초과하지않을때, 특수값 " 대기.P" 는처리 P 의상태위치 (67) 안으로기록되고, A 레지스터는 1 에의해증가되며, " 타이머리스트내의삽입 " 과정은실행된다. 이것은 A 레지스터내의값이처리 (P) 의작업공간의시간위치 (69) 안으로기록되게하고, 삽입프래그가값 1 로설정되며, B 레지스터가 TPTR 위치 (90) 에서포인트로설정되며, C 레지스터가 TPTR 위치 (90) 의내용으로설정된다. 그다음에타이머입력명령어는끝나고, 그상태는제 10b 도에도시된다. 삽입프래그가값 1 로설정될때, 처리기에의해실행된다른작용은 " 삽입단계 " 과정이다. 이러한과정에서볼때, 이것은 T 레지스터 (49) 를처리 (X)( 즉 25) 와연관된시간과함께부하되어지며, 처리 (P)( 즉 28) 과연관된시간과비교된다. 28 이 25 를초과하기때문에처리기는타이머리스트안으로처리 (P) 를삽입하기위한알맞는장소를발견하지못했고, " 삽입단계 " 과정은 B 레지스터를 T 링크위치 (68) 로의포인터를설정되도록하고, C 레지스터는상기위치의내용에설정된다. 그다음에과정은삽입프래그세트에남겨두고끝난다. 결과적인상황은제 10c 도에도시되어있다. 처리의다음작용은다시 " 삽입단계 " 과정을실행하게되는것이다. 이것은앞서설명했던방식과비슷하며제 10d 도에도시된상황으로끝난다. 다시한번처리기의다음작용이 " 삽입단계 " 과정을실행하게된다. 그러나이번에는, 처리 (Z)( 즉, 29) 와연관된시간은처리 (P)( 즉, 28) 과연관된시간을초과하여, 처리기는 on the timer list indicates to be 25. It looks on the timer list that it has three processings. The TPTR location (90) provides the pointer in the first processing in which it has the processing (X). T link position (68) of the processing (X) provides ***, the pointer in the third processing (Z) a pointer is included in the second processing (Y). The special value " deactivate which T link position (68) of the processing (Z) indicates that the processing (Z) is the last processing on the timer list. P" is included. The timer list can look at to be arranged with the most fast first processing to the great late last processing. The special value " atmosphere the clock register yet does not exceed A register when the processing P/6 executes the timer input command, the clock register and A register are compared. The insertion " process within P "it is recorded by the status position (67) of the processing P/6. A register is increased with 1" timer list is performed. This makes registered as the temporal position (69) inside of the work space of the processing (P). The insertion flag is set up as the value 1. And B register is set up in the TPTR location (90) as the point. And C register is set up as the content of the TPTR location (90). And then, the timer input command is finished. The state is illustrated in Figure 10b. When the insertion flag is set up as the value 1, the other action performed by a processor is "inserting step" process. When it looks at in this process, this is loaded with the time which is T register (49) related to the processing (X) (that is, 25). And the time is compared with the time related to the processing (P) (that is, 28). Because 28 exceeded 25, a processor was unable to discover the suitable place for inserting the processing (P) by the timer list. "inserting step" process is the pointer of T link position (68) B register set up. C register is set up in the content of a location. And then, the process leaves in the insertion flag set and the process is finished. The resultant situation is illustrated in Figure 10c. The next action of a processing again performs "the inserting step" process. This is finished in the situation which is similar to the mode which before illustrated and is illustrated in Figure 10d. Again, the next action of a processor performs "inserting step" process. But the time which this time, is related to the processing (Z) (that is, 29) makes the insertion flag a processor empty in excess of the time related to the

46 K2E-PAT Page 46 삽입프래그를텅비게하며, 처리 (Y) 의 T 링크위치 (68) 안으로처리 (P) 의작업공간포인터를기록하고, 처리 (P) 의 T 링크위치 (68) 안으로처리 (Z) 의작업공간포인터를기록함으로써처리 (Y 및 Z) 사이에타이머리스트안으로처리 (P) 를삽입시킨다. 그다음에처리는다음시간레지스터 (85) 를타이머리스트상의제 1 처리와연관된시간으로리세트하고유효시간프래그를값 1 로설정한다. 마지막으로처리기는처리 (P) 의 IPTR 위치 (65) 안으로처리 (P) 의명령어포인터를기록하며, 처리 (P) 가처리기의다음작용에따라디스케쥴되도록 SNP 프래그 (58) 을값 1 로설정한다. 결과적인상황은제 10e 도에도시된다. [ 실시예 4] [Embodiment 4] 이것은두개의타이머입력성분을지닌타이머교대처리 (X) 이다. 처리 (X) 는단지수행처리이고, 처리 (X) 는우선권 1 이며, 제 1 타이머입력성분내에규정된시간은 26 이며, 제 2 타이머입력성분은 25 인데, 이는제 11a 내지 11c 도에도시되어있다. 이것들은처리작업공간 (60) 의작업공간위치 (67 내지 69) 를위한연속상태를나타낸다. 제 11a 도는 " 타이머교대시작 " 명령어를실행하는바로직후에위치를나타낸다. 상태위치 (67) 는특수값 " 구동.P" 를포함하고, T 링크위치 (68) 은특수치 " 시간비세트 " 을포함한다. 제 1" 구동타이머 " 명령어실행되기바로전, A 레지스터는기계거짓값을포함하고, B 레지스터는 26 이있는타이머입력과연관된시간을포함한다. 구동타이머명령어가실행될때, 처리기는 T 링크위치 (68) 을판독하고, 처리기가어떠한타이머입력성분이전에심사되지않은것을지시하는 " 시간비세트.P" 값을포함하는것을발견한다. 그러므로처리기는 T 링크위치 (68) 을특수값 " 시간세트.P" 으로설정한다. 이것은제 11b 도에도시된위치이다. 제 2 " 구동타이머 " 명령어가실행되기바로직전에 A 레지스터는기계거짓값을포함하고, B 레지스터는 2 타이머입력성분과연관된시간인값 25 를포함한다. 구동타이머가실행될때, 처리는 T 링크위치 (68) 을판독하며, 시간위치가이전의타이머입력성분과연관된제일빠른시간을포함하는것을지시하는값 " 시간세트.P" 를포함하는것을발견한다. 그러므로처리기는시간위치 (69) 를판독하며, 25 인이러한성분을위하여규정된시간이값 26 을포함한시간 processing (P) (that is, 28). And it records the workspace pointer of the processing (P) by T link position (68) of the processing (Y). And then, a processing sets up the effective time flag as the value 1 a processing resets the next time register (85) to the time related to the first processing on the timer list. Finally, a processor records the instruction pointer of the processing (P) by the IPTR location (65) of the processing (P). And the processing (P) sets up the SNP flag (58) as the value 1 according to the next action of a processor as as possible. The resultant situation is illustrated in Figure 10e. This is the timer stagger (X) carrying two timer input components. The processing (X) is the performance processing. The processing (X) the priority 1, the time prescribed within the first timer input component 26, the second timer input component is 25. This is only illustrated in the 11a or 11c drawing. These show the continuous state for the work space location (67 through 69) of the processing work space (60). As to the 11a drawing, with executing "the timer alternation beginning" command it shows a location for the immediately after. The status position (67) is the special value " drive. P "T link position (68) is the speciality value it implies" time Bissett " is included. The immediately former, and A register the first "the drive timer" command is executed provide the time including the instrument false value, and B register is related to the timer input in which it has 26. " time ratio set in which when the drive timer command is executed, a processor reads T link position (68), and a processor indicates not to be examined before any timer input component. It discovers to include the P" value. Therefore, a processor is the special value " time set T link position (68). It sets up as P". This is the location shown in Figure 11b. Immediately, A register in the just before the second "drive timer" command is executed provides the value 25 including the instrument false value, and B register is the time related to 2 timer input component. The value " time set which when the drive timer is performed, a processing reads T link position (68), and indicates to include the great fast time when the temporal position is related to the timer input component of the previous. The it includes P" thing is discovered. Therefore, a processor reads the temporal position (69). Therefore, a processor records the new value (25) as the time inside of position. And a location is illustrated in Figure 11c.

47 K2E-PAT Page 47 위치로부터의시간판독보다더빠르다는것을결정한다. 그러므로처리기는시간위치안으로새로운값 (25) 을기록하며, 위치는제 11c 도에도시된다. [ 실시예 5] [Embodiment 5] 제 12a 내지 12c 도에도시된이실시예는처리 (P) 가디스케쥴안된두개의타이머입력성분을지닌타이머교대처리 (P) 를예시한다. 수행 (P) 이오직수행처리뿐이고, 그것은우선권 1 처리이며, 제 1 타이머입력성분에규정된시간이 26 이며, 제 2 타이머입력성분시간이 25 인것을추측할수있다. " 타이머교대시작 " 명령어의수행과타이머입력성분의심사는이전의실시예 4 에서설명되었고, " 타이머교대대기 " 명령어를실행하기바로직전의상황은제 11c 도에도시되었다. " 타이머교대대기 " 의제 1 동작은처리 (P) 의작업공간 (60) 의 0 위치안으로값 -1 을기록한다. 이것은다수의교대로부터성분을선택하는데사용된위치이다. 다음에처리기는, 클록레지스터내의시간이시간위치 (69) 내의시간을초과할때디스케쥴없이처리 (P) 가계속할수있는것을결정한다. 그러므로처리기는상태위치안으로특수값 " 준비.P" 를기록한다. 이것은비록클록레지스터가값 31 을나아가게하더라도제 12a 도에도시된위치를나타낸다. 제 1 " 비구동타이머 " 명령어바로전의위치는제 12b 도에도시되어있다. A 레지스터는 " 교대끝 " 명령어로부터의오프셋이제 1 타이머입력성분과연관된프로그램내의순차명령어로포함하고, B 레지스터는값 " 기계참 " 에포함하고 C 레지스터는 26 인타이머성분과연관된시간을포함한다. 그다음에처리는 T 링크위치 (68) 를판독하고, 값 " 시간세트.P" 을포함하는 " 비구동타이머 " 명령어를실행한다. 따라서처리는시간으로부터값 (30) 을판독하고, 30 이 26 을초과할때이타이머입력성분은선택된다. 그다음에처리기는처리작업공간의위치가아직값 -1 을포함할때이러한성분을선택하는 " 이는선택된처리인가?" 과정을실행한다. 결과적인상황이제 12c 도에도시된다. 제 2 타이머입력성분은지금선택될수없으며, 교대끝명령어가실행될때처리 (P) 를위한작업공간은아직제 12c 도에도시된것처럼남아있다. This embodiment shown in the 12a or 12c drawing exemplifies the timer stagger (P) in which the processing (P) carries two timer input components which are not good with the di schedule. The priority 1 processing lice, the time prescribed in the first timer input component of the performance (P) as to a that, only can guess 26, the that the second timer input component time is 25 thing the performance processing. "The timer alternation beginning" The performance of a command and examination of the timer input component were explained in the embodiment 4 of the previous. Immediately, the situation of the just before was illustrated in Figure 11c to execute "the timer alternation atmosphere" command. "The timer alternation atmosphere" The first operation records the value -1 as 0 inside of position of the work space (60) of the processing (P). This is the location selecting a component from a plurality of alternations but is used. Next, as to a processor, when the time within the clock register exceeds the time within the temporal position (69), it determines that the processing (P) can continue without the di schedule. Therefore, a processor is the special value " preparation with the state inside of position. P" is recorded. Although the clock register moves the value 31, this shows the location shown in Figure 12a. The location of the first "the deactivate timer" command immediately former is illustrated in Figure 12b. A register provides the time which includes to the sequential instruction within the program in which an offset from "the alternation end" command is related to the first timer input component, and included and which B register C register is related to 26 persons the timer component to the value "the instrument truth". And then, the value " time set a processing reads T link position (68). P "it implies" deactivate timer " command is executed. Therefore, a processing reads the value (30) from the time. This timer input component is selected when 30 exceeds 26. And then, a processor performs the process of selecting such component "this is the selected processing" when the location of the processing work space yet includes the value -1. The resultant situation is illustrated in Figure 12c. The second timer input component cannot be now selected. And when the alternation end command is executed, as it is yet illustrated in Figure 12c, the work space for the processing (P) remains.

48 K2E-PAT Page 48 [ 실시예 6] [Embodiment 6] 제 13a 내지 13f 도에도시된이실시예는처리 (P) 가디스케쥴된두개의타이머입력성분을지닌타이머교대처리 (P) 를나타낸다. 처리 (P) 는오직실행처리이고, 처리는우선권이며, 제 1 타이머입력성분내의규정된시간은 26 이며, 제 2 타이머입력내의규정된시간은 25 이며, 타이머리스트상에는처리가없다는것이추측된다. " 타이머교대시작 " 명령어의실행과 " 타이머입력성분 " 의심사는실시예 4에서설명되었고, " 타이머교대대기 " 명령어를실행하기바로전의위치는제 11c 도에도시되었다. " 타이머교대대기 " 명령어의제 1 동작은값 -1 을처리 (P) 의작업공간의 0위치안으로기록하는것이다. 처리기는시간위치 (69) 내의값을클록레지스터의값과비교하며, 처리가타이머입력때문에처리할수없다는것을발견하는것은처리의상태위치 (67) 을검사한다. 이것이 " 구동.P" 를포함할때처리는다이어리스트상에위치되며, 디스케쥴된다. 이것은제 13a 도에도시된위치이다. 유효시간프래그는타이머리스트가텅비지않은것을지시하는값 (1) 으로실정된다. 다음시간레지스터는처리 (P) 가실행하기로준비되는시간에있는값 (26) 을포함한다. TPTR 위치 (90) 는포인터를처리 (P) 의작업공간으로포함하며, 처리 (P) 의 T 링크위치 (68) 는처리가리스트상에서마지막처리인것을지시하는특수값 " 비처리.P" 를포함한다. 충분한시간이지나갔을때, 타이머는 " 타이머요청 " 신호를실시예 2 에서설명된처리기에서발생한다. 신호가발생될때상황은제 13b 도에도시된다. 처리가리스케쥴되었을때, 위치는제 13c 도에도시된다. 제 1 " 비구동타이머 " 명령어를실행하는바로전의상황은제 13d 도에도시되어진다. 타이머명령어가실행될때, T 링크위치 (68) 는판독되며, " 시간세트.P" 포함하는것이발견된다. 그다음에처리기는 26 인시간성분과연관된시간을또한이시간이 26 이되는시간위치 (69) 내에지시된시간과비교한다. 26 이 26 을초과하지않을때이성분은선택되지않는다. 그러므로처리기는 A 레지스러안으로기계거짓값을부하하고, 명령어는끝난다. 처리 (P) 가제 2 " 비구동타이머 " 명령어를실행하기바로직전의상황은제 13e 도에도시된다. 이명령어의실행은이성분이제 13f 도에도시된 This embodiment shown in the 13a or 13f drawing shows the timer stagger (P) carrying two timer input components in which the processing (P) is de-scheduled. The processing (P) is an execution. A processing the prescribed time within a priority, the first timer input component the prescribed time within 26, the second timer input is only presummed on 25, the timer list that it does not have a processing. "The timer alternation beginning" The execution of a command and examination of "the timer input component" were explained in the embodiment 4. Immediately, the concentration of mind location was illustrated in Figure 11c to execute "the timer alternation atmosphere" command. "The timer alternation atmosphere" The first operation of a command records the value -1 as 0 inside of position of the work space of the processing (P). A processor compares the value within the temporal position (69) with the value of the clock register. And it inspects the status position (67) of a processing to discover that a processing therefore cannot process with timer input. This is " drive. Is located on a processing is the diamond list when including P". And it is de-scheduled. This is the location shown in Figure 13a. The effective time flag consists of the value (1) which indicates that the timer list is not empty with actual condition. The next second register provides the value (26) which is in the time to be prepared that the processing (P) practices. The special value " nonprocessing in which the TPTR location (90) includes a pointer to the work space of the processing (P), and T link position (68) of the processing (P) a processing indicates on a list to be the last processing. P" is included. When enough time was passed, a timer is generated "the timer request" signal in the processor explained in the embodiment 2. A situation is illustrated in Figure 13b when a signal is generated. When it became a processing with reschedule, a location is illustrated in Figure 13c. The situation of a former is illustrated in Figure 13d the first "deactivate timer" command is executed. " time set T link position (68) is read the timer command is executed. The it implies with P" thing is discovered. And then, as to a processor, moreover, this time compares the time related to 26 persons the time factor within the temporal position (69) in which 26 becomes with the indicated time. A binary is not selected 26 does not exceed 26. Therefore, a processor carries a load of the instrument false value by A Regis. A command concludes. Immediately, the situation of the just before is illustrated in Figure 13e the processing (P) executes the second "the deactivate timer" command. The execution of this command is selected it brings a situation a binary is illustrated in Figure 13f.

49 K2E-PAT Page 49 것처럼상황을가져오면서선택되게한다. [ 실시예 7] [Embodiment 7] 이것은하나의타이머입력성분및하나의메세지채널입력성분을지닌타이머교대처리 (P) 를설명한것이다. 처리 (P) 는오직구동처리이고처리는우선권 1 을가지며, 규정된시간 (40) 을가지는것으로추측된다. 타이머리스트상에처리가없으며, 채널입력성분에의해언급된채널은처음에 " 준비 " 이며, 타이머입력성분은선택되지않는다. 이실시예는제 14a 내지 14d 도에도시되어있다. 처리 (P) 는 " 타이머교대시작 " 명령어를실행하고, 적당히레지스터를부하하며, " 구동타이머 " 명령어를실행한다. 그다음에처리는 " 구동채널 " 명령어를위해준비중레지스터를부하한다. 이것은제 14a 도에도시된상황을나타낸다. 채널이 " 준비 " 일때, " 구동채널 " 명령어의실행후상황은제 14b 도에도시되어있다. 그다음에처리는 " 타이머교대대기 " 명령어를실행한다. 클록레지스터내의시간은처리 (P) 를위하여시간위치 (69) 내에지시된시간 (40) 을초과하지않는값이다. 그러므로처리기는값 " 대기.P" 를포함하는상태위치 (67) 를검사하며, 따라서클록레지스터내의시간값이시간위치 (69) 안으로기록된다. " 타이머교대대기 " 명령어의완료의상황이제 14c 도에도시되어있다. " 비구동타어머 " 명령어가실행되기직전의상황은제 14d 도에도시되어있다. 타이머입력성분은시간위치 (69) 내의시간값 (12) 가성분과연관된시간을초과하지않기때문에선택되지않는다. 그다음에처리는채널입력성분을선택할 " 비구동채널 " 명령어를실행한다. 처리의시간처리 (69) 에기억된시간을 " 비구동타이머 " 명령어가실행할때, 비구동타이머명령어가효력있는모든타이머입력을위하여정수로남은표준시간을상기예에서볼수있다. 이것은연속 " 비구동타이머 " 명령어가달성될때시간의통행때문에가변시간과비교되는상이한타이머입력을피한다. [ 실시예 8] [Embodiment 8] 이것은 40 의시간을규정하는하나의타어머입력성분및채널 (70) 을통과하는하나의채널입력성분을갖는타이머교대처리의처리 (P) 를나타낸다. 이실시예는초기에타이머리스트상에두개의처리가있어, 34 및 36 의시간을규정하는이두개의처리를가정한다. 메세지채널은초기에 " This illustrates the timer stagger (P) carrying one timer input component and one message channel entry component. The processing (P) is the drive process and a processing only has the priority 1. And with having the prescribed time (40) it is presummed. It does not have a processing on the timer list. And the channel mentioned by the channel entry component "A preparation", the timer input component is not selected at first time. This embodiment is illustrated in the 14a or 14d drawing. The processing (P) executes "the timer alternation beginning" command. It befittingly carries a load of the register. And it executes "the drive timer" command. And then, a processing carries a load of the register for "the drive channel" command among a preparation. This shows the situation shown in Figure 14a. When a channel is "A preparation", a situation is illustrated after the execution of "the drive channel" command in Figure 14b. And then, the processing "the timer alternation atmosphere" executes a command. The time within the clock register is the value which does not exceed the indicated time (40) for the processing (P) within the temporal position (69). Therefore, a processor is the value " atmosphere. The status position (67) including P" is inspected. And therefore the temporal value within the clock register is recorded by the temporal position (69). "The timer alternation atmosphere" The situation of the completion of a command is illustrated in Figure 14c. "The deactivate timer" The situation of the just before is illustrated in Figure 14d that a command is executed. As to the timer input component, because the temporal value (12) within the temporal position (69) does not exceed the time related to a component, the time is not selected. And then, a processing executes the command selecting the channel entry component "the deactivate channel". When "the deactivate timer" command enforces the time memorized between the processing *** in the processing (69), the deactivate timer command can look at the normal time to remain in an example for all timer inputs having with effect as the fixed number. As to this, when the series "the deactivate timer" command is achieved, it avoids the different timer input which is compared with the variable time due to the passage of the time. 이것은 40 의시간을규정하는하나의타어머입력성분및채널 (70) 을통과하는하나의채널입력성분을갖는타이머교대처리의처리 (P) 를나타낸다. 이실시예는초기에타이머리스트상에두개의처리가있어, 34 및 36 의시간을규정하는이두개의처리를가정한다. 메세지채널은초기에 " 준비 " 가아니라, 타이머리스트상의제 1 처리가준비되기전에 " 준비 " 가된

50 K2E-PAT Page 50 준비 " 가아니라, 타이머리스트상의제 1 처리가준비되기전에 " 준비 " 가된다. 타이머교대처리를실행하기위한목적으로, 처리기는먼저 " 타이머교대시작 " 명령어와, 하나의타이머입력성분을위한 " 구동타이머 " 동작및채널 (70) 상에서 " 구동채널 " 동작을실행한다. 위치는제 15a 도에도시되어있다. 처리 (P) 는아직디스케쥴이아니며, " 상태 " 위치 (67) 는처리가교대입력을실행하는것을지시하기위한 " 구동.P" 를초기화하였다. T 링크위치 (68) 은타이머입력이심사되었던것을지시하는값 " 시간세트.P" 를설정하였다. " 시간 " 위치 (69) 는이경우에심사된오직타이머입력인 40 을시험하는어떤타이머입력의제일빠른시간을설정하였다. 타이머리스트는제각기 35 및 55 의스케쥴하는시간을지닌두개의디스케쥴된처리 (X, Y) 를갖는다. 그다음에처리기는처리 (P) 를위하여 " 타이머교대대기 " 명령어를실행한다. 이것은 " 준비 " 되었던채널입력이없는처리 (P) 의 " 상태 " 위치에서발견되며, 클록레지스터가제 15a 도내의시간 (11) 에포함할때, 시간은타이머입력을계속하도록처리 (P) 를위하여아직도달하지않고, 겨로가로서처리 (P) 는타이머리스트안으로삽입되며, 디스케쥴된다. 이것은제 15b 도에도시된위치를가져온다. 링크된타이머리스트는지금시간순서된순차내에모두세개의처리 (X, P 및 Y) 을갖는다. 약간의시간이지나채널 (70) 은상기채널을통과하여출력으로가려는출력형처리때문에 " 준비 " 된다. 채널이처리 (P) 의처리기술어를포함할때, 처리 (P) 는스케쥴되며, 제 15c 도에도시된상황을초래하는 " 비구동타이머 " 명령어를실행하기에앞서레지스터를부하한다. 그다음처리는 " 비구동타이머 " 동작을실행하며, 이것은, 처리 (P) 를위하여 "T 링크위치 "(68) 을판독하고, 처리가작업공간포인터를타이머리스트상에다음처리로포함할때, 처리는아직타이머리스트상에있는것을, 결정한다. 처리 (P) 가아직리스트상에있을때, 상기타이머입력성분을위한시간은아직도달하지않고, 결과적으로타이머성분은선택되지않는다. 그러므로 A 레지스터는기계거짓을설정하며 " 타이머리스트로부터삭제 " 과정은수행된다. 이것은삭제프래그를값 (1) 으로설정하고, B 레지스터에 TPTR 위치 (90) 로의포인터를부하하며, C 레지스터에 TPTR 위치 (90) 를부하한다. 다. 타이머교대처리를실행하기위한목적으로, 처리기는먼저 " 타이머교대시작 " 명령어와, 하나의타이머입력성분을위한 " 구동타이머 " 동작및채널 (70) 상에서 " 구동채널 " 동작을실행한다. 위치는제 15a 도에도시되어있다. 처리 (P) 는아직디스케쥴이아니며, " 상태 " 위치 (67) 는처리가교대입력을실행하는것을지시하기위한 " 구동.P" 를초기화하였다. T 링크위치 (68) 은타이머입력이심사되었던것을지시하는값 " 시간세트.P" 를설정하였다. " 시간 " 위치 (69) 는이경우에심사된오직타이머입력인 40 을시험하는어떤타이머입력의제일빠른시간을설정하였다. 타이머리스트는제각기 35 및 55 의스케쥴하는시간을지닌두개의디스케쥴된처리 (X, Y) 를갖는다. And then, a processor executes "timer alternation atmosphere" command for the processing (P). This is discovered in "the state" location of the processing (P) without the channel entry which became with "A preparation". And when the clock register includes in the time (11) of the 15a inside of a province, the time yet does not reach for the processing (P) in order to continue the timer input. It stands with the chaff furnace and this is inserted by the processing (P) is the timer list. And it is de-scheduled. This brings about the location shown in Figure 15b. The linked timer list now altogether has three processing (X, and P and Y) within the time *** consecutive. The time of a little is over and it passes through a channel and the channel (70) therefore the output type processing to run on an output "A preparation". When a channel includes the processing descriptor of the processing (P), the processing (P) is scheduled. And before executing the command leading to the situation "the deactivate timer" shown in Figure 15c, the register is carried a load of. Next, a processing enforces "the deactivate timer" operation. And this reads "T link position" (68) for the processing (P). When a processing includes the workspace pointer on the timer list to the next processing, a processing yet determines to have on the timer list. When it yet has the processing (P) on a list, the time for the timer input component yet does not reach. Consequently the timer component is not selected. Therefore, as to a register, the process is performed while setting up the instrument false "the deletion from the timer list". This sets up the deletion flag as the value (1). It carries a load of the pointer of the TPTR location (90) to B register. And it carries a load of the TPTR location (90) to C register.

51 K2E-PAT Page 51 그다음에명령어는제 15d 도에도시된것처럼위치를떠나면서끝난다. 삭제프래그가값 1에설정될때, 처리기의다음동작은 " 삭제단계 " 과정을수행하는데있다. TPTR 위치가처리 (X) 의작업공간포인터를포함할때, TPTR 위치는 C 레지스터로먼저부하되는처리 (X) 의작업공간포인터가되며, 그결과로 " 삭제단계 " 과정을수행하는데있어서, 정의된 " 삭제단계 " 의라인 2 의조건은 C 레지스터가처리 (P) 의작업공간포인터를포함하지않는다는점에서적용된다. 그러므로, 정의된 " 삭제단계 " 의라인 (5,6) 에따라, 처리는처리 (X) 의 T링크위치로의포인터를 B 레지스터에부하하고, B 레지스터에의해지시된위치의내용을 C 레지스터에부하함으로써, 타이머리스트내의다음의처리위에서행해지며, 그것은처리 (P) 의작업공간으로의포인터이다. 이것은제 15e 도에도시된상황이다. 그다음에, " 삭제단계 " 과정은끝나며, 삭제프래그가아직설정됐을때, 처리기의다음동작은다시 " 삭제단계 " 과정을수행한다. " 삭제단계 " 과정의라인 (7) 의조건은 C 레지스터가처리 (P) 인전류처리의작업공간포인터를포함하는것이지금발견되고있다. 이것은리스트로부터삭제되는처리가지금발견되는것을지시하며, 정의된 " 삭제단계 " 의라인 (9) 에따라삭제프레그는 0 으로된다. 이것은타이머리스트를통과하여또다른삭제단계를방지한다. 정의된 " 삭제단계 " 의라인 (11, 12) 에따라서, 처리 (P) 는처리 (P) 를위하여 T 링크위치 (68) 내에일반적으로가지고있는값을 C 레지스터안으로부하하고그것은처리 (Y) 의작업공간포인터로향하는포인터이다. 처리 (X) 를위하여 T 링크위치가있는 B 레지스터에의해지시된위치안으로향하는 C 레지스터의값을기록함으로써, 타이머리스트로부더제거된다. 바꾸어말하면, 처리 (P) 의 T 링크위치의내용이처리 (P) 의작업공간으로향하는포인터를처리 (Y) 의작업공간으로향하는포인터에의해교체함으로써변화가된다. 그다음에처리기는 B 레지스터가 TPTR 위치의내용이부하되는 " 삭제단계 " 과정의라인 (13) 을따라감으로써타이머 queue 상에서떠난처리가있는지를검사한다. 정의의라인 (15) 에따라서, 이것이값 " 비처리.P" 를갖는다면, 리스트상에서떠난처리가없다. 그다음에배리드시간프래그는 And then, as to a command, while leaving a location as it is illustrated in Figure 15d, it is finished. When the deletion flag is set up in the value 1, the next operation of a processor performs "the erase step" process. When the TPTR location includes the workspace pointer of the processing (X), the workspace pointer of the processing (X) which firstly is loaded in C register becomes the TPTR location. And the process is performed to the result "the erase step". The defined condition of the line 2 of "the erase step" is applied to that C register does not include the workspace pointer of the processing (P). Therefore, according to lines (5,6) of defined "the erase step", a processing carries a load of the pointer of T link position of the processing (X) to B register. The content of the location indicated by B register is carried a load of to C register. In that way a processing is performed in the following processing within the timer list. And that is the pointer of the work space of the processing (P). This is the situation shown in Figure 15e. And then, "the erase step" process was finished. And when the deletion flag was yet set up, the next operation of a processor again performs "the erase step" process. "The erase step" The condition of the line (7) of the process is now discovered to include the workspace pointer of the current process in which C register is the processing (P). This indicates that the processing deleted from a list is now discovered. And the deletion flag is according to the line (9) of defined "erase step" to 0. This passes through the timer list and it prevents the another erase step. According to lines (11, 12) of defined "the erase step", the processing (P) carries a load of the value which generally it has for the processing (P) within T link position (68) by C register and that is the pointer facing to the workspace pointer of the processing (Y). The value of C register facing to the inside of position indicated with B register in which has T link position for the processing (X) is recorded. In that way it removes with the timer leaes trough part and the value is removed. ***, by replacing the pointer in which the content of T link position of the processing (P) faces to the work space of the processing (P) with the pointer facing to the work space of the processing (Y) it is changed. And then, a processor inspects whether the where the content of the TPTR location is loaded "erase step" process has the processing left on the timer queue since B register chases the line (13) of the process or not. This according to the line (15), of the definition is the value " nonprocessing. It has P". If it is the case, it does not have the processing left on a list. And then, according to the line (17), the buried time flag is set up

52 K2E-PAT Page 52 라인 (17) 에따라서 0 로설정된다. as 0. 반면에, " 비처리.P" 보다다른값이정의의라인 (18) 에따라발견된다면, 타이머리스트상에또다른처리가있고, 다음시간레지스터는정의의라인 (20) 에따라서 B 레지스터에의해지시된처리의시간위치 (69) 로부터의시간을얻음으로써새롭게된다. 마지막으로타이머리스트로부터처리 (P) 를삭제한후, 값 " 시간비세트.P" 는정의된 " 삭제단계 " 과정의라인 (21) 에따라처리 (P) 의 T 링크위치 (68) 안으로기록된다. 이것은제 15f 도에서도시된위치를나타낸다. 처리 (P) 는더이상타이머상에있을수없으나, 아직전류스케쥴된처리가있다. 그러므로그것은 " 비처리채널 " 인다음명령어를실행한다. 이것은처리 (P) 의작업공간위치내에값 -1 을찾아내며, 그결과로채널 (70) 은처리의입력을위하여선택된다. 적당한코드오프셋은부하 (P) 를위하여작업공간의 0 위치안으로부하되어다음의명령어 " 교대끝 " 을완성할때, 코드오프셋이처리 (P) 를위하여명령어포인터에가해지므로, 처리는채널입력의선택에따라프로그램의올바른부분이이동한다. 메세지채널혹은타이머로부터교대입력을실행하는처리는위한프로그램 [ 실시예 ] [Embodiment] 이실시예프로그램은회전속도조절바퀴에의해매초당수회전을계산하기위해준비된다. 처리는하나는 " 회전 " 이라명명되고, 다른하나는매초당회전을표시하는 "rps" 라명명된두개의채널을통과하여전달하도록준비된다. 처리는회전속도조절바퀴가회전을행할때마다 " 회전 " 채널로부터입력이준비된다. 처리는또한타이머입력을받아서처리가예정된시간의발생에대해대답하도록한다. 이실시예에서예정된시간은 1 초기간의연속통과이다. 처리는 1 초동안발생했던다수의회전의채널자 "rps" 를통과하여각각의매초동안배출되도록준비한다. 프로그램에서다음의추가적인주해가사용된다. 처리기클록의전류값은 NOW 로표시된다. occam 처리는변수 : 현재 (now) On the other hand, " nonprocessing. The value which is different than P" is found out according to the line (18) of the definition. If it is the case, the value has the another processing on the timer list. The next time register is new by getting the time from the temporal position (69) of the processing indicated according to the line (20) of the definition by B register. Finally, the value " time ratio set the processing (P) is deleted from the timer list. According to the line (21) of P "it is defined" erase step " process, it is recorded by T link position (68) of the processing (P). This shows the illustrated location in Figure 15f. The processing (P) any more cannot have on a timer. But it has processing yet scheduled with current. Therefore, that executes a command after being "the nonprocessing channel". This seeks out the value -1 within the work space location of the processing (P). And the channel (70) is selected as the result for the input of a processing. When the appropriate the code offset is loaded for the load (P) by 0 location of the work space and it completes the following command "the alternation end", the code offset is applied for the processing (P) in the instruction pointer. Therefore, as to a processing, the right part of the program moves according to the selection of the channel entry. The program which the processing executing the alternation input from the message channel or the timer respects. This embodiment program is prepared in order to calculate the several occasions former per every second with the rotary speed control wheel. As to a processing, one is named because of being "A rotation". In order to pass through two channels which are named because of indicating a rotation per every second "rps" and it delivers the other one is prepared. As to a processing, an input is prepared from a channel whenever the rotary speed control wheel performs a rotation "A rotation". A processing receives the timer input and it moreover accounts for the generation of the time in which a processing is scheduled. In this preferred embodiment, the scheduled time is the continuity passage of 1 second period. As to a processing, in order to pass through the channel person "rps" of the rotation generated for 1 second of the multiple and it is ejected for each every second it prepares. In the program, the additional annotation is used. The current value of the processor clock is indicated as NOW. The occam processing is a variable:presently(now)

53 K2E-PAT Page 53 처리기클록의전류값을변수로지정한다. " 타이머 " 입력은 t 이후대기로표시한다. 처리기클록이시간 t 를초과한시간을가질때까지처리가진행되지않는다는것을이입력은규정한다. 이처리의프로그램은다음과같다. The current value of the processor clock is designated as a variable. "Timer" An input indicates after a t by an atmosphere. This input prescribes that a processing does not go on until it has the time when the processor clock exceeds the time t/6. The program of this processing is as follows. 1. VAR 앤드 of 주기, 회전 : 1.VAR and of cycle, and a rotation: 2. 순차 2. Consecutive. 3. 회전 : =0 3. rotation: =0. 4. 주기의단부 : 현재 4. the end part of a cycle: presently 5. 주기의단부 : 주기의단부 the end part of a cycle: the end part of a cycle. 6. 참일때 6. It is a truth. 7. ALT 7. ALT 8. 회전? 어느정도 8. The rotation?, to some extent. 9. 회전 : 회전 rotation: rotation 주기의단부이후대기 10. The end part of a cycle, next, an atmosphere. 11. 순차 11. Consecutive. 12. rsp : 회전 12. rsp: rotation. 13. 회전 : =0 13. rotation: = 주기의단부 : = 주기의단부 the end part of a cycle: the end part of the = cycle. 프로그램의라인 (1) 에서, 처리는두개의변수를사용하는데그중하나는일초주기내에발생하는다수의회전을세는데사용하는 " 회전 " 이라명명된것이고, 다른하나는일초간의전류주기의종료를지시하는처리기의클록값을기록하기위해사용되는 " 주기의단부 " 인것을규정한다. 라인 (2) 은순차가라인 (3 내지 6) 에서시작되는것으로규정한다. 라인 (3) 에서회전수의계산은 0 에서시작된다. 라인 (4) 에서처리기클록의전류값이판독되어, 라인 (5) 은일초주기의말미를위하여처리기의클로값을계산할수있다. 라인 (5) 에사용된값 은일초이내에처리기클록의배수이다. 라인 6 은라인 (7, 14) 사이를뒤따르는교대처리가연속적으로되풀이되는것을지시한다. 라인 (7) 은타이머교대처리로서처리와동일하게된다. 라인 (8, 10) 은두개의교대입력을설정한다. 라인 8 은만약회전속도조절바퀴가회전을끝냈다면 " 회전 " 채널로부터신호를입력한다. 만약이입력이선택된다면, 라인 (9) 상에서병행처리는회전수의증가로하여금일초주기의전류로계산하는것이실행된다. 라인 (10) 의타이머 In the line (1) of the program, it uses two variables to count the rotation of the multiple generated around the middle one is one second cycle it use "rotation"s a processing is named. Dissimilar one prescribes that one is used "the end part of a cycle" in order to record the clock value of the processor indicating the termination of the current cycle between one second. As to the line (2), it prescribes that a consecutive is commenced in the line (3 through 6). In the line (3), the calculation of the number of rotation is initiated in 0. In the line (4), the current value of the processor clock is read. The line (5) can calculate the claw value of a processor for the end of one second cycle. The value used for the line (5) is the drainage of the processor clock within one second. The line 6 indicates that the stagger following the line (7, 14) interval around is consecutively,sequentially,serially repeated. The line (7) is identical with a processing as the timer stagger. Lines (8, 10) set up two alternation inputs. As to the line 8, the rotary speed control wheel inputs a signal from a channel if it completed a rotation "A rotation". This input is selected. If it is the case, the overlap processing is performed on the line (9) to calculate as the current of one second cycle to the increment of the number of rotation. As to the timer input of the line (10), the current can be selected when the current of one second cycle was completed. This timer inputted with if,

54 K2E-PAT Page 54 입력은일초주기의전류가완료되었을때선택될수있다. 만약처리로입력되는이타이머가선택된다면, 라인 (12, 13 및 14) 상의병행처리는실행된다. 라인 (12) 은일초내에발생하는회전수의계산을지시하는 "rsp" 채널을통과하여출력을준비한다. 라인 (13) 은회전카운터를 0 으로리셋하고, 라인 (14) 은다음일초주기의끝시간을계산한다. 이러한프로그램을이행하는명령어편차는다음과같다. Image 3 not available Image 4 not available 이명령어순차에도시된것처럼라인 (1, 2) 은회전수계산을 0 으로초기화한다. 라인 (3, 4) 는처리기클록을판독할부하타이머를작동하기위해 pfix 기능을사용한다. 라인 (6 내지 11) 은연속 pfix 기능과일초주기의단부에서처리기의클록값을계산하기위한추가된정수기능을사용한다. 타이머교대입력은라인 (13) 에서시작하며라인 (13, 14) 은 " 타이머교대시작 " 작동하기위해 pfix 기능을사용한다. 라인 (15) 은포인터에 " 회전 " 채널을부하하며라인 (16a, 17) 은 " 구동채널 " 작동하기위한 pfix 기능을사용한다. 라인 (18) 은변수 " 주기의단부 " 값을부하한다. 라인 (19) 은감시값을부하하고, 라인 (20, 21) 은 " 구동타이머 " 작동하기위한 pfix 기능을사용한다. 라인 (22, 23) 은 " 타이머교대대기 " 를수행한다. 라인 (24 내지 27) 채널입력을재심사한다. 라인 (24) 은 " 회전 " 채널을동일시한다. 라인 (25) 는선택기참감시값을부하한다. 라인 (26) 을만약채널입력이선택된다면필요한명령어를부하한다. 라인 (28 내지 32) 는타이머입력을재심사한다. 라인 (28) 은변수 " 주기의단부 " 를부하한다. 라인 (29) 은감시값을부하하며, 만약처리가타이머입력을선택하고, 라인 (31, 31) 가 " 비구동타이머 " 를실행한다면, 라인 (30) 은필요한명령어오프셋을부하한다. 라인 (32a, 33) 은 " 교대단부 " 를실행한다. 라인 (35) 은만약채널입력이선택된다면실행될제 1 명령어이다. 라인 (45) 은만약타이머입력이선택된다면실행될제 1 명령어이다. 본발명은앞선실시예에항목에제한을두지않았다. a processing is selected. If it is the case, the overlap processing on lines (12, 13 and 14) is performed. The channel indicating the calculation of the number of rotation generated around one second "rsp" is passed through and an output is prepared for. The line (13) resets a rev-counter to 0. The line (14) calculates the end time of the next one second cycle. The command deviation fulfilling this program is as follows. Lines (1, 2) initialize the number of rotation calculation to 0 as it is illustrated in this command consecutive. As to lines (3, 4), in order to operate the load timer reading the processor clock, it uses the pfix function. In the end part of one second cycle and series pfix function, the line (6 through 11) uses the added function of water purification for calculating the clock value of a processor. As to the timer alternation input, while starting in the line (13), in order to operate with "the timer alternation beginning", lines (13, 14) use the pfix function. The line (15) carries a load of "A rotation" channel to a pointer and lines (16a, 17) use the pfix function for operating with "the drive channel". The line (18) carries a load of the variable "the end part of a cycle" value. The line (19) carries a load of the monitoring value. Lines (20, 21) use the pfix function for operating with "the drive timer". Lines (22, 23) perform "the timer alternation atmosphere". The line (24 through 27) channel entry is reexamined. The line (24) regards in the same light with "A rotation" channel. The line (25) pretty carries a load of the monitoring value with selector. If the channel entry is the line (26) selected, the necessary command is carried a load of. The line (28 through 32) reexamines the timer input. The line (28) carries a load of the variable "the end part of a cycle". The line (29) carries a load of the monitoring value. And a processing selects the timer input. Lines (31, 31) enforce "the deactivate timer". If it is the case, the line (30) carries a load of the necessary command offset. Lines (32a, 33) enforce "the alternation end part". The line (35) is the first command which is performed if the channel entry is selected. The line (45) is the first command which is performed if the timer input is selected. The present invention did not put a limit in the embodiment preceding in an item.

55 K2E-PAT Page 55 Claims Claim 1 각각의처리에대해그처리를식별하기위해제 1 포인터를형성하는단계와, 각각의처리에대해상기처리동안프로그램스테이지를지시하기위해제 2 포인터를형성하는단계와, 상기처리기에의해실행되는현행처리를지시하는것을포함하는처리기에의해실행동안다수의처리를스케쥴링하는단계와, 상기처리기에의해실행될처리의시간의존콜렉션을식별하는단계를포함하며, 최초의스케쥴링시간을가진상기콜렉션의처리가그다음처리로서지시되는다수의명령을가진프로그램을각각의병행처리가실행하는컴퓨터시스템내에서, 적어도일부의처리가시간의존처리인병행처리운영방법에있어서, 각각의스케쥴링시간은각각의처리에대해시간의존콜렉션내에제공되는것과, 상기현행처리의실행은현행처리가실행을연속하지않기전에스케쥴링시간을지시하는시간관련명령을포함하는순차명령을실행하는것과, (a) 상기스케쥴링시간이지금도달되었는지의여부를결정하고, (b) 상기스케쥴링시간이아직도달되지않았다는결정에응답하여 (i) 상기처리동안상기제 2 포인터를기억하는것과, (ii) 상기현행처리의실행을중지하는것과, (iii) 스케쥴링시간이콜렉션내의순차스케쥴링시간을형성하도록시간순콜렉션내의위치에서상기시간순콜렉션에중지된처리를부가하는것과, (iv) 또한스케쥴된처리를지시하기위해현행처리의지시를설정함으로서상기시간관련명령의실행에응답하는것과, 상기다음처리의스케쥴링시간이후의시간에서, 상기다음처리를지시하기위해현행처리의지시를설정함으로서현행처리를중지하는명령을실행하기위해응답하고, 상기다음처리동안제 2 포인터에의해지시된프로그램스테이지에서상기다음처리를실행하는단계를포함하는것을특징으로하는시간의존병행처리운영방법. Claim 2 제 1 항에있어서, 시간관련명령을실행한다음, 상기스케쥴링시간이지금도달되었는지의여부를결정하는단계가그스케쥴링시간이이미도달되었다는것을지시할때, 현행처리를중지함이없이실행을계속하는단계를더특징으로하는시간의 The time dependent overlap processing operation method including the thing enforcing the sequential order, the thing which decides whether or not; and (a) scheduling time now reached memorizes (i) processing during second pointer in response to the crystallization, the thing stopping the execution of (ii) existing processing, the thing, the thing, and the step that answers in order to set up the indication of the existing processing in order to indicate the next processing in the time of the scheduling time next of the next processing, execute the command stopping the existing processing; and practices the next processing with the next processing during second pointer in the indicated program stage of the overlap processing operation method in which it includes the step scheduling a plurality of processings for an execution, and the step distinguishing the time dependent collection of the processing performed with a processor with the processor which includes the step building up the first pointer, the step that builds up the second pointer in order to indicate the processing during program stage on each processing, and the thing instructing on the existing processing performed by a processor in order to distinguish the processing about each processing; and at least, the partial processing of the processing of the collection having the initial scheduling time is next the time dependent processing in computer system in which each overlap processing performs the program having indicated an plurality of commands as a processing, wherein: each scheduling time are comprised of the time related command which the execution of the thing, and existing processing provided within the time dependent collection indicates the scheduling time on each processing before the existing processing does not continue an execution; as to the, (b) scheduling time yet did not reach; the thing adds the stopped processing to the sequence of time collection in the location within the sequence of time collection so that (iii) scheduling time form the sequential scheduling time within a collection; and the thing sets up, answers the indication of the existing processing to the execution of the time related command in order to instruct on the processing moreover scheduled with (iv). The time dependent overlap processing operation method which indicates that the scheduling time of a step already reached; and more has the step that continues an execution without stopping the existing processing as a feature of claim 1, wherein the time related command is executed; and

56 K2E-PAT Page 56 존병행처리운영방법. Claim 3 제 1 항에있어서, (a) 각각의처리용으로다수의번지가능메모리위치를포함하는각각의작업공간을메모리내에확립하고, 각각의작업공간의상기위치에대응처리와관련된변수를기록하는단계와, (b) 처리하는스케쥴링시간의지시와그다음스케쥴링시간의처리동안상기제 1 포인터의지시를리스트로각처리의작업공간내에제공함으로써시간의존콜렉션을형성하는단계를더특징으로하는시간의존병행처리운영방법. Claim 4 제 1 항에있어서, 다수의처리스케쥴링은스케쥴링시간을대기하지않고스케쥴된콜렉션의처리를식별하는것을포함하고처리기에의해서실행동안준비하고, 그로써, 상기다음처리는스케쥴된콜렉션에부가되어, 스케쥴링시간이후에시간의존콜렉션으로부터제거되는단계를포함하는것을특징으로하는시간의존병형처리운영방법. Claim 5 제 3 항에있어서, 상기스케쥴된콜렉션은링크된리스트로서형성되며, 스케쥴된리스트상의각각의처리는스케쥴된리스트의그다음처리에적합한제 1 포인트의지시를작업공간에기억시키는단계를더특징으로하는시간의존병형처리운영방법. Claim 6 제 1 항내지 5 항중어느한항에있어서, 각각의처리에적합한우선순위를지시하고처리의제 1 및제 2 시간의존콜렉션을확립하는단계로서, 상기제 1시간의존콜렉션은공통제 1 우선순위의처리를포함하고, 상기제 2 시간의존콜렉션은상기제 1 우선순위와상이한공통제 2 우선순위의처리를포함하는것을더특징으로하는시간의존병형처리운영방법. Claim 7 제 1 항내지 5 항중어느한항에있어서, 처리들간에데이타통신을가능케하기위해다수의번지가능통신채널을통하여현행처리들간에메시지를전송함으로써, 각각의처리는두처리가대응하는프로그램스테이 whether or not is decided. The scheduling time now reached. The zone overlap processing operation method of the time it establishes each work space in memory; and to more have the step, recording the variable relating to the location of each work space to the processing reaction and the step that forms the time dependent collection by providing the indication of the processing during first pointer of the indication of the scheduling time to process with (b) and next scheduling time to a list within the work space of each processing, as a feature of claim 1, wherein whether it earns with (a) each *** of the multiple or not the available memory location is included. The time dependent medium processing operation method of claim 1, wherein a plurality of processing schedulings include to distinguish the processing of the collection which does not queue the scheduling time and is scheduled and it prepares with a processor for an execution; the next processing is added as that in the scheduled collection; and it includes the step removed after the scheduling time from the time dependent collection. The time dependent medium processing operation method which more has a step as a feature of claim 3, wherein the scheduled collection as described above is formed as the linked list; and scheduled each processing on the list memorizes the indication which is suitable for the next processing of the scheduled list of the first point in the work space. The time dependent medium processing operation method which is more done by a feature to include the processing of the common material 2 priority of any one of claims 1 through 5, wherein the period dependence collection it is the step that indicates the priority which is suitable for each processing includes the processing of the common material 1 priority; and the second time dependence collection is different with the first priority. The time dependent overlap processing operation method which more has the step enforcing the sequence instruction within the program which includes the communications statement to complete the message transfer between two processings when being in the program stage as a feature of

57 K2E-PAT Page 57 지에있을때두처리간에메시지전송을완성하게끔통신명령을포함하는프로그램내의순서명령을실행하는단계를더특징으로하는시간의존병행처리운영방법. Claim 8 제 1 항내지 5 항중어느한항에있어서, 다수의택일시간관련구성요소를갖는처리를설행함으로서, 각각의구성요소와관련된시간을지시하고어떤구성요소와도관련된시간이지금발생했는지의여부를결정하는단계를더특징으로하는시간의존병행처리운영방법. Claim 9 제 8 항에있어서, 어떤택일시간관련구성요소와도관련된최초시간이아직발생되지않았다면상기처리를디스케쥴링하고시간의존콜렉션에상기처리를부가하는단계를특징으로하는시간의존병행처리운영방법. Claim 10 제 9 항에있어서, 처리상태를지시하기위해또한상기처리가택일구성요소로하는것을지시하기위해적어도하나의특수값으로처리와관련된메모리위치내에적재하는단계를더특징으로하는시간의존병행처리운영방법. Claim 11 제 10 항에있어서, 적어도하나의택일구성요소가준비되므로서상기처리가디스케쥴될필요가없는것을지시하기위해제 1 특징값또는, 하나의택일구성요소와관련된시간의도착을대기시키는동안상기처리가디스케쥴되는단계를지시하기위해상이한특정값을메모리위치내에적재하는단계를더특징으로하는시간의존병행처리운영방법. Claim 12 제 8 항에있어서, 택일구성요소가여전히선택되어있지않은것을지시하기위해또한특정값을처리와관련된메모리위치내에적재하고, 상기처리가스케쥴될때택일처리구성요소중하나를선택하기위해상기또한특정값에응답하는단계를더특징으로하는시간의존병행처리운영방법. any one of claims 1 through 5, wherein in each processing it makes data telecommunication possible between processings, two processings correspond. The time dependent overlap processing operation method which is a processing the theory row box; and more has the step deciding whether or not indicated the time relating to each element and the time relating to any kind of element was now generated as a feature of any one of claims 1 through 5, wherein it has lots of the alternative time associated component. The time dependent overlap processing operation method having the step that adds a processing a processing to a descheduling and time dependent collection if the earliest time was not yet generated as a feature of claim 8, wherein it relates to any kind of alternative time associated component. The time dependent overlap processing operation method which more has the step that loads within the memory location relating to one special value to a processing at least as a feature in order to indicate a thing of claim 9, wherein moreover, a processing is done by the alternative element in order to indicate the process state. The time dependent overlap processing operation method which more has the step that loads the different definite value within the memory location in order to indicate the step that a processing is de-scheduled while having the arrival of the time on standby as a feature of claim 10, wherein it relates to the alternative element of the first feature value or the, one in order to indicate that a processing is no need to be de-scheduled since one or more alternative element is prepared. The time dependent overlap processing operation method which loads moreover, the definite value within the memory location relating to a processing in order to indicate a thing; and more has the step answering to a, moreover, the definite value as a feature in order to select one out of the alternative processing composition element when a processing is scheduled of claim 8, wherein the alternative element is not still selected.

58 K2E-PAT Page 58 Claim 13 제 8 항에있어서, 상기택일구성요소중적어도하나는통신채널을통하여메시지를입력시키는것을포함하고그방법은임의시간관련구성요소의초기시간이지금발생됐는지의여부를결정하고또한임의통신채널이지금메시지를입력하도록준비중인지의여부를결정하는단계를포함하는것을더특징으로하는시간의존병행처리운영방법. Claim 14 적어도일부의처리가시간의존인다수의병형처리를실행하기위한메모리및처리기와, 상기처리기에의해실행되는현행처리를지시하기위해번지가능기억소자를포함하는스케쥴링시스템과, 콜렉션내의처리에적합한각각의스케쥴링시간이후에상기처리기에의해서콜렉션대기실행을형성하는하나또는그이상의처리를식별하고스케쥴링시간을발생한후처리기에의해서실행에적합한콜렉션내의그다음처리를지시하기위해다음처리지시기를가진타이머리스트를포함하며, 청구범위제 1 항의방법을실행하는데사용하기위한마이크로컴퓨터에있어서, 기억위치 (69) 의세트는상기콜렉션내의처리가실행에적합하게준비되어있을때각각의스케쥴시간을식별하기위한상기타이머와관련되고, 제어시스템 (13, 14, 15, 32) 은최초스케쥴링시간을갖는선행처리와나중의스케쥴링시간을갖는다음처리간의시간순위치에서상기콜렉션에또한처리를부가하기위해제공되는것을특징으로하는마이크로컴퓨터. Claim 15 제 14 항에있어서, 상기메모리는각각의처리를위해다수의번지가능장소를갖는각각의작업공간 (60) 을제공하며, 상기시간순리스트의처리에적합한상기작업공간의각각은 (i) 대응처리와관련된변수를기록하기위한제 1 메모리위치와, (ii) 대응처리에적합한상기프로그램스테이지지시기용의제 2 메모리위치 (65) 와, (iii) 상기시간순리스트에그다음처리를식별하기위한제 3메모리위치 (68) 를포함하는것을더특징으로하는마이크로컴퓨터. The time dependent overlap processing operation method including a thing and the method is more done by a feature to include the step deciding whether or not and the initial time of the arbitrary time associated component was now generated decides whether or not is among a preparation so that moreover, the arbitrary communications channel now input a message of claim 8, wherein the alternative element, at least, one inputs a message through the communications channel. At least, the microcomputer which includes the timer list having scheduling system, and the next treatment basin time one or the processing described in the above forming the collection atmosphere execution after each scheduling time including the memory and the processor for practicing lots of the medium processing, and the available memory device in order to instruct on the existing processing performed by a processor, it earns, and is provided from the sequence of time location between a processing after having the scheduling time of preprocess and latter having control systems (13, 14, 15, 32) is the initial scheduling time the set of the storage position (69) relates to the timer it is suitable for an execution as to the microcomputer it executes a method of claim 1 in order to add moreover, a processing to a collection. As to the memory and the processor for, the partial processing is the time dependent. The next treatment basin time one or the processing described in the above forming the collection atmosphere execution after each scheduling time is suitable for the processing within a collection with a processor is distinguished and after being generated the scheduling time, the next processing within the collection which is suitable for an execution is indicated with a processor. The microcomputer which provides each work space (60); and more has each of the work space which is suitable for the processing of the sequence of time list to a feature to include the first memory location for recording the variable relating to (i) processing reaction, the second memory location (65) of the program stage indication appointment, and the third memory location (68) for distinguishing the next processing in (iii) sequence of time list of claim 14, wherein the memory has the available place whether it earns for each processing of the multiple or not, and the second memory location (65) of the program stage indication appointment is suitable for (ii) processing reaction.

59 K2E-PAT Page 59 Claim 16 제 14 항에있어서, 기억수단 (52, 53, 66) 은처리기 (12) 에의해실행에적합한스케쥴될처리준비의콜렉션을식별하기위해제공되고, 그곳에서그자체의스케쥴링시간이도달된후타이머리스트로부터의제거에따라처리가부가되는것을더특징으로하는마이크로컴퓨터. Claim 17 제 15 항또는제 16 항에있어서, 각처리의작업공간은타이머리스트와스케쥴된콜렉션이각각처리작업공간 (60) 을통하여링크된리스트를포함하도록스케쥴된콜렉션내의그다음처리를지시하기위해부가메모리위치 (66) 가제공되는것을더특징으로하는마이크로컴퓨터. Claim 18 제 14 항내지제 16 항중어느한항에있어서, 처리들간에동기화된메시지를전송하도록하기위해번지가능통신채널 (70, 25) 를더포함하는것을특징으로하는마이크로컴퓨터. Drawings Figure 1 The microcomputer which is provided in order to distinguish the collection of the scheduled processing preparation; and is more done by a feature that a processing is added according to a removal from the timer list. After the scheduling time of an itself reaches in that place of claim 14, wherein storage devices (52, 53, 66) are suitable for an execution with the processor (12). The microcomputer which is more done by a feature that the memory location (66) of the part is provided in order to instruct on the next processing within the collection which is scheduled so that a collection include the list linked through the respective processing task space (60) of claim 15 or 16, wherein the work space of each processing is scheduled with the timer list. The microcomputer which whether earns in order to makes transmit the message synchronized between processings as to any one of claims 14 through 16 or not more includes available communications channels (70, 25). Figure 2a

60 K2E-PAT Page 60 Figure 2b Figure 3

61 K2E-PAT Page 61 Figure 4

62 K2E-PAT Page 62 Figure 5

63 K2E-PAT Page 63 Figure 6 Figure 7

64 K2E-PAT Page 64 Figure 8 Figure 9a

65 K2E-PAT Page 65 Figure 9b Figure 9c Figure 9d

66 K2E-PAT Page 66 Figure 10a

67 K2E-PAT Page 67 Figure 10b Figure 10c

68 K2E-PAT Page 68 Figure 10d

69 K2E-PAT Page 69 Figure 10e

70 K2E-PAT Page 70 Figure 11a

71 K2E-PAT Page 71 Figure 11b Figure 11c

72 K2E-PAT Page 72 Figure 12a Figure 12b Figure 12c

73 K2E-PAT Page 73 Figure 13a Figure 13b Figure 13c

74 K2E-PAT Page 74 Figure 13d Figure 13e Figure 13f

75 K2E-PAT Page 75 Figure 14a Figure 14b Figure 14c