Microsoft PowerPoint - ARM9_uCOS-II_2004_10_14_for_print1.ppt

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1 교육목표및대상 교육목표 대상 Real-Time OS 와 ARM9 의이해 Real-Time OS 시스템을직접작성해보는개발경험축적 임베디드시스템개발자의능력배가 프로그램언어 (ASM,C) 사용가능자및임베디드시스템개발경험자 Real-Time OS 나 ARM 에대한개념을공부하고자하는개발자, 연구책임자및학생 -1 - 임베디드시스템교육센터

2 교육구성 학습 실습 RTOS 의이해 SMDS2410 시스템실습 uc/os-ii 의이해 ARM9 프로세서제어 ARM920T 의이해 uc/os - ARM9 포팅 S3C2410 의이해 RTOS 태스크모델링 -2 - 임베디드시스템교육센터

3 RTOS 개념 -3 - 임베디드시스템교육센터

4 -4 - 임베디드시스템교육센터

5 OS 란? Operating System 의약자 사전적의미 : 효율적조작을목적으로하는제어프로그램 일반응용프로그램들이각자의작업을수행하기위해시스템자원을요구할때서로간의충돌없이효율적으로사용할수있도록자원을관리하고프로그램들의작업명령을받아서처리하는시스템소프트웨어 Ex) DOS, Windows 98/NT, Mac OS, UNIX, Linux, OS/2-5 - 임베디드시스템교육센터

6 RTOS 란? Real-Time Operating System 의약자 Real-Time Concepts 상대적인관점임 (vs. 일반적인 OS 처리 ) 극히짧은시간내에제공되어야하는서비스는 DSP나 ASIC 등으로특화되어 H/W Real-Time으로분류 일반적의미 : 주어진제약시간안에할당된일을처리할수있는 S/W Real-Time을의미 Cf) Hard real-time, Soft real-time RT Systems : 제어시스템에서, 요구하는시간내에결과를출력하는시스템 -6 - 임베디드시스템교육센터

7 RTOS 시스템의구조 Application (Task) Application (Task) S/W OS Memory Management Comm. Management Task Management Time Management Scheduler Kernel Device Driver H/W -7 - 임베디드시스템교육센터

8 RTOS 의적용분야 RTOS 는여러시스템에적용되나특히임베디드시스템에많이사용됨 일반 OS 시스템설계보다디자인이더어려움 시간제약이있는시스템에사용 영상, 의료, 음향기계등의시간의존적시스템 흐름제어, 엔진제어, 로봇등의자동화시스템 복합기능의가전기기등 네트워크접속, 고성능전화설비등통신시스템 -8 - 임베디드시스템교육센터

9 프로그래밍방식분류 순차적단순프로그래밍 간단한제어시스템에유리 Ex) Foreground/Background 방식 OS 를기반으로한프로그래밍 일반적으로큰프로그램에유리 프로그램의모듈화가용이함 Scheduler 를이용한 Multi-Task 가가능함 메모리 /IO 등의자원관리가쉬움 OS에필요한 overhead( 메모리, CPU 등 ) 존재 Ex) Dos, WinCE, psos, VxWorks, Embedded Linux, Nucleus, Xinu, IOS, uc/os, ecos 등 -9 - 임베디드시스템교육센터

10 Foreground/Background Background : Function 을이용하여원하는기능을불러프로그램을무한수행하는것 Foreground : 인터럽트에의해 ISR(Interrupt Service Routine) 을수행하는것 임베디드시스템교육센터

11 OS Based Programming 일반 Embedded OS 기반 PC 와같이시간적으로처리지연이발생해도문제가없으며, 다양한 App. S/W 가지원되는경우유리 WinCE : 친숙한개발환경, License, Guarantee Embedded Linux : Free, 개발환경구축필요 Real-Time OS 기반 정확한처리시간이필요한임베디드시스템에적합 VxWorks : License, Guarantee RTLinux : 일반리눅스커널의 Scheduler를변경 In-house RTOS( 자체개발한 OS) : RTOS 시장의 50% 이상으로유료 or 무료 임베디드시스템교육센터

12 OS 기본개념 Task, Resource, Event Critical Section, Mutual Exclusion, Deadlock Multi-Tasking, Context Switching Kernel, Scheduler Non-Preemptive, Preemptive Priority, CPU Utilization Synchronization Inter-task Communication Reentrancy Interrupts, Clock Tick 임베디드시스템교육센터

13 Task, Resource, Event Task = Thread 하나의간단한프로그램으로 CPU 를사용하는작업 각각의우선순위, 스택영역을가짐 Resource 태스크가사용하는 Entity( 프로세서, I/O, 메모리등 ) Shared Resource 여러 Task 에의해공용되는자원 Event Task 에게작업을시작하도록지시할수있는상황 신호나메시지를주고받음 임베디드시스템교육센터

14 Critical Section, Mutual Exclusion Critical Section 여러 Task 들이공유자원에접근하는코드부분 Mutual Exclusion 오류방지를위해배타적으로공유자원을사용함 방법 : Test & Set, Scheduler 정지, Semaphore 등 Deadlock 공유자원문제로 Task들이서로끝없이기다리게되는상태를말함 주로대규모 Multi-Task Kernel에서일어남 해결책 : 사전자원점유, 자원해제순위, Semaphore 등의사용 임베디드시스템교육센터

15 Multi-tasking 정확히는 Multi-programming Scheduling을통하여 Task를전환하여여러작업들이동시에수행되는것처럼보이게하는것 모듈구조의 Application을제공 실시간 Application에서의복잡성을줄여줌 CPU의활용도를극대화 한순간에한개의Task 만이수행될수있으므로다른Task는대기준비모드 임베디드시스템교육센터

16 Context Switching Multi-task가가능하도록 Task를바꾸기위한교환과정 다른 Task를수행하기위해현재수행중인 Task의Context를스택에저장 새로운태스크의 Context를불러들임 실제작업을위한시간이아니므로 Overhead * Context : CPU Register, Stack 등의자원 임베디드시스템교육센터

17 Kernel OS 핵심기능의집합체 Task간의 Communication, Task 관리를위한 Multi-tasking 시스템관리자 Context Switching과같은기본적인서비스를제공 CPU 사용률향상을위해필수적으로필요한세마포어, 메일박스, 메시지큐, Time Delay등의통신방식제공 선점, 비선점커널 임베디드시스템교육센터

18 Scheduler 다음수행할작업을결정하는커널의한부분 대부분의실시간커널은우선순위에기반 배타적우선순위방식 동일우선순위허용방식 Kernel 이어떠한 Scheduling 방식을채택했는가에따라분류 Non-Preemptive Kernel Preemptive Kernel Ex) Time Slice, Round-Robin, FIFO, EDF 임베디드시스템교육센터

19 Non-Preemptive Kernel 현재진행중인프로세스가 CPU 사용을포기하기전까지는다른프로세스가진입할수없는구조 장점 : 짧은 Interrupt Latency 단점 : 나쁜 Task- Level Response 임베디드시스템교육센터

20 Preemptive Kernel 높은우선순위의 Task가언제라도 CPU의제어권을넘겨받을수있도록대기 거의모든 Real-time 시스템의체제가선점커널을사용 장점 : Deterministic 단점 : 자원관리에복잡한알고리즘이필요 임베디드시스템교육센터

21 Priority Task 처리의우선순위를뜻함 Static Priorities : 컴파일시에결정되어프로그램수행중에바꿀수없는우선순위방식 Dynamic Priorities : 프로그램수행중에우선순위가바뀔수있음 Priority Inversion Problem : Real-Time Kernel에서많이발생되는문제 우선순위역전 TASK1(H) (4) (12) (8) TASK2(M) TASK3(L) (1) (6) (10) (2) (3) (5) (7) (9) (11) 임베디드시스템교육센터

22 CPU Utilization 일반적으로높은우선순위의작업이작업실행횟수가더많음 임베디드시스템교육센터

23 Reentrancy 코드의재진입가능여부를나타냄 1 개이상의 Task 가동작할때공유자원을오류없이사용할수있는함수 임베디드시스템교육센터

24 Synchronization Synchronization : Event 발생을생성하거나기다리게하여작업의시작을맞추거나알려주는것 Semaphore등으로신호를전달할수있음 임베디드시스템교육센터

25 Event Flags 여러 Event 가발생하였을때 Task 의동기화를위한장치 Disjunctive Sync. : Task 가어떠한 Event 에도반응하여동기화되는것 Conjunctive Sync. : 모든 Event가다발생해야지동기화되는것 임베디드시스템교육센터

26 Inter-task Communication = IPC(Inter Process Communication) Task 혹은 ISR이다른 Task 들과정보교환을목적으로통신하는것 보통전역데이터나메시지전달방식을사용 전역변수사용시접근의배타성확보필요 통신방법 Semaphore, Mutual Exclusion (MUTEX) Mailbox, Message Queue Event Flags 임베디드시스템교육센터

27 Interrupts 하드웨어메커니즘 불특정한시간에발생하는 Event에대해 ISR 을만들어이를처리할수있게 CPU 할당을해주는서비스 실시간시스템에서는가능한한 Interrupt Disable Time이적도록해야함 Interrupt Nesting Interrupt Latency, Response, Recovery NMI(Non-maskable Interrupts) 임베디드시스템교육센터

28 Clock Tick 주기적인특별한인터럽트로시스템의심장 간격은 10~200ms 사이 주기가짧을수록시스템에부하를많이줌 임베디드시스템교육센터

29 uc/os-ii 임베디드시스템교육센터

30 임베디드시스템교육센터

31 uc/os 란? Jean J. Labrosse 의저서인 The Real-Time Kernel 에속한부록 Code 가몇개의파일로되어있는가장간단한구조의 RTOS 임 도서와같이제공되어 RTOS 의학습에적합 최근 License 를부여하고있으나학습용에는필요없음 uc/os-ii가상용소프트웨입니다. 국내라이센스진행절차는디오이즈에서수행합니다. ( 임베디드시스템교육센터

32 특징 (1/2) 코드의대부분이이식이가능한 C 로구성 임베디드시스템을위해 OS 의 ROM 화가능 옵션설정으로메모리 (ROM, RAM 등 ) 의크기조정가능 선점형실시간커널로서동작하므로높은우선순위태스크의응답시간이빠름 64개까지의 Multitasking 가능 (8개는시스템이사용 ) 기능이나서비스의실행시간예측가능 임베디드시스템교육센터

33 특징 (2/2) Task 의 Stack 크기를각기다르게설정가능 Stack 체크기능이있음 IPC(Event Flag, Mailbox, Message Queue, Semaphore, Mutex) 제공 Fixed-sized memory partition Time-related function 255레벨의 Nesting Interrupts 가능 파일시스템, Network에대한기본적인지원이되지않음 3 rd Party지원 or 유료구현가능 임베디드시스템교육센터

34 uc/os-ii 개요 Kernel Structure Task, 스케줄링, 인터럽트, 시스템초기화등 Task Management Task 의생성, 우선순위변경등 Time Management Task 의 Tick 카운터관리등 Intertask Communication ISR, 공유자원간의내부적통신 (IPC) 등 Memory Management 동적메모리할당, 고정메모리블록등 Porting 임베디드시스템교육센터

35 Kernel Structure Critical Section Tasks, Task State, Task Control Block Ready List Task Scheduling Locking and Unlocking the Scheduler Interrupt under uc/os-ii Idle Task, Statistics Task, Clock Tick uc/os-ii Initialization Starting uc/os-ii 임베디드시스템교육센터

36 Kernel Structure - Critical Section uc/os-Ⅱ 에서는코드의 critical sections 에접근할때 disable/enable interrupts 방법을사용하여보호 disable/enable interrupt 를위해 2 개의 macros 지원 OS_ENTER_CRITICAL( ) OS_EXIT_CRITICAL( ) 상기의 Macro 는 processor specific 하므로 OS_ CPU.H 에서포팅필요 임베디드시스템교육센터

37 Kernel Structure - Critical Sections : example x86에서의인터럽트 Enable/Disable의예 Method 1 #define OS_ENTER_CRITICAL( ) asm CLI #define OS_EXIT_CRITICAL( ) asm STI a total of 4 cycles Method 2 #define OS_ENTER_CRITICAL( ) asm PUSHF; CLI #define OS_EXIT_CRITICAL( ) asm POPF OS_ENTER_CRITICAL : 12 clock cycles OS_EXIT_CRITICAL : 8 clock cycles 임베디드시스템교육센터

38 Kernel Structure - Task States(1/3) OSTaskDel() WAITING DORMANT OSTaskDel() OSTaskCreate() OSTaskCreateExt() OSMBoxPost() OSQPost() OSPostFront() OSSemPost() OSTaskRusume() OSTaskDlyResume() OSTimeTick() READY Preempted OSMBoxPend() OSQPend() OSSemPend() OSTaskSuspend() OSTimeDly() OSTimeDlyHMSM() OSStart() OSIntExit() OS_TASK_SW() RUNNING ISR Interrupt OSIntExit() 임베디드시스템교육센터

39 Kernel Structure - Task States(2/3) DORMANT Task가 ROM 또는 RAM에있는 ( 살아있지않은?) 상태 스스로 or 다른 Task에의해 Delete된상태 READY 수행되어야할 Task들이등록된상태 mulitasking은 OSStart() 에의해시작 OSStart() 에의해높은우선순위 Task가실행되기위해스케쥴링 RUNNING 하나의 task 만이 RUN 상태 임베디드시스템교육센터

40 Kernel Structure - Task States(3/3) WAITING ISR Task 가 delay 되면 WAITING 상태 Timer 가 expire 될수도있고, Ready 상태로갈수도있다. RUNNING 상태의 Task는인터럽트가능 하나이상의Event에대한Task들을실행준비함 모든 task가 event나 time to expire(delay) 를대기 임베디드시스템교육센터

41 Kernel Structure - Task States : After OSInit() OSTCBPrioTbl[] [0] [1] [2] [3] OSTCBList Task Stack OS_TCB OSTCBStkptr OSRCBStkBottom Task Stack OS_TCB OSTCBStkptr OSRCBStkBottom [62] [63] [61] 0 * * 0 OSTCBNext OSTCBPrev OS_TaskStat() OSTCBNext OSTCBPrev OS_TaskIdle() 임베디드시스템교육센터

42 Kernel Structure - OS_TCB Free List OS_MAX_TASKS OS_TCB OS_TCB OS_TCB OSTCBFreeList 임베디드시스템교육센터

43 Kernel Structure - OS_TCB Data Structure(1/5) OS_STK *OSTCBStkPtr void *OSTCBExtPtr OS_STK*OSTCBStkBottom INT32U OSTCBStkSize INT16U OSTCBOpt INT16U OSTCBId os_tcb *OSTCBNext os_tcb *OSTCBPrev OS_EVENT *OSTCBEventPtr OS_EVENT void OS_STK INT8U INT8U INT8U INT8U INT8U INT8U *OSTCBEventPtr *OSTCBMsg OSTCBDly OSTCBStat OSTCBPrio OSTCBX OSTCBY OSTCBBitX OSTCBBitY 임베디드시스템교육센터

44 Kernel Structure - OS_TCB Data Structure(2/5) OSTCBStkPtr 이Task의마지막top-of-stack을표시함 Stack 크기는각각조절가능 Structure entry의처음에위치함 OSTCBExtPtr 확장된 TCB에대한사용자정의된곳의 Pointer uc/os-ii의코드변경없이확장된 TCB 사용가능 사용법 : OS_TASK_CREATE_EXT_EN = 임베디드시스템교육센터

45 Kernel Structure - OS_TCB Data Structure(3/5) OSTCBStkBottom Stack 의 bottom 을표시 Free Stack Size Current Location of Stack Pointer Used Stack Space Low Memory 0 0 : : 0 High Memory OSTCBStkBottom Deepest Stack Growth OSTCBStkSize Stack Growth Initial TOS 임베디드시스템교육센터

46 Kernel Structure - OS_TCB Data Structure(4/5) OSTCBStkSize OSTaskStkChk() 에서사용할정보 OS_TASK_CREATE_EXT_EN=1일경우만사용가능 OSTCBOpt OSTaskCreateExt() 으로전달될 Option 정보 OS_TASK_CREATE_EXT_EN=1 일경우만사용가능 임베디드시스템교육센터

47 Kernel Structure - OS_TCB Data Structure(5/5) OSTCBNext, OSTCBPrev Double link OS_TCBs 각 Task의 OSTCBDly 필드를 update할때사용할 c hain임 Task가생성, 삭제될때이 Linked List에적용됨 임베디드시스템교육센터

48 Kernel Structure -Ready List(1/2) 각 Task는실행되기위에 OSRdyGrp and OSRdyTbl[] 에등록됨 OSRdyTbl[] Table of tasks which are ready to run. INT8U OSRdyTbl[OS_LOWEST_PRIO/8 + 1] OSRdyGrp Each bit represents a group INT8U OSRdyGrp 그룹당 8개의 task를가지고있고, OSRdyTbl[ ] 의각 bit들은 task들에대응 Ex. ) Bit i in OSRdyGrp is 1 when any bit in SRdyTb l[i] is 임베디드시스템교육센터

49 Kernel Structure - Ready List(2/2) 임베디드시스템교육센터

50 Kernel Structure - Bit Map table INT8U const OSMapTbl[] /* Priority->Bit Mask lookup table */ INT8U const OSUnMapTbl[] /* Priority->Index lookup table */ Contents of OSMapTbl[] index Bit Mask(Binary) 임베디드시스템교육센터

51 Kernel Structure - Scheduling uc/os_ii 항상가장높은우선순위의 Task를실행 scheduler: 가장높은우선순위의Task를선정작업 OSSched(): Task-level scheduling OSIntExit(): ISR-level scheduling 임베디드시스템교육센터

52 Kernel Structure - Locking and Unlocking OSSchedLock() 이상의 scheduling 을방지함 호출된이후에는현재 Task 를 suspend 시킬수없음 Ex: OSMboxPend(), OSTimeDly() OSSchedLock() 과 OSSchedUnLock() 은항상pai r로사용 OSLockNesting OSSchedLock() 이불린회수를표시 OSLockNesting = 0 이면 scheduling이가능한상태임 임베디드시스템교육센터

53 Kernel Structure - Steps of OSSched() Step1 : OSSched() 가 ISR (i.e.,osintnesting > 0) 이나 scheduling disabled (i.e., OSLockNesting > 0) 상태인지체크하여맞다면, OSSched() 빠져나감 OSIntNesting is incremented in OSIntEnter(). OSLockNesting is incremented when your application calle d OSSchedLock() at least once. Step2 : 아니면, Ready List 중가장높은우선순위의 Task를실행준비함 Step3 : 가장높은우선순위 Task가현재의것인지체크 Step4 : 아니면, OS_TASK_SW() 를호출하여 context switching 시작 임베디드시스템교육센터

54 Kernel Structure - Idle Task μc/os-Ⅱ는항상하나의 Task는수행중이어야하므로실제일을하지않는Task를하나수행함 OS_LOWEST_PRIO : 이 Idle Task의우선순위는가장낮음 OSIdleCtr : Idle Task가수행되면계속이값을증가시키고프로그램의 CPU 사용률측정에사용 void OSTaskIdle (void *pdata) { pdata = pdata; for (;;) { OS_ENTER_CRITICAL(); OSIdleCtr++; OS_EXIT_CRITICAL(); } } 임베디드시스템교육센터

55 Kernel Structure - Statistic Task OSTaskStat( ) OS_TASK_STAT_EN = 1 로설정하면사용가능 매초마다값을계산함 OSCPUUsage signed 8-bit integer 값으로실제값 프로그램에서사용한 CPU Time 을 % 로표시 OSIdleCtrMax : 지금까지중최대사용값표시 OSStatInit( ) 위의 statistic task 를사용하기위해서는이함수를초기에호출하여설정하여야함 OSCPUUsage (%) = 100(1 OSIdleCtr OSIdleCtrMax ) 임베디드시스템교육센터

56 Kernel Structure - ISRs under µc/os-Ⅱ YourISR: Save all CPU register; Call OSIntEnter() or, increment OSIntNesting directly; Execute user code to service ISR; Call OSIntExit(); Restore all CPU registers; Execute a return from interrupt instruction; 임베디드시스템교육센터

57 Kernel Structure - Servicing an INT. Interrupt Request TASK Vectoring Saving Context Task Response Interrupt disabled No New HPT Or OSLockNesting>0 Notify kernel User ISR code Notify kernel Interrupt Recovery TASK Return from interrupt Restore Context Interrupt Response ISR signals a task Task Response Notify kernel Restore Context Return from interrupt New HPT TASK Interrupt Recovery 임베디드시스템교육센터

58 Kernel Structure - OSIntEnter() OS 에게인터럽트에진입함을알려주기위하여 OSIntEnter() 함수를호출함 전역변수인 OSIntNesting 를증가하여 interrupt nesting 을표현 void OSIntEnter (void) { OS_ENTER_CRITICAL(); OSIntNesting++; OS_EXIT_CRITICAL(); } 임베디드시스템교육센터

59 Kernel Structure - OSIntExit() ISR이끝나면 OSIntExit() 를호출하여 interrup t nesting counter값을감소시킴 nesting counter = 0이면인터럽트가끝났으므로OS는최상위 Task를실행시키기위해 scheduling을함 최상위 Task가실행준비가되면인터럽트에서실행할 Task로진입 임베디드시스템교육센터

60 Kernel Structure - OSIntCtxSw() Why not using OS_TASK_SW()? 인터럽트수행시이미 CPU register 등을저장하였으므로일의양을줄일수있음 OSIntCtxSw() 는단순히 processor의 stack p ointer(sp) 만조정하면됨 임베디드시스템교육센터

61 Kernel Structure - The stack frame LOW MEMORY Return address to caller of OSIntCtxSw() Processor Status Word Return Address to caller of OSIntExit() Saved Processor Registers Interrupt Return Address Processor Status Word High Memory SP Points Here! 5 SP must be adjusted to point here. This new SP is saved into the preempted task s OS_TCB 임베디드시스템교육센터

62 Kernel Structure - Clock Tick 시스템의심장인 Clock Tick은특별한주기 Timer Interrupt로서사용 전형적으로 10 ~ 200ms를주기로사용함 (PC 의경우 default tick rate = Hz) A tick source: A hardware timer AC power line(50/60hz) signal Ticker interrupts 는 multitasking 이시작된이후에 Enable 해야함 (crash 방지 ) 임베디드시스템교육센터

63 Kernel Structure - Delayed Tick Tick Interrupt 20ms Tick ISR All Higher Priority Tasks Delayed Task 19ms 17ms 27ms 높은우선순위의 Task 나 ISR 을실행시키기위해 1Tick Delay 가필요할수있음 임베디드시스템교육센터

64 Kernel Structure - Tick Code void main(void) {. OSInit(); /*initialize uc/os-ii*/.. /* Application initializaztion code... Create at least one task by calling OSTaskCreate() */.. Enable TICKER interrupts; /* DO NOT DO THIS HERE!! */.. OSStart(); /*starting Multitasking*/ } 임베디드시스템교육센터

65 Task Management(1/2) 최대 64 개의 TASK 를관리 최상위, 최하위우선순위의 TASK 4 개씩 : 시스템용 각각의 Task 는 Return Type 과 Argument 를가지고있지만 Return 값을전달하지않음 void yourtask(void *pdata) { for(;;){ /* User Code */ Osxxxx(); /* User Code */ } } 무한반복형 Task void yourtask(void *pdata) { for(;;){ /* User Code */ OSTaskDel(OS_PRIO_SELF); } } 1 회수행형 Task 임베디드시스템교육센터

66 Task Management(2/2) Task Creation Task Deletion Change a Task s Priority Suspend and Resume a Task Obtain Information about a Task 임베디드시스템교육센터

67 Task Management - Task Creation TASK들은 Multitasking의시작전이나다른 TASK에의해생성 스택도같이생성이되며, 스택영역은 C 컴파일의 malloc() 과같은기능의함수로동적할당가능 ISR(Interrupt Service Routine) 에서는 TASK를생성할수없음 Two functions for creating a task : OSTaskCreate() OSTaskCreateExt() 임베디드시스템교육센터

68 Task Management - OSTaskCreate() Format : OSTaskCreate(*task, *pdata, *ptos, prio) task : A pointer to the task's code pdata : A pointer to an argument that is passed to your t ask when it starts executing. ptos : A pointer to the task's top of stack. prio : The task's priority. Returns OS_NO_ERR : if the function was successful. OS_PRIO_EXIT : if the task priority already exist OS_PRIO_INVALID : if the priority you specify is higher th an the maximum allowed 임베디드시스템교육센터

69 Task Management - OSTaskCreateExt() Format: OSTaskCreateExt(*task, *pdata, *ptos, pri o, id, *pbos, stk_size, *pext, opt) Additional Arguments id : The task's ID ( ) pbos : A pointer to the task's bottom of stack stk_size : The size of the stack in number of elements pext : A pointer of TCB extension opt : Contains additional information (or options) about t he behavior of the task Returns : Same as OSTaskCreate() 임베디드시스템교육센터

70 Task Management - Task Stacks(1/2) Task 함수의외부에서정의되어야할자료 정적으로정의할경우 static OS_STK MyTaskStack[stack_size]; OS_STK MyTaskStack[stack_size]; 동적으로정의할경우 malloc() OS_STK *pstk* pstk; pstk = (OS_STK *)malloc malloc(stack_size); if pstk!=(os_stk*)0){ /*Make sure malloc() has enough space*/ Create the task; } 임베디드시스템교육센터

71 Task Management - Task Stacks(2/2) Stack 은연속적인메모리를가짐 Fragmentation Stack grows 3Kb From low to high memory. OS_STK_GROWTH is set to 0 in OS_CPU.H From high to low memory. A(1Kb) B(1Kb) C(1Kb) OS_STK TaskStack[TASK_STACK_SIZE]; OSTaskCreate(task, pdata,, &TaskStack& TaskStack[0], prio); 1Kb B(1Kb) 1Kb OS_STK_GROWTH is set to 1 in OS_CPU.H OS_STK TaskStack[TASK_STACK_SIZE]; OSTaskCreate(task, pdata,, &TaskStack& TaskStack[TASK_STACK_SIZE-1], prio); 임베디드시스템교육센터

72 Task Management - OSTaskStkChk() 특정 Task 의 Stack 메모리중사용하지않은양을측정할수있음 Free Stack Space Current Location of Stack Pointer Used Stack Space LOW MEMORY HIGH MEMORY OSTCBStkBottom Deepest Stack Growth Stack Growth Initial TOS OSTCBStkSize 임베디드시스템교육센터

73 Task Management Functions(1/2) OSTaskDel() - Deleting a Task Task 를삭제할수있는함수 Task 스스로도호출가능 해당 Task 는 DORMANT 상태로진입 OSTaskDelReq()- Requesting to Delete a Task 해당 Task 가스스로삭제되도록요청 현재수행중인 Task 가삭제되기를요청하면삭제될수있음 OSTaskChangePrio() Changing a Task s Priority Task 생성시에우선순위가결정되어있음 그러나이함수를사용하여변경가능 우선순위역전현상을해결가능 임베디드시스템교육센터

74 Task Management - Functions (2/2) OSTaskSuspend() Suspending a Task Suspend 된 task 는 OSTaskResume() 에의해다시동작가능한상태로변경됨 스스로혹은다른 Task 를 Suspend 할수있음 주의사항 : event (e.g., a message, a semaphore) 를기다리고있는 Task 의경우에는신호전달에문제발생주의 OSTaskResume() Resuming a Task OSTaskResume() 을호출하면다시동작가능한상태로될수있음 OSTaskQuery() Getting Info. about a Task Tasks 그자체나다른 Task 에대한기타정보를획득 (OS_CF G.H 에정의한 Task 정보를바탕 ) 원하는 Task 의 OS_TCB 의정보를갖고있음 Task 가수행되는 state 와, 그때사용될 functions 임베디드시스템교육센터

75 Time Management Clock time 을이용 시간과관련된함수를제공 OSTimeDly() OSTimeDlyHMSM() OSTimeDlyResume() OSTimeGet() OSTimeSet() 임베디드시스템교육센터

76 Time Management - Delaying a Task OSTimeDly() 사용자가지정하는 Clock time 의수만큼 Task 자신을 wait 상태로옮겨 Task 의실행을지연시킴 현재실행중인 Task 의실행을멈추고, ready 상태에있는가장높은우선순위의 Task 를실행 지정한시간이다되거나 OSTimeDlyResume() 에의해 ready 상태로가면다른대기중인 Task 들과경합을벌여가장높은우선순위일때에만실행됨 OSTimeDlyHMSM() OSTimeDly() 와같은기능 H( 시간 ), M( 분 ), S( 초 ) 와 m( 밀리초 = 10-3 초 ) 로직접사용자가지정함 임베디드시스템교육센터

77 Time Management Resume Delayed Task OSTimeDlyResume() 지연시킨 Task 를다시풀고 ready 상태로만듦 다른Task가지연된Task를wait 상태에서ready 상태로전환시킬때사용 이경우재실행된 Task는대기중시간이끝난것으로처리 임베디드시스템교육센터

78 Time Management - System Time Clock tick이발생시마다 32 bit Counter 변수의값을증가 OSStart() 의호출이후계속증가 (Tick rate이 100Hz라면 497일이되면다시초기화됨 ) OSTimeGet() Counter 의값을읽어오는데에사용 OSTimeSet() 사용자가지정한값으로 Counter 의값을설정 이 OSTime 에접근하는동안에는 Interrupt 를불능상태로만듦 임베디드시스템교육센터

79 Intertask Communication & Sync.(1/2) 공유데이터를보호하고 TASK 간의통신을위한여러가지방법들 여러 TASK 들이사용하고있는데이터들이임의로변경되지않도록함 한 TASK 가만들어낸정보를다른 TASK 가이용하기위하여전달할수있는채널 synchronization 과 coordination 을구현하기위한방법 semaphore IPC 를구현하는방법 mailbox, message queue 기타 : Mutex., Event Flags 임베디드시스템교육센터

80 Intertask Communication & Sync.(2/2) Semaphore Mailbox Message Queue Event Flags Mutex 임베디드시스템교육센터

81 IPC & Sync. - Semaphore semaphore를사용하기전에이자원에대한생성이필요 Semaphore 사용법 (initial value 설정 ) Signal event shared resource n identical resources 5 가지 semaphore service OSSemCreate() OSSemPend(), OSSemPost() OSSemAccept(), OSSemQuery() 임베디드시스템교육센터

82 IPC & Sync. Relationships(tasks, ISRs) OSSemCreate() Task OSSemPost() N OR OSSempend() OSSemAccept() OSSemQuery() Task ISR OsSemPost() OSSemAccept() N 임베디드시스템교육센터

83 IPC & Sync. - Creating a semaphore OSSemCreate() Steps : 1. ECB의 free list로부터하나를할당받음 2. ECB 설정 3. ECB로 Pointer 값을되돌려줌 pointer는 semaphore를다루는함수에사용됨 [OSSemPend(), OSSemPost(), OSSemA ccept(), and OSSemQuery()] 더이상의 ECB가없다면, OSSemCreate() 는 NULL pointer를돌려줌 임베디드시스템교육센터

84 IPC & Sync. - Waiting on a semaphore OSSemPend() steps : 1. Type 과 semaphore 확인 2. If semaphore =< 0, interrupt nest 확인 3. Else semaphore를기다리게하기위해 tas k를 Block 시킴 Error return : OS_ERR_EVENT_TYPE : type mismatch OS_ERR_PEND_ISR : ISR cannot made to wait OS_TIMEOUT : time up before get semaphore 임베디드시스템교육센터

85 IPC & Sync. - Signaling a semaphore OSSemPost() steps : 1. Type 확인 2. 어떤 task가 waiting 하고있는지최상위우선순위의것을선택함 3. Waiting하는 Task가없다면 semaphore를증가시키고 return ISR 에의해이함수가호출되면 context swit ch 이되지않고마지막 OSIntExit() 에서 context switching 함 임베디드시스템교육센터

86 IPC & Sync.- Getting a semaphore w/o waiting OSSemAccept() Function steps : 1. Type 과 semaphore 를확인 2. If count > 0, count 감소 3. if not, return count OSSemAccept() 를호출하는함수는 returned value 를확인할필요가있음 Return value = 0 semaphore 가가능하지않음 임베디드시스템교육센터

87 IPC & Sync. - status of a semaphore OSSemQuery() steps : 1. type 확인 2. ECB 의데이터를복사 semaphore가가지고있는ecb의포인터를제공 OS_EVENT structure로부터 OS_SEM_DATA s tructure로현재의 semaphore count값을복사함 임베디드시스템교육센터

88 IPC & Sync. - Message MailBox(1/2) Task 가독립적으로움직이지만이들사이의데이터교환을위한통로가필요 MailBox : Task 간에직접 data(message) 를주고받는데에사용 하나의 message (mailbox is full) 만전달가능 구성 message 를포함한데이터구조체를가리키는 Pointer 대기중인 TASK 의리스트 단순히 post 와 pend 여부만을검사하여 binary semaphore 처럼도사용가능 임베디드시스템교육센터

89 IPC & Sync. - Message MailBox(2/2) Mailbox는 OS_MBOX_EN = 1로하여야사용가능 사용하기전에이자원에대한생성이필요 5가지의 Mailbox service OSMboxCreate() OSMboxPost() OSMboxPend() OSMboxAccept() OSMboxQuery() 기능과사용법은 Semaphore 와동일 임베디드시스템교육센터

90 IPC & Sync. - Relationships OSMboxCreate() ECB Task ISR OSMboxPost() OSMboxPost() OSMboxAccept() OSEventType *OSEventPtr OSEventTbl OSEventGrp Ⅱ Mailbox OSMboxPend() OSMboxAccept() OSMboxQuery() Message Task 임베디드시스템교육센터

91 IPC & Sync. - mailbox as binary semaphore(1/2) non-empty mailbox를생성 Wait : OSMboxPend(); Signal : OSMboxPost(); OS_EVENT *MboxSem; void Task1(void *pdata) { INT8U err; for(;;){ OSMboxPend(MboxSem, 0, &err); /* Obtain resource */ OSMboxPost(Mbox, (void *)1); /* Release resource */ } } 임베디드시스템교육센터

92 IPC & Sync. - mailbox as binary semaphore(2/2) Task1 Post Pend ECB Task2 Pend Post message: Resource Task1 Pend Post 임베디드시스템교육센터

93 IPC & Sync. - mailbox as time delay(1/2) empty mailbox 생성 Delay task : OSMboxPend(); Cancel delay : OSMboxPost(); void Task1(void *pdata) void Task2(void *pdata) { { INT8U err; for(;;){ /* Delay task */ OSMboxPend(MboxTimeDly, TIMEOUT, &err); } INT8U err; for(;;){ /* cancel delay */ OSMboxPost(MboxTimeDly, (void *)1); } } } 임베디드시스템교육센터

94 IPC & Sync. - mailbox as time delay(2/2) Task1 Pend ECB message:null Task2 Post 임베디드시스템교육센터

95 IPC & Sync. - Message Queue Message mailbox의 array와같음 OS_Q_EN = 1로하여야사용가능 사용되기전에생성되어야함 FIFO와 LIFO queue 모두사용가능 Resource의개수만큼 message 포함가능 Counting semaphore로사용가능 임베디드시스템교육센터

96 IPC & Sync. - Message Queue Architecture Task OSQPost() OSQPostFront() OSQFlush() Message Queue Message* Message* Message* Message* Message* Message* Message* Task OSQPend() OSQAccept() OSQQuery() ISR OSQPost() OSQPostFront() OSQFlush() Size = N OSQCreate() ISR * OSQPend() OSQAccept() OSQQuery() 임베디드시스템교육센터

97 IPC & Sync. - Message Date Structure(1/4) OS_Event OSEventGrp void* MsgTbl[] OSEventTbl[] OSEventCnt OSEventPtr OS_Q OSQPtr OSQStart OSQSize OSQOut OSQIn OSQEnd OSQEntries OSQEntries OSQSize 임베디드시스템교육센터

98 IPC & Sync. - Message Date Structure(2/4) OSEventGrp OSEventGrp OSEventGrp OSEventFreeList OSEventTbl[] OSEventTbl[] OSEventTbl[] OSQFreeList OSEventCnt OSEventPtr OSQPtr OSQStart OSQSize OSQOut OSQIn OSQEnd OSQEntries OSEventCnt OSEventPtr OS Event Link List OSQPtr OSQStart OSQSize OSQOut OSQIn OSQEnd OSQEntries OS Message Queue Link List OSEventCnt OSEventPtr NULL NULL OSQPtr OSQStart OSQSize OSQOut OSQIn OSQEnd OSQEntries 임베디드시스템교육센터

99 IPC & Sync. - Message Date Structure(3/4) OSEventGrp OSEventTbl[] OSEventCnt OSEventPtr OSQPtr OSQStart OSQSize OSQOut OSQIn OSQEnd OSQEntries OSEventGrp OSEventTbl[] OSEventCnt OSEventPtr OSEventFreeList OSQFreeList OSQPtr OSQStart OSQSize OSQOut OSQIn OSQEnd OSQEntries OSEventGrp OSEventTbl[] OSEventCnt OSEventPtr NULL NULL OSQPtr OSQStart OSQSize OSQOut OSQIn OSQEnd OSQEntries 임베디드시스템교육센터

100 IPC & Sync. - Message Date Structure(4/4).OSQStart.OSQEnd.OSQOut Pointer to message.osqentries.osqin 임베디드시스템교육센터

101 IPC & Sync. - Creating a message queue Start To get OSEventFreeList Yes To get OSQFreeList Yes Initialize the Message Queue Header Linking OSEventFreeList to OSQFreeList which we got Reset the OSEventFreeList and OSQFreeList Return the pointer of Event object which we got No No Has error, return NULL pointer End 임베디드시스템교육센터

102 IPC & Sync. - Depositing a message queue Start Correct Event Type No Yes Yes Need to fire event Post event (That means insert a event) No If the queue table isn t full Yes Return the unsuccessful signal Do the system schedule No Insert a message in the message table Return the successful signal End 임베디드시스템교육센터

103 IPC & Sync. - Getting a message w/o waiting Start Correct Event Type No Yes If the queue table isn t empty Yes No Get a message from the message table Return the Null pointer Return the message pointer End 임베디드시스템교육센터

104 IPC & Sync. - Waiting for a message queue Start Is this a task? No No Correct Event Type Yes If the queue table isn t empty No Get a message from the message table Yes Yes Set a Event trap to wait the queue insert message event (with timeout) Have we got the message event? Yes No Is it still waiting for that event? No Yes Return the Null pointer Return the message pointer Getting the message from that event message Timeout!! Return the Null pointer End 임베디드시스템교육센터

105 Memory Management 일반 C언어 : malloc() 과 free() 로자유롭게메모리를할당 임베디드실시간시스템에서는 fragmentation 위험 보통 TASK 스택을할당시연속적인블록을사용하는알고리즘채택 malloc() 과 free() 의대안 연속된메모리구역에고정크기의메모리를얻기위한방법 모든메모리블록은같은크기 메모리의할당, 회수는일정시간에진행 하나이상의메모리파티션이존재가능 Start Address Block Memory partition 어플리케이션은다른크기의메모리블록을얻을수있음 임베디드시스템교육센터

106 Memory Management - MCBs MCB : Memory Control Blocks 데이터구조체를메모리분할의형식으로사용 typedef struct { /*MEMORY CONTROL BLOCK */ void *OSMemAddr; /*Pointer to beginning of memory partitio */ void * OSMemFreeList; /*Pointer to list of free memory blocks */ INT32U OSMemBlkSize; /*Size (in bytes) of each block of memory */ INT32U OSMemNBlks; /* Total number of blocks in this partition */ INT32U OSMemNFree; /* Number of memory blocks remaining in this partition */ } OS_MEM; 임베디드시스템교육센터

107 Memory Management - Function List(1/2) OSMemCreate( ) 어플리케이션은실행전에각파티션을생성해야함 메모리파티션을생성, 초기화가능 OSMemGet( ) 어플리케이션은생성된메모리파티션의하나로부터메모리블록획득 어플리케이션에서는자신에게필요한메모리양만사용 임베디드시스템교육센터

108 Memory Management - Function List(2/2) OSMemPut( ) 어플리케이션이메모리블록을사용하고난후적절한파티션으로메모리를돌려줄때사용 메모리블록을원래속해있던파티션으로되돌려주지않으므로사용주의 OSMemQuery() 메모리파티션에대한정보를얻음 비거나사용중인메모리블록을파악가능 정보 : OS_MEM_DATA 로불리는데이터구조체에위치 임베디드시스템교육센터

109 ARM Architecture 임베디드시스템교육센터

110 임베디드시스템교육센터

111 ARM Architecture - Contents ARM Architecture Overview ARM Programmer Model ARM Instruction Set Thumb Instruction Set ARM Assembly Programming ARM920T System Control Coprocessor ARM920T MMU ARM920T Cache, Write Buffer 임베디드시스템교육센터

112 ARM Architecture About Company Acorn Computer Group develops the world s first commercial RISC processor ARM pins out of Acorn and Apple the first embeddable RISC core ARM TI, Cirrus, Samsung license ARM, ARM7 core Thumb architecture, StrongARM ARM9TDMI family announced ARM10 family announced ARM11 The industry's leading provider of 32-bit embedded RISC microprocessors with almost 75% of the market 임베디드시스템교육센터

113 ARM Architecture - About ARM MPU ARM (Advanced RISC Machine) Architecture It s RISC (Reduced Instruction Set Computer) Large uniform register file Load/store architecture Simple addressing mode Uniform and fixed-length instruction field In addition, Shift + ALU data processing Auto increment/decrement addressing Load and store multiple Conditional execution Characteristic Small die size Low power Thumb instruction High code density High Performance, Lower Cost, Less Power 임베디드시스템교육센터

114 ARM Architecture - Embedded Products 임베디드시스템교육센터

115 ARM Architecture - Progression V6 V5TEJ XScale V5TE ARM926EJ ARM1020E V4T ARM9E SecureCore V4 ARM920T ARM7TDMI StrongARM ARM7 T: Thumb extension D: Debug extension M: Hardware multiplier I: EmbeddedICE extension E: DSP Enhanced J: Java extension V6: Media extension 임베디드시스템교육센터

116 ARM Architecture - ARM9TDMI Core B.D. IA[31:0] ID[31:0] A Bus IAReg Register Bank (31x PSR) MUL IINC B Bus Shifter C Bus Instruction Decode & Control Logic 32bit (16 bit) RISC ARM Architecture V4T 5 Stage Execution Pipelining Harvard Architecture DAReg 32 bit ALU DINC DDReg Scan Control ARM9TDM Control Address Data DA[31:0] DO[31:0] DI[31:0] TAP Controller Embedded ICE 임베디드시스템교육센터

117 ARM Architecture - ARM920T B.D. ARM9TDMI 16K I$, 16K D$ MMU Write Buffer AMBA AHB Interface CP Interface 임베디드시스템교육센터

118 ARM Architecture - Core Comparison Cache (I/D) MMU AHB Bus Thumb DSP Jazelle Clock ARM7TDMI x x o o x x 133 ARM720T 8K Unified o o o x x 100 ARM920 16K/16K o o o x x 250 ARM940 4K/4K MPU o o x x 180 ARM926EJ Various o Dual o o o ARM1020E 32K/32K o Dual o o x 325 ARM1020EJ Various MMU+ MPU Dual o o o StrongARM 16K/16K o NA x x x 206 Xscale 32K/32K o NA o o x 임베디드시스템교육센터

119 ARM Architecture - Coprocessor(CP15) Control standard memory and system facilities MMU and PU Cache and Write Buffer FCSE Endianness and High vector address Use only MCR, MRC coprocessor instructions in a privileged mode cond L CRn Rd Op_ Operation 1 Load/Store Source/Destination Source/Destination CP15 Operation 2 CR 임베디드시스템교육센터

120 ARM Architecture - ARM920T CP15 Reg Read ID Code Cache type Control Translation table base Domain access control Unpredictable Fault status Fault address Unpredictable Unpredictable Cache lockdown TLB lockdown Unpredictable Unpredictable FCSE PID Unpredictable Test configuration Write Unpredictable Unpredictable Control Translation table base Domain access control Unpredictable Fault status Fault address Cache operations TLB operations Cache lockdown TLB lockdown Unpredictable Unpredictable FCSE PID Unpredictable Test configuration Action Op_2 = 0 Op-2 = 1 2 registers for Instr./Data 2 registers for Instr./Data 2 registers for Instr./Data 임베디드시스템교육센터

121 ARM Programmer Model - Overview Data Types Processor Modes Registers Exceptions Memory Systems 임베디드시스템교육센터

122 ARM Programmer Model - Data Types Supported Data Types Byte : 8 bits Halfword : 16 bits (aligned to 2-byte boundaries) Word : 32 bits (aligned to 4-byte boundaries) Notes Unsigned: 0 ~ 2 N 1 Signed: -2 N-1 ~ +2 N-1 1 All data operations are performed on word quantities Load/Store transfer B, HW, W with zero-extending and sign-extending ARM instruction are exactly 1 word Thumb instruction are exactly 1 halfword 임베디드시스템교육센터

123 ARM Programmer Model - Modes Mode Description ID Comments User Normal program execution mode usr restriction System Privileged mode for operating system sys OS task FIQ When a fast interrupt fiq High-speed ch. IRQ When a normal interrupt irq Supervisor Exception mode for operating system svc SWI Abort When data or instruction prefetch abort abt Vir. Mem, MPro Undef When an undefined instruction und HW Emulation User and System mode share one bank of registers Exception mode: their own registers FIQ mode has private R8 ~ R14 the other modes have private R13 ~ R 임베디드시스템교육센터

124 ARM Programmer Model Registers User & System FIQ IRQ Supervisor Abort Undef R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R0 R1 R2 R3 R4 R5 R6 R7 R8_fiq R9_fiq R10_fiq R11_fiq R12_fiq R13_fiq R14_fiq R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_irq R14_irq R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_svc R14_svc R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_abt R14_abt R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_und R14_und PC(R15) PC(R15) Program Counter PC(R15) PC(R15) PC(R15) PC(R15) CPSR CPSR SPSR_fiq Program Status Register CPSR CPSR SPSR_irq SPSR_svc CPSR SPSR_abt CPSR SPSR_fiq 임베디드시스템교육센터

125 ARM Programmer Model - PSRs N Z C V Reserved I F T M Flag field Status field Condition Code Flags N Negative result from ALU Z Zero result from ALU C ALU operation caused V ALU Carryoperation overflowed Control bits I 1: disables IRQ F 1: disables FIQ T 1: Thumb, 0: ARM Extension field Control field Mode bits M[4:0] Mode 0b10000 User 0b11111 System 0b10001 FIQ 0b10010 IRQ 0b10011 Supervisor 0b10111 Abort 0b11011 Undefined CPSR (Current PSR): Hold the current status information SPSR (Saved PSR): Reserve the CPSR during exceptions 임베디드시스템교육센터

126 ARM Programmer Model - Exceptions Exception Type Reset Undefined Instruction SWI Prefetch Abort Data Abort Reserved IRQ FIQ Priority Mode Supervisor Undefined Supervisor Abort Abort IRQ FIQ Vector 0x x x x C 0x x x x C High Vector 0xFFFF0000 0xFFFF0004 0xFFFF0008 0xFFFF000C 0xFFFF0010 0xFFFF0014 0xFFFF0018 0xFFFF001C 임베디드시스템교육센터

127 ARM Programmer Model H/W Vectors 0x00 0x04 0x08 0x0c 0x10 0x14 0x18 0x1c Branch to Handler Branch to Handler Branch to Handler Branch to Handler Branch to Handler Branch to Handler Branch to Handler FIQ Handler Reset Undefined Instruction Software Interrupt Prefetch Memory Abort Data Memory Abort Reserved Normal Interrupt Fast Interrupt Interrupt Handler 임베디드시스템교육센터

128 ARM Programmer Model - LR & Return Exception Type Reset Undefined Instruction SWI Prefetch Abort Data Abort Reserved IRQ FIQ R14 from ARM Unpredictable Undefined instruction + 4 SWI instruction + 4 Aborted instruction + 4 Aborted instruction + 8 Next instruction + 4 Next instruction + 4 Return MOVS PC, R14 MOVS PC, R14 SUBS PC, R14, #4 SUBS PC, R14, #8 SUBS PC, R14, #4 SUBS PC, R14, # 임베디드시스템교육센터

129 ARM Programmer Model - Endian Support Dual-Endian Big Endian Processor : (like IBM, Motorola, SPARC) High-order-byte-first, human-friendly type Little Endian Processor: (like DEX VAX, Intel X86) Low-order-byte-first, computer-friendly type Store 4Bytes Word to Memory at N N N+1 N+2 N+3 B0 B1 B2 B3 MSB B3 B2 B1 LSB B0 B3 B2 B1 B0 N N+1 N+2 N+3 Little Endian Big Endian 임베디드시스템교육센터

130 ARM Programmer Model - Alignment Aligned Access Good for performance Byte: 4N, 4N+1, 4N+2, 4N+3 Half Word: 4N, 4N+2 Word: 4N Unaligned Access Good for memory usage Half Word: 4N+1, 4N+3 Word: 4N+1, 4N+2, 4N+3 4N 4N+4 4N+8 4N+C N 4N+4 4N+8 4N+C Aligned Access Unligned Access 임베디드시스템교육센터

131 ARM Programmer Model - Dual-Endian shift logic for big-endian operand Reg MSB B3 B2 B1 LSB B0 D3 D2 D1 D0 B3 B2 B1 B0 D3 D2 D1 D0 B3 B2 B1 B0 D3 D2 D1 D0 B3 B2 B1 B0 Endianness Shift Logic in Byte Load Byte Load HW Load W shift logic for little-endian operand Data Bus Latch Memory D3 N+3 D2 N+2 D1 N+1 D0 N D3 D2 D1 D0 B3 B2 B1 B0 D3 D2 D1 D0 B3 B2 B1 B0 D3 D2 D1 D0 B3 B2 B1 B0 Load Byte Load HW Load W 임베디드시스템교육센터

132 ARM Instruction - Set ARM Instruction Characteristics Data Processing Instructions Load and Store Instructions Branch Instructions SWP and SWI Coprocessor Instructions 임베디드시스템교육센터

133 ARM Instruction - Characteristics RISC Instruction Fixed length 32-bit Load/Store Architecture Simple format and Simple addressing mode 5-stage pipelining Conditional Execution Shifted operand Instruction Fetch Fetch Instruction Shift Decode Reg Decode Read Reg + Memory Reg ALU Access Write Decode Execute Memory Write 임베디드시스템교육센터

134 ARM Instruction - v4t Instructions cond 0 0 I Opcode S Rn Rd Shifter_operand cond cond cond cond cond Data Processing/ PSR Transfer A S Rd Rn Rs Rm Multiply U A S RdHi RdLo Rn Rm Multiply Long B 0 0 Rn Rd Rm Data Swap P U I W L Rn Rd Ad_mode 1 S H 1 cond P U B W L Rn Rd Offset Rm Ad_mode Branch and Exchange HW Data Transfer Single Data Transfer cond Undefined cond P U S W L Rn Register List Block Data Transfer cond L Signed_immed_24 Branch cond cond cond P U N W L Rn CRd Op_1 CRn CRd Op_1 L CRn Rd cond SWI number CP# CP# CP# Op_2 Op_2 Offset 0 1 CRm CRm Co-processor Data Transfer Co-processor Data Operation Co-processor Register Transfer Software Interrupt 임베디드시스템교육센터

135 ARM Instruction - Condition Field Cond Reserved Cond Mnemonic EQ NE CS/HS CC/LO MI PL VS VC HI LS GE LT GT LE AL (NV) Meaning Equal Not Equal Carry set / unsigned >= Carry clear / unsigned < Minus/Negative Plus/Positive or Zero Overflow No overflow Unsigned higher Unsigned lower or same Signed >= Signed < Signed > Signed <= Always Unpredictable Condition flag state Z = 1 Z = 0 C = 1 C = 0 N = 1 N = 0 O = 1 O = 0 C=1 & Z=0 C=0 Z=1 N==V N!=V Z==0,N==V Z==1 or N!=V 임베디드시스템교육센터

136 ARM Instruction - Data Processing cond 0 0 I Opcode S Rn Rd Shifter_operand Opcode Mnemonic AND EOR SUB RSB ADD ADC SBC RSC TST TEQ CMP CMN ORR MOV BIC MVN Meaning Logical AND Logical Exclusive OR Subtract Reverse subtract Add Add with carry Subract with carry Reverse Subract with carry Test Test Equivalence Compare Commom Logical OR Move Bit clear Move Not Action Rd = Rn AND shifter_operand Rd = Rn EOR shifter_operand Rd = Rn - shifter_operand Rd = shifter_operand - Rn Rd = Rn + shifter_operand Rd = Rn + shifter_operand + Carry Rd = Rn shifter_operand NOT(Carry) Rd = shifter_operand - Rn NOT(Carry) Update flags after Rn AND shifer_opernad Update flags after Rn EOR shifer_opernad Update flags after Rn - shifer_opernad Update flags after Rn + shifer_opernad Rd = Rn OR shifter_operand Rd = shifter_operand Rd = Rn AND NOT(shifter_operand) Rd = NOT(shifter_operand) 임베디드시스템교육센터

137 ARM Instruction - Load/Store cond 0 1 I P U B W L Rn Rd Offset_mode 1 Source or Destination Base Register Load/Store Write-back(Auto-index) Unsigned byte/word Up/Down Pre-/Post-index bit immediate 0 Offset register Shift type Immediate shift length #shift sh 0 Rm 임베디드시스템교육센터

138 ARM Instruction - Load/Store Multiple Stack Implementation Ascending Stack Full Ascending (FA) Stack Empty Ascending (EA) Stack SP N+3 N+2 N+1 N SP N+3 N+2 N+1 N Descending Stack Full Descending (FD) Stack Empty Descending (ED) Stack SP N+3 N+2 N+1 N SP N+3 N+2 N+1 N 임베디드시스템교육센터

139 ARM Instruction - Branch Branch / Branch with Link Instruction (B, BL) cond L Signed_immed_24 1: LR PC+4, PC target_addr Branch and exchange Instruction (BX) cond SBO SBO SBO Rm 임베디드시스템교육센터

140 ARM Instruction - Status Register Access MRS (Move PSR to Registers) cond R 0 0 SBO Rd SBZ SPSR/CPSR Destination MSR (Move Register to PSR) cond 0 1 I 1 0 R 1 0 field_mask SB0 Operand f/s/x/c 1 Immediate align (ROR 2x#ror) 11 #rot bit immediate 0 Operand register 11 SBZ 4 3 Rm 임베디드시스템교육센터

141 ARM Instruction - Exception-generating Software Interrupt (SWI) cond SBO Immed_24 Ignored by ARM processor R14_svc Address of SWI instruction + 4 SPSR_svc CPSR[4:0] CPSR Supervisor mode CPSR[7:5] I = 1, F = unchanged, T = 0 PC To return 0x MOVS PC, R 임베디드시스템교육센터

142 ARM Instruction - Coprocessor Co-processor Data Operation Coprocessor Data Operation (CDP) cond Op_1 CRn CRd CP# Op_2 0 CRm Operation 1 First operand CR Destination CR Coprocessor Number Operation 2 Second operand CR Coprocessor Load/Store Operation cond P U N W L Rn CRd CP# Offset_8 Source or Destination Base Register Load/Store Write-back(Auto-index) Data size (Coprocessor dependent) Up/Down Pre-/Post-index 임베디드시스템교육센터

143 ARM Instruction - Thumb 16-bit Re-encoded Subset of the ARM Instruction Set Use Advantages of 32-bit Architecture with Restriction Example: ADD Rd, #immediate Rd 8-bit immediate Major op-code: Move/compare/add/sub With immediate value Immediate value Thumb Code Always Condition Code Minor op-code: ADD Destination and Source Register ARM Code Rd 0 Rd bit immediate 임베디드시스템교육센터

144 ARM Instruction - Thumb State Registers User & System FIQ IRQ Supervisor Abort Undef R0 R1 R2 R3 R4 R5 R6 R7 SP LR R0 R1 R2 R3 R4 R5 R6 R7 SP_fiq LR_fiq R0 R1 R2 R3 R4 R5 R6 R7 SP_irq LR_irq R0 R1 R2 R3 R4 R5 R6 R7 SP_svc LR_svc R0 R1 R2 R3 R4 R5 R6 R7 SP_abt LR_abt R0 R1 R2 R3 R4 R5 R6 R7 SP_und LR_und PC PC Program Counter PC PC PC PC CPSR CPSR SPSR_fiq Program Status Register CPSR CPSR SPSR_irq SPSR_svc CPSR SPSR_abt CPSR SPSR_fiq 임베디드시스템교육센터

145 ARM Instruction - Mapping Registers Thumb State R0~R7 Access via Special instruction Stack Pointer (SP) Link Register (LP) Program Counter (PC) CPSR SPSR ARM State R0~R7 R8~R12 Stack Pointer (R13) Link Register (R14) Program Counter (R15) CPSR SPSR 임베디드시스템교육센터

146 MMU - Memory Hierarchy Fast and Expensive Registers Cache Main Memory Secondary Storage (Disk) Off-line Storage Performance Cost/bits Locality Principle Program access a relatively small portion of the address space at any instant of time. Temporal Locality Programs tends to use recent information Spatial Locality Memory location referenced recently is more likely to be referenced than farther memory location Slow and Inexpensive 임베디드시스템교육센터

147 MMU - Memory Terminology Block: minimum unit of data Hit, Miss Hit Ratio: the fraction of memory access found in the upper level Miss Ratio = 1 - (Hit Ratio) Hit Time << Miss Penalty To Processor From Processor Upper Level Memory Blk X Lower Level Memory Blk Y 임베디드시스템교육센터

148 MMU - Memory Management Functions Dynamic memory allocation Virtual memory implementation and Virtual address space Virtual-to-Physical address translation Memory protection and Task security Virtual Memory MPU Virtual Address MMU Physical Address Physical Memory Disk Physical Address Virtual Address 임베디드시스템교육센터

149 MMU - ARM920T MMU 1MB(section), 64KB(large pages), 4KB(small pages), 1KB(tiny pages) Access permissions for sections Subpage access permissions for large and small pages 16 domains implemented in hardware 64 entry I TLB and 64 entry D TLB Hardware page table walks RR replacement algorithm Invalidate whole TLB or TLB entry Independent lockdown of ITLB and DTLB 임베디드시스템교육센터

150 MMU - Paging Organization Virtual and physical address space partitioned into blocks of equal size Page transferring is expensive due to Disk Access Virtual/Physical Address Space Example 31 Virtual Address Virtual Page Number Page Offset 0 Translation Physical Page Number Page Offset 0 Physical Address 임베디드시스템교육센터

151 MMU - Microprocessor Cache Cache Improve Overall System Performance Reducing read and write cycle time by using fast memory Improving memory bus utilization MPU address Data(hit) Cache Cache Cache Controller miss Memory bus address MEMORY update data Memory data 임베디드시스템교육센터

152 MMU - ARM920T Memory System I$ IVA C13 IMVA IMMU IPA ARM9TDMI DVA C13 ID DD DMVA DMMU DPA Write buffer AMBA Interface D$ PA TAG RAM 임베디드시스템교육센터

153 MMU - Cached MMU Memory System Access control hardware AP Domain TLB Translation table work hardware Abort C,B Bits PA Main Memory ARM VA Cache And Write buffer Cache line fetch hardware 임베디드시스템교육센터

154 MMU - Cache and Write Buffer Cache s Feature Separate 16KB instruction and 16KB data caches Virtually-addressed 64-way associative cache 8-word line with 1 valid bit and 2 dirty bit per line for halfline write-back Write-through and write-back by C and B Pseudo-random or round-robin replacement Independently lockable PA TAG RAM for TLB miss during write-back and interrupt latency Efficient cleaning of caches Write Buffer s Feature 16-word data buffer 4-address address buffer Can be drained under software control 임베디드시스템교육센터

155 System Initialization 임베디드시스템교육센터

156 임베디드시스템교육센터

157 Initialization Code Initialization Flow Flow Functions Clock & Power Initialization Memory System Initialization Setup Exception Handling I/O Device Initialization Run Environment Setup Exception Vector Initialization Disable Watch Dog Timer Disable Interrupt Clock Configuration Memory Bank Initialization Stack Initialization Setup Exception Handler Initialization RW/ZI Data Area Jump to Main 임베디드시스템교육센터

158 Exception Vector Table AREA Init, CODE, READONLY ENTRY b ResetHandler b HandlerUndef b HandlerSWI b HandlerPabort b HandlerDabort b. b HandlerIRQ b HandlerFIQ ;handler for Undefined mode ;handler for SWI interrupt ;handler for PAbort ;handler for DAbort ;reserved ;handler for IRQ interrupt ;handler for FIQ interrupt HandlerSWI 0x C 0x x x B HandlerPabort B HandlerSWI B HandlerUndef B ResetHandler HandlerUndef ResetHandler 임베디드시스템교육센터

159 Initialization for Reset(1/2) ResetHandler ldr r0,=wtcon ;watch dog disable ldr r1,=0x0 str r1,[r0] ldr ldr str r0,=intmsk r1,=0xffffffff ;all interrupt disable r1,[r0] ;To reduce PLL lock time, adjust the LOCKTIME ldr r0,=locktime ldr r1,=0xffffff str r1,[r0] ; Configure MPLL ldr r0, =MPLLCON ldr r1,=((m_mdiv<<12)+(m_pdiv<<4)+m_sdiv) str r1,[r0] Watch dog timer disable 0x x All interrupts disable 0xffffffff 0x4a Setting PLL Lock Time 0x4c x00ffffff t_lock_m = 4K/12M = 333 us t_lock_u = 333 us Setting MPLL Fout 0x0005c042 0x4c Mpll = (m*fin)/(p*2^s), m = MDIV+8, p = PDIV+2, s = SDIV 임베디드시스템교육센터

160 Initialization for Reset(2/2) ;Watchdog timer WTCON EQU 0x ;Interrupt control register INTMSK EQU 0x4a ;Clock Controller LOCKTIME EQU 0x4c MPLLCON EQU 0x4c ; Fin = 12MHz, Fout = 50MHz M_MDIV EQU 0x5c M_PDIV EQU 0x4 M_SDIV EQU 0x2 ;Watchdog timer BWSCON EQU 0x SMRDATA DATA ;BUSWIDTH=32 DCD 0x ;BWSCON DCD 0x20 ;MRSR 임베디드시스템교육센터

161 Memory Bank Initialization ;Set memory control registers ldr r0, =SMRDATA ldr r1, =BWSCON ;BWSCON Address add r2, r0, #52 ;End address of SMRDATA 0 ldr r3, [r0], #4 str r3, [r1], #4 cmp r2, r0 bne %B0 Set memory control registers SMRDATA 0x x x BANKCON0 BANKCON1 SDRAM config. 0x10 0x20 0x20 Memory REFRESH BANKSIZE MRSR6 MRSR7 BANK6/7 SIZE 32M/32M 0x10 0x20 latency: 2clks 0x20 Special Register 임베디드시스템교육센터

162 Stack Initialization bl InitStacks ;Initialize stacks InitStacks mrs r0, cpsr bic r0, r0, #MODEMASK ; Undefined mode & Interrupt disable orr r1, r0, #UNDEFMODE NOINT msr cpsr, r1 ; UndefMode ldr sp, =UndefStack orr r1, r0, #ABORTMODE NOINT msr cpsr, r1 ; AbortMode ldr sp, =AbortStack ;IRQMode ;FIQMode orr r1, r0, #SVCMODE msr cpsr, r1 ;SVCMode ldr sp, =SVCStack mov pc, lr ; return LTORG ; Literal Pool Origin SVC mode Undef mode Abort mode IRQ mode FIQ mode SVC mode R13_und = 0x33ff7400 R13_abt = 0x33ff7800 R13_irq = 0x33ff7c00 R13_fiq = 0x33ff8000 R13_svc = 0x33ff 임베디드시스템교육센터

163 Setup Handler ; Setup IRQ handler ldr r0, =HandleIRQ ldr r1, =IsrIRQ ; M[HandleIRQ] IsrIRQ str r1, [r0] ; Setup FIQ handler ; Setup Undefined Handler ; Setup SWI handler ; Setup DABORT handler ; Setup PABORT handler HandlerIRQ HANDLER HandleIRQ /* HandlerIRQ sub sp, sp, #4 ;to store IsrIRQ stmfd sp!, {r0} ;Save r0 ldr r0, =HandleIRQ ldr r0,[r0] ; r0 IsrIRQ str r0, [sp,#4] ;store IsrIRQ ldmfd sp!, {r0,pc} ;jump to */ IsrIRQ sub sp, sp, #4 ;to store handler stmfd sp!,{r8-r9} ;save r8-r9 ldr r9, =INTOFFSET ; which INT? ldr r9, [r9] ; r9 INT number ldr r8, =HandleEINT0 ; r8 HandleEINT0 add r8, r8, r9, lsl #2 ; Handler address ldr r8,[r8] ; r8 Handler str r8,[sp,#8] ; store Handler addr ldmfd sp!,{r8-r9,pc} ; jump to Handler HandleReset HandleUndef HandleSWI HandlePabort HandleDabort HandleReserve HandleIRQ HandleFIQ HandleEINT0 HandleEINT1 HandleTimer0 HandleRTC IsrIRQ Timer0ISR 0x33FFFF00 0x33FFFF04 0x33FFFFFC 임베디드시스템교육센터

164 RW/ZI Data Initialization ;Copy and paste RW data/zero initialized data ldr r0, = Image$$RO$$Limit ; RO limit ldr r1, = Image$$RW$$Base ; RW limit ldr r3, = Image$$ZI$$Base ; ZI base cmp r0, r1 ; Check that they are different beq %F2 ; if RO_limit = RW_base goto 2 1 cmp r1, r3 ; Copy RW data upto ZI_limit ldrcc r2, [r0], #4 ; if r1 < r3 strcc r2, [r1], #4 bcc %B1 2 ldr r1, = Image$$ZI$$Limit ; Top of zero init segment mov r2, #0 3 cmp r3, r1 strcc r2, [r3], #4 ; Zero Initialize if r3<r1 bcc %B3 bl Main ;jump to Main Load View ZI_LIMIT ZI_BASE RW RO (1) RO_LIMIT = RW_BASE Zero-Initialized Region ZI_BASE RW_BASE RO_BASE 0x ZI RW RO ZI_LIMIT RO_LIMIT Zero-Initialized Region ZI_BASE RW_BASE RO_BASE 0x (2) RO_LIMIT!= RW_BASE ZI RW RO ZI_LIMIT RO_LIMIT 임베디드시스템교육센터

165 Porting uc/os-ii on ARM 임베디드시스템교육센터

166 임베디드시스템교육센터

167 uc/os-ii Requirements uc/os-ii Requirements 해당 Processor 의 C compiler 가존재하는가? 해당 Processor가일정주기의 Tick을생성할수있는가? Interrupt가 C에서허가 / 금지가가능한가? 충분한양의데이터를유지할수있는가? 해당 Processor가 Stack 관련연산과 CPU Register를 Stack에저장할수있는가? ARM-9 satisfies all requirements 임베디드시스템교육센터

168 uc/os-ii HW/SW Architecture. uc/os-ii uc/os-ii Processor Processor Independent Code Independent Code OS_CORE.C OS_CORE.C OS_MBOX.C OS_MBOX.C OS_MEM.C OS_MEM.C OS_Q.C OS_Q.C OS_SEM.C OS_SEM.C OS_TASK.C OS_TASK.C OS_TIME.C OS_TIME.C ucos_ii.c ucos_ii.c ucos_ii.h ucos_ii.h Application Software Application Software uc/os-ii Config. uc/os-ii Config. Application Application Specific Code Specific Code OS_CFG.H OS_CFG.H INCLUDES.H INCLUDES.H uc/os-ii uc/os-ii Processor/Compiler Specific Code Processor/Compiler Specific Code OS_CPU.H OS_CPU.H OS_CPU_A.ASM OS_CPU_A.ASM OS_CPU_C.C OS_CPU_C.C uc/os-ii Architecture Application Software Processor-Independent Code Application-Specific Code Processor/Compiler Specific Code CPU CPU 임베디드시스템교육센터

169 RTOS Application Program Structure 전체프로젝트폴더 SDMK2410 Startup, 기본드라이버코드폴더 APIs 드라이버를기반으로한시스템운영 API 코드폴더 ucos_ii RTOS 코드와 Porting 코드폴더 주실험프로그램 : xx_main.c, ARM Project 프로그램 : xx_main.apj (SDT compiler 기준 ) 임베디드시스템교육센터

170 Port Summary (Data Types, Macro) Data Types Name INT8U INT8S INT16U INT16S INT32U INT32S OS_STK Type unsigned 1-byte signed 1-byte unsigned 2-byte signed 2-byte unsigned 4-byte signed 4-byte Processor-specific Macro OS_CPU_SR Processor-specific OS_ENTER_CRITICAL() OS_EXIT_CRITICAL() OS_STK_GROWTH 임베디드시스템교육센터

171 Port Summary (Function) Functions OSStartHighRdy() OSCtxSw() OSIntCtxSw() OSTickISR() OSTaskStkInit() User Hook Function OSInitHookBegin(), OSInitHookEnd() OSTaskCreateHook(), OSTaskDelHook(), OSTaskSwHook(), OSTaskStatHook() OSTCBInitHook(), OSTimeTickHook(), OSTaskIdleHook() 임베디드시스템교육센터

172 OS_CPU.H (Data Types) Definition integer data types. Processor마다 integer types의크기가다름 (16bit CPU) unsigned int = 16-bit unsigned data. typedef unsigned int INT16U ARM9 (32bit CPU) unsigned int = 32-bit unsigned data. typedef unsigned int INT32U OS_STK : 해당 CPU 의 Stack 의단위크기정의. ARM9 typedef unsigned int OS_STK 임베디드시스템교육센터

173 OS_CPU.H (Critical Section) Critical Section Kernel 은특정영역에서 Interrupt 발생을금지할수있어야함. OS_CRITICAL_ENTER mrs r0,cpsr; // PSR 을 R0 에읽음. stmfd sp!,{r0}; // PSR 을스택에저장. orr r0,r0,#noint; // Disable IRQ msr CPSR_c,r0; OS_CRITICAL_EXIT ldmfd sp!,{r0}; // 스택에저장했던 PSR을읽음. msr CPSR_c,r0; // Restore PSR 임베디드시스템교육센터

174 OS_CPU.H (Stack Growth) OS_STK_GROWTH 사용 Processor 의 Stack 의방향결정. ARM9 어느방향으로든가능하며, 컴파일러에의존적. SDT 및 ADS에서는 LDMFD/STMFD 명령을사용. LDMFD(Post-Increment Load) STMFD(Pre-Decrement Store) 따라서 High to low의방향을가짐. #define OS_STK_GROWTH 1 // High to low 임베디드시스템교육센터

175 OS_CPU_C.C Should write 10 simple C functions. OSTaskStkInit() OSTaskCreateHook() OSTaskDelHook() OSTaskSwHook() OSTaskIdleHook() OSTaskStatHook() OSTimeTickHook() OSInitHookBegin(), OSInitHookEnd() OSTCBInitHook The only required function is OSTaskStkInit(). The other nine functions must be declared, but do not need to contain any code 임베디드시스템교육센터

176 OS_CPU_C.C (OSTaskStkInit()) R14 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 CPSR SPSR High Low Task Context R13(SP) 는따로저장하기때문에저장하지않음. Nested Interrupt를위하여 SPSR을저장. LDMFD/STMFD 명령에적합하도록생성 임베디드시스템교육센터

177 OS_CPU_C.C (OSTaskStkInit()) OSTaskStkInit() 목적 : Task 의스택을 Context Switching Out 된상태인것처럼스택을초기화. Pseudo-code for OSTaskStkInit() OS_STK OSTaskStkInit( void (*task)(void *pd), void *pdata, OS_STK *ptos, INT16U opt) { Setup stack frame to contain desired initial values of all regs. Return new top-of-stack pointer to caller. } 임베디드시스템교육센터

178 OS_CPU_C.C (OSTaskStkInit()) OSTaskStkInit() for ARM9 OS_STK *OSTaskStkInit* (void (*task)(void *pd), void *pdata* pdata,, OS_STK *ptos* ptos,, INT16U opt) { OS_STK *stk* stk; opt = opt; /* 'opt' is not used, prevent warning */ stk = ptos; /* Load stack pointer */ *(stk stk) ) = (OS_STK)task; /* Entry Point */ *(-- --stk)) = (INT32U)0; /* lr */ *(-- --stk)) = (INT32U)0; /* r12 */ *(-- --stk)) = (INT32U)0; /* r11 */ *(-- --stk)) = (INT32U)0; /* r10 */ *(-- --stk)) = (INT32U)0; /* r9 */ *(-- --stk)) = (INT32U)0; /* r8 */ *(-- --stk)) = (INT32U)0; /* r7 */ *(-- --stk)) = (INT32U)0; /* r6 */ *(-- --stk)) = (INT32U)0; /* r5 */ *(-- --stk)) = (INT32U)0; /* r4 */ *(-- --stk)) = (INT32U)0; /* r3 */ *(-- --stk)) = (INT32U)0; /* r2 */ *(-- --stk)) = (INT32U)0; /* r1 */ *(-- --stk)) = (INT32U)pdata; /* r0 : argument */ *(-- --stk)) = (INT32U)(SVCMODE 0x0); /* CPSR */ *(-- --stk)) = (INT32U)(SVCMODE 0x0); /* SPSR */ return (stk( stk); } 임베디드시스템교육센터

179 OS_CPU_C.C (OSxxxHook()) OSxxxHook() Function Called by other internal function. Hook functions and caller functions. Function Name OSTaskCreateHook() OSTaskDelHook() OSTaskSwHook() OSTaskStatHook() OSTimeTickHook() OSTCBInitHook() OSTaskIdleHook() OSInitHookBegin() OSInitHookEnd() Called By OS_TCBInit(). OSTaskDel(). OSCtxSw(), OSIntCtxSw(). OSTaskStat(). OSTimeTick(). OS_TCBInit(). OS_TaskIdle(). On Entering OSInit(). On Leaving OSInit() 임베디드시스템교육센터

180 OS_CPU_A.ASM 어셈블러로만작성될수있는코드유지. 다음 4 가지함수를유지. OSStartHighRdy() 최우선순위의 Task 를실행하는함수. OSCtxSw() 세마포어 Post같은 Task의요청에의한 Context Switching 함수. OSIntCtxSw() Interrupt가발생하여 Context Switching시호출되는함수. OSTickISR() OS 가사용하는 Tick 을위한 ISR 임베디드시스템교육센터

181 OS_CPU_A.ASM (OSStartHighRdy()) OSStartHighRdy() 목적 : 최우선순위 Task 를실행하는함수. Pseudo-Code for OSStartHighRdy() void OSStartHighRdy (void) { Call OSTaskSwHook(); OSRunning = TRUE; // Get the stack pointer of the task to resume; StackPointer = OSTCBHighRdy->OSTCBStkPtr OSTCBStkPtr; } Restore all CPU registers from the new task s s stack; Return to new task 임베디드시스템교육센터

182 OS_CPU_A.ASM (OSStartHighRdy()) OSStartHighRdy() for ARM9 OSStartHighRdy BL OSTaskSwHook ; Call user defined task switch hook LDR r4,=osrunning ; Indicate that multitasking has started MOV r5,#1 ; OSRunning = 1 STRB r5,[r4] LDR r4,=ostcbhighrdy ; Get highest priority task TCB address LDR r4,[r4] ; r4 <= OSTCBHighRdy->OSTCBStkPtr OSTCBStkPtr LDR sp,[r4] ; SP <= OSTCBHighRdy->OSTCBStkPtr OSTCBStkPtr LDMFD sp!,{r4} ; pop new task's spsr MSR SPSR_cxsf,r4 LDMFD sp!,{r4} ; pop new task's psr MSR CPSR_cxsf,r4 LDMFD sp!,{r0-r12,lr,pc} r12,lr,pc} ; pop new task's r0-r12,lr r12,lr & pc 임베디드시스템교육센터

183 OS_CPU_A.ASM (OSCtxSw()) OSCtxSw() 목적 : Task 의요청에의한 Context Switching 을수행하는함수. Pseudo-Code for OSCtxSw() void OSCtxSw(void) { Save CPU registers. //Save the current task s s SP into the current task s s OS_TCB OSTCBCur->OSTCBStkPtr OSTCBStkPtr = SP; OSTaskSwHook(); OSTCBCur = OSTCBHighRdy; OSPrioCur = OSPrioHighRdy; // Get the stack pointer of the task to resume. SP = OSTCBHighRdy->OSTCBStkPtr OSTCBStkPtr; } Restore all CPU registers from the new task s s stack. Return to new task 임베디드시스템교육센터

184 OS_CPU_A.ASM (OSCtxSw()) OSCtxSw() for ARM9 OSCtxSw STMFD sp!,{lr} ; PUSH PC STMFD sp!,{r0-r12,lr} ; PUSH all CPU register and LR MRS r4,cpsr STMFD sp!,{r4} ; PUSH CPSR MRS r4,spsr STMFD sp!,{r4} ; PUSH SPSR LDR r4,=ospriocur ; OSPrioCur = OSPrioHighRdy LDR r5,=ospriohighrdy LDRB r6,[r5] STRB r6,[r4] LDR r4,=ostcbcur ; Get current task TCB address LDR r5,[r4] STR sp,[r5] ; Store sp in preempted tasks's TCB BL OSTaskSwHook ; call Task Switch Hook LDR r6,=ostcbhighrdy LDR r6,[r6] LDR sp,[r6] ; get new task's stack pointer STR r6,[r4] ; set new current task TCB address LDMFD sp!,{r4} ; pop new task's spsr MSR SPSR_cxsf,r4 LDMFD sp!,{r4} ; pop new task's psr MSR CPSR_cxsf,r4 LDMFD sp!,{r0-r12,lr,pc} ; pop new task's r0-r12,lr & pc 임베디드시스템교육센터

185 OS_CPU_A.ASM (OSIntCtxSw()) Interrupt 가발생하여, Task Switching 이발생하는경우 임베디드시스템교육센터

186 OS_CPU_A.ASM (OSIntCtxSw()) Pseudo-Code for OSIntCtxSw() A lot of the code is identical to OSCtxSw() except Need not save the CPU registers (already done by ISR) Should adjust stack pointer. void OSIntCtxSw(void) { Adjust the stack pointer to remove calls to OSIntExit(), OSIntCtxSw(); //Save the current task s s stack pointer in the current task s s OS_TCB. OSTCBCur->OSTCBStkPtr OSTCBStkPtr = StackPointer; OSTaskSwHook(); OSTCBCur = OSTCBHighRdy; OSPrioCur = OSPrioHighRdy; } //Get the stack pointer of the task to resume StackPointer = OSTCBCur->OSTCBStkPtr OSTCBStkPtr; Restore all processor registers from the new task s s stack. Execute a return from interrupt instruction 임베디드시스템교육센터

187 OS_CPU_A.ASM (OSIntCtxSw()) OSIntCtxSw() for ARM9 OSIntCtxSw() 는 Flag 만세트. OSIntCtxSw LDR r0,=osintctxswflag MOV r1,#1 STR r1,[r0] MOV pc,lr ; OSIntCtxSwFlag = True ISR 에서위의 Flag 를체크하여 Context Switching 실행. UCOS_IRQHandler STMFD sp!,{r0-r3,r12,lr} ; 아래의함수에서사용되는 Register 저장. ;APCS에따라, r0-r3만을저장함. BL OSIntEnter ; ISR에진입하였음을설정 BL C_IRQHandler ; ISR Handler BL OSIntExit ; ISR을빠져나오면서, Task Switching 처리 LDR r0,=osintctxswflag ; Task Switching이일어나야하는가? LDR r1,[r0] CMP r1,#1 BEQ _IntCtxSw ; Task Switching이필요하면 _IntCtxSw로. LDMFD sp!,{r0-r3,r12,lr} SUBS pc,lr,#4 ; 아니면, 그냥 Return 임베디드시스템교육센터

188 OS_CPU_A.ASM (OSIntCtxSw()) _IntCtxSw _IntCtxSw MOV r1,#0 ; OSIntCtxFlag = 0 STR r1,[r0] LDMFD sp!,{r0-r3,r12,lr} ; ISR이저장한Stack 내용 POP. STMFD sp!,{r0-r3} ; 도중사용을위해 IRQ 스택에 r0-r3만저장. MOV r1,sp ; adjust SP_irq ADD sp,sp,#16 SUB r2,lr,#4 MRS r3,spsr ; 현재 Task의 PSR에 NOINT로설정하여, ORR r0,r3,#noint MSR spsr_c,r0 ; 이를 SPSR에넣고, LDR r0,=.+8 MOVS pc,r0 ; 원래 Mode로진입함. STMFD sp!,{r2} ; PUSH current task s PC STMFD sp!,{r4-r12,lr} ; PUSH current task's r4-r12,lr MOV r4,r1 ; r4 = SP_irq MOV r5,r3 ; r5 = SPSR_irq (PSR of current task) LDMFD r4!,{r0-r3} ; IRQ 스택에저장한 r0-r3 POP. STMFD sp!,{r0-r3} ; PUSH current task s r0-r3. STMFD sp!,{r5} ; PUSH current task s CPSR. MRS r4,spsr STMFD sp!,{r4} ; PUSH current task s SPSR. LDR r4,=ostcbcur ; Get current task TCB address LDR r5,[r4] ; 현재 Task의스택포인터저장. STR sp,[r5] ; OSTCBCur->OSTCBStkPtr = SP 임베디드시스템교육센터

189 OS_CPU_A.ASM (OSIntCtxSw()) _IntCtxSw (continued) BL OSTaskSwHook ; call Task Switch Hook LDR LDR LDRB STRB r4,=ospriocur r5,=ospriohighrdy r5,[r5] r5,[r4] ; OSPrioCur = OSPrioHighRdy LDR r6,=ostcbhighrdy LDR r6,[r6] ; get new task's stack pointer LDR sp,[r6] ; StackPointer = OSTCBCur->OSTCBStkPtr OSTCBStkPtr; STR r6,[r4] ; OSTCBCur = OSTCBHighRdy LDMFD sp!,{r4} MSR SPSR_cxsf,r4 LDMFD sp!,{r4} MSR CPSR_cxsf,r4 ; pop new task's spsr ; pop new task's psr LDMFD sp!,{r0-r12,lr,pc} r12,lr,pc} ; pop new task's r0-r12,lr r12,lr & pc 새로운 Task 로스위칭. (OSCtxSw() 와동일 ) 임베디드시스템교육센터

190 ucos Multi-task Program(1/3) void Main(void) { System_Init(); } OSInit(); OSTaskCreate(TaskStart, (void *)0, (void *)&TaskStartStk[TASK_STK_SIZE - 1], 0); OSStart(); 임베디드시스템교육센터

191 ucos Multi-task Program(2/3) void TaskStart (void *data) { data = data; Timer0_Start(); OSTaskCreate(Task1, (void *)0, (void *)&TaskStk[1][TASK_STK_SIZE - 1], 2); OSTaskCreate(Task2, (void *)0, (void *)&TaskStk[2][TASK_STK_SIZE - 1], 3); } while(1) { Uart_Printf( a task"); } OSTimeDlyHMSM(0, 0, 1, 0); 임베디드시스템교육센터

192 ucos Multi-task Program(3/3) void Task1(void *data) { while(1) { Led_Display(1); OSTimeDlyHMSM(0, 0, 0, 200); Led_Display(2); OSTimeDlyHMSM(0, 0, 0, 200); } } void Task2(void *data) { while(1) { Uart_Printf(" r ntest r n r n"); OSTimeDlyHMSM(0, 0, 0, 500); } } 임베디드시스템교육센터

193 Application Program Test 1. UART Programming 임베디드시스템교육센터

194 임베디드시스템교육센터

195 UART Universal Asynchronous Receiver and Transmitter 3 개의 interrupt 혹은 DMA 기반의 UART 최고 bps 지원 ( 그이상지원을위해외부클럭필요 ) Two 16 bytes FIFOs, infra-red(ir) Tx/Rx support 임베디드시스템교육센터

196 UART Operations Data transmission Start bit, 5~8 data bits, parity bit(option), 1 ~ 2 stop bits Break condition: 0 state for 1 frame transmission time Data reception Start bit, 5~8 data bits, parity bit(option), 1 ~ 2 stop bits Set error flags Overrun error: when received data has overwritten Parity error: unexpected parity condition Frame error: No valid stop bit Break condition Receive time-out condition 임베디드시스템교육센터

197 UART Operations Interrupt Request Generation Type Rx interrupt FIFO mode 1. RFIFO reaches trigger level 2. RFIFO does not reaches trigger level and no data during 3 word time Non-FIFO mode receive data becomes full Tx interrupt Error interrupt TFIFO reaches trigger level Frame error, Parity error, break signal Overrun when RFIFO is full Baud-Rate Generation Transmit data becomes empty All errors Baud rate divisor UBRDIV = (int)(pclk UCLK/(bps*16))-1 PCLK: UART reference clock Baud rate: 110, 1200, 2400, 9600, 14400, 19200, 38400, 57600, 76800, Ex) baud-rate: bps, PCLK = 40MHz UBRDIVn = (int)( /(115200x16))-1 = (int)(21.7)-1 = 임베디드시스템교육센터

198 UART Registers(1/4) ULCON: UART Line Control Register (0x00) I Parity Mode S Word Len Infra-Red Mode 0: Normal mode, 1: IR mode Parity Mode 0xx: No parity, 100: Odd, 101: Even, 110: parity forced as 1 111: parity forced as 0 UCON: UART Control Register (0x00) 10 CS 9 TIT RIT RTO REI LB SB T Mode R Mode Send break Loop back mode Rx error state interrupt Rx time out enable Rx interrupt type 0: pulse, 1: level Tx interrupt type 0: pulse, 1: level Clock Selection 0: PCLK, 1: UCLK Data bit size 00: 5, 01: 6, 10: 7, 11: 8 Stop bit size 0: 1, 1: 2 For tramsmit/receive buffer register 00: diable, 01: interrupt request or polling 10: DMA0 request for UART0 DMA3 request for UART2 11: DMA1 request for UART 임베디드시스템교육센터

199 UART Registers(2/4) UFCON: UART FIFO Control Register (0x00) TFIFO Trigger Level 00: empty, 01:4B, 10: 8B, 11: 12B 7 6 TFTL RFTL 0 TFR RFR FE RFIFO Trigger Level 00:4B, 01: 8B, 10: 12B, 11: 16B UMCON: UART Modem Control Register (0x00) AFC RTS Auto Flow Control 0: disable 1: enable FIFO Enable RFIFO Reset TFIFO Reset UBRDIV: UART Baud Rate division Register (0x0000) Request to Send 0: inactivate nrts 1: activate nrts When AFC is disabled 15 > 임베디드시스템교육센터

200 UART Registers(3/4) UTRSTAT: UART Tx/Rx Status Register (0x6) 2 1 TE TBE 0 RBR Receive buffer data ready for Non-FIFO Transmit buffer empty for Non-FIFO Transmitter empty 1: Transmit buffer & shifter register empty UERSTAT: UART Error Status Register (0x00) 3 BD 2 1 FE PE 0 OE Overrun error Parity error Frame error Break Detect UTXH: UART Transmit Buffer Register (0x00) URXH: UART Receive Buffer Register (0x00) 임베디드시스템교육센터

201 UART Registers(4/4) UFSTAT: UART FIFO Status Register (0x00) 9 TFF 8 RFF Tx FIFO Count Rx FIFO Count Number of data in Rx FIFO Number of data in Tx FIFO Rx FIFO Full 0: not full, 1: full Tx FIFO Full 0: not full, 1: full 임베디드시스템교육센터

202 Application Program 전체프로젝트폴더 SDMK2410 Startup : 2410init.s, 2410addr.a, Memcfg.a, Option.a Ex. Driver : 2410addr.h, uart.c, uart.h, ioport.c, ioport.h 주실험프로그램 : xx_main.c ARM Project 프로그램 : xx_main.apj (SDT compiler 기준 ) 임베디드시스템교육센터

203 Final Project Keyboard Driver LCD Driver Barbel Shop Problem 임베디드시스템교육센터

204 임베디드시스템교육센터

205 Keyboard Experiment 임베디드시스템교육센터

206 Keyboard encoder (Block Diagram) SPI Comm. Channel Interface to host CPU. Keyboard Scanner & State Control Scans 8x14 matrix Implements 3 modes Power Management Minimize power drain. Drain 20uA in the stop mode. System Monitor Input Signal Used to maintain state control. Programmable I/O General purpose I/O Can be used as a wake-up signal 임베디드시스템교육센터

207 Keyboard encoder (Operation) Keyboard Scanner 매 512us 마다, 1 개 column lines(c0-c13) 을선택하여 R0- R7 을읽으며, 눌려진키는 R0-R& 에서 Low 로나타난다. 모든 Column Lines 에대해검사하는것은약 9.2ms 가걸린다. Debounce 및 Ghost key 를제거한후, 해당키코드는 SPI Channel 의 Transmit Buffer 로저장된다. Keyboard Scanning N-Key Rollover 방식사용. 눌려진 Key 가발견되기만하면, 다른키가눌려진상태가있더라도 SPI Channel 을통하여 Host 로보내어짐. 눌려진 Key 가 release 될경우, 해당 break code 가 SPI Channel 을통하여 Host 로보내어짐 임베디드시스템교육센터

208 Keyboard encoder (State) Three modes of keyboard and switch operation Related to power States Send All Keys Normal state Send Wake-up Keys Only Entering when WUKO(Wake-Up Key Only) Signal is active. Transmit only keys programmed to be wake-up keys. Send No Keys Entering on critically low level of battery voltage 임베디드시스템교육센터

209 SPI Operation Procedure Initialization. Set a GPIO Control Reg. to function as SPI. SPI0 : GPECON, GPGCON SPI1 : GPGCON Set Baud Rate Prescaler Reg. (SPREn) Set SPICONn to configure properly the SPI module. SPI Master and Slave must use the same parameters. Parameters : CPOL(Clock Polarity), CPHA(Clock Phase) SPI Read/Write Operation. (1) Set nss(gpio) to low to activate the Slave. (2) checks REDY(SPSTAn) and write data to SPTDATn. (3) wait until REDY(SPSTAn) is set. (4) Set nss(gpio) to high to deactivate the Slave and read the d ata from SPRDATn 임베디드시스템교육센터

210 Interface to Keyboard. S3C2410 EINT1 ATN SPI1 MOSI MISO SCLK MOSI MISO UR5HCSPI-SA SCLK Interface to key coder GPB[6] nss Interrupt : EINT1 SPI Interface : SPI1 nss : GPB[6] Sequence (1) Key Stroke. (2) Interrupt to CPU. (using ATN-EINT1) (3) Start Read/Write Operation 임베디드시스템교육센터

211 Key Codes Key Codes Range from 1 to 0x73 Key Scan Code Scan Code = Column Number * 8 + Row Nu mber + 1 Break Code = Scan C ode 0x80 Key Calculation Column Number [Scan Code / 3] Row Number Scan Code % 임베디드시스템교육센터

212 Keyboard ISR Routine. KBD_ISR() { // SPI Read on TAGD bit diable. // Refer S3C2410X01 CLEAR_KBD_nSS(); // First, nss to Low. while(!(rspsta1&0x1)); // Check ready state rsptdat1=0xff; // Second, Dummay data to SPTDATn while(!(rspsta1&0x1)); // Check ready state SET_KBD_nSS(); // Third, nss to High. data = rsprdat1; // Then, Read the data. } if ( data & 0x80 ) { // Ignore released key code. ; } else { key = GET_SCAN_CODE(data); if ( key & 0x8000 ) { /* If Special Key... */ ; } else { PutKbdBuf( key ); } } 임베디드시스템교육센터

213 LCD Experiment 임베디드시스템교육센터

214 TFT LCD displays features Supports 1, 2, 4 or 8 bpp palettized color displays for TFT. Supports 16, 24non-palettized true-color displays for color TFT. Supports maximum 16M color TFT at 24-bit per pixel mode. Support multiple screen size 640*480, 320*240, 160*160 Maximum virtual screen size(16 bpp mode) : 2048*1024 LCDSADDR1/2 : LCDBASEU, LCDBASEL OFFSIZE PAGEWIDTH OFFSIZE LINEVAL+1 LCDBASEU Before scrolling... View Port (LCD panel size) LCDBASEL After scrolling 임베디드시스템교육센터

215 LCD Controller REGBANK 17 programmable registers set 256*16 palette memory LCDCDMA transfer the video data in frame memory to LCD driver can be displayed on the screen without CPU intervention VIDPRCS Receives the video data from LCDCDMA Send the video data through the VD[23:0] data port to the LCD driver after changing data format TIMEGEN Timing and rates Generates VFRAME, VLINE, VCLK, VM(STN) / VSYNC, HSYNC, VCLK, VDEN(TFT) System Bus REGBANK TIMEGEN LPC3600 VIDEO MUX LCDCDMA VIDRPCS VD[15:0] LPC3600 : LTS350A1-PD1 or LTS350Q1-PD 임베디드시스템교육센터

216 EXTERNAL INTERFACE SIGNAL(1/2) VFRAME / VSYNC Frame synchronous signal (STN) Vertical synchronous signal (TFT) VLINE / HSYNC Line synchronous pulse signal (STN) Horizontal synchronous signal (TFT) VCLK Pixel colock signal (STN / TFT) VD[23:0] LCD pixel data output ports (STN / TFT) VM / VDEN AC bias signal for the STN LCD driver (STN) Data enable signal (TFT) LEND Line end signal (TFT) LCD_PWREN LCD panel power enable control signal 임베디드시스템교육센터

217 EXTERNAL INTERFACE SIGNAL(2/2) 임베디드시스템교육센터

218 LCD PALETTE USAGE Palette supports 5:6:6(R:G:B) and 5:5:5:1(R:G:B:I) format #define PALETTE (0x4D000400) Read/Write Operation VSTATUS of LCDCON5 register must be checked 임베디드시스템교육센터

219 LCD Palette Usage(TFT) 1/3 8bpp(bit per pixel) Palette : 0x4D000050, 5:6:5=R:G:B static const unsigned short DEMO256pal[] ={0xf800, 0x07e0, 0x001f, 0xffff, }; static const unsigned char DEMO256[] ={0x01, 0x01, 0x02, 0x02, 0x01, 0x01,}; 256color * 16bit = 64K Color 8bit : 256 Color 16bpp 임베디드시스템교육센터

220 LCD Palette Usage(TFT) 2/3 24 bpp static const unsigned char DEMO256(16)[] ={0xf80000, 0x00f800, 0x0000f8,,}; static const unsigned char DEMO256(24)[] ={0xff0000, 00ff00, 0000ff,,}; 임베디드시스템교육센터

221 LCD Palette Usage(TFT) 3/3 for(i=starty; i<endy; i++) //y { for(j=0; j<240; j++)//x { framebuffer8bittft[(i)][(j)/4]= } } C ( framebuffer8bittft[(i)][j/4] & ~(0xff000000>>((j)%4)*8) ) ( ((int)temp[j+(i%53)*240])<<((4-1-((j)%4))*8) ); BIT CLEAR BIT MASK A & B B A C 임베디드시스템교육센터

222 Program Flow MMU_Init() Palette_Init() MMU_EnableICache() Lcd_Port_Init() Port_Init() Lcd_Init(MODE_TFT_8BIT) Isr_Init() Glib_Init(MODE_TFT_8BIT) Uart_Init(0,115200) Glib_ClearScr(0, MODE_TFT_8BIT) ( (void (*)(void)) (function[i][0]) )() Glib_Rectangle(0,0,239,319,255) Glib_Line(0,0,239,319,255) 임베디드시스템교육센터

223 Final Project 1 Job 1 : Display bumping ball to LCD Job 2 : Display text editor to LCD Job 3 : Display kernel statistics to console 임베디드시스템교육센터

224 임베디드시스템교육센터

225 Layout of LCD screen Text editor Hello This is text editor screen Bumping Ball 임베디드시스템교육센터

226 Final Project 2 Solving Barber Shop Problem 임베디드시스템교육센터

227 Barber Shop Modeling 무엇을모델링할것인가? Door Casher Sofas Barbers Customers Barber Chairs 임베디드시스템교육센터

228 Barber Shop Modeling 태스크로정의되어야하는오브젝트는? Customers, barbers, casher 리소스로정의되어야하는오브젝트는? Barber shop, Sofas, barber chairs, money, and receipt 태스크오브젝트와리소스오브젝트의관계는? Customers barber shop Customers sofas Customers barbers Barbers casher 임베디드시스템교육센터

229 Barber Shop Modeling( Job Slicing Example ) Customer enter the barber shop sit on one of the sofas sit on a barber chair let others sit on the sofa let a barber cut my hair stand up from the barber chair leave the barber chair pay exit shop Barber choose one who is the next cut hair Cashier accept pay 임베디드시스템교육센터

230 Display Example OutDoor : ABCDEFGHIJKLMNOPQRSTUVWXYZ InDoor : ABCDEFGHIJKLMNOPQRSTUVWXYZ Sofa : ABCDEFGHIJKLMNOPQRSTUVWXYZ Barber Chair: ABCDEFGHIJKLMNOPQRSTUVWXYZ Cashier : ABCDEFGHIJKLMNOPQRSTUVWXYZ OutDoor : YZ InDoor : STUVWX Sofa : PQR Barber Chair: MNO Cashier : L 임베디드시스템교육센터

231 Appendix Appendix01. ARM 개발환경 Appendix02. S3c2410 Appendix03. SMDK2410 Appendix04. BMP(bit map file format) Appendis05. WAVE PCM soundfile format 임베디드시스템교육센터

232 임베디드시스템교육센터

233 Appendix01. ARM 개발환경 ADS(ARM DEVELOPER SUITE ) 1.2 Openice 임베디드시스템교육센터

234 ADS Major Components Code Generation Tools ARM and Thumb ANSI C Compilers Embedded C++ Compilers Assemblers, Linker C and C++ runtime libraries CodeWarrior IDE Project manager Integrated build facilities Integrated editor GUI tool configuration Debuggers GUI (AXD) Command-line Debug Targets ARMulator, Instruction Set Simulator Angel debug monitor Multi-ICE JTAG ARM Firmware Suite Angel debug monitor MicroHAL ARM Applications Library Documentation Online hypertext based Hardcopy On-line help 임베디드시스템교육센터

235 ARM Firmware Suite (AFS) What s Firmware? Low level software that initializes a system s hardware Firmware Suite objectives and strategy Provide low level driver and support routines with standard API (uhal) Runs on bare metal or as part of a semi-hosted application Introduce a more modular approach Deliberately restricted in scope/features Application Processor specifics separated out RTOS Well partitioned board specific code C Libs Easily re-targeted to different platforms Angel Reusable, OS neutral MicroHAL Included in ADS Angel debug monitor Hardware platform MicroHAL 임베디드시스템교육센터

236 ARM Application Library What is the ARM Applications Library Highly optimized software suite of useful routines Handcrafted by ARM architecture experts Excellent examples of how to optimize for ARM Royalty free inclusion in application software Some of the functions in the Application Library DSP Transformations DCT, FFT DSP Filtering FIR, IIR & LMS Mathematics 임베디드시스템교육센터

237 OPENice32-A900 (JTAG Debug Tool) Support a variety of ARM cores ARM7TDMI,ARM720T,ARM9TDMI,ARM920T, ARM922T, ARM940T, ARM1020 including CDMA and Wireless Devices Non-Intrusive User Friendly GUI SMU setting High speed Downloading (USB/Ethernet)-190Kbps Flash Downloading & Debugging Support S/W and H/W Breakpoint Writing & Reading data to SFR On-Board Programming Support ARM SDT/ADS and Linux GDB Convenient and rapid firmware upgrade 임베디드시스템교육센터

238 Development Environment Serial Port Cable Debug Host OPENice32-A900 Serial Port Cable or USB/Ethernet Cable Target Board JTAG Cable 임베디드시스템교육센터

239 About Code Warrior for the ADS Metrowerks CodeWarior IDE version 4.0 ARM-specific configuration panels that enable you to Configure the ARM development tools Project Manager *.c source armcc C Compiler *.o armlink Linker *.axf Image Code run *.s armasm Assembler *.o *.b armlib Librarian 임베디드시스템교육센터

240 Software Development Process C 소스파일 어셈블리소스파일 컴파일러 어셈블러 라이브러리처리기 오브젝트파일 오브젝트파일 라이브러리 링커 형식변환기 실행파일 HEX 파일 매스크공정 에뮬레이터 시뮬레이터 다운로더 ROM Writer 시스템메모리 EPROM, 프로세서 ROM, 프로세서 하드웨어에뮬레이션 소프트웨어에뮬레이션 임베디드시스템교육센터

241 Project New Project Executable Image, Object Library, Makefile Importer Wizard Add Files to Project Current Build Target Release Debug DebugRel 임베디드시스템교육센터

242 Build Target Settings Target Settings ARM C Compiler Architecture or Processor Byte order Optimization Level Preprocessor ARM Linker LinkType RO base(0x ) RW base ARM from ELF Output format 임베디드시스템교육센터

243 Appendix02. S3c2410 Block Diagram and Features Memory Controller Timer UART Interrupt Controller I/O Ports 임베디드시스템교육센터

244 S3C2410 Applications Cellular Smartphones Printer S3C2410 RISC Microprocessor Palm PC GPS PDA / Organizers e-book Digital STB and NCs 임베디드시스템교육센터

245 S3C2410 Block Diagram ARM920T Instruction MMU InstructionC ACHE (16KB) External Coproc Interface JTAG ARM9TDMI Processor core (Internal Embedded ICE) AMBA Bus I/F Data MMU Data CACHE (16KB) WriteBack PA Tag RAM LCD CONT. LCD DMA USB Host CONT. ExtMaster NAND CONT. NAND Flash Boot Loader A H B B U S BUS CONT. Arbitor/Decode Interrupt CONT. Power Management Memory CONT. SRAM/NOR/SDRAM Clock Generator (MPLL/UPLL) Bridge & DMA(4Ch) UART 0, 1,2 I2C USB Device SDI/MMC Watchdog Timer BUS CONT. Arbitor/Decode SPI 0, 1 A P B B U S I2S GPIO RTC ADC Timer/PWM 0~3,4(internal) 임베디드시스템교육센터

246 S3C2410 Features(1/4) Integrated System for hand-held devices and general embedded applications ARM920T + IP (Intellectual Property) System Manager 8 banks each of which 128Mbyte 1Gbyte 6 memory banks for ROM, SRAM 2 memory banks for ROM, SRAM, SDRAM Programmable size and access cycles Clock & Power Manager Clock can be fed selectively to each block by software Normal, Slow, Idle, Stop, SL_IDLE mode 임베디드시스템교육센터

247 S3C2410 Features(2/4) Interrupt Controller 55 Interrupt source Timer with PWM (Pulse Width Modulation) 4-ch 16-bit Timer with PWM, 1-ch 16-bit internal Timer RTC (Real-Time Clock) Full clock feature, KHz operation General Purpose Input/Output Ports 24 external interrupt ports 117 multiplexed input/output ports UART 3-channel UART with DMA-based/interrupt-based DMA Controller 4-ch DMAC with burst transfer mode 임베디드시스템교육센터

248 S3C2410 Features(3/4) A/D Converter 8-ch multiplexed ADC LCD Controller STN LCD support TFT LCD support 1, 2, 4, 8 bpp palette color displays 16 bpp non-palette true-color displays 640x480, 320x240, 160x160 NAND Flash Boot Loader Supports booting from NAND Flash memory 4KB internal buffer for booting Supports storage memory for NAND Flash memory after booting 임베디드시스템교육센터

249 S3C2410 Features(4/4) Watchdog Timer 16-bit with interrupt request or system reset at time-out IIC-BUS interface 1-ch multi-master IIC-Bus IIS-BUS interface 1-ch IIS-bus for audio interface with DMA-based USB port host, 1-port device SD Host interface SDIO Card, SD Memory Card Protocol version 1.0 Multimedia Card Protocol version 2.11 SPI interface 2-ch Serial Peripheral Interface Protocol version 2.11 compatible 임베디드시스템교육센터

250 Memory Controller 0x4000_0000 0x3800_0000 0x3000_0000 0x2800_0000 0x2000_0000 0x1800_0000 0x1000_0000 0x0800_0000 0x0000_0000 OM[1:0]=01,10 SROM/SDRAM (ngcs7) SROM/SDRAM (ngcs6) SROM (ngcs5) SROM (ngcs4) SROM (ngcs3) SROM (ngcs2) SROM (ngcs1) SROM (ngcs0) Not using NAND flash for boot ROM OM[1:0]=00 SROM/SDRAM (ngcs7) SROM/SDRAM (ngcs6) SROM (ngcs5) SROM (ngcs4) SROM (ngcs3) SROM (ngcs2) SROM (ngcs1) Boot Internal SRAM(4KB) Using NAND flash for boot ROM 2/4/8/16/32/64/128MB 2/4/8/16/32/64/128MB 128MB 128MB 128MB 128MB 128MB 128MB 1GB HADDR[29:0] 0x57FF_FFFF 0x5000_0000 0x4800_0000 Special Function Register(APB) Special Function Register(AHB) 임베디드시스템교육센터

251 Clock & Power Management 12MHz 임베디드시스템교육센터

252 Timer Timer Period Calculation PCLK Timer Clock [Hz] = PCLK/(Prescaler+1)/Division Factor Min: 66M/256/16 = KHz ( us) Max: 66M/1/2 = 33MHz (0.0303uS) Timer Duration[sec] = (Data value+1) X Timer Clock Period Max: 65536X uS = sec Low Duration = (Data value +1 Compare value) X Timer Clock Period 8-bit Prescaler 1/2 1/4 Clock divider1/8 1/16 TCLK MUX Timer Clock TCMPB TCMP Control Logic TCNTB TCNT MUX TOUT 임베디드시스템교육센터

253 Timer Operations Basic Timer Operation Start bit=1 Timer is started TCNTn=TCMPn Auto-reload TCNTn=TCMPn Timer is stopped TCMPn 1 0 TCNTn TCNTBn=3 TCMPBn=1 Manual update=1 Auto-reload=1 TOUTn TCNTBn=2 TCMPBn=0 Manual update=0 Auto-reload=1 Auto-reload=0 Interrupt request Interrupt request 임베디드시스템교육센터

254 UART Universal Asynchronous Receiver and Transmitter 임베디드시스템교육센터

255 Interrupt Controller Features FIQ or IRQ to ARM920T after arbitration 55 interrupt source (24 external, 31 internal) Fixed or Rotate Priority INTPND SRCPND MASK INTOFFSET PRIORITY IRQ MODE FIQ 임베디드시스템교육센터

256 I/O Ports Features 117 multi-functional input/output pins Port A (GPA): 23 output ports Port B (GPB): 11 in/out ports Port C (GPC), Port D (GPD), Port E (GPE): 16 in/out ports Port F (GPF): 8 in/out ports Port G (GPG): 16 in/out ports Port H (GPH): 11 in/out port If the multiplexed functions on a pin are not used 임베디드시스템교육센터

257 Appendix03. SMDK 임베디드시스템교육센터

258 SMDK2410 Overview Evaluate basic operations of SC32410 and develop codes Components Evaluation board and Accessories Monitor program, Libraries, Example applications Features Boot ROM : AMD 8Mbit 1 EA HW size boot ROM: 1MB Intel StrataFlash 16MBx3 SAMSUNG NAND flash 64M-byte 1EA (smart media card) SDRAM: 32M Byte 2EA: 64MB TFT LCD and Touch panel interface 3-ch UART, 2-port USB host SD host(mmc) interface, Smart media card, Multi-ICE interface, RTC X-tal input logic, IIC, ADC interface SPI interface, IIS interface, EINT interface, IrDA interface 64 keyboard, Ethernet interface, PCMCIA interface, LED display 임베디드시스템교육센터

259 SMDK2410 (S3C2410 Evaluation Board) ATX Power Input 3.3V 3.3V 5V 12V UART2 IrDA UART0 COM1 UART1 COM2 USB Device USB Host USB Host Regulator(1.8V) Peripheral Power MAX3232C MAX3232C VDDRTC VDDCPU VDDADC Touch panel VDDMPLL Smart Media Card Ethernet Socket VDDUPLL PCMCIA Socket AMD FLASH (Bank0 or Bank1) VDDIO RTC X-tal (32.7KHz) Main X-tal (12MHz) ngcs0 or ngcs1 DATA/ADDR/Cont. ARM920T S3C2410X01 DC/DC IIC LCD Connector ADC Connector Ext. Headers Main Switch STRATA FLASH (Bank1 or Bank0) SDRAM (Bank6) Power LED Status LED ngcs1 or ngcs0 ngcs6 Reset Switch Keyboard Cont. EINT n Switches MIC IIS SPK Jack SPI Connector JTAG Port MMC Socket 임베디드시스템교육센터

260 Application Program Environment Single Thread Application Multi Thread Application Application Program Libraries Boot Program - vector handler -system init SMDK2410 Board Application Program Embedded OS BSP SMDK2410 Board 임베디드시스템교육센터

261 Setup Environment Host PC LPT1 COM1 RS232 cable USB host USB cable ATX power OPENice32- A900 USB host USB device UART0 3.3V 5V 12V Regulator 1.8V JTAG S3C2410X01 SMDK 임베디드시스템교육센터

262 Address Space Design ARM Address Space 0xFFFFFFFF 0xF x x x x x x MB 256MB 256MB 256MB 256MB 256MB 256MB 4GB S3C2410 Address Space 0x5FFFFFFF 0x x x x x x x MB 128MB 128MB 128MB 128MB 128MB 128MB 128MB 128MB 128MB SMDK2410 Address Space 0x33FFFFFF 0x x31FFFFFF 0x x0BFFFFFF 256MB 0x x000FFFFF 0x MB 8MB 8MB 8MB 8MB 8MB 8MB 8MB 32MB 1MB SDRAM Intel Flash AMD Flash 임베디드시스템교육센터

263 Address Space Design SDRAM Address Partition 0x33FFFFFF 0x x x Video Data 0x Non Cachable 16MB- 64K Non Cachable 16MB Non Cachable 16MB Downlod Area 16MB 0x33FFFFFF 0x33FF MB Cachable 0x33FFC000 0x33FF4800 0x33FF4000 0x33FF0000 SMDK2410 Initialize Routine 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB Stack Area 8KB Heap & RW Area 24KB 0x33FFFF20 0x33FFFF1C 0x33FFFF04 0x33FFFF00 64KB 0x33FF8000 0x33FF8000 0x33FF7C00 0x33FF7800 0x33FF7400 0x33FF7000 0x33FF6C00 HandleRTC... HandleTIMER0... HandleEINT0 HandleFIQ HandleIRQ HandleReserve HandleDabort HandlePabort HandleSWI HandleUndef HandleReset 1KB 1KB 1KB 1KB 1KB 3KB 256B Translation Table FIQ Stack IRQ Stack Abt Stack Und Stack SVC Stack User Stack 임베디드시스템교육센터

264 Appendix04. Bit Map 임베디드시스템교육센터

265 BMP MS-Windows standard format black&white-, 16-color, 256-color, Truecolor 의영상을표현한다. 16-color and 256-color 영상은 run length encoding 으로압축이가능하다. OS/2-BMP format 도존재한다 임베디드시스템교육센터