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1 Page 1 of 23 Additional Resources: µc/os-ii Author: Source: HiTEL Digital Sig Date: µ (1) uc/os-ii RTOS uc/os-ii EP7209 uc/os-ii, EP7209 EP7209,, CPU ARM720 Core CPU ARM7 CPU wwwnanowitcom10 ' ' uc/os-ii, Stack 4 OSTaskStkInit 5 IRQ OSTickISR 6 OSStartHighRdy 7 OSCtxSw 8 OSIntCtxSw 9

2 Page 2 of 23 (2) EP7209 ARM7 StrongARM uc/os Context Switcher,, CPU EP7209 uc/os-ii wwwnanowitcom uc/os-ii 1 EP7209 CPU ARM720T 720 ARM7 MMU StrongARM MMU psos 25 ARM Software Development 251 Tool, ARM 1 Evaluation CD Linux, Linux SDT ARM7 C ASM 2 Board NANOWIT EP7209, 1Mega Byte Flash 375K SRAM RAM uc/os-ii, Serial Flash Write, uc/os Serial Timer 3 Kernel Source uc/os-ii labrosse, CPU Kernel 8086 wwwucos-iicom CPU ARM7 CPU,, ARM7 4 MicroC/OS-II (labrosse)

3 Page 3 of 23, uc/os-ii, uc/os-ii , CPU, ARM7 5 ARM7 Data sheet EP7209 Data sheet ARM7, ARM7 CPU, CPU Data Sheet EP7209 Data Sheet IRQ, Serial ARM7, Core uc/os OS OS, OS, OS WinCE Embedded Linux, psos, VxWorks uc/os-ii OS, Linux, uc/os, (3) Stack uc/os RTOS Multi-Tasking Time Sharing,, CPU ( ) OS,? Context Switching CPU

4 Page 4 of 23,, 8086 CPU ( - ) 5 6,, Multi-Tasking CPU 10, CPU ( ) Tasking , 3, ( CPU ),,, 3, CPU, Multi-Tasking,,? 10 10, 1, CPU C, Single-Tasking, Multi-Tasking?, Task Stack Task,?, Multi-Tasking, Task Stack,, Context Switching,,

5 Page 5 of 23 RTOS Multi-Tasking Task Task Process Thread (?) CPU RTOS Task, Task TCB Task Control Block TCB Task Stack Task Task Priority Multi-Tasking Stack, Context Switching, Task Stack OS OS, uc/os CPU C Context Switcher Stack,,, Linux psos uc/os CPU CPU,,, Task Context Switching, Task * ARM7 Context Context CPU ARM Context? ARM r0-r12, r13 (sp), r14 Link r15 r0-r12, Stack 8086 Stack 226Page Stack (High Memory) 15 r15(pc) 14 r14(lr) 13 r12 12 r11 11 r10 10 r9 9 r8 8 r7 7 r6 6 r5 5 r4 4 r3 3 r2 2 r1 1 r0

6 Page 6 of 23 0 CPSR <- ptcb->ostcbstkptr Stack (Low Memory) CPSR ARM7 Flag? Task A Task TCB TCB ptcb ptcb- >OSTCBStkPtr Task CPU r13 r13 ARM7?, Task, ptcb- >OSTCBStkPtr r13, r13 TCB, r13 r15 r15,, JUMP, r15 Task ( Linux psos uc/os OS Linux ) (4) OSTaskStkInit uc/os C 8086, lx86l 8086 Os_cpu_cc OSTaskStkInit Hook,, C OSTaskStkInit

7 Page 7 of 23 OSTaskStkInit * OSTaskStkInit Task? Task TCB, TCB Task Stack, Task,, TCB Stack OSTaskStkInit Task uc/os, Task OSTaskCreate RTOS Task Visual C Java Thread OSTaskCreate OS_Taskc OSTaskCreate INT8U OSTaskCreate (void (*task)(void *pd), -> 1 void *pdata, -> 2 OS_STK *ptos, -> 3 INT8U prio) -> 4, Task, Task, Task Task, Task, Task, Task Task ( ),,?, Context Switching "Context Switching,, ", Task,, Task Task?,?, Stack TASK Ready Q, Task TCB CPU Task Stack '?

8 Page 8 of 23 OSTaskStkInit Stack Task * OSTaskStkInit, Stack Stack Ready Q ( Task ) ' ' Stack (High Memory) 15 r15(pc) 14 r14(lr) 13 r12 12 r11 11 r10 10 r9 9 r8 8 r7 7 r6 6 r5 5 r4 4 r3 3 r2 2 r1 1 r0 0 CPSR <- ptcb->ostcbstkptr Stack (Low Memory) OSTaskStkInit 01: void * OSTaskStkInit(void (*task)(void *pd),void *pdata, 02: void *ptos,int16u opt) 03: { 04: INT32U *stk; 05: opt = opt; 06: stk = (INT32U *)ptos; 07: *(--stk) = (INT32U)task; // r15 08: *(--stk) = (INT32U)0; // r14 09: *(--stk) = (INT32U)0; // r12 10: *(--stk) = (INT32U)0; // r11 11: *(--stk) = (INT32U)0; // r10 12: *(--stk) = (INT32U)0; // r9 13: *(--stk) = (INT32U)0; // r8 14: *(--stk) = (INT32U)0; // r7 15: *(--stk) = (INT32U)0; // r6 16: *(--stk) = (INT32U)0; // r5 17: *(--stk) = (INT32U)0; // r4 18: *(--stk) = (INT32U)0; // r3 19: *(--stk) = (INT32U)0; // r2 20: *(--stk) = (INT32U)0; // r1 21: *(--stk) = (INT32U)pdata; // r0

9 Page 9 of 23 22: *(--stk) = (INT32U)0; // CPSR 23: return ((void *)stk); 24: } 24,? OSTaskStkInit Task, Task CPU Program Counter Task Stack, INT16U *stk; INI32U ARM7 32, 5, 6 stk 7 22 *(--stk), Full & Decrement Stack r15 r0, CPSR r15, Task r15 Task r14 r1 r13 sp r0 pdata 8086, C 8086 Stack ARM, r0 pdata r0 C ARM7,,, ' ',?,,,,,

10 Page 10 of 23, (5) IRQ OSTickISR IRQ uc/os RTOS, RTOS RTOS, 1/100 OSTimeTick, OSTickISR, 1/100, OSTimeTick, Timer Context Switching TaskA, 100 Tick Block, Block, TaskB Ready TaskB TaskB 100 Tick, TaskA TaskB TaskA Context Switching Tick RTOS, 1 Timer 1/100, 100 Tick 1, 100 Tick Context Switching Tick, 100,? Stack A A? (Stack), Context Switching,?, Context Switching, Context Switching, Context Switching,

11 Page 11 of 23!!!!!! Stack Context Switching? Stack r15 r0, CPSR ARM7 ARM7 Data Sheet EP Supervisor -, IRQ, CPU IRQ, r13 r14 IRQ r13 Stack Pointer, IRQ Stack?, Task Stack, IRQ SVC r13, 8086, ARM, ARM : IRQHandler 02: stmfd sp!,{r0-r3} 03: mov r1,#register_base 04: ldr r2,=intsr1 05: ldr r0,[r1,r2] 06: tst r0,#0x100 07: bne TimerIRQ ; Check Timer IRQ 08: ldmfd sp!,{r0-r3} 09: subs pc,lr,#4 10: TimerIRQ 11: ldr r2,=tc1eoi ; Timer 1 Interrupt Clear 12: str r0,[r1,r2] 13: 14: mov r2,sp ; copy IRQ's sp -> r2 15: add sp,sp,#16 ; recover IRQ's sp 16: sub r3,lr,#4 ; copy return address -> r3 17: 18: LDR r0,=irq_2 19: MOVS pc,r0 20: IRQ_2 21: stmfd sp!,{r3} ; push SVC's pc 22: stmfd sp!,{r4-r12,lr} ; push SVC's r14, r12-r4 23: mov r4,r2 24: ldmfd r4!,{r0-r3} 25: stmfd sp!,{r0-r3} ; push SVC's r3-r0

12 Page 12 of 23 26: mrs r5,cpsr 27: stmfd sp!,{r5} ; push SVC's PSR 28: B OSTickISR ; Real Body Timer IRQ, Vector Table 01, IRQ 1 CPU IRQ, 2 r13 r14 IRQ, 3 IRQ CPSR SPSR, CPSR IRQ 4 irq r14 ' +4' ARM7 Exception 2 stmfd sp!,{r0-r3} r0 r3 4?! IRQ, SVC Task 3 6, IRQ Timer IRQ EP r0 IRQ, 6 Timer IRQ, 10 8,9 IRQ Return IRQ 10, 11,12, CPU, IRQ, 14 Stack r0 r3 IRQ IRQ,, 14, r0-r3 IRQ 14 mov r2,sp r2 IRQ IRQ SVC, r0 r3 15 add sp,sp,#16, IRQ, IRQ sp,, 16 sub r3,lr,#4 lr, r14_irq? ' +4' r3? r3 IRQ SVC IRQ r14 r13_irq(sp) r2

13 Page 13 of 23 18: LDR r0,=irq_2 19: MOVS pc,r0 20: IRQ_2 IRQ SVC MOVS pc IRQ_2,, IRQ SVC, IRQ 1 SPSR IRQ PSR CPSR 2 r13 r14 SVC r13 r14 (1) CPSR IRQ IRQ IRQ IRQ (2), r13 add sp,sp,#16 stmfd 21 stmfd sp!,{r3} r3 Stack Stack??? IRQ SVC Task!!!, r15 r3? sub r3,lr,#4 r3 (!!!) 22 stmfd sp!,{r4-r12,lr} ARM? r14 r4 r12, Stack? r0 r3 irq? IRQ IRQ? r2 IRQ sp r0 r3 IRQ 23,24 25 Task r0-r3? CPSR CPSR Stack, r5 Stack 26, 27!!! IRQ Stack?, TT

14 Page 14 of 23,!!! 8086, 28 OSTickISR Pseudocode OSTaskISR 1 2 OSIntEnter(), OSIntNesting 3 OSTimeTick() 4 OSIntExit() 5 6 (1) IRQ (2) OSTickISR : OSTickISR 02: LDR r0,=osintnesting ; Notify uc/os-ii of ISR 03: LDRB r1,[r0] 04: ADD r1,r1,#1 05: STRB r1,[r0] 06: BL OSTimeTick ; Process system tick 07: BL OSIntExit ; Notify uc/os-ii of end of ISR 08: LDMFD sp!,{r0} 09: MSR CPSR_xsf,r0 10: LDMFD sp!,{r0 - r12, lr, pc} OSIntNesting++ 6 OSTimeTick(), 7 OSIntExit 8 10 ( ) Stack 8 CPSR (9 ), 10 IRQ ARM7 uc/os-ii ARM7 uc/os-ii 70%

15 Page 15 of 23 (6) OSStartHighRdy OSStartHighRdy uc/os 198 Page OS_CPU_AASM OSStartHighRdy uc/os Task uc/os? 01: void main (void) 02: { 03: PC_DispClrScr(DISP_FGND_WHITE + DISP_BGND_BLACK); 04: OSInit(); 05: PC_DOSSaveReturn(); 06: PC_VectSet(uCOS, OSCtxSw); 07: RandomSem = OSSemCreate(1); 08: OSTaskCreate(TaskStart, (void *)0, 09: (void *)&TaskStartStk[TASK_STK_SIZE - 1], 0); 10: OSStart(); 11: } 8086 main 8 Task, 10 OSStart, OSStartHighRdy, OSStartHighRdy Context Switching, Task Context Switching Task, Task Stack, OSStartHighRdy Task,? OSStartHighRdy OSStartHighRdy 5 1 OSTaskSwHook() 2 Task Stack Point sp 3 OSRunning TRUE 4 sp 5 Task, : OSStartHighRdy 02: BL OSTaskSwHook 03: LDR r0,=osrunning

16 Page 16 of 23 04: MOV r1,#1 05: STRB r1,[r0] 06: LDR r0,=ostcbhighrdy 07: LDR r0,[r0] 08: LDR sp,[r0] 09: LDMFD sp!,{r0} 10: MSR CPSR_xsf,r0 11: LDMFD sp!,{r0 - r12, lr, pc} Hook, 3-4 OSRunning TRUE 6-8 TCB Task Stack sp 9-11 Task Stack 5, (7) OSCtxSw OSCtxSw OSCtxSw() os_cpuh OS_TASK_SW() OS_TASK_SW() OSSched() 8086 #define OS_TASK_SW() asm INT ucos, ARM7 INT SWI, 8086 OSCtxSw OSSched() uc/os Task, Task Task OSCtxSw Context Switching

17 Page 17 of 23, Task OSIntCtxSw,, OSCtxSw, OSStartHighRdy, Task, 201 OSCtxSw 1 Register Task Stack 2 Stack Pointer TCB OSTCBStkPtr 3 OSTaskSwHook() 4 OSTCBCur = OSTCBHighRdy 5 OSPrioCur = OSPrioHighRdy 6 Task Stack Pointer sp 7 8 Task (1),(2) (3) User Hook, (4) (5) OSTCBCur Task TCB OSTCBHighRdy ReadyQ Task TCB, uc/os, Task, OSSched(), OS_TASK_SW(), Context Switching OSCtxSw Context Switching, (4) (5) (6) (8) OSStartHighRdy() Task : OSCtxSw 02: STMFD sp!,{lr} 03: STMFD sp!,{r0 - r12, lr} 04: MRS r0,cpsr 05: STMFD sp!,{r0} 06: LDR r0,=ostcbcur 07: LDR r0,[r0] 08: STR sp,[r0] 09: BL OSTaskSwHook 10: LDR r0,=ostcbcur 11: LDR r1,=ostcbhighrdy 12: LDR r2,[r1] 13: STR r2,[r0] 14: LDR r0,=ospriocur 15: LDR r1,=ospriohighrdy

18 Page 18 of 23 16: LDRB r3,[r1] 17: STRB r3,[r0] 18: LDR sp,[r2] 19: LDMFD sp!,{r0} 20: MSR CPSR_xsf,r0 21: LDMFD sp!,{r0 - r12, lr, pc} (1) 6 8 (2) OSTCBCur->OSTCBStkPtr=sp 9 (3) Hook (4), (5) OSTCBCur = OSTCBHighRdy OSPrioCur = OSPrioHighRdy 18 (6) Task Stack sp 19,20,21 Stack Task, 2 (8) OSIntCtxSw OSIntCtxSw uc/os,,, uc/os Context Switching OSCtxSw OSIntCtxSw, OSCtxSw, OSIntCtxSw OSCtxSw, Call, Context Switching Context Switching

19 Page 19 of 23 OSCtxSw, CPU, Task, Call OSIntCtxSw,, OSIntExit Context Switching OSIntCtxSw OSIntCtxSw Task ( ) CPU, Context Switching Task Task ( ) 2 Stack Pointer TCB OSTCBStkPtr 3 OSTaskSwHook 4 OSTCBCur = OSTCBHighRdy 5 OSPrioCur = OSPrioHighRdy 6 Task Stack Pointer sp 7 8 Task OSCtxSw, (1) OSCtxSw 1 Register Task Stack 2 (1) 4, CPU 3, Stack (High Memory) 15 r15(pc) 14 r14(lr) 13 r12 12 r11 11 r10 10 r9 9 r8 8 r7 7 r6

20 Page 20 of 23 6 r5 5 r4 4 r3 3 r2 2 r1 1 r0 0 CPSR <- ptcb->ostcbstkptr Stack (Low Memory),,, sp OSIntCtxSw sp CPSR sp OSIntCtxSw (2) TCB OSTCBStkPtr (1) OSTickISR LDR r0,=osintnesting LDRB r1,[r0] ADD r1,r1,#1 STRB r1,[r0] BL OSTimeTick BL OSIntExit <- OSIntCtxSw LDMFD sp!,{r0} MSR CPSR_xsf,r0 LDMFD sp!,{r0 - r12, lr, pc} 4 OSIntExit, OS_Corec OSIntExit, OSIntExit, OSIntCtxSw, OSIntExit OSIntCtxSw, OSIntExit lr OSTickISR OSIntExit lr lr OSIntExit lr,, 01: OSIntCtxSw 02: ADD sp,sp,#4

21 Page 21 of 23 03: LDR r0,=ostcbcur 04: LDR r0,[r0] 05: STR sp,[r0] 06: BL OSTaskSwHook 07: LDR r0,=ostcbcur 08: LDR r1,=ostcbhighrdy 09: LDR r2,[r1] 10: STR r2,[r0] 11: LDR r0,=ospriocur 12: LDR r1,=ospriohighrdy 13: LDRB r3,[r1] 14: STRB r3,[r0] 15: LDR sp,[r2] 16: LDMFD sp!,{r0} 17: MSR CPSR_xsf,r0 18: LDMFD sp!,{r0 - r12, lr, pc} OSIntCtxSw 3 OSCtxSw 6 OSIntCtxSw 3 ADD sp,sp,#4 ARM 32, OSTickISR 4 (9) uc/os * OS_CPUH CPU ARM

22 Page 22 of 23 - Type INT16U 16 unsigned, 86 unsigned int, ARM unsigned short - OS_STK_GROWTH OS_STK_GROWTH, ARM 1 Decrement Stack, IDLE Task - OS_ENTER_CRITICAL(), OS_EXIT_CRITICAL() Critical Section, CPSR I 1 splx() - OS_TASK_SW() 86 asm INT ucos, OSCtxSw() * EP7209 EP7209 SYSCON1,TC1D,INTMR1,TC1EOI SYSCON1 1 Prescale, 2KHz EP7209 Data Sheet 76 Page TC1D INTMR1 IRQ Enable, TC1EOI EP7209, ARM7 wwwucos-iicom ucos-ii ARM uc/os (?) Cirrus Logic EP7209 Processor Cirrus Logic Website

23 Page 23 of 23 EP7209 Product Data Sheet (DEC '99, DS453PP2 : 212 Kb) EP7209 Development Kit Product Bulletin (JAN '00, DK453PP04 : 322 Kb) EP7209 Product Bulletin (DEC '99, PB453PP2 : 970 Kb) EP7209 Development Kit Quick Start User's Guide (SEP '01, DS453DKQS-1 : 463 Kb) Errata: EP7209 Data Sheet Change (JAN '00, ER453C1 : 6 Kb) Errata: EP7209 Rev D Silicon Change (JUN '00, ER453D1 : 12Kb) Send to a colleague Print this document Copyleft 1998~2003,2004 Chang-woo YANG Last Modified: 09/30/ :30:31

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untitled Embedded System Lab. II Embedded System Lab. II 2 RTOS Hard Real-Time vs Soft Real-Time RTOS Real-Time, Real-Time RTOS General purpose system OS H/W RTOS H/W task Hard Real-Time Real-Time System, Hard