EDA-Lab 3000 Series

Transcription

1 E-Lab 000 Series User s Guide info@libertron.com Libertron o.,ltd E-Lab 000 Series

2 ontents Require Hardware Environment (P)... Installation Guide... Product Overview... Features... Main oard escription... Jumper Pin Setting... Pin Out Table... Main oard P Layout... Main oard Schematic...0 Spartan-II Target FPG oard Schematic... Virtex/Virtex-E Target FPG oard Schematic... SpartanXL/X000XL/X000XL Target FPG Schematic... Libertron o.,ltd E-Lab 000 Series

3 Require Hardware Environment (P) Pentium Processor PU Windows, Windows, Windows NT System Memory : M OMPK isc rive EPP Mode Parallel Port Mouse VG isplay Minimum Mbytes H Space Libertron o.,ltd E-Lab 000 Series

4 Installation Guide. E-Lab 000 Series 를연결하여사용할퍼스널컴퓨터의프린터포트를 EPP 모드 로변경합니다.. EPP 모드로의변경은퍼스널컴퓨터의 MOS IOS 셋업을통하여확인합니다.. MOS IOS 셋업은퍼스널컴퓨터의전원을 On 한상태에서키보드 el 키나 F 키 (P 제조사에따라다름 ) 를눌러서들어갑니다.. esignpro Shop 를컴팩트디스크드라이브에넣습니다.. Setup.exe 파일을실행하여설치를시작합니다.. 설치완료후새로생성된 esignpro Shop 윈도우내에서 EPP river 를실행합니다.. 시스템을다시부팅시킵니다. 주 > 퍼스널컴퓨터에서 EPP 모드를지원하지않을경우리버트론기술지원부로연락 하여기술지원을받도록합니다. Libertron o.,ltd E-Lab 000 Series

5 Product Overview E-Lab 000 시리즈는 FPG 회로설계검증용장비로써교육과정및회로개발에활용할수있 도록고안된개발장비이다. Eda-Lab 000 시리즈는 P ased Socket 방식으로하나의메인보드에서다양한종류의 FPG 를사용할수있도록경제적으로고안되어있다. 메인보드가지원하는 FPG 는 만게이트에서 00 만게이트 FPG 까지지원가능하다. 또한 esignpro Shop 에뮬레이션프로그램을사용하여 FPG onfiguration 및 Micom 프로그램다운로딩, 테스트패턴출력, FPG 핀상태모니터링등의다양한기능을사용할수있다. E-Lab 000 시리즈에기본장착된 bit Micom 은회로설계자에게로직설계와 Micom 프로그래밍을함께사용하여보다강력한시스템설계를할수있도록 FPG 와데이터및어드레스를공유하고있다. 또한 개의확장포트는회로설계자에게다양한활용기회를하도록되어있으며, 여러개의애플리케이션보드와간단한연결만으로사용할수있도록되어있다. Libertron o.,ltd E-Lab 000 Series

6 Features 구분 항목 사양 비고 사용자회로검증용 Target FPG 보드 FPG 옵션리스트참조 ( 별도문서 ) FPG 디바이스선택장착 XS0_PQ0 기본장착 보드 제어 및 보드제어용 FPG P 와보드간의 인터페이스제공 0(0 겸용 ) Micom Subsystem FPG 와 Micom SRM Kbytes E (Micom+Local Memory) 이공유 EPROM Kbytes E RS- : Port VG : Port(its) PS/ : Port 확장보드커넥터 : Pin * E Parallel Port : Port( 보드제어용 ) 커넥터 ore 전원선택점퍼 : E RS- 입, 출력선택점퍼 : E 메인보드 ownloading/jtg 연결커넥터 : E 보드클럭출력커넥터 : E ontrol ata 출력커넥터 : E Status ata 입력커넥터 : E L : E( har* Row) E-Lab -Segment LE : E( igit) LE : E( it) 디스플레이소자 System Status heck LE : E ata Monitoring LE : E (ontrol ata LE 개, Status ata LE 개 ) 사용자용 : PUSH_SW E 스위치 IPSW Pin E 보드제어용 : PUSH_SW E IPSW Pin E 부속물 esignpro Shop 소프트웨어 - 변환전원어댑터 다운로드케이블 사용자매뉴얼 ownloading FPG esign(*.bit File) Micom Program(*.hex File) Soft ebugging(emulation) ontrol ata Signal( 개 ) Forcing Status ata Signal( 개 ) Monitoring Manual lock( 개 ) 0V/0V 0Hz to V/ IEEE 호환 Parallel able (: 연결 ) E-Lab User s Guide WIN//NT 공유기케이블 Libertron o.,ltd E-Lab 000 Series

7 Main oard escription 0 0 Libertron o.,ltd E-Lab 000 Series

8 . ontrol FPG 주요기능 P Interface : EPP Mode 를통한 P Interface it File ownloading : Target FPG 로 it File 을 ownloading 한다. Hex File ownloading : Local Memory 의 SRM 으로 Hex File 을 ownloading 한다. Hex File 의최대용량은 Kbytes 이다. FPG Reset : Target FPG 의 FPG_RST Pin 으로 ctive L 의 Reset Pulse 를출력한다. Micom Reset : Micom 의 MIOM_RST Pin 으로 ctive H 의 Reset Pulse 를출력한다. ontrol ata Port : esignpro Shop 에서작성된 Test Pattern 을 ontrol ata Port 로출력한다. Status ata Port : Status ata Port 로입력된 Signal 을 esignpro Shop 으로전송한다.. Target FPG : 0Pin 컨넥터 개가 Target FPG Option / 와연결된다. E-Lab 에서지 원되는 Xilinx FPG 는 SpartanXL, X000XL, X000XL, Virtex, Virtex-E, SpartanII 가지 원되며지원가능한 Gates ounts 는 0,000 ~,000,000 게이트까지이다.. System Memory : Kbytes 의 EPROM 영역과 Kbytes 의 SRM 영역으로구성된다. Kbytes 의 SRM 영역중 Kbytes 는 esignpro Shop 을통하여 Hex File 을다운로딩받을수있다. System Memory 와 Target FPG 간에는 ata Signal M[0..] 와 ddress Signal M[0..], 그리고 ontrol Signal MREN, MSE, MSWE, MSOE, MSHE, MSLE 가연결되어있다.. it Micom : Intel MS- 계열의 0 이기본장착되어있다. Micom 은 LE Signal 로 Latch 된 ddress us 와 ata us 는 LS 을통하여분리된다. Target FPG 와 Micom 은 Local Memory 의 ddress us 와 ata us 를서로공유할수있도록공통으로연결되어있다. Micom 사용자의경우 Local Memory 의 SRM 을 Program Memory 로사용하면 esignpro Shop 을통한 Hex File ownloading 기능으로프로그램작성을편하게할수있다. Libertron o.,ltd E-Lab 000 Series

9 . onfiguration Memory : Target FPG 를 onfiguration 하는방법으로는크게세가지방법이있다. 첫째는 onfiguration Memory 를통한방법으로 Power On 과동시에 onfiguration 이이루어진다. onfiguration Memory 에는 JTG(IEEE.) Pin 을통하여 it File 을프로그래밍할수있다. 둘째는 esignpro Shop 을통한 onfiguration 방법으로 it File 을 ownloading 받아 ontrol FPG 를통하여 onfiguration 한다. 셋째는 ownloading able 을통하여 onfiguration 하는방법으로별도의 able 이필요하다. < 표 ->FPG 별 onfiguration Size 및 PROM 구성법 FPG onfiguration its PROM escription XS0XL 0. XV0 SpartanXL XS00, XV0 SpartanII XS00,,0 XV0 SpartanII XV00, XV0 Virtex XV00,,00 XV0 Virtex XV00E,,0 XV0 Virtex-E XV00,, XV0 + XV0 Virtex XV000E,,0 XV0 + XV0 Virtex-E. Expansion Port : Target FPG 의 Pin 개와 FPG_LK, FPG_RST 그리고 lock 입 력전용 Pin 인 FPG_GK 가연결되어있다. 또한 +V 와 의전원이연결되어 있어사용자가회로를꾸미기쉽도록구성되어있다.. Expansion Port : Target FPG 의 Pin 개와 FPG_LK, FPG_RST 그리고 lock 입 력전용 Pin 인 FPG_GK 가연결되어있다. 또한 +V 와 의전원이연결되어 있어사용자가회로를꾸미기쉽도록구성되어있다.. Expansion Port : Local Memory, Micom, Target FPG 에연결되어있는 M[0..] 과 M[0..] 의 us 가연결되어있고, Micom 의 MIOM_LK, MIOM_RST, MWR, MR 가연결되어있어 Micom 을이용한회로응용에사용할수있도록구성되어있다. 또한 +V 와 의전원이연결되어있어사용자가회로를꾸미기쉽도록구성되어있다.. L(Liquid rystal isplay) : Target FPG 와 L[0..], L_[0..], L_EN 의 Signal Name 으로연결된 L 는 haracter y Row 의크기를갖는다. Libertron o.,ltd E-Lab 000 Series

10 0. -Segment LE : 자리의 -Segment LE 가 Target FPG 와연결되어있다. 연결된 Signal Name 은 -Segment ata Pin 인 LE[0..] 와 -Segment ommon Pin 인 IGIT[..] 이 다. 디지털시계회로실험을하기에편하도록 자리의 -Segment LE 로구성되어있다.. LE : it 의 LE 가 Target FPG 에연결되어있다. 연결된 Signal Name 은 LE[0..] 이 다. LE 의구동신호는 ctive H 이다.. Power Module : 개의정전압 Regulator 와 개의 djustable Regulator 로구성된다. 하나의정전압 Regulator 는세개의 Expansion Port 에 +V 의전원을공급한다. 다른하나의정전압 Regulator 는 Main oard 상의 +V 전원이필요한 I 들에전원을공급한다. 하나의 djustable Regulator 는 Target FPG 의 핀구동전원을공급한다. 정상적인출력전압은 +. ~ +.V 이다. 다른하나의 djustable Regulator 는 Main oard 상에 전원이필요한 I 들에전원을공급한다. < 표 ->Regulator 별설정전압및허용전류치 E-Lab omponent Voltage Range(V) Max urrent() escription U LM +.V ~ +.V. djustable Regulator U LM0 +.V ~ +.V. Voltage Regulator U0 LM +.V ~ +.V. djustable Regulator U LM0 +.V ~ +.V. Voltage Regulator. ontrol ata Port : ontrol FPG 와연결된 ontrol ata Port Pin 은 esignpro Shop 에서작성된 Test Pattern 을출력하는기능을가지고있다. 출력되는 Test Pattern 은출력신호가 H 가되면 ontrol ata Monitoring LE 로나타내어진다. ontrol ata Monitoring LE 에대한설명은아래와같다. ~ : ontrol ata 로 Test Pattern 출력시점멸함. ontrol ata 출력이 H 일때 LE On 상태이고, L 일때 LE Off 상태임.. Status ata Port : Status ata Port Pin 을통하여입력된신호는 ontrol FPG 를통하여 esignpro Shop 으로전송되고, 입력되는 Status Signal 이 H 가되면 Status ata Monitoring LE 로나타내어진다. Status ata Monitoring LE 에대한설명은아래와같다. ~ : Status ata 로입력되는외부신호가있는경우점멸함. 고속의신호는정확한상태표시가안될수도있음. Status ata 입력이 H 일때 LE On 상태이고, L 일때 LE Off 상태임. Libertron o.,ltd 0 E-Lab 000 Series

11 . Push Switch : Main oard 상의 개의 Push Switch 는 Target FPG 와 PUSH[..] 의 Signal Name 으로연결되어있다. 개의 Push Switch 는누를때 ctive L 의신호를출력한다.. Oscillator : Main oard 상의 개의 Oscillator 는 Target FPG 와 Micom 에공급되는 lock 을발생한다. Target FPG 와 FPG_LK, MIOM_LK 의 Signal Name 으로연결되어있 다. < 표 ->Oscillator 별사용가능주파수 E-Lab 기본제공 Oscillator Maximum Useable Oscillator OS 0Mhz ~ 0Mhz OS.Mhz ~ 0Mhz < 참고 > 클럭분주기능은 E-Lab 에서는지원하지않는다. 클럭분주가필요할때에는사용자가 직접분주하여사용해야한다. < 참고 > 주파수체배기능은 SpartanII, Virtex, Virtex-E 에서는 Library 로지원한다. 주파수체배를지원하는 Library 는 LKLL 이다. LKLL 은. 에서 까지의분주기능과 0 도간격의 lock 위상차출력, 그리고 배수의입력주파수체배가가능하다. 주파수체배기능은 개의 LKLL 을사용하여최대 체배까지가능하다.. Power Switch : Main oard 와 Target FPG 의전원을 On/Off 하는스위치이다.. Input Jack : E-Lab 의 - Power dapter 에서입력되는 +V/ 의전원을입력 받는단자이다. 단자의가운데가 +V 이고, 주변이 이다.. EPP Port : ontrol FPG 에서 P Interface 용으로사용하는 Parallel Port 이다. E-Lab 과 esignpro Shop 을연결하기위해선 P Parallel Port 가 EPP Mode 로설정되어있어야한 다. Libertron o.,ltd E-Lab 000 Series

12 < 표 ->P 와 E-Lab 간의 Parallel able 연결법 Signal Name E-Lab P Parallel Port(EPP Mode) escription N_STROE P- - P_0 P- ata 0 P_ P- ata P_ P- ata P_ P- ata P_ P- ata P_ P- ata P_ P- ata P_ P- ata N_K P USY P- Wait P_H P- - N_UTOF P- ata Strobe N_SELETIN P- ddress Strobe N. - - Not onnected 0. PS/ Port : Target FPG 와 PS_, PS_ 의 Signal Name 으로연결되어있다. PS/ Port 로 Key oard 나 Mouse 를이용한회로설계실험을할수있다.. VG Port : RG 각각 it 씩할당된 it VG Port 는 Target FPG 와 R[0..], G[0..], [0..], HSYN, VSYN 의 Signal Name 으로연결되어있다. VG Port 를이용하여모니 터에간단한디스플레이회로를구현하는실험에사용할수있다.. RS- Port : RS- Line river 인 MX 로입 출력되는 RS- Port 는 Micom 을통한 Serial ommunication 실험이나 FPG 를통한 URT 구현및검증실험에사용하도록되어있다. Main oard 상의 JP0 을통하여 Micom, FPG 로의통신입 출력경로를설정할수있다. FPG 와는 FRX, FTX 로 Micom 과는 MTX, MRX 의 Signal Name 으로연결되어있다.. ownload/jtg Port : Target FPG 의 onfiguration 관련핀들과연결된컨넥터로써 Target FPG onfiguration 및 onfiguration Memory 인 PROM 을프로그래밍할수있다. 이때에는별도의 Xilinx Parallel ableiii, X-hecker able, MultiLINX able 이나리버트론제품인 EEPROM Writer 를사용할수있다.. System heck LE : Main oard 의전원상태와동작상태, 그리고 Target FPG 의 onfiguration 상태를나타내는 LE 이다. 사용자는 LE 를확인하여아래와같은상태 를확인할수있다. Libertron o.,ltd E-Lab 000 Series

13 < 표 ->System heck LE Main oard Label Name escription LE 이상시발생될사항 Expansion Port +V 전원출력상태표시 Expansion Port 로공급되는 +V 전원이상발생 0 Main oard +V 전원출력상태표시 Main oard 로공급되는 +V 전원이상발생 Micom 동작안함디스플레이장치동작안함 Target FPG 전원공급상태표시 Target FPG 동작안함 Main oard 전원출력상태표시 Main oard 동작상태표시 ontrol FPG 이상발생 Target FPG onfiguration 완료상태표시 esignpro Shop 을사용하여 it 파일다운로딩후확인해야함. oard ontrol Push Switch : Target FPG 와 Micom 의 Reset 신호를발생하는 Push Switch, ontrol FPG Register Reset 신호를발생하는 Push Switch 로구성되어있다. 두개의 Push Switch 에대한동작설명은아래와같다. < 표 ->oard ontrol Push Switch 동작설명 Signal Name E-Lab ctive escription Push Switch 를 누르면 Target FPG 의 SYS_RST S L FPG_RST 와 MIOM_RST 신호를동시에발생시킨다. Target FPG 의경우 ctive L 상태의 Reset 신호가발생하며, Micom 의경우 ctive H 상태의 Reset 신호가발생한다. ONT_RST S L Main oard 제어용 FPG 내부레지스터및회로의 RESET 스위치로써스위치를누르면보드전체의초기화가된다. Libertron o.,ltd E-Lab 000 Series

14 Jumper Pin Setting. JP : Select Jumper Pin Target FPG 의 ore 로공급되는전원선택점퍼로써 Target FPG 변경시에먼저확인하셔야합니다. ore 로공급되는전원핀은 핀입니다. JP +.V +.V < 표 -> Target FPG 별 ore 전압 () ore 전압 () FPG 비고 +.V Virtex-E 전압범위 ±% +.V Virtex, Spartan-II 전압범위 ±% SpartanXL, X000XL, X000XL 전압범위 +.0V ~ +.V. JP0 : RS- Out Select Jumper Pin RS- 통신실험을위해서 Micom 내부의 URT 를사용하거나 Target FPG 내부에 URT 를구현하여사용할경우 URT 와관련된송, 수신신호를설정하는점퍼입니다. JP0 Micom Mode FPG Mode Micom Mode : Micom 에있는 URT 를사용하여 RS- 통신실험을할수있다. FPG Mode : FPG 에 URT 설계하여 RS- 통신실험을할수있다. Libertron o.,ltd E-Lab 000 Series

15 . ontrol IP Switch Setting S0 : Mode Setting IP Switch Target FPG 의 onfiguration Mode Pin 과 Micom 의 Enable Pin 신호가연결되어있습니다. ON S0 < 표 -> IP Switch 번호별연결신호 Number Signal Name ctive(on) State ME L(0) M L(0) M L(0) M0 L(0) < 표 -> 신호이름별상태설명 Signal Name State escription ME H() 0 사용 (ROM) L(0) 0 사용 (Romless) M : M : M0 L : L : L (0 : 0 : 0) Master-serial Mode L : L : H (0 : 0 : ) Master-serial Mode(P) L : H : L (0 : : 0) Slave Parallel Mode(P) L : H : H (0 : : ) Slave Parallel Mode H : L : L ( : 0 : 0) oundary-scan Mode(P) H : L : H ( : 0 : ) oundary-scan Mode H : H : L ( : : 0) Slave-serial Mode(P) H : H : H ( : : ) Slave-serial Mode < 참고 > P : Pre-configuration Pull-ups 표 - 은 FPG 종류에따라서차이가날수있습니다.(Spartan-II 기준임 ) 표 - 에서 Slave Parallel Mode, Slave Parallel Mode(P) 는실제 E-Lab 의 Mode Pin 상태 확인 L( 메인보드좌측상단 ) 에는나타나지않습니다. 이유는 E-Lab 회로도를참조하거나, 본매뉴얼 페이지의 < 표 -> 을참조하시기바랍니다. Libertron o.,ltd E-Lab 000 Series

16 Pin Out Table Target FPG Pin Out Table < 표 -> Signal Name E-Lab Spartan II (PQ0) Virtex (PQ/HQ0) Virtex-E (PQ/HQ0) SpartanXL (PQ0) X000XL/XL (PQ/HQ0) FPG_TMS JP- TM0 JP- TM JP- TM JP- TM JP- TM JP- 0 0 TM JP- 0 0 TM JP- TM JP-0 0 TM0 JP- TM JP- TM JP- 0 0 TM JP- 0 0 TM JP- TM JP- 0 TM JP-0 TM JP- TM JP- TM JP- TM0 JP- TM JP- TM JP- 0 TM JP-0 TM JP- TM JP- TMR JP- 0 0 TMWR JP- TPSEN JP- TLE JP- TMINT0 JP-0 TMINT JP- 0 0 MREN JP- MSE JP- 0 0 MSWE JP- MSOE JP- MSHE JP- MSLE JP- FPG_M JP- 0 FPG_M0 JP Libertron o.,ltd E-Lab 000 Series

17 < 표 -> Signal Name E-Lab Spartan II (PQ0) Virtex (PQ/HQ0) Virtex-E (PQ/HQ0) SpartanXL (PQ0) X000XL/XL (PQ/HQ0) FPG_M JP- (N) IPSW JP- IPSW JP- IPSW JP- IPSW JP- 0 IPSW JP- 0 0 IPSW JP- IPSW JP- IPSW JP- PUSH JP- PUSH JP- 0 0 PUSH JP- 0 PUSH JP- FRX JP- FTX JP-0 FPG_RST JP- MIOM_LK JP- FPG_LK JP- 0 VSYN JP- HSYN JP- JP- 0 JP-0 G JP- G0 JP R JP- 0 0 R0 JP- 0 0 TPS_ JP TPS_ JP LE0 JP LE JP LE JP LE JP- LE JP- LE JP- 00 LE JP- 0 LE JP- 0 FPG_ONE JP Libertron o.,ltd E-Lab 000 Series

18 < 표 -> Signal Name E-Lab Spartan II (PQ0) Virtex (PQ/HQ0) Virtex-E (PQ/HQ0) SpartanXL (PQ0) X000XL/XL (PQ/HQ0) FPG_PROG JP- 0 FPG_INIT JP- 0 IGIT JP- 0 IGIT JP- 0 IGIT JP- 0 IGIT JP- IGIT JP- IGIT JP- 0 0 SEG0 JP-0 SEG JP- SEG JP- SEG JP- 0 SEG JP- 0 0 SEG JP- SEG JP- SEG JP-0 L0 JP- L JP- L JP- L JP- L JP- L JP- L JP-0 L JP- L_0 JP- L_ JP- 0 0 L_EN JP- 0 EXP JP- EXP JP- EXP JP-0 EXP JP- EXP JP- EXP JP- 0 0 EXP JP- 0 EXP0 JP- 0 0 EXP JP- FPG_IN JP- EXP JP- FPG_LK JP- Libertron o.,ltd E-Lab 000 Series

19 < 표 -> Signal Name E-Lab Spartan II (PQ0) Virtex (PQ/HQ0) Virtex-E (PQ/HQ0) SpartanXL (PQ0) X000XL/XL (PQ/HQ0) FPG_TO JP- FPG_TI JP- EXP JP- 0 EXP JP- EXP JP- EXP JP- EXP JP- 0 0 EXP JP- EXP JP-0 EXP0 JP- EXP JP- EXP JP- EXP JP EXP JP- 0 0 EXP JP EXP JP EXP JP EXP JP EXP JP EXP JP- 0 0 FPG_GK JP- 0 0 FPG_GK JP- EXP JP-0 EXP0 JP- EXP JP- EXP JP EXP JP- EXP JP- EXP JP- EXP JP- EXP JP- 0 0 EXP JP- 00 EXP JP EXP0 JP- 0 EXP JP- 0 EXP JP- 0 EXP JP- 0 EXP JP- 0 FPG_TK JP- 0 Libertron o.,ltd E-Lab 000 Series

20 < 표 -> Signal Name E-Lab JP- JP- JP- JP- JP- JP- JP- JP- JP- JP- JP- JP- JP- JP- JP- JP- JP- JP- JP- JP- JP- JP- JP- JP-0 JP- JP- JP- JP-0 JP- JP- JP- JP- JP- JP-0 JP- JP- JP- JP- JP- JP- JP- JP- JP- JP- JP- JP-0 Spartan II (PQ0),,,,,,,,,, 0, 0, 0,, 0,,, 0,,, 0,,,,, 0, Virtex (PQ/HQ0),,, 0,,,, 0,, 0 0,, 0, 0,, 0,,,,,,, 0,,,,,, 0, 0,, Virtex-E (PQ/HQ0),,, 0,,,, 0,,, 0, 0,, 0,, 0, 0,, 0,,,,,,, 0,,,,,, 0, 0,, SpartanXL (PQ0), 0 0, 0, 0 0, 0, 0, 0 0,, 0,,,,,, 0,,,, 0,, X000XL/XL (PQ/HQ0), 0 0, 0, 0 0, 0, 0, 0 0,, 0,,,,,, 0,,,, 0,, Libertron o.,ltd 0 E-Lab 000 Series

21 < 표 ->Expansion Port Pin Out Table Signal Name E-Lab JP escription EXT_+V JP-, EXP JP- EXP JP- EXP JP- EXP JP- EXP JP- EXP JP- EXP JP- EXP0 JP-0 EXP JP- EXP JP- EXP JP- EXP JP- EXP JP- EXP JP- EXP JP- EXP JP- EXP JP- EXP0 JP-0 EXP JP- EXP JP- EXP JP- EXP JP- JP-, FPG_LK JP- FPG_GK JP- FPG_RST JP- N. JP-0,, Not onnect JP-, Libertron o.,ltd E-Lab 000 Series

22 < 표 ->Expansion Port Pin Out Table Signal Name E-Lab JP escription EXT_+V JP-, EXP JP- EXP JP- EXP JP- EXP JP- EXP JP- EXP JP- EXP JP- EXP0 JP-0 EXP JP- EXP JP- EXP JP- EXP JP- EXP JP- EXP JP- EXP JP- EXP JP- EXP JP- EXP0 JP-0 EXP JP- EXP JP- EXP JP- EXP JP- JP-, FPG_LK JP- FPG_GK JP- FPG_RST JP- N. JP-0,, Not onnect JP-, Libertron o.,ltd E-Lab 000 Series

23 < 표 ->Expansion Port Pin Out Table Signal Name E-Lab JP escription EXT_+V JP-, M0 JP- System Memory ata 0 M JP- System Memory ata M JP- System Memory ata M JP- System Memory ata M JP- System Memory ata M JP- System Memory ata M JP- System Memory ata M JP-0 System Memory ata M0 JP- System Memory ddress 0 M JP- System Memory ddress M JP- System Memory ddress M JP- System Memory ddress M JP- System Memory ddress M JP- System Memory ddress M JP- System Memory ddress M JP- System Memory ddress M JP- System Memory ddress M JP-0 System Memory ddress M0 JP- System Memory ddress 0 M JP- System Memory ddress M JP- System Memory ddress M JP- System Memory ddress JP-, MIOM_LK JP- Micom lock MWR JP- Micom Write Signal MIOM_RST JP- Micom Reset Signal MR JP-0 Micom Read Signal N. JP-, Not onnect JP-, Libertron o.,ltd E-Lab 000 Series

24 < 표 ->ontrol ata Pin Out Table Signal Name E-Lab escription FPG_OUT0 JP- ontrol ata it 0 Pin(LS) FPG_OUT JP- ontrol ata it Pin FPG_OUT JP- ontrol ata it Pin FPG_OUT JP- ontrol ata it Pin FPG_OUT JP- ontrol ata it Pin FPG_OUT JP- ontrol ata it Pin FPG_OUT JP- ontrol ata it Pin FPG_OUT JP- ontrol ata it Pin FPG_OUT JP- ontrol ata it Pin FPG_OUT JP- ontrol ata it Pin FPG_OUT0 JP- ontrol ata it 0 Pin FPG_OUT JP- ontrol ata it Pin FPG_OUT JP- ontrol ata it Pin FPG_OUT JP- ontrol ata it Pin FPG_OUT JP- ontrol ata it Pin FPG_OUT JP- ontrol ata it Pin(MS) Libertron o.,ltd E-Lab 000 Series

25 < 표 -0>Status ata Pin Out Table Signal Name E-Lab escription FPG_SIN0 JP- Status ata it 0 Pin(LS) FPG_SIN JP- Status ata it Pin FPG_SIN JP- Status ata it Pin FPG_SIN JP- Status ata it Pin FPG_SIN JP- Status ata it Pin FPG_SIN JP- Status ata it Pin FPG_SIN JP- Status ata it Pin FPG_SIN JP- Status ata it Pin FPG_SIN JP- Status ata it Pin FPG_SIN JP- Status ata it Pin FPG_SIN0 JP- Status ata it 0 Pin FPG_SIN JP- Status ata it Pin FPG_SIN JP- Status ata it Pin FPG_SIN JP- Status ata it Pin FPG_SIN JP- Status ata it Pin FPG_SIN JP- Status ata it Pin(MS) Libertron o.,ltd E-Lab 000 Series

26 < 표 ->ownload & JTG Pin Out Table Signal Name E-Lab JP escription +V JP- FPG_IN JP- Target FPG in Pin JP- EXP JP- Target FPG Pin JP- EXP JP- Target FPG Pin FPG_LK JP- Target FPG LK Pin L JP- Target FPG Pin FPG_ONE JP- Target FPG ONE Pin L0 JP-0 Target FPG Pin FPG_IN JP- Target FPG IN Pin SEG JP- Target FPG Pin FPG_PROG JP- Target FPG PORGRM Pin SEG JP- Target FPG Pin FPG_INIT JP- Target FPG INIT Pin IGIT JP- Target FPG Pin EXP JP- Target FPG USY Pin FPG_TMS JP- Target FPG TMS Pin EXP JP- Target FPG WRITE Pin FPG_TK JP-0 Target FPG TK Pin EXP JP- Target FPG S Pin PROM_TI JP- XV00 PROM TI Pin FPG_TI JP- Target FPG TI Pin FPG_TO JP- Target FPG TO Pin Libertron o.,ltd E-Lab 000 Series

27 < 표 ->Main oard lock Pin Out Table Signal Name E-Lab JP escription FPG_LK JP- FPG Input lock MIOM_LK JP- Micom Input lock MNUL_LK0 JP- Programmed y esignpro Shop Manual lock 0 MNUL_LK JP- Programmed y esignpro Shop Manual lock JP-,, Libertron o.,ltd E-Lab 000 Series

28 < 표 ->Micom Port & Timer Interrupt Pin onnect Table Signal Name E-Lab JP escription MT0 JP- Micom Timer Interrupt 0 Pin MT JP- Micom Timer Interrupt Pin MP0 JP- Micom Port.0 Pin MP JP- Micom Port. Pin MP JP- Micom Port. Pin MP JP- Micom Port. Pin MP JP- Micom Port. Pin MP JP- Micom Port. Pin MP JP- Micom Port. Pin MP JP-0 Micom Port. Pin Libertron o.,ltd E-Lab 000 Series

29 Main oard P Layout Libertron o.,ltd E-Lab 000 Series

30

31 Main oard Schematic Libertron o.,ltd 0 E-Lab 000 Series

32 esigned y elisys. E-Lab 000(uffer Part) Tuesday, October, 00 Title Size ocument Number Rev ate: Sheet of FPG_0 FPG_ FPG_ FPG_S FPG_S FPG_ FPG_S FPG_ FPG_S FPG_S0 FPG_S FPG_ FPG_ FPG_S FPG_S FPG_ FPG_ FPG_0 FPG_ FPG_ FPG_ FPG_ FPG_ FPG_ FPG_S FPG_S FPG_S FPG_S FPG_S FPG_S FPG_S0 FPG_S UFF_EN UFF_EN UFF_EN UFF_EN FPG_SIN0 FPG_SIN FPG_SIN FPG_SIN FPG_SIN FPG_SIN FPG_SIN FPG_SIN FPG_SIN FPG_SIN FPG_SIN0 FPG_SIN FPG_SIN FPG_SIN FPG_SIN FPG_SIN FPG_SIN FPG_SIN FPG_SIN FPG_SIN FPG_SIN FPG_SIN FPG_SIN0 FPG_SIN FPG_SIN0 FPG_SIN FPG_SIN FPG_SIN FPG_SIN FPG_SIN FPG_SIN FPG_SIN FPG_OUT FPG_OUT FPG_OUT FPG_OUT FPG_OUT FPG_OUT FPG_OUT0 FPG_OUT FPG_OUT0 FPG_OUT FPG_OUT FPG_OUT FPG_OUT FPG_OUT FPG_OUT FPG_OUT FPG_OUT FPG_OUT FPG_OUT0 FPG_OUT FPG_OUT FPG_OUT FPG_OUT FPG_OUT FPG_OUT0 FPG_OUT FPG_OUT FPG_OUT FPG_OUT FPG_OUT FPG_OUT FPG_OUT FPG_S[0..] FPG_[0..] UFF_EN FPG_SIN[0..] +V RP Y0 SM-0-Y RP Y0 SM-0-Y U LS(SM Type) SOI0P-00MIL G G Y Y Y Y Y Y Y Y U LS(SM Type) SOI0P-00MIL G G Y Y Y Y Y Y Y Y JP ONTROL T HEER-.-P 0 SM-P 0 SM-P JP STTUS T HEER-.-P 0 SM-P 0 SM-P RP Y0 SM-0-Y JP ONTROL T HEER-.-P U LS(SM Type) SOI0P-00MIL G G Y Y Y Y Y Y Y Y JP STTUS T HEER-.-P RP Y0 SM-0-Y U LS(SM Type) SOI0P-00MIL G G Y Y Y Y Y Y Y Y

33 FPG_SIN[0..] FPG_[0..] UFF_EN FPG_0 FPG_ FPG_ FPG_ FPG_ FPG_ FPG_ FPG_ UFF_EN FPG_ FPG_0 FPG_ FPG_ FPG_ FPG_ FPG_ FPG_ UFF_EN U G G LS0(SM Type) SOI0P-00MIL U G G Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y LS0(SM Type) SOI0P-00MIL R 0(SM Type) SM-P R 0(SM Type) SM-P R 0(SM Type) SM-P R 0(SM Type) SM-P R 0(SM Type) SM-P R 0(SM Type) SM-P R0 0(SM Type) SM-P R 0(SM Type) SM-P R 0(SM Type) SM-P R 0(SM Type) SM-P R 0(SM Type) SM-P R 0(SM Type) SM-P R 0(SM Type) SM-P R 0(SM Type) SM-P R 0(SM Type) SM-P R 0(SM Type) SM-P LE LE-SM- LE LE-SM- LE LE-SM- LE LE-SM- LE LE-SM- LE LE-SM- LE LE-SM- LE LE-SM- 0 LE LE-SM- LE LE-SM- LE LE-SM- LE LE-SM- LE LE-SM- LE LE-SM- LE LE-SM- LE LE-SM- +V +V +V +V +V +V +V +V +V +V +V +V +V +V +V +V TT0 TT TT TT TT TT TT TT TT TT0 TT TT TT TT TT TT STT0 +V STT +V STT +V STT +V STT +V STT +V STT +V STT +V STT +V STT0 +V STT +V STT +V STT +V STT +V STT +V STT +V LE LE-SM- LE LE-SM- 0 LE LE-SM- LE LE-SM- LE LE-SM- LE LE-SM- LE LE-SM- LE LE-SM- LE LE-SM- LE LE-SM- LE LE-SM- LE LE-SM- 0 LE LE-SM- LE LE-SM- LE LE-SM- LE LE-SM- R0 0(SM Type) SM-P R 0(SM Type) SM-P R 0(SM Type) SM-P R 0(SM Type) SM-P R 0(SM Type) SM-P R 0(SM Type) SM-P R 0(SM Type) SM-P R 0(SM Type) SM-P R 0(SM Type) SM-P R 0(SM Type) SM-P R0 0(SM Type) SM-P R 0(SM Type) SM-P R 0(SM Type) SM-P R 0(SM Type) SM-P R 0(SM Type) SM-P R 0(SM Type) SM-P Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y U G G LS0(SM Type) SOI0P-00MIL U G G LS0(SM Type) SOI0P-00MIL FPG_SIN0 FPG_SIN FPG_SIN FPG_SIN FPG_SIN FPG_SIN FPG_SIN FPG_SIN UFF_EN FPG_SIN FPG_SIN0 FPG_SIN FPG_SIN FPG_SIN FPG_SIN FPG_SIN FPG_SIN UFF_EN Title E-Lab 000(LE isplay Part) Size ocument Number Rev esigned y elisys. ate: Tuesday, October, 00 Sheet of

34 PS_ +V PS_ PS_ PS_ JP PS ONN(Female) PS-ONNETOR 0 G0 G R0 R 0 G0 G R0 R RP Y RRY-Y RP Y RRY-Y VSYN HSYN VSYN HSYN 0 P VG Port SUP-F-P / IP-E-P / IP-E-P TX_INF RX_INF / IP-E-P U + V V+ - TO + RI - RO V- TI TO TI 0 RI RO MXSE(SM Type) SOIP-0MIL / IP-E-P +V RX TX TX_ONT RX_ONT TX_ONT RX_ONT M0 SM-P P RS- SUP-F-P RX TX JP0 MRX FRX MTX FTX RS- Select HEER-.-P-X MRX FRX MTX FTX RX_INF TX_INF JP0 P INF(OM) HEER-.-P Title E-Lab 000(onnector Part) Size ocument Number Rev esigned y elisys. ate: Tuesday, October, 00 Sheet of

35 MIOM Enable Pin(/0) EXP : EXP : USY L : EXP : S FPG_IN : IN, 0 FPG_ONE : ONE FPG_INIT : INIT L0 : SEG : FPG_PROG : PROG FPG_LK : LK Signal Name : Pin escription EXP : IGIT : SEG : EXP : WRITE esigned y elisys. E-Lab 000 Series(ontrol FPG Part) Tuesday, October, 00 Title Size ocument Number Rev ate: Sheet of M ONT_ONE ONT_LK M0 ONT_IN ONT_PROG M M ONT_INIT ONT_ONE ONT_ONE ONT_INIT MIOM_OS FPG_OS MIOM_OS FPG_OS MIOM_LK FPG_LK FPG_ FPG_ FPG_ FPG_ FPG_ FPG_ FPG_ FPG_ FPG_ FPG_0 FPG_ FPG_ FPG_ FPG_ FPG_ FPG_S FPG_S0 FPG_S FPG_S FPG_S FPG_S FPG_S FPG_S FPG_S FPG_S FPG_S FPG_S0 FPG_S FPG_S FPG_S FPG_S MNUL_LK0 ONT_LK ONT_IN FPG_0 MNUL_LK TX_ONT RX_ONT FPG_RST MIOM_RST M0 M SYS_RST ME LE_EN MREN ONT_RST ONT_PROG ONT_INIT FPG_IN EXP L_EN L_ L_0 L0 L L L L L L L EXP FPG_M0 FPG_M FPG_M MSE MSWE MSOE MSHE MSLE SEG SEG IGIT FPG_INIT FPG_PROG FPG_ONE EXP FPG_LK EXP EXP FPG_RUN_LE ME FPG_LK MIOM_LK MNUL_LK0 MNUL_LK M0 M M M M M M M M0 M M M M M ONT_RUN_LE M M M M0 M M M M M M P_ P_ N_UTOF N_K P_ P_H N_SELETIN P_ USY P_ N_STROE P_ P_0 P_ FPG_[0..] FPG_S[0..] L[0..] MIOM_RST LE_EN MSE MREN MSOE MSWE MSLE MSHE FPG_M0 FPG_M FPG_M SYS_RST ONT_RST FPG_IN EXP EXP SEG SEG IGIT FPG_INIT FPG_PROG FPG_ONE EXP FPG_LK EXP EXP RX_ONT TX_ONT MIOM_LK FPG_LK FPG_RST L_EN L_ L_0 ME UFF_EN M[0..] M[0..] +.V +.V +.V +V +.V +V +V +.V +V LE(SM Type) LE-SM- M0(SM Type) SM-P JP ONTROL FPG MOE HEER-.-P-X R 0(SM Type) SM-P M0 SM-P M0(SM Type) SM-P 0 SM-P 0 M0(SM Type) SM-P U S0-PQ0 PQFP0P ,TRY,IRY (),VREF () TMS,VREF,VREF,VREF,IRY,TRY,VREF,VREF,VREF M M0 M PWN STTUS,VREF,VREF,VREF GK GK0,VREF,VREF,VREF ONE PROGRM (INIT) (),VREF,VREF () (),VREF () LK (OUT,USY) (IN,0),VREF,VREF () TK,VREF,VREF,VREF GK GK,VREF,VREF,VREF (WRITE) (S) TI TO OS MIOM LOK HO-00-OS N Output V OS FPG LOK HO-00-OS N Output V U T00 PL0P-SOKET 0 0 N T N LK N RESET/OE N E N N N N EO REY N SER_EN N N V LE(SM Type) LE-SM- R 0(SM Type) SM-P JP LOK Input HEER-.-P M0 SM-P M0 SM-P M0(SM Type) SM-P R X(ip Type) RRY-

36 JP 0 L WM-0M HEER-.-P L_0 L_ L_EN L0 L L L L L L L +V L_0 L_ L_EN R 0(ip Type) VOLUME +V R R/W L[0..] 0(/W) +V IPSW[..] IPSW IPSW IPSW IPSW IPSW IPSW IPSW IPSW R (ip Type) RRY- 0 S SW IP-(ip Type) IPSW-P LE[0..] LE0 LE LE LE LE LE LE LE U0 G G Y Y Y Y Y Y Y Y LS0(SM Type) SOI0P-00MIL LE_OUT0 LE_OUT LE_OUT LE_OUT LE_OUT LE_OUT LE_OUT LE_OUT SEG_IG SEG_ SEG_F SEG_IG LE_OUT0 LE_OUT LE_OUT LE_OUT LE_OUT LE_OUT LE_OUT LE_OUT SEG_IG SEG_ SEG_IG S-SR(ip Type) S- S-SR(ip Type) S- R X(ip Type) RRY- +V S PUSH_SW S PUSH_SW S PMS00 PMS00 R X(ip Type) RRY- PUSH PUSH PUSH PUSH[..] U igit igit igit igit igit igit F E G athode ommon SN-0 SN-0 P IG E SEG_E SEG_ F P SEG_P IG SEG_ 0 IG G SEG_G IG SEG_IG IG IG SEG_IG PUSH_SW S PUSH_SW S ONT_RST S SYS_RST PMS00 PMS00 PMS00 PMS00 PUSH SYS_RST ONT_RST SYS_RST ONT_RST SEG[0..] SEG0 SEG SEG SEG SEG SEG SEG SEG U G G Y Y Y Y Y Y Y Y LS(SM Type) SOI0P-00MIL SEG_OUT0 SEG_OUT SEG_OUT SEG_OUT SEG_OUT SEG_OUT SEG_OUT SEG_OUT SEG_OUT0 SEG_OUT SEG_OUT SEG_OUT SEG_OUT SEG_OUT SEG_OUT SEG_OUT RP Y0(ip Type) RRY-Y RP Y0(ip Type) RRY-Y SEG_ SEG_ SEG_ SEG_ SEG_E SEG_F SEG_G SEG_P IGIT[..] IGIT IGIT IGIT IGIT IGIT IGIT U ULN00(ip Type) SOIP-0MIL 0 OM SEG_IG SEG_IG SEG_IG SEG_IG SEG_IG SEG_IG +V +V M0 M0 SM-P SM-P 0 M0 SM-P Title E-Lab 000(isplay) Size ocument Number Rev esigned y elisys. ate: Tuesday, October, 00 Sheet of

37 EXT_+V EXP EXP EXP EXP EXP EXP EXP EXP EXP EXP EXP FPG_LK FPG_RST JP EXPNSION HEER-.-P-X EXP EXP EXP EXP0 EXP EXP EXP EXP EXP0 EXP EXP FPG_GK EXT_+V FPG_GK EXT_+V FPG_LK FPG_RST EXP EXP EXP EXP EXP EXP EXP EXP EXP EXP EXP FPG_LK FPG_RST JP EXPNSION HEER-.-P-X EXP EXP EXP EXP0 EXP EXP EXP EXP EXP0 EXP EXP FPG_GK EXT_+V FPG_GK JP MIOM_LK MIOM_RST EXT_+V MIOM_LK MIOM_RST M0 M M M M0 M M M M M0 M EXPNSION HEER-.-P-X M M M M M M M M M M M MWR MR EXT_+V MWR MR M[0..] M[0..] EXP[..] EXP[..] Title E-Lab 000(Expansion Part) Size ocument Number Rev esigned y elisys. ate: Tuesday, October, 00 Sheet of

38 esigned y elisys. E-Lab 000(it Micom Part) Tuesday, October, 00 Title Size ocument Number Rev ate: Sheet of MWR M M M M M0 LE MREN LE_EN PSEN M M M M M MP M M ME MP MP MR MP M M MP M M M MP MIOM_RST M0 MP M M MP0 MINT M M M M M0 M M M M M0 M M M M M M M M M M M M M M M M M M M M M M0 M M M0 M0 M0 M M M M M M M M M M M0 M M M M M0 M M M M M M M M M0 M M M M M M MSOE MSHE MSLE MSE MSWE MT MT0 MSE MINT0 MIOM_LK MTX MRX LE M[0..] M[0..] MSE MSWE MSOE MSHE MSLE LE_EN MREN MINT0 MINT MIOM_RST MIOM_LK ME MWR MR PSEN LE MTX MRX +V +V +V R.K(SM Type) SM-P U 0(ip Type) IP0P-00MIL 0 0 E/VP X X RESET INT0 INT T0 T P.0 P. P. P. P. P. P. P. P0.0 P0. P0. P0. P0. P0. P0. P0. P.0 P. P. P. P. P. P. P. R WR PSEN LE/P TX RX U (ip Type) IPP-00MIL E OE O0 O O O O O O O U LS(SM Type) SOI0P-00MIL 0 O G Q0 Q Q Q Q Q Q Q R X(ip Type) RRY- M0 SM-P JP MIOM PORT 0(ip Type) HEER-.-0P 0 M0 SM-P M0(SM Type) SM-P M0 SM-P U SVLH- TSOPP-00MIL E WE OE HE LE V V N N N

39 +V +V +V R 0 RRY- R 0 RRY- R.K(SM Type) SM-P P_H USY N_K P_ P_ P_ P_ P_ P_ P_ P_0 N_SELETIN N_UTOF N_STROE RP Y0 RRY-Y RP Y0 RRY-Y RP Y0 RRY-Y RP Y0 RRY-Y IP-P IP-P IP-P IP-P 0 IP-P IP-P IP-P IP-P IP-P 0 IP-P IP-P 0 0 P EPP PORT SUP-F-P IP-P Title E-Lab 000(Parallel Port) Size ocument Number Rev esigned y elisys. ate: Tuesday, October, 00 Sheet of

40 +V +V J + / IP-E-P + / IP-E-P HS0-PTER-J POWER JK P S POWER SW SF0R U K0 LM0-HETSINK IN VOUT 0(SM Type) SM-P 0(SM Type) SM-P U K0 LM0-HETSINK IN VOUT +V +V + / IP-E-P EXT_+V +V + / IP-E-P R 0(SM Type) SM-P 0 0(SM Type) SM-P R 0(SM Type) SM-P 0(SM Type) SM-P LE LE-SM- 0 LE LE-SM- +V +V U LM VIN + / IP-E-P + / IP-E-P U0 LM VIN J J LM-HETSINK VOUT + 0/ IP-E-P LM-HETSINK VOUT + 0/ IP-E-P R 0/%(SM Type) SM-P R0 0(ip Type) VOLUME R 0/%(SM Type) SM-P R 0(ip Type) VOLUME R 0(SM Type) SM-P LE LE-SM- R 0(SM Type) SM-P LE LE-SM- + / IP-E-P + / IP-E-P N00(ip Type) IOE-IP 0(SM Type) SM-P N00(ip Type) IOE-IP 0(SM Type) SM-P +.V +.V +.V N00(ip Type) IOE-IP +.V +.V JP Power Selection HEER-.-P-X Title E-Lab 000(Power Part) Size ocument Number Rev esigned y elisys. ate: Tuesday, October, 00 Sheet of

41 M[0..] M0 M M M RP TM0 TM TM TM M M M M Y0 SM-0-Y RP0 TM TM TM TM M[0..] M0 M M M M M M M M M M0 M M M M M Y0 SM-0-Y RP Y0 SM-0-Y RP Y0 SM-0-Y RP Y0 SM-0-Y RP TM0 TM TM TM TM TM TM TM TM TM TM0 TM TM TM TM TM MSE MSOE MSLE TM0 TM TM TM TM TM TM TM TM TM TM TMR TPSEN TLE TMINT MSE MSOE MSLE JP FPG_TMS TM TM TM TM TM0 TM TM TM TM TM0 TM TM TM TMWR TMINT0 MREN MSWE MSHE FPG_M FPG_M0 MREN MSWE MSHE FPG_M FPG_M0 FRX FPG_RST MIOM_LK VSYN G0 R0 IPSW IPSW IPSW IPSW IPSW PUSH PUSH FRX FPG_RST MIOM_LK VSYN G0 R0 LE0 LE LE LE JP FPG_M IPSW IPSW IPSW PUSH PUSH FTX FPG_LK HSYN 0 G R TPS_ TPS_ LE LE LE LE FPG_ONE FPG_M FTX FPG_LK HSYN 0 G R FPG_ONE FPG_INIT L_ FPG_IN FPG_LK FPG_INIT IGIT IGIT IGIT SEG SEG SEG SEG L0 L L L L_ EXP EXP EXP EXP0 FPG_IN FPG_LK JP FPG_PROG IGIT FPG_PROG IGIT IGIT SEG0 SEG SEG SEG L L L FPG_GK L L_0 L_EN L_0 EXP L_EN EXP EXP EXP EXP EXP FPG_TO FPG_TI EXP EXP EXP EXP0 EXP EXP EXP EXP FPG_GK EXP0 EXP EXP EXP EXP EXP EXP EXP FPG_TK JP EXP EXP EXP EXP EXP EXP EXP EXP EXP EXP FPG_GK EXP FPG_GK EXP EXP EXP EXP EXP0 EXP EXP MR MWR PSEN LE MINT0 MINT PS_ PS_ MR MWR PSEN LE MINT0 MINT PS_ PS_ Y0 SM-0-Y RP Y0 SM-0-Y RP TMR TMWR TPSEN TLE TMINT0 TMINT TPS_ TPS_ HEER 0 HEER-.-0P-X HEER 0 HEER-.-0P-X EXP[..] EXP[..] L[0..] LE[0..] IPSW[..] PUSH[..] SEG[0..] IGIT[..] HEER 0 HEER-.-0P-X HEER 0 HEER-.-0P-X Y0 SM-0-Y FPG_M0 R R.K(SM Type) SM-P FPG_M.K(SM Type) SM-P FPG_M R.K(SM Type) SM-P FPG_ONE R 00(SM Type) SM-P EXP K(SM Type) R SM-P SM-P M0 M0(SM Type) SM-P FPG_IN EXP FPG_LK FPG_IN EXP FPG_LK 0 M0 SM-P M0 SM-P M0 SM-P M0 SM-P M0 SM-P M0 SM-P M0 SM-P M0 SM-P EXP K(SM Type) R SM-P Signal Name : Pin escription FPG_IN : IN, 0 EXP : EXP : L : L0 : SEG : SEG : IGIT : FPG_INIT : INIT FPG_PROG : PROG FPG_ONE : ONE EXP : USY FPG_LK : LK EXP : S EXP : WRITE +V FPG_LK FPG_ONE FPG_IN FPG_PROG FPG_INIT EXP EXP EXP FPG_TI S0 ME FPG_M ME FPG_M FPG_M0 SETUP SW IPSW-P JP FPG_IN EXP EXP L L0 0 SEG SEG IGIT FPG_TMS FPG_TK 0 PROM_TI FPG_TO OWNLO/JTG PIN HEER-.-P-X R0.K(SM Type) SM-P R.K(SM Type) SM-P PROM_TI FPG_TMS FPG_TK L0 FPG_PROG 0(SM Type) SM-P FPG_INIT SEG FPG_ONE IGIT PROM_EO 0 N N TI N TMS TK F N 0 N LK 0 N V N V N U XV00 PLP-SOKET N OE/RESET E V N EO N 0 N N TO N N N 0 EXP L SEG FPG_TMS FPG_TK L0 FPG_PROG FPG_INIT SEG PROM_EO IGIT 0 N N TI N TMS TK F N 0 N LK 0 N V N V N U XV00 PLP-SOKET N OE/RESET E V N EO N 0 N N TO N N N 0 FPG_TI EXP L SEG Title E-Lab 000(Target FPG onnector Part) Size ocument Number Rev esigned y elisys. Tuesday, October, 00 ate: Sheet of

42 Spartan-II Target FPG oard Schematic Libertron o.,ltd E-Lab 000 Series

43 TM0 TM TM TM TM TM TM TM TM TM TM TMR TPSEN TLE TMINT MSE MSOE MSLE IPSW IPSW IPSW IPSW IPSW PUSH PUSH FRX FPG_RST MIOM_LK VSYN G0 R0 LE0 LE LE LE FPG_INIT IGIT IGIT IGIT SEG SEG SEG SEG L0 L L L L_ EXP EXP EXP EXP0 FPG_IN FPG_LK FPG_TO FPG_TI EXP EXP EXP EXP0 EXP EXP EXP EXP FPG_GK EXP0 EXP EXP EXP EXP EXP EXP EXP FPG_TK JP HEER 0 HEER-.-0P-X JP HEER 0 HEER-.-0P-X JP HEER 0 HEER-.-0P-X JP HEER 0 HEER-.-0P-X FPG_TMS TM TM TM TM TM0 TM TM TM TM TM0 TM TM TM TMWR TMINT0 MREN MSWE MSHE FPG_M FPG_M0 FPG_M IPSW IPSW IPSW PUSH PUSH FTX FPG_LK HSYN 0 G R TPS_ TPS_ LE LE LE LE FPG_ONE FPG_PROG IGIT IGIT IGIT SEG0 SEG SEG SEG L L L L L_0 L_EN EXP EXP EXP EXP EXP EXP EXP EXP EXP EXP EXP EXP EXP EXP EXP EXP FPG_GK EXP EXP EXP EXP EXP EXP0 EXP EXP M0 M0 FPG_TO FPG_TI EXP EXP EXP EXP EXP EXP EXP EXP0 EXP EXP EXP EXP EXP EXP EXP EXP EXP EXP FPG_GK FPG_GK EXP EXP0 EXP EXP EXP EXP EXP EXP EXP EXP EXP EXP0 EXP EXP EXP EXP FPG_TK SM-P L L L L L_0 L_ L_EN EXP EXP EXP EXP EXP EXP EXP EXP0 EXP FPG_IN EXP FPG_LK M0 TO TI (S) (WRITE),VREF,VREF,VREF GK GK,VREF,VREF,VREF TK FPG_TMS TM0 TM TM TM TM TM TM TM TM0 TM TM TM TM TM TM TM TM TM M0 SM-P LK (OUT,USY) (IN,0),VREF,VREF () (),VREF (),IRY,TRY (),VREF () (),VREF,VREF () (INIT) PROGRM U SPRTN-II / PQ0 PQFP0P TMS,VREF,VREF,VREF,IRY,TRY,VREF,VREF,VREF M M L L L L0 SEG SEG SEG SEG SEG SEG SEG SEG0 IGIT IGIT IGIT IGIT IGIT IGIT FPG_INIT FPG_PROG ONE,VREF,VREF,VREF GK0 GK,VREF,VREF,VREF STTUS PWN M FPG_M0 FPG_M MSLE MSHE MSOE MSWE MSE MREN TMINT TMINT0 TLE TPSEN TMWR TMR TM TM TM TM TM TM FPG_ONE LE LE LE LE LE LE LE LE0 TPS_ TPS_ R0 R G0 G 0 HSYN VSYN FPG_LK MIOM_LK FPG_RST FTX FRX PUSH PUSH PUSH PUSH IPSW IPSW IPSW IPSW IPSW IPSW IPSW IPSW FPG_M SM-P SM-P Title E-Lab 000(Spartan-II) Size ocument Number Rev esigned y LGKIM.0 Tuesday, May 0, 00 ate: Sheet of

44 Virtex/Virtex-E Target FPG oard Schematic Libertron o.,ltd E-Lab 000 Series

45 HEER-.-0P-X HEER-.-0P-X HEER-.-0P-X PQFP0P Virtex-E <-> Virtex oard ifference Pin Number Virtex-E : ddtional Pin P, P, P, P, P, P, P0, P HEER-.-0P-X SM-P SM-P SM-P SM-P Title E-Lab 000(VIRTEX-E) Size ocument Number Rev esigned y LGKIM.0 Monday, May, 00 ate: Sheet of

46 SpartanXL/X000XL/X000XL Target FPG Schematic Libertron o.,ltd E-Lab 000 Series

47 TM0 TM TM TM TM TM TM TM TM TM TM TMR TPSEN TLE TMINT MSE MSOE MSLE IPSW IPSW IPSW IPSW IPSW PUSH PUSH FRX FPG_RST MIOM_LK VSYN G0 R0 LE0 LE LE LE FPG_INIT IGIT IGIT IGIT SEG SEG SEG SEG L0 L L L L_ EXP EXP EXP EXP0 FPG_IN FPG_LK FPG_TO FPG_TI EXP EXP EXP EXP0 EXP EXP EXP EXP FPG_GK EXP0 EXP EXP EXP EXP EXP EXP EXP FPG_TK JP HEER 0 HEER-.-0P-X JP HEER 0 HEER-.-0P-X JP HEER 0 HEER-.-0P-X JP HEER 0 HEER-.-0P-X FPG_TMS TM TM TM TM TM0 TM TM TM TM TM0 TM TM TM TMWR TMINT0 MREN MSWE MSHE FPG_M FPG_M0 FPG_M IPSW IPSW IPSW PUSH PUSH FTX FPG_LK HSYN 0 G R TPS_ TPS_ LE LE LE LE FPG_ONE FPG_PROG IGIT IGIT IGIT SEG0 SEG SEG SEG L L L L L_0 L_EN EXP EXP EXP EXP EXP EXP EXP EXP EXP EXP EXP EXP EXP EXP EXP EXP FPG_GK EXP EXP EXP EXP EXP EXP0 EXP EXP M0 M0 M0 M0 SM-P TM0 TM TM FPG_TI FPG_TK TM TM TM TM TM TM0 TM FPG_TMS TM TM TM TM TM TM TM TM TM0 TM TM TM TM TM TMR TMWR TPSEN TLE TMINT0 TMINT MREN MSE MSWE MSOE MSHE MSLE FPG_M FPG_M0 FPG_M IPSW IPSW IPSW IPSW IPSW IPSW IPSW IPSW PUSH PUSH PUSH PUSH FRX FTX FPG_RST VSYN HSYN FPG_INIT 0 G G0 R R0 TPS_ TPS_ LE0 LE LE LE LE LE LE LE MIOM_LK U ().SGK. ().PGK. (). (). (0) () () () () ().TI () ().TK (). () (). () () () () (0) () () () () (0) () () () () ().TMS () () (). () ().0 () () () () (0) () () () () (0). () (). () () () () () () () () () () () () (0) (). () (). () (0) () () () () () () () () () () () () () () (0) () () () () (0). () ().S. () () () () () ().PGK. () ().0.WS ().SGK O.TO O.M LK I.M0 ().SGK.OUT I.M ().0.IN ().PGK () (0).H () () (0).RLK.RY/USY () (). () () ().L () () () () () () () () () () () (0) () () (0) () () () () () (). () () () () () () () () () ().RS (0) (). () (0) ().INIT (). () () () () () () () () () ().S0 () (). () () (0) () () (0) () (0) () (0) () (0) () (0) () (0) () (0) () (0). () (0) (0) (0) () (00) () () () ().PGK () (). () PROGRM ().SGK ONE SPRTN-XL PQFP0P N V V V V V V V V V V0 V V V V V V FPG_GK EXP EXP EXP EXP EXP0 EXP EXP EXP EXP EXP EXP EXP EXP EXP EXP0 EXP EXP EXP EXP EXP EXP EXP EXP EXP EXP EXP EXP0 EXP EXP EXP EXP EXP EXP FPG_GK EXP FPG_TO FPG_LK FPG_IN EXP EXP EXP EXP0 EXP EXP EXP EXP EXP EXP L_EN L_ L_0 L L L L0 L L L L SEG SEG SEG SEG SEG SEG SEG0 IGIT SEG IGIT IGIT IGIT IGIT FPG_LK IGIT FPG_PROG FPG_ONE SM-P SM-P SM-P Title E-Lab 000(Spartan-XL / X000XL) Size ocument Number Rev esigned y LGKIM.0 Tuesday, May 0, 00 ate: Sheet of

48 Revision History Ver ate Revision Initial ocument Release Update Product Overview 표 - 내용수정 회로도 V. 로교체 표 -(Page ) 하단내용추가 회사이름변경 ( 기존의 elisys esign Lab -> Libertron o.,ltd), 내용수정 Libertron Home Page(WWW) : (Include File ownload, FPG User s Forum) Technical Support tech@libertron.com Telephone : 0-- Fax : 0-- Libertron o.,ltd E-Lab 000 Series