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1 Device Driver in Linux Embedded System Lab. II

2 UART LCD Ethernet USB Embedded System Lab. II 1

3 Asynchronous Serial Communication -- UART Universal asynchronous receiver/transmitter Transmit bits in a single channel simplex (one way) half-duplex (one direction at a time) full-duplex (two way) A sequence of bits packet or character ASCII code 7 bits for 128 characters (alphabet, numerical, and control) fixed length or variable length Start, stop, and parity bits Embedded System Lab. II 2

4 Connection and signal characteristics Data terminal equipment and data communication equipment Logic '1' (marking) -3v to -25v with respect to signal ground Logic 0 (spacing) +3v to +25v Not assigned between -3v and +3v (a transition region) EIA RS232 Embedded System Lab. II 3

5 RS232(2) DTE FEP DB25 DCE MOD DB25 1 FG FG 2 TX > 2 TX 3 RX < RX 4 RTS > 4 RTS 5 CTS < CTS 6 DSR < DSR 7 SG SG 8 DCD < DCD 20 DTR > 20 DTR Flow control (handshaking) signals to avoid buffer overflow or lock-up. RTS : to prepare the DCE device for accepting transmission CTS : to inform the DTE device that transmission may begin DCD: data carrier detected DSR: DCE ready SG: system ground DTR: DTE ready Embedded System Lab. II 4

6 Signal Format for ASCII Character data, start, stop, and (even or odd) parity bits Embedded System Lab. II 5

7 UART(1) PC Com Port - EIA-574 RS-232 pin out DB-9 pin used for Asynchronous Data Embedded System Lab. II 6

8 UART(2) Is Your Interface a DTE or a DCE? Find out by following these steps: The point of reference for all signals is the terminal (or PC). Measure the DC voltages between (DB25) pins 2 & 7 and between pins 3 & 7. Be sure the black lead is connected to pin 7 (Signal Ground) and the red lead to whichever pin you are measuring. If the voltage on pin 2 (TD) is more negative than -3 Volts, then it is a DTE, otherwise it should be near zero volts. If the voltage on pin 3 (RD) is more negative than -3 Volts, then it is a DCE. If both pins 2 & 3 have a voltage of at least 3 volts, then either you are measuring incorrectly, or your device is not a standard EIA-232 device. Call technical support. In general, a DTE provides a voltage on TD, RTS, & DTR, whereas a DCE provides voltage on RD, CTS, DSR, & CD. Embedded System Lab. II 7

9 UART(3) This is a standard 9 to 25 pin cable layout for async data on a PC AT serial cable Description Signal 9-pin DTE 25-pin DCE Source DTE or DEC Carrier Detect CD 1 8 from Modem Carrier Detect RD 2 3 from Modem Transmit Data TD 3 2 from Terminal/Computer Data Terminal Ready DTR 4 20 From Terminal/Computer Signal Ground SG 5 7 from Modem Data Set Ready DSR 6 6 from Modem Request to Send RTS 7 4 from Terminal/Computer Clear to Send CTS 8 5 from Modem Ring Indicator RI 9 22 from Modem Embedded System Lab. II 8

10 UART(4) RS-232 interface RS-232(EIA Std.) applicable to the 25 pin interconnection of Data Terminal Equipment (DTE)and Data Communication Equipment (DCE) using serial binary data Pin Description EIA CKT From DCE To DCE Pin Description EIA CKT From DCE To DCE 1 2 Frame Ground Transmitted Data AA BA D(Data) Secondary Transmitted Data Transmitted Sig. Element Timing SBA DB T(Timing) D 3 Received Data BB D 16 Secondary Received Data SBB D 4 Request Data CA C(Control) 17 Received Sig. Element Timing DD T 5 Clear to Send CB C 18 Undefined 6 Signal Set Ready CC C 19 Secondary Request to Send SCA C 7 Singnal Gnd/Common Return AB 20 Data Terminal Ready CD C Rcvd. Line Signal Detector Undefined Secondary Rcvd. Line Sig. Detector Secondary Clear to Send CF SCB C C C Sig. Quality Detector Ring Indicator Data Sig. Rate Selector(DCE) Data Sig. Rate Selector(DTE) Undefined CG CE CI CH C C C C T Embedded System Lab. II 9

11 UART(5) RS232D used RJ45 type connectors (similar to telephone connectors) Pin No. Signal Description Abbr. DTE DCE 1 DCE Ready, Ring Indicator DSR/RI 2 Received Line Signal Detector DCD 3 DTE Ready DTR 4 Signal Ground SG 5 Received Data RxD 6 Transmitted Data TxD 7 Clear To Send CTS 8 Request To Send RTS Embedded System Lab. II 10

12 LC()? Liquid Crystal Display(1),.. Embedded System Lab. II 11

13 Liquid Crystal Display(2) LCD LCD ( W/cm2). ( 10V) IC,. Embedded System Lab. II 12

14 Liquid Crystal Display(3) (mm), ( cm) ( mm ). (portable)..,. ( m).. (back light).. (-30-40). Embedded System Lab. II 13

15 LCD LCD LCD LCD (electrically addressed) LCD (optically addressed) LCD Embedded System Lab. II 14

16 LCD 'OFF',. (.) 'ON',. (.),. Embedded System Lab. II 15

17 LCD Hardware overview PXA255 PXA250 Core MMU Interrupt Controller Bridge Dynamic Memory Controller LCD Controller DMA GPIO TFT LCD & Touch screen ADS 7843 LCD CON Embedded System Lab. II 16

18 (Ethernet)(1) Ethernet Commonly used to refer to all carrier sense multiple access collision detection (CSMA/CD) LANS that generally conform to Ethernet specifications, including IEEE Embedded System Lab. II 17

19 Ethernet(2) (Signaling) (Base-band) Manchester digital Encoding (Broadband) differential PSK (data rate) 1~100Mbps Embedded System Lab. II 18

20 Baseband: Ethernet(3) ( ) Mbps 10Base2:, 185m 10Base5:, 500m 10Base-F: 10Base-T: Twisted Pair cable (Broadband): ( PSK) : 10Broad36 Embedded System Lab. II 19

21 Ethernet(4) IEEE 802 Embedded System Lab. II 20

22 Ethernet(5) (Frame Format) Preamble(7) - alert, timing, start synchronization SFD(Start frame delimiter) - DA(Destination address) - SA(Source address) - PDU / (PDU) - 46~1500 CRC -, CRC-32 Embedded System Lab. II 21

23 Ethernet(6) (Control) HDLC I-Frame S-Frame U-Frame P/F N(S) N(R) Code Poll/final bit Embedded System Lab. II 22

24 ACCESS Method : CSMA/CD Ethernet(7) Carrier Sense Multiple Access with Collision Detection : "Listen before talk" Node Common Line Data : Listen before talk : Collision : Listen while talk, Embedded System Lab. II 23

25 Ethernet(8) CSMA/CD,,, jamming jamming Carrier Sense Multi Access Collision Dection No Yes No Yes No Yes Embedded System Lab. II 24

26 Ethernet Controller Ethernet Hardware SMSC 10/100 Ethernet Single Chip LAN91C111 Internal 32Bit Wide Data Path 8Kbytes Internal Memory (Receive and Transmit FIFO Buffers) External 25MHz-output pin for an external PHY and MAC MSC0,1 - Static Chip Select 1,2 (Bank 1,2) Base Address = 0x04000_0000 (Pri) 0x0800_0000(sec) Primary Ethernet D(31:0) Secondary Ethernet D(31:0) Logic ncs1 ncs2 ADDR (15:2) WE# OE# A(15:2) DQM(3:0)# WE# OE# A(15:2) DQM(3:0)# Embedded System Lab. II 25

27 Universal Serial Bus USB(1) Motivation Connection of the PC to the telephone Ease-of-use Port expansion Goals for the Universal Serial Bus Ease-of-use for PC peripheral expansion Low-cost solution that supports transfer rates up to 480 Mb/s Full support for real-time data for voice, audio, and video Protocol flexibility for mixed-mode isochronous data transfers and asynchronous messaging Integration in commodity device technology Comprehension of various PC configurations and form factors Provision of a standard interface capable of quick diffusion into product Enabling new classes of devices that augment the PC s capability Full backward compatibility of USB 2.0 for devices built to previous versions of the specification Embedded System Lab. II 26

28 Universal Serial Bus USB (2) Feature Easy to use for end user Single model for cabling and connectors Electrical details isolated from end user (e.g., bus terminations) Self-identifying peripherals, automatic mapping of function to driver and configuration Dynamically attachable and reconfigurable peripherals Wide range of workloads and applications Suitable for device bandwidths ranging from a few kb/s to several hundred Mb/s Supports isochronous as well as asynchronous transfer types over the same set of wires Supports concurrent operation of many devices (multiple connections) Supports up to 127 physical devices Supports transfer of multiple data and message streams between the host and devices Allows compound devices (i.e., peripherals composed of many functions) Lower protocol overhead, resulting in high bus utilization Embedded System Lab. II 27

29 Universal Serial Bus USB (3) Isochronous bandwidth Guaranteed bandwidth and low latencies appropriate for telephony, audio, video, etc. Flexibility Supports a wide range of packet sizes, which allows a range of device buffering options Allows a wide range of device data rates by accommodating packet buffer size and latencies Flow control for buffer handling is built into the protocol Robustness Error handling/fault recovery mechanism is built into the protocol Dynamic insertion and removal of devices is identified in user-perceived real-time Supports identification of faulty devices Synergy with PC industry Protocol is simple to implement and integrate Consistent with the PC plug-and-play architecture Leverages existing operating system interfaces Embedded System Lab. II 28

30 Universal Serial Bus USB (4) Low-cost implementation Low-cost subchannel at 1.5 Mb/s Optimized for integration in peripheral and host hardware Suitable for development of low-cost peripherals Low-cost cables and connectors Uses commodity technologies Upgrade path Architecture upgradeable to support multiple USB Host Controllers in a system Embedded System Lab. II 29

31 Universal Serial Bus USB (5) Embedded System Lab. II 30

32 Universal Serial Bus USB (6) Taxonomy of Application Space Embedded System Lab. II 31

33 USB H/W Architectural(1) Physical Interface Embedded System Lab. II 32

34 USB H/W Architectural(2) Embedded System Lab. II 33

35 USB Host Controller Host Controller OHCI(Open Host Controller Interface : Compaq ) UHCI(Universal Host Controller Interface : Intel ) capability USB Client Driver USB Core Host Controller Driver Host Controller (Compaq or Intel) Embedded System Lab. II 34 Linux USB Device Driver Stack

36 USB Hub enable/disable reset/resume robustness/recover Embedded System Lab. II 35

37 USB Data Flow Type Control Transfers: Used to configure a device at attach time and can be used for other device-specific purposes, including control of other pipes on the device. Bulk Data Transfers: Generated or consumed in relatively large and bursty quantities and have wide dynamic latitude in transmission constraints. Interrupt Data Transfers: Used for timely but reliable delivery of data, for example, characters or coordinates with human-perceptible echo or feedback response characteristics. Isochronous Data Transfers: Occupy a prenegotiated amount of USB bandwidth with a prenegotiated delivery latency. (Also called streaming real time transfers). Embedded System Lab. II 36

38 USB ( ), (client) USB Embedded System Lab. II 37

39 USB host controller low level (SIE) H/W + S/W USB system S/W Client S/W standard device S/W Embedded System Lab. II 38

40 USB bus interface low level (SIE) USB logical device Function common view point high-level Embedded System Lab. II 39

41 , unidirection, transfer S/W owner endpoint FIFO : stream() message(usb ) default control pipe : endpoint 0 map 1 S/W client Embedded System Lab. II 40

42 USB Embedded System Lab. II 41

hd1300_k_v1r2_Final_.PDF

hd1300_k_v1r2_Final_.PDF Starter's Kit for HelloDevice 1300 Version 11 1 2 1 2 3 31 32 33 34 35 36 4 41 42 43 5 51 52 6 61 62 Appendix A (cross-over) IP 3 Starter's Kit for HelloDevice 1300 1 HelloDevice 1300 Starter's Kit HelloDevice