RF RF(Radio Frequency) [2]. RF RF,, M/W, [3]. RF (isolation) (feedback) (oscillation) (interference) [4]. 1 ICS ICS. (multi path fading) (distortion),

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1 韓國電磁波學會論文誌第 20 卷第 12 號 2009 年 12 月論文 RF A Study on Digital RF System with Interference Cancellation System 주지한 이상주 Ji-Han Joo Sang-Joo Lee 요약 RF RF. RF(Radio Frequency) DSP(Digital Signal Processing) FPGA(Field Programmable Gate Array). DSP FPGA ICS(Interference Cancellation System) RF,. LMS(Least Mean Square) IF(Intermediate Frequency),. Abstract In this paper, in order to improve a service quality and to broaden the service coverage in the mobile communication system a study on a digital RF repeater employed with an Interference Cancellation System(ICS) is performed. The digital RF repeater employed with an ICS is implemented to remove interference and feedback signals which are disadvantages of a conventional(or general) RF repeater. This thesis presents the design and experiments of the new wireless repeater. The proposed wireless repeater consists of a RF repeater mounted with digital engine. The digital ICS engine consists of a DSP and FPGA. The digital engine and RF circuit are designed into a one-piece. After developing hardware through the digital platform they are also designed and fabricated into a one-piece in order to apply a best performance repeater system. The method of removing interference and feedback signals is an adaptive IF technique employed with a LMS algorithm. The powerful performance and fast convergence speed is obtained by using this method. Key words : RF Reapeter, ICS, LMS. 서론 WCDMA(Wideband Code Division Multiple Access). (repeater) [1]., M/W(microwave) M/W, LIG (LIG Nex1) : :

RF RF(Radio Frequency) [2]. RF RF,, M/W, [3]. RF (isolation) (feedback) (oscillation) (interference) [4]. 1 ICS ICS. (multi path fading) (distortion), (doppler). (multi path fading) RF,,, RF, [5].

2 RF RF(Radio Frequency) [2]. RF RF,, M/W, [3]. RF (isolation) (feedback) (oscillation) (interference) [4]. 1 ICS ICS. (multi path fading) (distortion), (doppler). (multi path fading) RF,,, RF, [5]., [6]. RF ICS(Interference Cancellation System) (multi path fading), 그림 1. ICS Fig. 1. Instruction of ICS repeater system.. RF. [7].,.,,. WCDMA HS- DPA(High Speed Down-link Packet Access), CDMA RF WCDMA, WCDMA 3GPP(3rd Generation Partnership Project) EVM(Error Vector Magnitude) [8]. RF. RF, 1253

3 韓國電磁波學會論文誌第 20 卷第 12 號 2009 年 12 月. WCD- MA ICS, (donor). RF, DSP(Digirtal Signal Processing), CPU(Central Processing Unit),, RF (forward link) (reverse link), DSP Xilinx Virtex4 FPGA 16 bit DAC(Digital to Analog Convertor) 14 bit Dual ADC(Analog to Digital Convertor), CPU Atmel 128 cpu chip. (microstrip).,, (service) (donor). LMS(Least Mean Square) (Finite Impulse Response: FIR), (adaptive filter). (signal to noise ratio), ACLR (Adjacent Channel Leakage Ratio) EVM (Error Vector Magnitude). RF DSP AGC(Automatic Gain Control).. 간섭신호제거기법 2 WCDMA ICS IF. RF IF. IF IF, 그림 2. WCDMA ICS Fig. 2. Internal structure of WCDMA ICS repeater.. IF (cross correlation) [9]. LMS,, (1). (1). (2),. (2), 0., 1254

4 RF.,,. (3), LMS. μ (4) IF,.. IF,.,,.. (Least Mean Square: LMS)... LMS,. IF LMS FIR. 3 WCDMA ICS. RF 62.5 MHz IF ADC(Analog to Digital Convertor), ADC 50 MHz 12.5 MHz. FPGA(Field Programmable Gate Array) DDC(Digital Down Convertor) LMS, ALC(Automatic Level Control) DUC(Digital Up Convertor) DAC(Digital to Analog Convertor) 62.5 MHz IF. DAC HPA (High Power Amplifier). LMS. 4 WCDMA ICS. FPGA Xilinx Vertex, ADC DAC TI. DDC,, DUC, Pre- Buffer, ALC, LMS, CPU, Clock-distributer 그림 3. ICS Fig. 3. Internal structure of ICS repeater. 1255

韓國電磁波學會論文誌第 20 卷第 12 號 2009 年 12 月 표 1. RF Table 1. Specification of the RF system. 그림 4. WCDMA ICS Fig. 4. Internal structure of WCDMA ICS repeater.. Pre-Buffer, ALC, CPU. 3-1 하드웨어플랫폼.

5 韓國電磁波學會論文誌第 20 卷第 12 號 2009 年 12 月 표 1. RF Table 1. Specification of the RF system. 그림 4. WCDMA ICS Fig. 4. Internal structure of WCDMA ICS repeater.. Pre-Buffer, ALC, CPU. 3-1 하드웨어플랫폼. 설계및제작 1 ICS RF. WCDMA. 5 ICS. DSP, FPGA,. IF/RF, IF / RF DSP. 6 DSP, Digital Signal Processor TI DSP TMS320C Xilinx FPGA, (SDRAM 16 MB, Flash 4 MB), 10/100, Dual RS-232 SDR. DSP,,,. DSP RS-232, JTAG, Uplink Downlink 1, , MHz MHz 3 dbp-p 3 dbp-p Input power range Maximun output power System delay EVM PCDE Frequency stability Tx/Rx isolation Noise figure ( ) Spectrum emission mask Spurious emissions InBand spurious Out band ACLR 50 dbm/ Total 27 dbm/total db (30 db) ACLP - 2nd harmonics Stop band rejection 9 us 12.5 % 35 db 0.01 ppm 1.5 : db dbm/fa 37 dbm/fa 43 dbm/total db (30 db) 7 db - 3 Gpp TS Gpp TS category A 40 dbc 45 f c ±5 MHz 50 f c ±10 MHz 10 dbc 1,937.5 MHz 10 dbc 1,962.5 MHz 80 dbc 12 dbm/3.84 MHz 10 dbc 2,127.5 MHz 10 dbc 2,152.5 MHz. TI TMS320C MHz (clock) 32 bit. 4, 2 MCBSP(Multi-Channel Buffered Serial Ports) 2 I2C (port). 4 MByte (flash memory), 16 MByte SD- 1256

RF 그림 5. Fig. 5. Platform block-diagram. 그림 6. DSP Fig. 6. Photograph of DSP module. 그림 7. FPGA Fig. 7. Photograph of FPGA module.

UART DUAL UART (chip) 115,200 bps, 2. (ethernet) SMSC LAN91C111 10/100 Mbps (network).

IF VGA(Variable Gain Amplifier) OP-AMP ADC ADC. (bus) FPGA. DAC IF.

6 RF 그림 5. Fig. 5. Platform block-diagram. 그림 6. DSP Fig. 6. Photograph of DSP module. 그림 7. FPGA Fig. 7. Photograph of FPGA module. RAM(Synchronous Dynamic RAM). SDRAM 128 MByte DSP (oscillator), 50 MHz 6 DSP, 100 MHz EMIF. UART DUAL UART (chip) 115,200 bps, 2. (ethernet) SMSC LAN91C111 10/100 Mbps (network). FPGA IF ADC DAC, ADC DAC DDS(Direct Digital Synthesizer), (chip) DSP FPGA 4. IF VGA(Variable Gain Amplifier) OP-AMP ADC ADC. (bus) FPGA. DAC IF. FPGA MHz, 12 Bit, 65 db (signal to ratio) ADC DAC MHz DDS RF IF, 2 IF 2 IF. FPGA DSP, ADC DAC, DDC(Digital Down Converter), DUC(Digital Up Converter),. 3-2 플랫폼소프트웨어 (real time operation system) DSP/BIOS. SOFT HARD. SOFT (task), HARD [10]. 8 umon. 1257

韓國電磁波學會論文誌第 20 卷第 12 號 2009 年 12 月 그림 9. Fig. 9. Application layer and driver components. 그림 8. umon Fig. 8. Functional block-diagram of umon. (boot loader),,...,. 9.. API IOM. OS DSP/BIOS API.

7 韓國電磁波學會論文誌第 20 卷第 12 號 2009 年 12 月 그림 9. Fig. 9. Application layer and driver components. 그림 8. umon Fig. 8. Functional block-diagram of umon. (boot loader),,...,. 9.. API IOM. OS DSP/BIOS API.. 9, DSP/BIOS 3 (PIP/PIO, SIO/DIO, GIO). PIP/ PIO SIO/DIO API DSP/BIOS PIP SIO. API. GIO API.., Chip Support Library(CSL),,. 10. IOM_ Packets. IOM_ Packets. 3-3 WCDMA ICS 중계기설계및구현 11 WCDMA Tx/Rx 1258

WCDMA Tx/Rx Fig. 11. Frequency band of WCDMA Tx/Rx.. 4 FA,. 12.

8 RF 그림 10. Fig. 10. Flow of mini-driver. 그림 12. WCDMA ICS Fig. 12. Structure of WCDMA ICS repeater. (a) WCDMA Tx (a) Frequency band of WCDMA Tx (b) WCDMA Rx (b) Frequency band of WCDMA Rx 그림 11. WCDMA Tx/Rx Fig. 11. Frequency band of WCDMA Tx/Rx.. 4 FA,. 12. LNA(Low Noise Amplifier) (noise figure) IF 그림 13. ICS Fig. 13. Fabrication of WCDMA ICS repeater.. IF ADC DDC.,, DUC IF, IF RF. 13 ICS. 1259

9 韓國電磁波學會論文誌第 20 卷第 12 號 2009 年 12 月 RF DSP, CPU,, CPU. CPU DSP FPGA., 9 V. PLL(Phase Lock Loop) RF Saw Filter. FPGA. ADC dual, CPU.,,. ADC FPGA power meter. FA on/off,,. WCDMA ICS CPU DSP, RF. DSP FPGA, CPU FPGA. CPU.. WCDMA ICS 중계기시험및결과 14.. 그림 14. Fig. 14. Test set-up of multi-path-fading test. 그림 15. (I+25 db) Fig. 15. Oscillation(I+25 db) db db I+30 db. SNR FA. 10 db

10 RF 그림 16. (I+30 db) Fig. 16. Oscillation(I+30 db). 그림 19. (Tx) Fig. 19. Band flatness(tx). 그림 17. ICS (I+10 db) Fig. 17. Output spectrum of ICS repeater(i+10 db). 그림 18. ICS (I+20 db) Fig. 18. Output spectrum of ICS repeater(i+20 db). 그림 20. ICS (Tx) Fig. 20. Group delay(tx). 20 db I+20 db., 55 dbm, up-link. 19. ±1 db, FA. RF /,

韓國電磁波學會論文誌第 20 卷第 12 號 2009 年 12 月 그림 21. (Tx) Fig. 21. Return loss(tx). 그림 22. EVM, PCDE, (Tx) Fig. 22. EVM, PCDE, frequency stability(tx).... 21. 1.5:1. 22 EVM, PCDE, frequency stability. EVM 8.

11 韓國電磁波學會論文誌第 20 卷第 12 號 2009 年 12 月 그림 21. (Tx) Fig. 21. Return loss(tx). 그림 22. EVM, PCDE, (Tx) Fig. 22. EVM, PCDE, frequency stability(tx) :1. 22 EVM, PCDE, frequency stability. EVM 8.12 %, PCDE db, frequency error 1.77 Hz 9 usec. EVM 12.5 %.. 결론 RF. LMS IF, ALC. DSP, TI 6713 DSP, FPGA Xilinx Vertax. ICS RF,. dual ADC DAC, RF DSP CUP., 20 db I+20 db EVM 10 %, ICS. 참고문헌 [1] Paul Burns, Software Defined Radio for 3G, Artech House, [2] J. Glossner, D. Lancu, J. Lu, E. Hokenek, and M. Moudgill, "A software-defined communications baseband design", IEEE Commun. Magazine, pp , Jan [3] A. Higashi, T. Taguchi, and K. Ohno, "Performance of coherent detection and rake for DS-CDMA uplink channels", Proc. VTC'95, pp , Chicago, Jul [4] Walter Tuttlebee, Software Defined Radio: Enabling Technologies, John Wiley & Sons Ltd., Chichester, [5] X. H Huang, K. L. Du, "A unified software radio architecture", IEEE Signal Processing Workshop, 1262

RF pp. 330-333, Mar. 2001. [6] Joseph Mitola III, Software Radio Architecture, John Wiley & Sons Inc., New York, 2000. [7] D. B.

[8] Hiroshi Harada, Ramjee Prasad, Simulation and Software Radio for Mobile Communications, Artech House, Massachusetts, 2002. [9], " SDR IF ",, 19(11), pp. 85-108, 2002 11. [10] J. G.

12 RF pp , Mar [6] Joseph Mitola III, Software Radio Architecture, John Wiley & Sons Inc., New York, [7] D. B. Chester, "Digital IF technology for 3G systems: An introduction", IEEE Commun. Magazine, vol. 37, no. 2, pp , Feb [8] Hiroshi Harada, Ramjee Prasad, Simulation and Software Radio for Mobile Communications, Artech House, Massachusetts, [9], " SDR IF ",, 19(11), pp , [10] J. G. Proakis, Digital Communication, McGraw- Hill, New York, [11], " ",, 13(3), pp , [12], " ",, [13], " ",, : ( ) : ( ) : ( ) : LIG ( ) [ 주관심분야 ] Microwave Active/Passive Circuit, Radar System : ( ) : ( ) : LIG ( ) [ 주관심분야 ], 1263

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<313920C0CCB1E2BFF82E687770> 韓國電磁波學會論文誌第 19 卷第 8 號 2008 年 8 月論文 2008-19-8-19 K 대역 브릭형 능동 송수신 모듈의 설계 및 제작 A Design and Fabrication of the Brick Transmit/Receive Module for K Band 이 기 원 문 주 영 윤 상 원 Ki-Won Lee Ju-Young Moon