PSpice User Manual
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1 Cadence PSD 14.2 / PSpice Training Guide Schematic Capture Capture CIS Orcad Capture Digital/Analog/Mixed-Signal Simulation NC-Sim PSpice PSpice Advanced Analysis Option Routing SPECCTRA PCB Layout Allegro Orcad Layout Design Suites PCB Design Expert PCB Design Studio Slide 1 OrCAD PSpice, Release 9.2.3
2 1 Start Capture New PSpice project New PSpice design Capture Menu & Icon Tool palette Understand the project structure Project Manager Common file extensions Entering a Simulation Design Place Parts & Part Browser Draw Symbols Edit Properties & Display Value Unit Library Place Power & Ground Passive device & PSpice Template.model Device Type.Subckt define / Subcircuit DC Bias Point & Simulation profile Schematic Design Create Simulation profile (DC Bias point) Run PSpice & Error message Bias Display & Output result Create Simulation profile (DC Sensitivity Analysis) Create Simulation profile (DC Sweep Analysis) Markers Customizing the Probe Display PSpice Netlist & Simulation Flow DC Bias Error Small Signal DC Gain.TF Create Simulation Profile / output result PSpice A/D Probe Window AC Sweep Analysis Schematic Design (only AC source) Create AC Simulation profile (Noise analysis) Use advanced markers / Run PSpice View result 1 (Noise Analysis) View result 2 (Noise Analysis) Slide 2 OrCAD PSpice, Release 9.2.3
3 2 Trace Expression Impedance Analysis Simulating a Text Circuit File Create a PSpice circuit file in the Text Editor Understand the structure of a circuit file Understand the structure of a subcircuit Perform an analysis on a text circuit file View the result in the probe window Stimulus Edit Analog Source Digital Source Transient Analysis Schematic Design (Source setup) Setting up Transient Analysis Foruier Analysis Run PSpice & View the results in Probe Parametric Analysis Transient Analysis & View results Slide 3 OrCAD PSpice, Release Param setting 1 (Schematic). Param setting 2 (Simulation Setting) Performance Analysis & View result Type of Device parameter Model Editor Way to edit a Model PSpice Model edit (14.xx & Web patch) Local and Global model library Model Editor Structure Edit a Model MC Analysis Device and Lot Tolerances Setting up MC / WC Analysis Viewing Output File, Probe Plots and Histograms Example Creating Subcircuits from a Schematic Types of Simulation Models Create subcircuit from a Schematic Example
4 3 Creating a PSpice Part Drawing tools Creating a part Required properties for Simulation use to model editor PSpice Template Part properties User properties PSpice Template Edit PSpice Template Design Structure (Hierarchical / Flat Design) Place hierarchical block Place hierarchical pin Hierarchical design structure Flat design structure Design structure review Capture symbol Analog Behavioral Models Hot Key Digital Analog Behavior Modeling library Expression ABM (E device : E Value) ABM (E device : E FREQ) How Digital Components are Modeled Place Digital part Wiring digital part Digital Power and Ground Setting up digital simulation Viewing Digital Results Buses Slide 4 OrCAD PSpice, Release 9.2.3
5 Not Course Object MS Office & OS Circuit Design VHDL library VHDL Simulation tools Capture CIS (Orcad( PCB process) PSpice Advanced Analysis Option Advanced Analysis library (Use Model Editor).PRP Stress parameter format Sensitivity Analysis Circuit Optimizer (+3 Optimizer engines) Monte carlo Analysis Smoke(Stress) Analysis Slide 5 OrCAD PSpice, Release 9.2.3
6 SPICE? PSpice?? Slide 6 OrCAD PSpice, Release 9.2.3
7 Start Capture New PSpice project New PSpice design Capture Menu & Icon Tool palette Understand the project structure Project Manager Common file extensions Slide 7 OrCAD PSpice, Release 9.2.3
8 New PSpice project File menu >> New >> Project PSpice Project Capture.. Note :: Slide 8 OrCAD PSpice, Release 9.2.3
9 New PSpice Design File menu >> New >> Project Analog or or Mixed A/D A/D PSpice Project Slide 9 OrCAD PSpice, Release 9.2.3
10 Capture Menu & Icon Menu bar PSpice Tool bar Tool bar Part Editor tool bar Slide 10 OrCAD PSpice, Release 9.2.3
11 Tool Palette Tool Palette : Design icon Slide 11 OrCAD PSpice, Release 9.2.3
12 Understand the project structure Project Manager Schematic Editor Session Log Menu // Window // session log log Slide 12 OrCAD PSpice, Release 9.2.3
13 Project Manager Slide 13 OrCAD PSpice, Release 9.2.3
14 Common file extensions.opj - OrCAD Project file.dsn - Design file.dbk - Design backup file.net - Simulation netlist.als - alias file.sim - Simulation profile.dat - Probe data file.out - Simulation output file.olb - Symbol library.lib - Simulation model library Slide 14 OrCAD PSpice, Release 9.2.3
15 Entering a simulation Design Place Parts Part Browser Draw Symbols Edit Property Display Value Place Net alias Unit Place Power Place Ground Slide 15 OrCAD PSpice, Release 9.2.3
16 Place Part Capture Menu <P> Toolbar button Place>Part menu or or Slide 16 OrCAD PSpice, Release 9.2.3
17 Part Browser Slide 17 OrCAD PSpice, Release 9.2.3
18 Design Tool Menu : Tool Palettes Draw symbols Rotated Mirrored Slide 18 OrCAD PSpice, Release 9.2.3
19 Edit Property display value Slide 19 OrCAD PSpice, Release 9.2.3
20 Design Tool Menu : Tool Palettes Place Net alias Wire Place >> Net Alias. or or <N> key : %, &, ~, *, and spaces. Wire Netlist,. Slide 20 OrCAD PSpice, Release 9.2.3
21 Design Tool Menu : Tool Palettes Unit Slide 21 OrCAD PSpice, Release 9.2.3
22 Place Power Capture Menu Place>power <F> Toolbar button or or Capture Symbol library Power Symbol Net alias, Page. Source.olb. 4, library / capsym.olb. VCC VCC_ARROW VCC_BAR VCC_WAVE Slide 22 OrCAD PSpice, Release 9.2.3
23 Place Ground Capture Menu Place>Ground <G> Toolbar button or or PSpice 0, Capsym.olb PCB Netlist Symbol. 0 PSpice Netlist 0, Floating. Slide 23 OrCAD PSpice, Release 9.2.3
24 Library Passive device PSpice Template.Model defile.model Device Type.Subckt define / Subcircuit.Subckt example / subcircuit Slide 24 OrCAD PSpice, Release 9.2.3
25 Design Tool Menu : Tool Palettes Passive Device 1 R1 2 Symbol library 1k L uH C n Model library Slide 25 OrCAD PSpice, Release 9.2.3
26 Design Tool Menu : Tool Palettes PSpice Template R Device PSpice Template <analog.olb R> 1 R1 2 1k Slide 26 OrCAD PSpice, Release 9.2.3
27 Design Tool Menu : Tool Palettes. Model define Slide 27 OrCAD PSpice, Release 9.2.3
28 Design Tool Menu : Tool Palettes. Model <model name> name> Slide 28 OrCAD PSpice, Release 9.2.3
29 Design Tool Menu : Tool Palettes Device Type Slide 29 OrCAD PSpice, Release 9.2.3
30 Design Tool Menu : Tool.Subckt Palettes define / Subcircuit General form: form: SUBCKT <name> [node]* [OPTIONAL: +<<interface node>=<default value>>*] +[PARAMS: <<name>=<text value>>*] Subcircuit definition.ends.ends Slide 30 OrCAD PSpice, Release 9.2.3
31 Design Tool Menu : Tool.Subckt Palettes example / Subcircuit Slide 31 OrCAD PSpice, Release 9.2.3
32 Design Tool Menu DC : Tool Bias Palettes Point & Simulation profile Schematic Design Create Simulation profile (DC Bias point.op) Run PSpice Error message Bias Display & Output result Create Simulation profile (DC Sensitivity Analysis.SENS) Create Simulation profile (DC Sweep Analysis.DC) Markers Customizing the Probe Display PSpice Netlist & Simulation Flow DC Bias Error1,2 Small-signal DC gain.tf Create Simulation profile / output result PSpice A/D Probe Window Slide 32 OrCAD PSpice, Release 9.2.3
33 Design Tool Menu : Tool Palettes Schematic Design 1 1 R1 1k R,, C,, VDC Place // Place part 10V V1 1 2 R2 1k 1 2 C1 1n R,C R,C // Analog.olb VDC // Source.olb Ground Place // Place Ground 0 // source.olb Place // Place Wire Net Net alias Slide 33 OrCAD PSpice, Release 9.2.3
34 Design Tool Menu : Tool Bias Palettespoint Simulation profile Profile PSpice > New Simulation Profile or or Simulation settings Window Analysis tab tab :: bias point PSpice Commands ::.OP.OP Slide 34 OrCAD PSpice, Release 9.2.3
35 Design Tool Menu : Tool Run PalettesPSpice / Error Message PSpice // Run PSpice Or Or Or Or <F11> key key Check Output File File :: Simulation PSpice AD AD Probe Window // View // Output Output File Simulation option, netlist, bias info info.. R_R1 In In Out Out 1 k <error > $ <error > ERROR -- --Missing value DRC Check Create Netlist Bias calculation Simulation option Slide 35 OrCAD PSpice, Release 9.2.3
36 Design Tool Menu : Tool Palettes Bias Display PSpice // Bias points // Enable bias Or Or Slide 36 OrCAD PSpice, Release 9.2.3
37 Design Tool Menu : Tool Palettes DC Sensitivity Analysis Profile PSpice > New Simulation Profile or or Simulation settings Window Analysis tab tab :: bias point Output Option Perform Sensitivity Analysis (.SENS) Output Box V(R2) Slide 37 OrCAD PSpice, Release 9.2.3
38 Design Tool Menu : Tool Run Palettes PSpice / Output result PSpice // Run PSpice or or or or <F11> key key Slide 38 OrCAD PSpice, Release 9.2.3
39 Design Tool Menu : Tool DC Palettes Sweep Simulation profile Sweep Variable Voltage Source Current Source Global parameter Model parameter Temperature Ex) Ex) Voltage source :: Source Reference Name V1 Sweep Type Variable Sweep Ex) Ex) V1 0V 10V 0.2V Linear Start Value :: 0,, End Value :: Increment :: Slide 39 OrCAD PSpice, Release 9.2.3
40 Design Tool Menu : Tool Palettes Markers PSpice // Markers // Voltage level or or R1 1k Voltage/level Markers Wire Wire Voltage Deferential Marker Marker 10V V1 V V+ R2 1k 1 2 V- I W 1 2 C1 1n 0 Current Marker Marker Wire Wire Power Power Dissipation Marker Marker Wire Wire Slide 40 OrCAD PSpice, Release 9.2.3
41 Design Tool Menu Customizing : Tool Palettes the Probe Display Change trace colors. Change trace symbols. Trace Trace Properties Change grid grid spacing. Change axis axis display range. Change axis axis configuration. Plot Plot // Axis Axis Setting Setting X Grid Grid & Y Grid Grid Change line line pattern. Change Line width. Trace Trace Properties Add Plot Plot & Add Add Y Axis Plot Plot // Add Add Plot Plot to to Window Plot Plot // Add Add Y Axis Slide 41 OrCAD PSpice, Release 9.2.3
42 PSpice A/D Probe Window Trace Trace Menu Menu Plot Plot Menu Menu Output Output Window Simulation Status Status Window Output Output File File Simulation result result Simulation Queue Queue Edit Edit Simulation Setting Setting Slide 42 OrCAD PSpice, Release 9.2.3
43 PSpice A/D Probe Window V V(1) 2V V(2) I(R2) 4V W(R2) 6V 8V 10V V_V1 <Axis <Axis Setting> Probe Probe Window Axis,, Axis Axis Setting Open Open Axis Axis Tab Tab :: X,, Y Axis Axis Data Data Range, Range, Scale, Scale, Fourier, Performance Grid Grid Tab Tab :: X, X, Y Grid Grid Spacing, Grid Grid <Data Copy> Trace Trace Name Ctrl Ctrl + C C X X,, Y Data Point Copy,, Point Setting Sweep Sweep type Sweep Incremental Value list list Point Copy,, Data Window Word Word Copy Copy Graphic Copy Probe Probe Window Menu Window // Copy Copy to to Clipboard Background Graphic Slide 43 OrCAD PSpice, Release 9.2.3
44 PSpice A/D Probe Window Menu // Trace // Add Trace,, Function Trace Trace Expression R1 I(R1)*(V(Input)-V(Output)),, Expression I(R1)*(V(Input)-V(Output));Power_R1 Probe Probe Window Power_R1 10*log10(v(inoise)*v(inoise)/8.28e-19);Noise_Figure Display Slide 44 OrCAD PSpice, Release 9.2.3
45 Design Tool Menu PSpice : Tool PalettesNetlist & Simulation Flow DRC(Design Rule check) Checking for for Unconnected Nets Checking for for Invalid References Checking for for Duplicate References Create Netlist ** source ABC R_R k 1k ** ** R_R1 +node node Value R_R k 1k C_C n 1n V_V V 10V ** ** V_V1 +node node Value Bias Point Calculation Slide 45 OrCAD PSpice, Release 9.2.3
46 Design Tool Menu : Tool Palettes DC Bias Error 1 10V V1 R1 1k C1 1n error L1 1 2 C2 1n 10uH C3 1n R2 1k ERROR -- --Node N00683 is is floating ERROR -- --Node N00723 is is floating DC Capacitor Open error floating.. R1 C1 error L1 1 2 C3 10V V1 1k 1n R3 1G C2 1n 10uH 1n R2 1k ,, -,, Error PSpice Open Short Slide 46 OrCAD PSpice, Release 9.2.3
47 Design Structure DC Bias Error 2 ERROR -- --Voltage source and/or inductor loop loop involving V_V2 You You may may break the the loop loop by by adding a series resistance L1 R1 L uH uH 0Vdc V1 0Vdc V1 0 0 R2 1G C1 1n C1 1n I1 0Adc I1 0Adc 0 Slide 47 OrCAD PSpice, Release
48 Design Management : Manager Small-Signal Tool DC Gain R2 10K 1Vdc 0 V1 R1 1k 3 2 R4 1k V V VCC ua741 U2 7 V+ 5 + OS2-4 VEE OUT OS1 V R3 1k VCC V2 0 VEE V3-15V 0 0 Slide 48 OrCAD PSpice, Release 9.2.3
49 Design Transfer Management : Manager Function Tool setting / Output Result PSpice Probe Window // View View // Output SMALL-SIGNAL CHARACTERISTICS V(R_R3)/V_V1 = E+01 INPUT RESISTANCE AT AT V_V1 = 9.999E+02 OUTPUT RESISTANCE AT AT V(R_R3) = E-03 Slide 49 OrCAD PSpice, Release 9.2.3
50 Design Management Tool Menu : Tool : Manager PalettesAC Tool Sweep Analysis Schematic Design (only AC Source) Create AC Simulation profile (Noise analysis) Use advanced markers / Run PSpice View result ; use toggle cursor Use measurement result View result 1 (Noise Analysis) View result 2 (Noise Analysis) Trace Expression Probe Window Impedance Analysis Run PSpice & View result Slide 50 OrCAD PSpice, Release 9.2.3
51 Design Management : Manager Tool Schematic Design Place Part >> Source.olb >> VAC 1Vac 0Vdc 1 V1 R1 1 10k 2 R2 100meg C n 0 Cutoff frequency 1/2*pi*R*C,,,, Opamp Slide 51 OrCAD PSpice, Release 9.2.3
52 Design Create Management : Manager Simulation Tool profile (Noise Analysis) PSpice >> New Simulation profile >> AC Sweep / Noise.. End End Frequency sweep Decade Point Noise Noise I/V I/V Source Source :: Noise Reference name name Interval Interval : : Hz..,, (Frequency Response,Noise) Slide 52 OrCAD PSpice, Release 9.2.3
53 Use Advanced Marker / Run PSpice 1 R1 1 10k 2 2 VP VDB 1Vac 0Vdc V1 R2 100meg C n 0 Slide 53 OrCAD PSpice, Release 9.2.3
54 Design Management View : Manager Result Tool ; use toggle cursor Slide 54 OrCAD PSpice, Release 9.2.3
55 Design Management : Manager Use Tool measurement results Slide 55 OrCAD PSpice, Release 9.2.3
56 Design Management View : Manager Result Tool 2 (Noise Analysis) Slide 56 OrCAD PSpice, Release 9.2.3
57 Design Management View : Manager Result Tool 2 (Noise Analysis) Slide 57 OrCAD PSpice, Release 9.2.3
58 Design Management : Manager ToolTrace Expression TOTAL,, Trace Add Expression Integral = S( S( )) Root Root = SQRT( )) Multi Multi = ** Noise Variables = PSpice Help Help menu Noise Analysis,, Function R1 I(R1)*(V(Input)-V(Output)),, Expression I(R1)*(V(Input)-V(Output));Power_R1 Probe Window Power_R1 10*log10(v(inoise)*v(inoise)/8.28e-19);Noise_Figure Display Trace Expression Slide 58 OrCAD PSpice, Release 9.2.3
59 Design Management : Manager Tool Probe Window Menu // View View // Zoom Fit Fit :: Auto Auto Range In In :: Out Out :: Area Area :: Pan Pan New New Center :: Menu // Plot Plot // Label Plot Menu // Trace // Cursor Display ::,, Probe Cursor Display A1 A1 Cursor A2 A2 Cursor Dif A1 A2 Peak Peak Mix,, Max Slide 59 OrCAD PSpice, Release 9.2.3
60 Impedance Analysis +- V2 DC = 0 +- V3 DC = 0 +- V4 DC = 0 +- V5 DC = 0 1Vac 0Vdc V1 1 R1 50 L1 5m 1 R2 50 L2 10m 1 R3 50 L3 15m 1 R4 50 L4 20m 2 C1 1u 2 C2 1u 2 C3 1u 2 C4 1u 0 Slide 60 OrCAD PSpice, Release 9.2.3
61 Run PSpice / View result Slide 61 OrCAD PSpice, Release 9.2.3
62 Design Management Tool Menu : Tool : Simulating Manager Palettes Tool a Text Circuit File Create a PSpice circuit file in the Text Editor. Understand the structure of a circuit file. Understand the structure of a subcircuit. Perform an analysis on a text circuit file. View the results in the Probe Window. Slide 62 OrCAD PSpice, Release 9.2.3
63 Design Management Tool Menu : Tool : Manager PalettesRunning Tool Simulation Slide 63 OrCAD PSpice, Release 9.2.3
64 Design Management Tool Menu : Tool : Manager PSpice Palettes Tool Circuit File Format Title line - Comment by default. Circuit Description Device instantiation.slide 40 Model definitions Slide 25 Subcircuit definitions Slide 28 Simulation controls Slide 30.AC,.DC,.TRAN.Probe.Options.After.END statement Slide 64 OrCAD PSpice, Release 9.2.3
65 Design Management Tool Menu : Comments Tool : Manager Palettes Tool within a Circuit File Any line beginning with an asterisk * is a comment. * This line is a comment and would not be simulated. semi-colon anywhere in a line makes the remainder of the line a comment. R k ; this is added only for stubbing. Slide 65 OrCAD PSpice, Release 9.2.3
66 Design Management : Manager Tool Stimulus Edit Simulation profile for Transient Analysis Analog Source Sinusoidal Single Frequency FM Exponential Piecewise Linear (PWL) Piecewise Linear (PWL_File) Use ABM(Analog Behavior Modeling) Use E device Use parameter Digital part SourceSTM.olb Slide 66 OrCAD PSpice, Release 9.2.3
67 Source V I Sin Simulation profile for Transient,,,, General Setting :: Transient Monte Carlo // Worst Case ::.. Parametric Sweep :: Temperature (Sweep) :: General Setting Save Save Bias Bias Point Point :: Bias Bias Point Load Load Bias Bias Point Point :: Load Run Run to to time time :: Start Start saving data data after after :: Maximum Step Step :: Step Step size Skip Skip the the initial transient ::,, Slide 67 OrCAD PSpice, Release 9.2.3
68 Source V I Sin Sinusoidal V1 V1 VOFF = 0.4V 0.4V VAMPL = 1V 1V DF DF = FREQ = 5Khz 5Khz PHASE = TD TD = 1ms 1ms R1 R1 10meg 0 Slide 68 OrCAD PSpice, Release 9.2.3
69 Source SFFM Single frequency FM V1 V1 VOFF = 0.4V 0.4V VAMPL = 1V 1V DF DF = FREQ = 5Khz 5Khz PHASE = TD TD = 1ms 1ms R1 R1 10meg 0 Voff=offset Vampl=amplitude Fc=Frequency Carrier Fm=Frequency Modulation MOD=Modulation Index Slide 69 OrCAD PSpice, Release 9.2.3
70 Source Exp Exponential V1 V1 = 1 V2 V2 = 5 V2 V2 TD1 TD1 = 0.5m 0.5m TC1 TC1 = 0.1m 0.1m TD2 TD2 = 1.5m 1.5m TC2 TC2 = 1m 1m R1 R1 10meg 10meg 0 TD1 TD1 = 1 Time Delay TC1 TC1 = 1 1 TD2 TD2 = 2 Time Delay TC2 TC2 = 2 2 Slide 70 OrCAD PSpice, Release 9.2.3
71 Source Pulse PULSE V3 V3 V V1 V1 = 1 V2 V2 = 5 TD TD = 1m 1m TR TR = 0.1m 0.1m TF TF = 0.3m 0.3m PW PW = 0.5m 0.5m PER PER = 2m 2m R1 R1 10meg 0 V1,V2 = Pulse Offset,Peak Value TD TD = Time Time Delay TR TR = Rise Rise Time Time TF TF = Fall Fall Time Time PW PW = Pulse Width PER PER = Period Slide 71 OrCAD PSpice, Release 9.2.3
72 Source PWL(Piece Wise Linear) Piecewise Linear(PWL) Tn Tn = Time Time T1 T1 = 0 T2 T2 = 0.5m 0.5m V4 V4 T3 T3 = 1m 1m T4 T4 = 2m 2m T5 T5 = 3m 3m T6 T6 = 4m 4m T7 T7 = 4.5m 4.5m T8 T8 = 5m 5m Vn Vn = Voltage Voltage V1 V1 = V2 V2 = 1 V3 V3 = -1-1 V4 V4 = -3-3 V5 V5 = 2 V6 V6 = 3 V7 V7 = V8 V8 = R1 R1 10meg 0 V3 VPWL V7 VPWL_RE_FOREVER V6 VPWL_FILE <FILE> V4 VPWL_F_RE_FOREVER <FILE> Part Part Name File source File File :: File : : Property Editor V8 VPWL_RE_N_TIMES V5 VPWL_F_RE_N_TIMES <FILE> Note Note :: File Slide 72 OrCAD PSpice, Release 9.2.3
73 Source PWL(Piece Wise Piecewise Linear) Linear(PWL_File) V6 VPWL_FILE <FILE> Tn=Time Vn=Voltage PWL_FILE Source <File> C:\ Source TSF TSF :: Time Time Scale Scale Factor Factor VSF VSF :: Voltage Voltage Scale Scale Factor Factor Slide 73 OrCAD PSpice, Release 9.2.3
74 Source (AMB Use - MULT) to ABM(Analog Behavior Modeling) SUM DIFF ABM.olb MULT Slide 74 OrCAD PSpice, Release 9.2.3
75 Source (AMB - Evalue) Use to ABM(E Device) Evalue Expression = IF( IF( )<0,0,5) :: 0 0, 0, 5 5 Evalue Evalue :: Slide 75 OrCAD PSpice, Release E1 IN+ OUT+ IN- OUT- EVALUE V(%IN+, %IN-) G1 IN+ OUT+ IN- OUT- GVALUE V(%IN+, %IN-) Gvalue Gvalue ::
76 Source (Parameter - Special) Use to parameter Parameter Source Setting Special.olb Param,, Value.. VDC(V1) DC value.. V1 = 0 V2 = {Vpeak} TD = {delay} TF = 1u TR = 1u PW = {duty*1/frequency} PER = {1/frequency} V1 0 R1 1k PARAMETERS: Vpeak = 1 frequency = 1K duty = 0.2 delay = 0.2m ) ) = R2 R2 // R1+R2 R1 R2 20%, 50K 50K,, Parameter Load = 50k 50k Ratio Ratio = 0.2,, Schematic R1 R2,, R1 R1 Value = {load*(1-ratio)} R2 R2 Value = {load*(ratio)} Pulse Wave,, Pulse Freq Duty Attribute,,,, Slide 76 OrCAD PSpice, Release 9.2.3
77 Digital Source Digital part OrCAD OrCAD PSpice PSpice source source.lib,,,, source DigClock CLK STIM1 S1 STIM8 S8 DigClock digital signal source digital digital signal COMMAND1 COMMAND2 COMMAND3 Properties Editor 0s 0s 0 1s 1s 1 2s 2s 0 COMMAND1 COMMAND2 COMMAND3 STIM8 8 bit 8bit Signal source 0s 0s s 1s s 2s FileStim1 F1 FILENAME = file1.stm SIGNAME = signal FileStim1 PWL PWL,, Digital Digital Signal Bit Bit.. Bus Wire Wire Wire Bit Signal Name DSTM4 F1 FILENAME = SIGNAME = ^ Slide 77 OrCAD PSpice, Release 9.2.3
78 Stimulus Editor SourceSTM.olb S S V9 Implementation = I1 Stimulus Editor (StmEd) transient analog digital sources Stimulus Editor Source Implementation,, Implementation name,,. VSTIM,, ISTIM, DIGSTIM1 ~ Sourcstm.lib,, Implementation = DSTM1 S1 DSTM2 S2 DSTM3 S32 Implementation = Implementation = Implementation = Sin Sin Wave Stimulus Open VSTIM Place/Part Sourcstm.olb VSTIM EDIT EDIT // PSpice Stimulus Stimulus Editor Open New New Stimulus SIN SIN radio radio Name SIN Implementation Name OK OK Sin Sin Source (0 (01 60) 60) OK OK 60Hz 60Hz sine sine sin sin wave File File Save Save toolbar button VSTIM Implementation = SIN Update,, Stimulus Editor Menu // Stimulus // New Slide 78 OrCAD PSpice, Release 9.2.3
79 Design Management : Manager Tool Transient Analysis DC,, L C Schematic design (Source Setup) Create Simulation profile(transient Analysis) Run PSpice & View result Create Simulation profile(fourier Analysis) Run PSpice & View result Slide 79 OrCAD PSpice, Release 9.2.3
80 Schematic design (Source Setup) L u L R1 2 D1 Dbreak D2 Dbreak VOFF = 0 VAMPL = FREQ = 60 V1 1m 1m IC = C1 1m 1 2 R D4 Dbreak D3 Dbreak -- :: 120V, 60Hz, 0V 0V offset -C1 :: value = 1m, 1m, IC IC = 170V 170V ( ( )) -- Diode Breakout.olb Dbreak Breakout.olb Device type,, implementation Name Schematic,, Ideal Model parameter Slide 80 OrCAD PSpice, Release 9.2.3
81 Transient Setup Transient Analysis :: Slide Slide 81 OrCAD PSpice, Release 9.2.3
82 Run PSpice / View Result C1 170V L1 1 :: C1 1 R2 2 2 : :,, R1 R1 R1 + Slide 82 OrCAD PSpice, Release 9.2.3
83 Fast Fourier Transform PSpice FFT(Fast Fourier Transform) (Fourier Analysis) FFT Data,,,, FFT,,,,,, Output,,,,,,,,,, THD Trace >> >> Fourier Slide 83 OrCAD PSpice, Release 9.2.3
84 Fourier Analysis / Run PSpice Center :: ( )) Number of of :: Output :: Run RunPSpice >> >> Probe Window View View >> >> output file file Fourier Analysis Data Data Fourier components of of Transient Response (Output Variable) ~~~~ Slide 84 OrCAD PSpice, Release 9.2.3
85 View Output :: -- RMS Slide 85 OrCAD PSpice, Release 9.2.3
86 Design Management : Manager Parametric Tool Analysis Transient Analysis View Results.Param setting 1 (Schematic Entry).Param Setting 2 (Simulation setting) Run PSpice & View Result Performance Analysis & View Result Type of Device parameter Temperature of Resistor (Device Modeling) Temperature Sweep (Simulation Setting) Temperature Sweep for diode Slide 86 OrCAD PSpice, Release 9.2.3
87 Transient Analysis Transient analysis Time Domain simulation.. Probe Oscilloscope,, X voltage current Y IPWL I1 T1 = 0 T2 = 10m T3 = 10.1m I1 = 0 I2 = 0 I3 = R L1 1 I 1 2 C1 1 IPWL (0 (00, 0, 10m 10m 0, 0, 10.1m 1) 1) R L C Simulation setting.tran m 20m L1 2 Marker R1 R1 R1 R1 = ,, 1,, ohm 0 Slide 87 OrCAD PSpice, Release 9.2.3
88 View result Slide 88 OrCAD PSpice, Release 9.2.3
89 .Param Setting 1 (Schematic Entry) Component Value {variable}.. :: Component Value { { }} Param Variable // // Special.olb >> >> Param Parametric Sweep Option >> >> Global parameter >> >> Variable Sweep type type Component Value Value {{ }} Component Value { Variable } } Parameter Special.olb >> >> Param Schematic {Val} Val New New Column 1 2 PARAMETERS: val = 1 R1 {val} Slide 89 OrCAD PSpice, Release 9.2.3
90 .Param Setting 2 (Simulation Setting) Parametric { } } Global parameter,, Sweep Variable Type Voltage Source,, Current Source,, Model parameter,, Temperature Slide 90 OrCAD PSpice, Release 9.2.3
91 Run PSpice & View result R1 R1 : : 0.5ohm ~ 1.5ohm 0.1ohm Trace Expression ::-I(L1)@3 Trace Expression ::-I(L1)@10 Slide 91 OrCAD PSpice, Release 9.2.3
92 Performance Analysis 1 Goal Goal Function // Measurements >> >> Performance Analysis AC AC Cutoff frequency Function Measurements,,,,.. < > 1 1 Performance Analysis (Probe Window) Trace // Performance Analysis Performance Analysis Ok Ok : : Goal Goal Function Trace Add Goal Goal Function Wizard : : Step >> >> More Slide 92 OrCAD PSpice, Release 9.2.3
93 Performance Analysis Wizard Goal Goal Function Ok Ok Plot X Parametric Sweep >> >> More Slide 93 OrCAD PSpice, Release 9.2.3
94 Performance Analysis 3 Risetime_StepResponse(trace name) Performance analysis Wizard OK 4 Goal Goal Function Wizard Goal Goal Function Function L Choose a Measurement Rise Time Wave Rising Time 10% 90% 90% Point Point Goal Goal Function,, Measurements Next Slide 94 OrCAD PSpice, Release >> >> More
95 Performance analysis : Step3 Performance Analysis 4 Goal Goal Function Evaluation Simulation -I(L1) Name of of trace trace to to search Trace Name Trace Name Slide 95 OrCAD PSpice, Release 9.2.3
96 Performance analysis : Step3 View result Point P1 P1 :: Rise Point Point P2( Rise Point) P3( Rise 10% 10% )) P4( Rise 90% 90% ) Plot Plot Display Y P3 P3 Point P4 Rval Rval Risetime_StepResponse(-I(L1)) Slide 96 OrCAD PSpice, Release
97 Type of Device parameters Model Parameter parametric Analysis,, Power Diode D1n4002 Break down voltage 100V(4002), 300V(4003), 600V(4004) BV D1 D1N4002 *** *** Power Diode *** ***.MODEL D1N4002 D (IS=14.11E-9 N=1.984 RS=33.89E-3 IKF=94.81 XTI=3 + EG=1.110 CJO=51.17E-12 M=.2762 VJ=.3905 FC=.5 ISR=100.0E-12 + NR=2 BV=100.1 IBV=10 TT=4.761E-6).model D1N4003 ako:d1n4001 D(Bv=300) ;; use use non-rep. peak peak voltage.model D1N4004 ako:d1n4001 D(Bv=600) ;; use use non-rep. peak peak voltage Slide 97 OrCAD PSpice, Release 9.2.3
98 Temperature of Resistor(Device Modeling) Sweep R L C,, Datasheet,, TC1 TC2 Parameter Value Modeling R*(1+TC1*(T-Tnom)+TC2*(T-Tnom)²) 1000ohm=146, 1Mega ohm=243 2 TC1 TC2 Tnom = 27,, TC1 TC2 Slide 98 OrCAD PSpice, Release 9.2.3
99 Temperature Sweep(Simulation setting) Sweep R L C,, Slide 99 OrCAD PSpice, Release 9.2.3
100 Parametric Analysis (Temperature Sweep) Sweep for diode Vf 2mV // C C Vf Vf Vdc V1 R1 1 Sweep Variable V1 V1 start start value :: 1 1 end end value :: 2 Increment :: 0.01V Option Parametric Value list list ::-100, -100, 0, 0, D1 D1N Slide 100 OrCAD PSpice, Release 9.2.3
101 Design Management : Manager Tool Model Editor Way to edit a model PSpice model editor 14.xx PSpice model editor 14.2 Web patch Local and Global model libraries Referencing a model Editing model parameter Model editor structure1 (Model list) Model editor structure2 (Spec entry) Model editor structure3 ( Parameter table) Edit a Zener voltage Edit a diode model Slide 101 OrCAD PSpice, Release 9.2.3
102 Parametric Analysis (Temperature Ways Sweep) to Edit a Model Model file Device ASCII format,, Simulation Model library Capture Symbol,, Capture Symbol Simulation Capture.. PSpice Template Syntax Simulation Model library Equation Model Model parameter Text Format,, Model Editor Graphic Model Text Slide 102 OrCAD PSpice, Release 9.2.3
103 Parametric Analysis (Temperature PSpice Sweep) Model editor 14.xx Slide 103 OrCAD PSpice, Release 9.2.3
104 Parametric Analysis PSpice (Temperature Model Sweep) editor 14.2 Web patch Device Parameter Window Stress Device,, PSpice Advanced Analysis Parameter Slide 104 OrCAD PSpice, Release 9.2.3
105 Parametric Analysis Local (Temperature and Sweep) Global Model Libraries Global Library Local Library Global Model library :: Global library,, Nom.lib(Master library) Local Model library :: Local Library Design Capture Model Editor Local Model Note Note :: Slide 105 OrCAD PSpice, Release 9.2.3
106 Parametric Analysis (Temperature Referencing Sweep) a Model Breakout part Model Model Name(Implementation Name) Schematic Part Part Name Breakout part Ideal Model Schematic,, Type Device Rbreak Implementation Name Vendor part part D2 Breakout part part Part Part Value D1N4002 Implementation Name R1 Rbreak 1k D1 Dbreak Slide 106 OrCAD PSpice, Release 9.2.3
107 Parametric Analysis (Temperature Editing Sweep) Model Parameter Model parameter Datasheet Parameter,, Bipolar transistor Bf (forward beta) Datasheet forward beta,, datasheet Parameter Diode Bv (Breakdown voltage) datasheet zener voltage Datasheet Device parameter Library Indexing PSpice Index Index,, Index Index Error Error Directory //.. Slide 107 OrCAD PSpice, Release 9.2.3
108 Parametric Analysis Model (Temperature Editor Sweep) Structure (Model list) <Model List List Window> Model Name Schematic part Implementation Name PSpice Device Type Model list Model Name Spec,, Device Type Unknown PSpice VHDL Model Unknown Model Type,, Slide 108 OrCAD PSpice, Release 9.2.3
109 Parametric Analysis Model (Temperature Editor Sweep) Structure (Spec Entry) <Spec Entry Entry window> Spec Spec Entry Entry Window Model list list Window list list Model Spec Plot Device Type Spec Entry Entry Window,, Model Parameter Table Data Data Datasheet Characteristic Curve Slide 109 OrCAD PSpice, Release 9.2.3
110 Parametric Model Analysis (Temperature Editor Sweep) Structure (Parameter Table) <Text parameter Table> Model List Model Spice Parameter Table Table Value,, Spec Spec Entry Window Plot Update Model parameter Default Value Parameter,, Curve parameter Slide 110 OrCAD PSpice, Release 9.2.3
111 Model Editor Edit Zener Voltage 1 0Vdc 0Vdc V1 V1 R1 R1 1k 1k V D1 D1 D1N750 D1N750 0 PSpice model parameter model model Monte Carlo Worst Case Case analysis Slide 111 OrCAD PSpice, Release 9.2.3
112 Model Editor Edit Zener Voltage 2 D1 D1 D1N750.model D1N750 D(Is=880.5E-18 Rs=.25 Ikf=0 Ikf=0 N=1 N=1 Xti=3 Xti=3 Eg=1.11 Cjo=175p M= Vj=.75 Fc=.5 Isr=1.859n Nr=2 Nr=2 Bv=4.7 Ibv=20.245m Nbv= Ibvl=1.9556m Nbvl= Tbv1= u) ** Motorola pid=1n750 case=do gjg gjg ** 1mA, Capture Menu // Edit Edit // Pspice Model Model Editor Model Editor D1N750 BV Set,, BV Breakdown Voltage D1N750 BV 4.7 SET 8.0 Models list Attribute BV 8.0 Capture,, Save Save As As Slide 112 OrCAD PSpice, Release 9.2.3
113 Parametric Analysis (Temperature Sweep) Edit Diode Model <Example Circuit> Dbreak Edit // PSpice Model Model Editor Junction capacitance (1m, (1m, 120p) (1, (1, 73p) 73p) (3.75, 45p) 45p) Reverse leakage (6, (6, 20n) 20n) Reverse breakdown (Vz=7.5, Iz=20m, Zz=5) (LIB) (LIB) File File // Create Capture Part Part (OLB (OLB )) Slide 113 OrCAD PSpice, Release 9.2.3
114 Design Management : Manager Monte Tool Carlo Analysis Statistical analysis The Mean / Standard Deviation Device and Lot Tolerances Setting up MC Analysis Setting up WC Analysis View Result & Histograms Example 1 (Design Entry) Edit a model Run pspice & performance Analysis View result & histogram Example 2 Slide 114 OrCAD PSpice, Release 9.2.3
115 Statistical analysis Monte Carlo Analysis Device Model parameter Tolerance (Random) Device Tolerance LOT LOT Tolerance Data,, Sample ,000 5? %? data:11.960,, ,, ,, ,, ! 5 Sample? Slide 115 OrCAD PSpice, Release 9.2.3
116 The mean / standard deviation 1 5 Sample :11.962, : % 5 Sample 13.53%? sample Sample 13.53% Slide 116 OrCAD PSpice, Release 9.2.3
117 The mean / standard deviation 2 (Sample) ( ) ) 7 AA 7 B B ( a ):5.0 ( a ) :0.05 ( b ):5.0 ( b ):1.0 Slide 117 OrCAD PSpice, Release 9.2.3
118 The mean / standard deviation 3. A A ( ) ) B B A A :: 3 7 a:0.05 b: : a = b 7 :: Slide 118 OrCAD PSpice, Release 9.2.3
119 The mean / standard deviation x1 1 1 x2 2 ( i)= Xi -X 2 x3 3 3 x4 4 4 x5 5 X = 5 (Sum of of Square) "0" "0" S S (N) n n n ( ( ( I) I).).) ( ( (( Xi Xi- - X )= Xi- X =n =n Xi Xi--n X =0 =0 (, (, n Xi Xi = n X )) Slide 119 OrCAD PSpice, Release s = (Xi - X ) 2 /n-1 ( ( ) )
120 Parametric Analysis (Temperature Device Sweep) & LOT Tolerance Device Tolerance :: R L C Part Attribute TOLERANCE DEV Tolerance,, R = 1K 1K DEV DEV = 10% Random 0.9K 0.9K ~ 1.1K 1.1K LOT Tolerance :: R=1K LOT 10% 10%,, DEV DEV : : R L C Part attribute TOLERANCE DEV DEV LOT :: Breakout part Rbreak, Lbreak, Cbreak ) ) MODEL R RES(R=1 LOT=30% DEV=2%) Slide 120 OrCAD PSpice, Release 9.2.3
121 Setting up MC Analysis Monte Monte Carlo Carlo,, Monte Monte Carlo Carlo Output Output Variable : Worst-case/Sensitivity Number of of :: Use Use :: (Sample :: 100, 100, Report Data Data :: 10000) (Guassian, Uniform Distribution) Save Save data data from from :: Random Number :: Random Number (Seed Number) Slide 121 OrCAD PSpice, Release 9.2.3
122 Setting up WC Analysis Vary Vary devices ~ :: Tolerances Limit Limit devices devices to to :: limit limit Save Save data data from from ~ :: limits apply to topspice and and Probe: Analog Analog display display in in Probe Probe traces, traces, or or 2 times times the the number number of of sections, whichever is is greater greater Digital Digital display display in in Probe Probe traces, traces, or or 2 times times the the number number of of sections, whichever is is greater greater Size Size of of a.dat.dat file file 2GB 2GB Number of of analog analog nodes nodes that that can can be be sstored in in a.dat.dat file file 2**31 2**31 (~2,147K) Number of of digital digital nodes nodes that that can can be be stored stored in in a.dat.dat file file 2**15 2**15 (~32K) (~32K) Monte Monte Carlo Carlo analysis 10,000 10,000 runs runs Slide 122 OrCAD PSpice, Release 9.2.3
123 Parametric Analysis (Temperature View Sweep) Result & Histograms Goal function Histograms Text View View // output Slide 123 OrCAD PSpice, Release 9.2.3
124 Monte Carlo Exam1 Example 1 (Design Entry) Monte-Carlo component tolerance.. PSpice,, component library (( Breakout.olb) Breakout part Tolerance Edit R Parameter R=1 R=1 :: DEV=5% :: Device Tolerance LOT=20% :: Edit // PSpice Model Model Editor Slide 124 OrCAD PSpice, Release 9.2.3
125 Passive Component Modeling Edit a model PSpice PSpiceModel Editor Editor (( // Edit Edit // PSpice PSpiceModel )),, Rbreak Properties Editor Implementation Name Model editor Rbreak(Model name) Capture.lib.lib,, Implementation name Slide 125 OrCAD PSpice, Release 9.2.3
126 Monte Carlo Run Exam1 (Simulation PSpice Result) & Performance Analysis Monte Monte Carlo Carlo Setting 10 Uniform Distribution Monte carlo carlo Simulation Parametric Performance,, Histogram Monte Carlo :: Trace // Performance Analysis Slide 126 OrCAD PSpice, Release 9.2.3
127 Monte Carlo Exam1 (Simulation View Result) Result & Histograms Trace Trace // Performance Analysis Goal Goal Function Histogram Mean Sigma : V : V Slide 127 OrCAD PSpice, Release 9.2.3
128 Example 2 Parametric Analysis ( ) Parametric Variable :: Source( ) ) >> >> Parametric -- (Vin) rise-edge trigger,, 1msec Delay V(out) -Delay 1.1 ms, ms, 0.9 ms ms V1 = 0 V2 = {vin} TD = 1m TR = 1n TF = 1n PW = 10m PER = 20m PARAMETERS: R2 = 3.7 R1 = 6.3 vin = 10 vdc = 10 Vin V2 V R11 10k monte1 V C3 0.1u Cbreak R9 {R2} monte1 R {R1} monte V+ 7 ua741 5 VU2 OS2 OUT 6 OS1 V- 1 out {vdc} R13 100k monte1 V3 0 Slide 128 OrCAD PSpice, Release 9.2.3
129 Example 2 Parametric Analysis ( ) V(out) ) ) +,,--5% Parametric Analysis C3 C3 R11 V(out) C3 C3 Dev=5%,, R11 R11 Dev=5% MC MC N Sample :: Distribution :: Uniform R9, R9, R10 5% 2 2 Slide 129 OrCAD PSpice, Release 9.2.3
130 Design Management Creating : Manager Tool Subcircuit from a schematic Types of Simulation Models Create subcircuit from a schematic Create and configuring subcircuit Example (Slide 75 ; Transient Analysis) Slide 130 OrCAD PSpice, Release 9.2.3
131 Types of Simulation Models Type of Simulation Model Text-based model definition Text-based Subcircuit definition Underlying graphical definition (a schematic) Model and Subcircuit definitions + Takes less storage space than a schematic file More difficult to edit Underlying schematic definition Easy to edit the underlying schematic + Allows cross-probing Requires more storage space Requires more configuration management Slide 131 OrCAD PSpice, Release 9.2.3
132 Subcircuit Creating Create Subcircuits from a Schematic To prepare a schematic for conversion to a subcircuit: Add interface ports Remove sources Slide 132 OrCAD PSpice, Release 9.2.3
133 Subcircuit Creating Create and Configuring the Subcircuit 1 From Project Manager Tools > Create Netlist. 2 PSpice tab. 3 Subcircuit Format Netlist Netlist Slide 133 OrCAD PSpice, Release 9.2.3
134 Subcircuit Example Create (Slide 75 : Transient Analysis) :: Power Source Port Subcircuit Format Netlist Tool Tool // Create Netlist // PSpice Tab Tab Model editor Capture Symbol File File // Create Capture Part Part Capture Symbol Edit Edit File File // open open library // OLB OLB Part Part Edit Edit Simulation Simulation Setting // library tab lib Run Run Simulation Slide 134 OrCAD PSpice, Release 9.2.3
135 Completed subcircuit PARAMETERS: RMS = 120 Peak = {RMS*Sqrt(2)} load = L2 L2 U2 U Out+ IN+ IN+ OUT+ 1mH V2 V2 RLOAD1 FREQ = VAMPL = {Peak} VOFF = 0 {load} Out- IN- IN- OUT- SUBCKT_FULLWAVE_RECT Slide 135 OrCAD PSpice, Release 9.2.3
136 Design Management : Manager Creating Tool a PSpice Part Drawing Tools Creating a Part Required properties for Simulation Use to Model Editor Slide 136 OrCAD PSpice, Release 9.2.3
137 Subcircuit Create Drawing Tools Select Place Polyline Place IEEE Symbol Place Pin Place Pin Array Place Line3 Place Rectangle Place Ellipse Place Arc Place Text Slide 137 OrCAD PSpice, Release 9.2.3
138 Subcircuit Create Creating a Part Part Body Body Part Part Property display Required Properties for Simulation Part PSpice Template IMPLEMENTATION TYPE IMPLEMENTATION Slide 138 OrCAD PSpice, Release 9.2.3
139 Subcircuit Create Use to Model Editor Model Editor File File // Create Capture part part (Export to to capture part part library) Create part part for for library Error Error Capture Part Part open open Edit Edit part part Save Save Simulation setting Library Slide 139 OrCAD PSpice, Release 9.2.3
140 Design Management : Manager ToolPSpice Template Part Properties User Properties PSpice Template Edit PSpice Template Slide 140 OrCAD PSpice, Release 9.2.3
141 Part Properties Part properties Pop-up Pop-up Menu Menu Part Part Properties Column Column Display Display Format Format Properties Type Type Filter Filter Area Area Area Area Slide 141 OrCAD PSpice, Release 9.2.3
142 Part Editor User properties Analog.olb R1 Discrete.olb R2 1k R R1 Analog.olb R2 Discreate.olb Property Editor R1 R2 PSpice Template R2 R1 PSpice Template PSpice Template Part Editor,,.. Part Part Editor Editor Menu Menu Bar Bar // Options Menu Menu Bar Bar / / Options / / Part Part Properties Slide 142 OrCAD PSpice, Release 9.2.3
143 Part User Properties User properties R User Properties Implementation ::,, implementation Pin Pin Number Pin Pin Name Name Part Part Reference :: R? R? R1,R2 Schematic PSpice Template :: PSpice Netlist Part Part library Syntax Pin Pin Name & Pin Pin number. PSpice Netlist Node Reference Pin Name PCB Netlist Pin Pin Number Pin Pin Number Visible Value True Resistor < 1 2 > Pin Pin Name Visible Value True Resistor Slide 143 OrCAD PSpice, Release 9.2.3
144 PSpice Template PSpice Template PSpice PSpiceTemplate PSpice Template Part netlist entry PSpice syntax,, PSpice A/D Capture,, PSpice Template PSpice PSpiceTemplate Translate )) R R PSpice Template R^Refdes %1 %1%2 %2@Value PSpice Template Translate Netlist R_R k 1k :: R1(R^Refdes) 1 (%1) 2 (%2),, (@Value) 1K 1K.. Template PSpice Template PSpice Template Pin Pin name Order.model.subcircuit Device implementation name PSpice A/D.. (Bipolar transistor Q) Q) Simple resistor (R) (R) example <Spice parameter,, Device > R Orcad Capture REFDES VALUE Slide 144 OrCAD PSpice, Release 9.2.3
145 PSpice Template PSpice Template Model Model property example Template %1 %1%2 Translation X_U1 0 vcc vcc7411,, MODEL Model property X_U1 0 vcc Template R^@refdes %1 %1%2 %2?tolerance \n.model R^@refdes R=1 R=1 Dev=@tolerance,, Tolerance R&@refdes %1 %1%2 %2@@value -or- -or-r_r1 0 vcc vcc5k,, Tolerance Template Translation Netlist Translation R^@refdes %1 %1%2 %2 R^@refdes R=1 R=1 Dev=@tolerance Or Or R_R1 0 vcc vccr_r1 5k 5k.model R_R1 R=1 R=1 Dev=5 Slide 145 OrCAD PSpice, Release 9.2.3
146 PSpice Template Example Edit PSpice Template M1 MbreakN M2 MbreakN Symbol N-channel MOSFET M1 Bulk Bias 0,, M2 Bulk Bias Symbol M2 PSpice Template %d %d%g %g%s %s%b \n+ \n+ \n+ \n+ \n+ \n+ \n+ \n+ M1 PSpice Template %d %d%g %g%s %s %s \n+ \n+ \n+ \n+ \n+ \n+ \n+ \n+ Symbol Spice Parameter,, PSpice Template Syntax Bulk Bulk Template syntax,, Model Editor Mos Type Capture Part 3 (S, G, G, D) Mosfet Default,, 4 (S, G, G, D, D, B) Mosfet,, PSpice Template,, Part Part Editor Bulk Bulk Slide 146 OrCAD PSpice, Release 9.2.3
147 PSpice Template Example Edit PSpice Template M1 M2 MbreakN MbreakN M1 PSpice Template %d %d%g %g%s %s %s \n+ \n+ \n+ \n+ \n+ \n+ \n+ \n+ @MODEL?/L?/L\n+ L Model parameter Capture Schematic Parameter MOSFET Spice parameter,, Capture Schematic Spice parameter Breakout.olb,, Slide 147 OrCAD PSpice, Release 9.2.3
148 Design Design Management : Manager Structure Tool (Hierarchy, Flat Design) Place hierarchical block Place hierarchical pin Hierarchical design structure Flat Design structure Design structure review Capture Symbol Slide 148 OrCAD PSpice, Release 9.2.3
149 Place Hierarchical Block Menu / Place / Hierarchical block Slide 149 OrCAD PSpice, Release 9.2.3
150 Place Hierarchical Pin Menu / Place / Hierarchical pin Slide 150 OrCAD PSpice, Release 9.2.3
151 Descend Hierarchy Slide 151 OrCAD PSpice, Release 9.2.3
152 Hierarchical Design Structure Project Manager Sub Sub Page Page Main Main Page Page Slide 152 OrCAD PSpice, Release 9.2.3
153 Flat Design Structure Flat Flat Design Menu / Place / Off-page Connector Page1 Page U6 D0 D1 D2 D3 D4 D5 D6 D7 D8 W R XI RS FL/RT Q0 9 Q1 10 Q2 11 Q3 12 Q4 16 Q5 17 Q6 18 Q7 19 Q8 13 HC11_D0 HC11_D1 HC11_D2 HC11_D3 HC11_D4 HC11_D5 HC11_D6 HC11_D7 FF 8 EF 21 HC11_F2_FL- XO/HF 20 HC11_F2_EM- DSP_D0 DSP_D1 DSP_D2 DSP_D3 DSP_D4 DSP_D5 DSP_D6 DSP_D B1 B2 B3 B4 B5 B6 B7 B8 U81 A1 2 A2 3 A3 4 A4 5 A5 6 A6 7 A7 8 A8 9 74ALS245 G 19 DIR Off-page connector.. Schematic page page off-page connector Matching Slide 153 OrCAD PSpice, Release 9.2.3
154 Design Structure review 10V VCC V1 0 VCC VCC R1 10 R2 10 N1 N1 Page 1 N2 N2 Page Page R5 10 R6 20 R3 R7 VEE VEE 10 Offpage1 Offpage V V2 R4 R8 0 VEE 10 Port1 Port Slide 154 OrCAD PSpice, Release 9.2.3
155 Capture Symbol VCC VCC_WAVE PORTLEFT-L PORTNO-L OFFPAGELEFT-L OFFPAGELEFT-R Slide 155 OrCAD PSpice, Release 9.2.3
156 Design Management : Manager Analog Tool Behavioral Models Analog Behavior Modeling library Expression ABM (E device : E Value) ABM (E device : E FREQ) Slide 156 OrCAD PSpice, Release 9.2.3
157 ABM (Analog Behavior Analog Modeling) Behavior Modeling library ABM(The Analog Behavioral Modeling) lookup table,,.. ABM.Olb,, limiter,,,,,, Filter, S Laplace( )),, Table,, Analog behavioral parts parts :: mathematical function & lookup table table Digital behavioral parts parts :: functional and and timing --ABM ABM library ;; PSpice Template E^@REFDES %out %out 0 VALUE {{ LOG(V(%in)) }} E^@REFDES ;; standard. E E (E (E device); Voltage Controled Voltage source %in %in,,%out %out;; input input,, output pins pins VALUE {{ log(v(%in))} ;; log log E device expression. E1 IN+ OUT+ IN- OUT- EVALUE LOG(V(%IN+)) Slide 157 OrCAD PSpice, Release 9.2.3
158 Expression Slide 158 OrCAD PSpice, Release 9.2.3
159 ABM (Expression) Expression Slide 159 OrCAD PSpice, Release 9.2.3
160 ABM (Other Function) Expression Table(X,X1,Y1,X2,Y2 ) :: X(node name) X1 Y1 Ex) Ex) Table(V(in),v(in)>0,10,v(in)<0,-10) V(in) + 10V,,- - 10V SDT(X) :: Integral = S(X) S(X) DDT(X) :: Derivative = D(X) D(X) MIN(X,Y) :: X Y MAX(X,Y) :: X Y LIMIT(X,min,max) :: if if X < min min,, then then min min if if X > max max,, then then max max,, else else x SGN(X) ::(( if if X > ), ), (( if if X < )),, (( if if X=0 X=0 0 )) STP(X) :: if if X > 0 1,, otherwise 0 IF(X,Y,Z) :: X X,, Y,,,, Z,, IF(i(V2)>0,TABLE(i(V2),30A,0.5, 100A,8.0),TABLE(i(V2), -100A,8.0, -30A,0.5))))*SDT(v(%in+, %in-)) Slide 160 OrCAD PSpice, Release 9.2.3
161 ABM (E device : E Value) ABM(The Analog Behavioral Modeling) lookup table,, Test EVALUE ABM ABM EXPR Column,, Probe Probe Window Trace Trace Expression ABS( ABS( )) (() ) V(%IN+, %IN-) %IN-).. Slide 161 OrCAD PSpice, Release 9.2.3
162 ABM (E device : E Value) Node Reference Node Voltage Current Expr Expr = ABS(V(vin))*gain Tran. 0 2ms 2ms 0 Run Run Simulation VIN VIN Slide 162 OrCAD PSpice, Release 9.2.3
163 ABM (E device : E FREQ) EFREQ EXPR TABLE DATA Table Format (0, 0, 0, 0) (Freq, DB /DC,, ) (5k, (5k, 0, 0, -5760) 5KHz 0db Low Low Pass Pass Filter 5kHz 5kHz 0dB 6kHz 60dB Slide 163 OrCAD PSpice, Release 9.2.3
164 Design Management : Manager Tool Hot key P : Place part W : Place Wire G : Place Ground F : Place Power B : Place Bus E : Place Bus Entry J : Place Junction R : Rotate H : Mirror Horizontal V : Mirror Vertical I : Zoom In O : Zoom Out T : Place Text Y : Place poly line Ctrl + A : Select All Ctrl + Z : Undo Ctrl + X : Cut Ctrl + C : Copy Ctrl + mouse : Copy Ctrl + V : Paste Ctrl + F : Find F4 : Repeat Place F11 : Run PSpice F12 : View Simulation Result Shift + Wiring : Slant line Art + Mouse : Move C + Mouse : Screen Panning Slide 164 OrCAD PSpice, Release 9.2.3
165 Design Management : Manager Tool Digital How Digital Components are Modeled Place Digital part Wiring digital part Digital Power and Ground Setting up digital simulation Viewing Digital Results Buses Slide 165 OrCAD PSpice, Release 9.2.3
166 How Digital Components Are Modeled Digital components are all modeled as subcircuits. PSpice A/D does contain digital primitives for basic devices such as buffers, inverters, and flip-flops (RS, JK, D), as well as logic blocks, pin delay devices, and I/O models. This greatly speeds up simulations over systems that model digital devices at the transistor level. Slide 166 OrCAD PSpice, Release 9.2.3
167 Placing Digital Parts Place digital symbols on a schematic the same way you place analog symbols: 1 Open the part browser. 2 Select symbol from parts list or type in its name. 3 Left click to place one or more symbols. 4 Right click to end placement. Slide 167 OrCAD PSpice, Release 9.2.3
168 Wiring Digital Parts Wire digital devices together the same way you do analog components. One difference: you can leave some classes of digital outputs unconnected. Optionally, place a NOCONNECT symbol on any unconnected pins. Slide 168 OrCAD PSpice, Release 9.2.3
169 Digital Power and Ground Power and ground for digital devices are globally connected through invisible pins on the symbols. To tie pins high or low, use the HI or LO symbols instead of voltage sources or grounds. 1 2 U1A There are also PULLUP and PULLDOWN symbols available. U?A 3 Digital Power and and Ground Pin Pin 7400 ** TTL/CMOS TTL/CMOS power power supply supply.subckt.subcktdigifpwr AGND AGND + optional: optional: DPWR=$G_DPWR DGND=$G_DGND + params: params: VOLTAGE=5.0v REFERENCE=0v VDPWR VDPWR DPWR DPWR DGND DGND {VOLTAGE} {VOLTAGE} R1 R1 DPWR DPWR AGND AGND 1MEG 1MEG VDGND VDGND DGND DGND AGND AGND {REFERENCE} R2 R2 DGND DGND AGND AGND 1MEG 1MEG.ends.ends Dig_IO.lib // DIGIFPWR Slide 169 OrCAD PSpice, Release 9.2.3
170 Setting up Digital Simulation Transient analysis is the only basic analysis you can perform on a digital circuit. Normally, the only thing you must change in the Gate-level dialog is the flip-flop initialization setting. By default, flip-flops are set to start in the unknown state. Set them to start in either the 0 or 1 state. Slide 170 OrCAD PSpice, Release 9.2.3
171 Viewing Digital Results View digital traces in Probe just like analog signals. Main difference: digital signals have a state rather than a voltage or current level. Digital Probe State Displayed As High single green lines Low single green lines Unknown double red lines Rising transitions double yellow lines falling transitions double yellow lines Tri-state triple blue lines. Slide 171 OrCAD PSpice, Release 9.2.3
172 Buses You can also view buses in Probe. Buses can be viewed as binary, hex, octal or decimal. Buses are displayed as double green lines with the value written between the lines. Slide 172 OrCAD PSpice, Release 9.2.3
173 Use the Internet Model Spice Model Down load load Site Site (PSpice Community Site) Site) :: PSpice Vender site site link link (Spice model & vender site site link link & Spice Application note note down) (spice site site etc) All All semiconductor manufacture company Spice Model Capture library down *.lib *.lib or or *.mod or or *.txt *.txt Model editor Open (( lib Open Save as lib )) Model editor // file file menu // Create Capture part. part. Lib Lib Olb Olb Create Create parts parts for for library lib Capture Capture,, Capture.. Slide 173 OrCAD PSpice, Release 9.2.3
174 Design Management : Manager ToolExample Circuit Lab Slide 174 OrCAD PSpice, Release 9.2.3
175 : NAND / NOR NAND / NOR COMMAND1 = 0s 0 COMMAND2 = 10ms 1 COMMAND3 = 20ms 0 COMMAND4 = 30ms 1 COMMAND5 = 40ms 0 COMMAND6 = 50ms 1 V DSTM1 S1 NAND_A U3A NAND_OUT :: Stim1 // Source.olb 74ls00,, 74ls02 Port Port :: Place // hierarchical port port COMMAND1 = 0s 0 COMMAND2 = 20ms 1 COMMAND3 = 40ms 0 COMMAND4 = 60ms 1 DSTM2 S1 NAND_B V 74LS00 V Tran Tran 60ms COMMAND1 = 0s 0 COMMAND2 = 10ms 1 COMMAND3 = 20ms 0 COMMAND4 = 30ms 1 COMMAND5 = 40ms 0 COMMAND6 = 50ms 1 V DSTM3 S1 NOR_A U4A NOR_OUT COMMAND1 = 0s 0 COMMAND2 = 20ms 1 COMMAND3 = 40ms 0 COMMAND4 = 60ms 1 DSTM4 S1 NOR_B V 74LS02 V Slide 175 OrCAD PSpice, Release 9.2.3
176 : / Half / Full Adder // COMMAND1 = 0s 0 COMMAND2 = 10ms 1 COMMAND3 = 20ms 0 COMMAND4 = 30ms 1 COMMAND5 = 40ms 0 COMMAND6 = 50ms 1 COMMAND1 = 0s 0 COMMAND2 = 20ms 1 COMMAND3 = 40ms 0 COMMAND4 = 60ms 1 COMMAND1 = 0s 0 COMMAND2 = 40ms 1 COMMAND3 = 80ms 0 DSTM1 S1 DSTM2 S1 DSTM3 S1 IN1 IN2 IN3 1 V V U1A U2B LS U1B U2A LS U2C V 74LS08 SUM 8 V CARRY V Slide 176 OrCAD PSpice, Release 9.2.3
177 : EX-OR EX-OR EX EX --OR OR IN1 IN2 1 2 U8A 3 COMMAND1 = 0s 0 COMMAND2 = 10ms 1 COMMAND3 = 20ms 0 COMMAND4 = 30ms 1 COMMAND5 = 40ms 0 COMMAND6 = 50ms 1 COMMAND1 = 0s 0 COMMAND2 = 20ms 1 COMMAND3 = 40ms 0 COMMAND4 = 60ms 1 DSTM1 S1 DSTM2 S1 IN1 IN2 V U3A V U5A U4A 7408 U6A U7A V Y 7408 Slide 177 OrCAD PSpice, Release 9.2.3
178 INVERTER (TTL) TTL TTL +VCC R1 3.6k R2 1.6k Q4 R VCC 5V V1 0 V2 INPUT INPUT V1 = 0 V2 = 5 TD = 0 TR = 1u TF = 1u PW = 2m PER = 4m 0 V Q1 q2n3904 D1 Dbreak Q2 q2n3904 R4 1k V q2n3904 D2 Dbreak OUTPUT Q3 q2n Slide 178 OrCAD PSpice, Release 9.2.3
179 INVERTER (CMOS) CMOS CMOS +VDD_14 Input_1 D1 Dbreak MbreakP M12 M11 Output_2 +VDD_14 5V V1 Input_1 V1 = 0 V2 = 5 V2 TD = 0 TR = 1u TF = 1u PW = 2m PER = 4m D2 Dbreak 0 0 MbreakN 0 Slide 179 OrCAD PSpice, Release 9.2.3
180 3 Phase AC Source 3 PHASE AC SOURCE 3 Phase AC AC Source Slide 180 OrCAD PSpice, Release 9.2.3
181 PULSE GENERATION // Generation Slide 181 OrCAD PSpice, Release 9.2.3
182 DIFFERENTIAL / INTEGRAL Slide 182 OrCAD PSpice, Release 9.2.3
183 RLC Conductance & CONDUCTANCE Impedance / IMPEDANCE RLC RLC Conductance // Impedance Slide 183 OrCAD PSpice, Release 9.2.3
184 IMPEDANCE MATCHING Slide 184 OrCAD PSpice, Release 9.2.3
185 FFT(Fast Fourier Transform) Slide 185 OrCAD PSpice, Release 9.2.3
186 Diode Parameter Sweep Slide 186 OrCAD PSpice, Release 9.2.3
187 Biased Positive limiter Biased Positive limiter Slide 187 OrCAD PSpice, Release 9.2.3
188 Sample and Hold Circuit Slide 188 OrCAD PSpice, Release 9.2.3
189 Bias Bias point detail 12V VIN 1 I I R 67 2 Iz Iz D1 D1N750 Ir Ir 1 RL 1k VIN VIN --Vz Vz R = II I I = Iz Iz + Ir Ir Ir= Ir= Vz Vz // RL RL 2 0 Zener Voltage :: 5V Slide 189 OrCAD PSpice, Release 9.2.3
190 : Bias Bias point detail VIN 12V 1 R1 1k I I 2 Ib Ib Iz Iz Q1 Q2N3904 Vbe Vbe D1 D1N750 Vz Vz Io Io 1 2 Vo Vo RL 1k VIN VIN Vz Vz R = (( I I = Iz Iz )) I I BV BV = 5V 5V 0 Slide 190 OrCAD PSpice, Release 9.2.3
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