RDR W 5V 2A VAC USB Charger INN2023K

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제목사양애플리케이션작성자문서번호날짜 InnoSwitch TM -CH INN2023K 를사용하는 10W CV/CC USB 충전기용레퍼런스디자인보고서 85VAC 264VAC 입력, 5V, 2A 출력 (USB 케이블의끝 ) 휴대전화 / USB 충전기 애플리케이션엔지니어링부서 RDR-420 2014 년 11 월 11 일 개정 1.

1 제목사양애플리케이션작성자문서번호날짜 InnoSwitch TM -CH INN2023K 를사용하는 10W CV/CC USB 충전기용레퍼런스디자인보고서 85VAC 264VAC 입력, 5V, 2A 출력 (USB 케이블의끝 ) 휴대전화 / USB 충전기 애플리케이션엔지니어링부서 RDR 년 11 월 11 일 개정 1.0 요약및기능 InnoSwitch-CH 업계최초의절연형안전정격피드백통합 AC/DC IC 1 차측레귤레이션의간편함에더해진 2 차측컨트롤의모든이점 ±3% CV, ±5% CC 레귤레이션 트랜스포머종류변경에민감하지않음 부하타이밍에무관한과도응답 더작고저렴한출력커패시터 10mW 미만의무부하입력전력 케이블전압강하보상 고효율을위한동기정류방식내장 특허정보여기에설명한제품및애플리케이션 ( 제품의외장트랜스포머구성및회로포함 ) 은하나이상의미국및해외특허의대상이되거나파워인테그레이션스 () 에서출원중인미국및해외특허신청의대상이될수있습니다. 파워인테그레이션스 () 의전체특허목록은 에서확인할수있습니다. 파워인테그레이션스 () 는고객에게 < 에명시된특정특허권에따라라이센스를부여합니다 Hellyer Avenue, San Jose, CA USA.

2 목차 1 소개 파워서플라이사양 회로도 회로설명 입력 EMI 필터링 InnoSwitch-CH IC 1 차측 InnoSwitch-CH IC 2 차측 PCB 레이아웃 BOM 트랜스포머사양 전기적구성도 전기적사양 재료 트랜스포머제작구성도 트랜스포머지침 트랜스포머그림 트랜스포머디자인스프레드시트 성능데이터 활성모드효율 (USB 소켓 ) 과라인비교 활성모드효율 (USB 소켓 ) 과부하비교 Q1, SR FET 와병렬상태에서쇼트키다이오드가없을때의효율 Q1, SR FET 와병렬상태에서쇼트키다이오드 SS16 이있을때의효율 무부하시의입력전력 평균효율 (USB 소켓 ) 효율기준 VAC 입력시의평균효율 VAC 입력시의평균효율 케이블끝에서측정한 CV/CC 레귤레이션 오픈케이스써멀성능 파형 부하과도응답 ( 케이블끝 ) 부하과도응답 (USB 소켓 ) 스위칭파형 InnoSwitch-CH 파형 SR FET 파형 출력리플측정 리플측정기술 측정결과 전도성 EMI... 36, Inc. Page 2 of 51

3 12.1 2A 저항부하, 플로우팅출력 (PK / AV) A 저항부하, 인공핸드접지 (PK / AV) 모니터설정 (HDMI) 이있는스마트폰 (QP / AV) 방사 EMI 가청노이즈 조명서지및 ESD 테스트 디퍼렌셜모드테스트 커먼모드테스트 ESD 테스트 개정내역 중요사항 : 이기판은안전절연거리요구사항에맞도록디자인되었지만엔지니어링프로토타입은아직기관승인을받지않은상태입니다. 따라서 AC 입력을프로토타입보드에제공하도록절연트랜스포머를사용하여모든테스트를수행해야합니다. Page 3 of 51

이문서에는파워서플라이사양, 회로도, 부품목록 (BOM), 트랜스포머규격서, 인쇄회로기판레이아웃및성능데이터가들어있습니다.

4 1 소개 본문서는 IC InnoSwitch-CH 제품군의디바이스를사용한 2A, 5.0V USB 충전기에관한엔지니어링보고서입니다. 이설계는뛰어난성능을발휘하면서높은수준의집적도를통해높은전력밀도및효율을선사할수있도록고안되었습니다. 이문서에는파워서플라이사양, 회로도, 부품목록 (BOM), 트랜스포머규격서, 인쇄회로기판레이아웃및성능데이터가들어있습니다. Figure 1 Populated Circuit Board Photograph, Top. Figure 2 Populated Circuit Board Photograph, Bottom., Inc. Page 4 of 51

5 2 파워서플라이사양 아래표는디자인의최소허용성능을나타냅니다. 실제성능은결과섹션에나열되어있습니다. 설명 기호 최소 일반 최대 단위 설명 입력전압 V IN VAC 2 선식 P.E. 없음 주파수 f LINE 50 50/60 64 Hz 무부하시의입력전력 10 mw 230 VAC 출력출력전압 V OUT V 0.35V 케이블저항강하 과도출력전압 V OUT(T) V 0A - 2A - 0A 부하변동케이블끝출력케이블끝 출력리플전압 V RIPPLE 150 mv 출력케이블끝 출력케이블보상 V CBL mv 2A 출력전류시 출력전류 CC 지점 I OUT A 오토-리스타트전압 V AR V 케이블끝 상승시간턴온 t R 20 ms 정격출력전력 P OUT 10 W 효율 평균 25%, 50%, 75%, 100% η AVE[BRD] 84 % USB 소켓에서측정 η AVE[CBL] 80 % 0.38V 케이블저항강하 10% η 10% 79 % 환경 출력케이블임피던스 R CBL 190 mω 전도성 EMI CISPR22B / EN55022B 인공핸드를통해부하플로우팅또는그라운딩 저항부하, 6dB 마진 휴대전화및 TV 에연결됨 (MHL 연결사용 ) 6dB 마진 안정성 IEC950 / UL1950 클래스 II 충족하도록설계 가청노이즈 25 db 3cm 지점에서측정 라인서지 커먼모드 (L1/L2-PE) 6 kv 링웨이브, 커먼모드 : 12 Ω ESD ±16.5 ±8 주변온도 T AMB 0 40 kv kv o C 접촉공중방전성능저하없음밀폐형인클로저에서자유대류, 임해고도 Page 5 of 51

6 3 회로도 Figure 3 Schematic., Inc. Page 6 of 51

7 4 회로설명 4.1 입력 EMI 필터링 퓨즈 F1 은 1 차측에서부품의치명적인결함발생시보호기능을제공합니다. 정류다이오드 (D1-D4) 의낮은정격서지전류, 그리고벌크스토리지커패시터 C2 및 C4 의상대적으로큰용량으로인한낮은임피던스때문에돌입제한써미스터 (RT1) 가필요했습니다. 특히 PCB 에서케이스까지의높이면에서제한된공간으로인해물리적으로작은다이오드가 D1-D4 용으로선택되었습니다. 커패시터 C2 와 C4 는정류된 AC 입력의필터링을제공하고 L1 및 L2 와함께 π( 파이 ) 필터를구성하여디퍼렌셜모드 EMI 를감소시킵니다. 낮은값의 Y 커패시터 (C8) 는커먼모드 EMI 를줄여줍니다. 4.1 InnoSwitch-CH IC 1 차측트랜스포머 1 차측의한쪽은정류된 DC 버스에연결되어있고다른쪽은 InnoSwitch-CH IC(U1) 의 650V 파워 MOSFET 에연결됩니다. D1, R1, R14 및 C1 으로구성된저가의 RCD 클램프는트랜스포머및출력패턴인덕턴스의효과를통해피크드레인전압을제한합니다. IC 는 AC 가처음인가될때내부고전압전류소스를사용하여 BPP 핀커패시터 (C6) 를충전함으로써자체적으로가동됩니다. 정상동작시 1 차측블록은트랜스포머의보조권선으로부터전력을공급받습니다. 여기서나온출력은플라이백권선으로구성되고정류및필터링된후 (D2 및 C5) Current Limit 저항 R4 를통해 BPP 핀에공급됩니다. ON/OFF 컨트롤을사용하여출력레귤레이션이이루어지고활성화된스위칭사이클의수는출력부하에따라조정됩니다. 고부하시에는대부분의스위칭사이클이활성화되고경부하나무부하시에는대부분의사이클이비활성화되거나스킵됩니다. 사이클이활성화되면파워 MOSFET 은 1 차측전류가특정작동상태의디바이스 Current Limit 에이를때까지 ON 으로유지됩니다. 4 개의작동상태 (Current Limit) 범위가있으며, 1 차측전류스위칭패턴의주파수컨텐츠는트랜스포머자속밀도와가청노이즈생성이매우낮은레벨에있는경부하상태가될때까지가청범위밖에있게됩니다. Page 7 of 51

8 4.2 InnoSwitch-CH IC 2 차측 InnoSwitch-CH 의 2 차측은출력전압과출력전류를감지하고동기정류를제공하는 MOSFET 을구동합니다. 트랜스포머 2 차측은 Q1 에서정류되고 C10 으로필터링됩니다. 스위칭과도상태동안고주파링잉은 Q1 양단에높은전압을발생시키고스너버 R7 및 C9 를통해방사 EMI 가줄어듭니다. 손실을줄이기위해 Q1 에서 SR( 동기정류 ) 을제공합니다. Q1 의게이트는 R5 및 IC 의 FWD 핀을통해감지되는권선전압을기반으로 ON 상태가됩니다. Continuous Conduction Mode 작동중파워 MOSFET 은 2 차측에서 1 차측의새스위칭사이클을명령하기직전에 OFF 상태가됩니다. 불연속모드에서 MOSFET 은 MOSFET 의전압강하가기준값아래로떨어지면 OFF 상태가됩니다. 1 차측 MOSFET 의 2 차측컨트롤은동기정류 MOSFET 과동시에 ON 상태가되지않도록합니다. MOSFET 구동신호는 SR/P 핀에서출력됩니다. IC 는 2 차권선순방향전압이나출력전압을통해자체전원을공급받습니다. CV 동작동안출력전압은디바이스에전원을공급하고 VO 핀으로공급됩니다. CC 동작동안출력전압이떨어지면디바이스에서 2 차권선을통해직접자체전원을공급하게됩니다. 1 차측 MOSFET 의온 - 타임동안, 2 차권선에서나타나는순방향전압이 R5 와내부레귤레이터를통해디커플링커패시터 C7 을충전하는데사용됩니다. 감지된출력전압이 3V 아래로떨어지면오토 - 리스타트상태가됩니다. 출력전류는손실을최소화하기위해 35mV 의기준값으로 IS 와 GND 핀사이에서내부적으로감지됩니다. 내부전류센싱기준값이초과되면디바이스에서활성화된스위칭사이클의수를조정하여고정된출력전류를유지합니다. CC 기준값이하에서디바이스는정전압모드로작동됩니다. 레귤레이션출력전압의경우, 출력전압은저항분배기 R8 및 R9 의작동을통해감지됩니다 (FB 핀의레퍼런스전압은 1.265V)., Inc. Page 8 of 51

9 5 PCB 레이아웃 특별히지정하지않은경우 PCB 구리두께는 2oz(2.8mils / 70µm) 임 Figure 4 Printed Circuit Layout, Top. Page 9 of 51

10 Figure 5 Printed Circuit Layout, Bottom., Inc. Page 10 of 51

11 6 BOM Item Qty Ref Des Description Mfg Part Number Mfg 1 1 C1 1 nf, 250 V, Ceramic, X7R, 0805 GRM21AR72E102KW01D Murata 8.2 µf, 400 V, Electrolytic, (8 x 14) Capxon 2 2 C2 C4 8.2 µf, 400 V, Electrolytic, (8 x 14), Alternate part 400AX8.2M8X16 Rubycon 3 1 C5 22 µf, 16 V, Ceramic, X5R, 0805 C2012X5R1C226K TDK 4 1 C6 1 µf, 25 V, Ceramic, X5R, 0805 C2012X5R1E105K TDK 5 1 C7 2.2 µf, 25 V, Ceramic, X7R, 0805 C2012X7R1E225M TDK 6 1 C8 100 pf, Ceramic, Y1 440LT10-R Vishay 7 1 C9 1.5 nf, 200 V, 10%, Ceramic, X7R, C152KAT2A AVX 8 1 C µf, 6.3 V, Al Organic Polymer, Gen. Purpose, 20% RS80J561MDN1JT Nichicon 9 1 C pf 100 V 10 % X7R C101JAT2A AVX 10 1 C16 1 µf, 50 V, Ceramic, X5R, D105KAT2A AVX 11 1 D1 600 V, 1 A, Rectifier, Glass Passivated, POWERDI123 DFLR Diodes, Inc D2 200 V, 1 A, Rectifier, Glass Passivated, POWERDI123 DFLR Diodes, Inc D3 D4 D5 D6 800 V, 1.5 A, Gen Purpose, SMA 800 V, 1.5 A, Gen Purpose, SMA, Alternate part S2KA-13-F RS2MA-13-F Diodes, Inc. Diodes, Inc F A, 250 V, Slow, RST Belfuse 15 1 J1 Test Point, BLK, Miniature THRU-HOLE MOUNT 5001 Keystone 16 1 J2 Test Point, WHT, Miniature THRU-HOLE MOUNT 5002 Keystone 17 1 J3 Connector USB Female Type A USB-AF-DIP-094-H GOLDCONN 18 1 L1 100 µh, A, 20% RL Renco 19 1 L2 4.7 µh, 600 ma SMD INDUCTOR, MULTILAYER MLZ2012N4R7LT000 TDK 20 1 Q1 60 V, 15 A, N-Channel, PowerPAK SO-8 SI7478DP-T1-E3 Vishay 21 1 R1 200 kω, 5%, 1/8 W, Thick Film, 0805 ERJ-6GEYJ204V Panasonic 22 1 R4 3 kω, 5%, 1/10 W, Thick Film, 0603 ERJ-3GEYJ302V Panasonic 23 1 R5 47 Ω, 5%, 1/10 W, Thick Film, 0603 ERJ-3GEYJ470V Panasonic 24 1 R7 20 Ω, 5%, 1/8 W, Thick Film, 0805 ERJ-6GEYJ200V Panasonic 25 1 R8 100 kω, 1%, 1/16 W, Thick Film, 0603 ERJ-3EKF1003V Panasonic 26 1 R9 34 kω, 1%, 1/16 W, Thick Film, 0603 ERJ-3EKF3402V Panasonic 27 1 R kω, 5%, 1/10 W, Thick Film, 0603 ERJ-3GEYJ334V Panasonic 28 1 R kω, 5%, 1/10 W, Thick Film, 0603 ERJ-3GEYJ104V Panasonic 29 1 R14 30 Ω, 5%, 1/4 W, Thick Film, 1206 ERJ-8GEYJ300V Panasonic 30 1 RT1 NTC Thermistor, 10 Ohms, 0.7 A MF72-010D5 Cantherm 31 1 T1 Custom (see transformer section for material set) SNX-R1776 Santronics 32 1 U1 InnoSwitch-CH IC esop-r16b INN2023K Power Integrations Page 11 of 51

12 7 7.1 트랜스포머사양 전기적구성도 FL, #24 AWG Bare wire 4 WD1: Primary 54T - #30 AWG 3 nc WD3: Shield 6 WD4: Secondary 5T 22 AWG_TIW 전기적사양 Figure 6 Transformer Electrical Diagram. Primary Inductance Pins 3-4, all other windings open, measured at 100 khz, 0.4 V RMS. 546 µh ±5% Resonant Frequency Pins 3-4, all other windings open khz (min) Primary Leakage Pins 3-4, with pins 5-6 shorted, measured at 100 khz, 0.4 Inductance V RMS. 25 µh (max) 7.3 재료 10T #34 AWG 1 2 WD2: Bias 9T 2 x #34 AWG Item Description [1] Core: EE1621; PC-40 or equivalent. [2] Bobbin: EE1621-Vertical 8 pins (4/4) Shen Zhen Xin Yu Jia Technology Ltd. [3] Magnet Wire: #30 AWG, double coated. [4] Magnet Wire: #34 AWG, double coated. [5] Magnet Wire: #22 AWG, Triple Insulated Wire. [6] Tape: 3M 1298 Polyester Film, 2 mil thick, 5.5 mm wide. [7] Epoxy: Devcon, 5 Minute Epoxy, No ; or equivalent. [8] Bus wire: #24 AWG, Belden Electronics Div; or equivalent. [9] Varnish: Dolph BC , Inc. Page 12 of 51

13 7.4 트랜스포머제작구성도 WD4: Secondary 5T #22 AWG_TIW WD3: Shield 10T #34 AWG (wound in parallel with ) WD2: Bias 9T 2x#34 AWG NC WD1: Primary 54T - #30 AWG 트랜스포머지침 Winding Preparation WD1 Primary Insulation WD2 & WD3 Bias & Shield Insulation WD4 Secondary Insulation Finish Figure 7 Transformer Build Diagram. For the purpose of these instructions, bobbin is oriented on winder such that pin side is on the left side. Winding direction is clockwise direction. Start at pin 3, wind 54 turns wire item [2] in 3 layers (18T/layer) with tight tension. At the last turn bring the wire back to the left and finish at pin 4. 1 layer of tape [6] for insulation. Use 3 wires item [4], start at pin 1, and wind 9 turns from left to right. At the last turn, bring 2 wires to the left to terminate at pin 2 for WD2. Then continue winding on the 3 rd wire 1 more turn and left no-connect for WD3. 1 layer of tape [6] for insulation. Start at pin 6, wind 5 turns wire item [5], spread wire evenly. At the last turn bring the wire back to the left and finish at pin 5. 2 Layer of tape [6] to secure the windings. Gap core halves for 546 µh inductance. Place epoxy item [7] onto both center legs of core halves, (see illustration below). Wrap core halves and bus wire item [8] with tape, (see illustration below). Varnish with item [9]. Page 13 of 51

oriented on winder such that pin side is on

Winding direction is clockwise direction.

item [2] in 3 layers (18T/layer) with tight

14 7.6 트랜스포머그림 Winding Preparation For the purpose of these instructions, bobbin is oriented on winder such that pin side is on the left side. Winding direction is clockwise direction. WD1 Primary Start at pin 3, wind 54 turns wire item [2] in 3 layers (18T/layer) with tight tension. At the last turn bring the wire back to the left and finish at pin 4., Inc. Page 14 of 51

Insulation 1 layer of tape [6] for insulation.

15 Insulation 1 layer of tape [6] for insulation. WD2 & WD3 Bias & Shield Use 3 wires item [4], start at pin 1, and wind 9 turns from left to right. At the last turn, bring 2 wires to the left to terminate at pin 2 for WD2. Then continue winding on the 3 rd wire 1 more turn and left noconnect for WD3. 2 wires for WD2 Page 15 of 51

16 3 rd wire left NC for WD3 Insulation 1 layer of tape [6] for insulation. WD4 Secondary Start at pin 6, wind 5 turns wire item [5], spread wire evenly. At the last turn bring the wire back to the left and finish at pin 5. Insulation 2 layer of tape [6] to secure the windings., Inc. Page 16 of 51

primary side Wrap core halves and bus wire item

17 Gap core halves for 546 µh inductance. Place epoxy item [7] onto both center legs of core halves, (see illustration beside). Finish bus wire item [8] left ~ 40 mm floating on primary side Wrap core halves and bus wire item [8] with tape, (see illustration below). Varnish with item [9]. Page 17 of 51

18 8 트랜스포머디자인스프레드시트 ACDC_InnoSwitch- CH_101614; Rev.2.0; Copyright Power Integrations 2014 INPUT INFO OUTPUT UNIT ACDC_InnoSwitch_101614_Rev2-0; InnoSwitch- CH Continuous/Discontinuous Flyback Transformer Design Spreadsheet ENTER APPLICATION VARIABLES VACMIN 85 V Minimum AC Input Voltage VACMAX 265 V Maximum AC Input Voltage fl 50 Hz AC Mains Frequency VO V Output Voltage (continuous power at the end of the cable) IO A Power Supply Output Current (corresponding to peak power) Power 10.6 W Continuous Output Power, including cable drop compensation n Efficiency Estimate at output terminals. Use 0.8 if no better data available Z 0.50 Z Factor. Ratio of secondary side losses to the total losses in the power supply. Use 0.5 if no better data available tc 3.00 mseconds Bridge Rectifier Conduction Time Estimate CIN Info ufarad!!! Input capacitor is too small. Recommnded to increase CIN above uf to ensure VMIN>70 V ENTER InnoSwitch VARIABLES InnoSwitch-CH INN20x3 INN20x3 User defined InnoSwitch Cable drop compensation 6% 6% Select Cable Drop Compensation option Complete Part Number INN2023K Final part number including package Chose Configuration INC Increased Current Limit Enter "RED" for reduced current limit (sealed adapters), "STD" for standard current limit or "INC" for increased current limit (peak or higher power applications) ILIMITMIN A Minimum Current Limit ILIMITTYP 0.75 A Typical Current Limit ILIMITMAX A Maximum Current Limit fsmin Hz Minimum Device Switching Frequency I^2fmin A^2kHz Worst case I2F parameter across the temperature range VOR V Reflected Output Voltage (VOR <= 100 V Recommended) VDS 5.00 V InnoSwitch on-state Drain to Source Voltage KP 0.80 Ripple to Peak Current Ratio at Vmin, assuming ILIMITMIN, and I2FMIN (KP < 6) KP_TRANSIENT 0.46 Worst case transient Ripple to Peak Current Ratio. Ensure KP_TRANSIENT > 0.25 ENTER BIAS WINDING VARIABLES VB V Bias Winding Voltage VDB 0.70 V Bias Winding Diode Forward Voltage Drop NB 9.32 V Bias Winding Number of Turns PIVB V Bias winding peak reverse voltage at VACmax and assuming VB*1.2 ENTER TRANSFORMER CORE/CONSTRUCTION VARIABLES Core Type Custom Custom Enter Transformer Core Core EE1621 EE1621 Enter core part number, if necessary Bobbin 0 Enter bobbin part number, if necessary AE cm^2 Core Effective Cross Sectional Area LE cm Core Effective Path Length AL nh/t^2 Ungapped Core Effective Inductance BW mm Bobbin Physical Winding Width, Inc. Page 18 of 51

19 M 0.00 mm Safety Margin Width (Half the Primary to Secondary Creepage Distance) L 3 3 Number of Primary Layers NS 5 5 Number of Secondary Turns DC INPUT VOLTAGE PARAMETERS VMIN 62 Warning 62 V!!! Minimum DC Input Voltage < 70 Volts. Increase VACMIN or increase CIN VMAX 375 V Maximum DC Input Voltage CURRENT WAVEFORM SHAPE PARAMETERS DMAX 0.50 Duty Ratio at full load, minimum primary inductance and minimum input voltage IAVG 0.21 A Average Primary Current IP A Peak Primary Current assuming ILIMITMIN IR A Primary Ripple Current assuming ILIMITMIN, and LPMIN IRMS 0.31 A Primary RMS Current, assuming ILIMITMIN, and LPMIN TRANSFORMER PRIMARY DESIGN PARAMETERS LP 546 uhenry Typical Primary Inductance. +/- 5% to ensure a minimum primary inductance of 518 uh LP_TOLERANCE % Primary inductance tolerance NP 54 Primary Winding Number of Turns ALG 187 nh/t^2 Gapped Core Effective Inductance BM 2868 Gauss Maximum Operating Flux Density, BM<3000 is recommended BAC 1147 Gauss AC Flux Density for Core Loss Curves (0.5 X Peak to Peak) ur 2694 Relative Permeability of Ungapped Core LG 0.20 mm Gap Length (Lg > 0.1 mm) BWE 16.2 mm Effective Bobbin Width OD 0.30 mm Maximum Primary Wire Diameter including insulation INS 0.05 mm Estimated Total Insulation Thickness (= 2 * film thickness) DIA 0.25 mm Bare conductor diameter AWG 31 AWG Primary Wire Gauge (Rounded to next smaller standard AWG value) CM 81 Cmils Bare conductor effective area in circular mils CMA 259 Cmils/Amp Primary Winding Current Capacity (200 < CMA < 500) TRANSFORMER SECONDARY DESIGN PARAMETERS Lumped parameters ISP 7.37 A Peak Secondary Current, assuming ILIMITMIN ISRMS 3.33 A Secondary RMS Current IRIPPLE 2.67 A Output Capacitor RMS Ripple Current CMS 667 Cmils Secondary Bare Conductor minimum circular mils AWGS 21 AWG Secondary Wire Gauge (Rounded up to next larger standard AWG value) VOLTAGE STRESS PARAMETERS VDRAIN 517 V Maximum Drain Voltage Estimate PIVS 54 V Output Rectifier Maximum Peak Inverse Voltage, assuming the primary has a Voltage spike 40% above VMAX and VO*1.05 TRANSFORMER SECONDARY DESIGN PARAMETERS 1st output VO V Main Output Voltage directly after output rectifier IO A Output DC Current PO W Output Power VD V Output Synchronous Rectification FET Forward Voltage Drop Page 19 of 51

20 NS Turns Output Winding Number of Turns ISRMS A Output Winding RMS Current IRIPPLE A Output Capacitor RMS Ripple Current PIVS1 54 V Output Rectifier Maximum Peak Inverse Voltage, assuming the primary has a Voltage spike 40% above VMAX and VO*1.05 Recommended MOSFET QM6006 Recommended SR FET for this output RDSON_HOT Ohm RDSon at 100C VRATED 60 V Rated voltage of selected SR FET CMS1 667 Cmils Output Winding Bare Conductor minimum circular mils AWGS1 21 AWG Wire Gauge (Rounded up to next larger standard AWG value) DIAS mm Minimum Bare Conductor Diameter ODS mm Maximum Outside Diameter for Triple Insulated Wire, Inc. Page 20 of 51

21 9 성능데이터 All measurements performed with external room ambient temperature and 60 Hz input for 115 VAC range and 50 Hz for 230 VAC input range 활성모드효율 (USB 소켓 ) 과라인비교 Efficiency (%) Input Voltage (VAC) Figure 8 Efficiency vs Line Voltage, Room Temperature Page 21 of 51

22 활성모드효율 (USB 소켓 ) 과부하비교 Q1, SR FET 와병렬상태에서쇼트키다이오드가없을때의효율 Efficiency (%) VAC 115 VAC 230 VAC 265 VAC Load (%) Figure 9 Efficiency vs Load, Room Ambient, Inc. Page 22 of 51

23 90 85 Efficiency (%) VAC 115 VAC 230 VAC 265 VAC Load (%) Figure 10 - Efficiency vs Load (log scale to demonstrate light load performance) Page 23 of 51

24 9.2.2 Q1, SR FET 와병렬상태에서쇼트키다이오드 SS16 이있을때의효율 Efficiency (%) VAC 115 VAC 230 VAC 265 VAC Load (%) Figure 11 Efficiency vs Load, Room Temperature, 60 Hz., Inc. Page 24 of 51

25 9.3 무부하시의입력전력 Input Power (mw) Input Voltage (VAC) Figure 12 No Load Input Power vs. Input Line Voltage, Room Temperature. Page 25 of 51

26 평균효율 (USB 소켓 ) 효율기준 Test Average Average Average Average 10% 10% Load Load Model <6 V <6 V <6 V <6 V <6 V <6 V Voltage Voltage Voltage Voltage Voltage Voltage Effective Now 2016 Now 2016 Now 2016 Power [W] Energy Star 2 New IESA2007 CoC v5 Tier 1 CoC v5 Tier 2 CoC v5 Tier 1 CoC v5 Tier 2 10% 74.2% 78.7% 76.0% 79.0% 66.6% 69.7% VAC 입력시의평균효율 Q1, SR FET 와병렬상태에서쇼트키다이오드없음 Load (%) V IN (V RMS ) I IN (A RMS ) P IN (W) PF %ATHD V OUT (V DC ) I OUT (A DC ) P OUT (W) Efficiency (%) Average Efficiency (%) Q1, SR FET 와병렬상태에서쇼트키다이오드 SS16 Load (%) V IN (V RMS ) I IN (A RMS ) P IN (W) PF %ATHD V OUT (V DC ) I OUT (A DC ) P OUT (W) Efficiency (%) Average Efficiency (%) , Inc. Page 26 of 51

27 VAC 입력시의평균효율 Q1, SR FET 와병렬상태에서쇼트키다이오드없음 Load (%) V IN (V RMS ) I IN (A RMS ) P IN (W) PF %ATHD V OUT (V DC ) I OUT (A DC ) P OUT (W) Efficiency (%) Average Efficiency (%) Q1, SR FET 와병렬상태에서쇼트키다이오드 SS16 Load (%) V IN (V RMS ) I IN (A RMS ) P IN (W) PF %ATHD V OUT (V DC ) I OUT (A DC ) P OUT (W) Efficiency (%) Average Efficiency (%) Page 27 of 51

28 9.5 Output Voltage (V) 케이블끝에서측정한 CV/CC 레귤레이션 VAC 110 VAC 230 VAC 265 VAC Output Current (A) Figure 13 Output Voltage vs, Output current, Room Temperature., Inc. Page 28 of 51

Figure 16 Transformer Side. 110 VAC, 2 A Load.

29 10 오픈케이스써멀성능 Room ambient. Figure 14 Transformer Side. 85 VAC, 2 A Load. Ambient = 26.3 ºC. Figure 15 InnoSwitch-CH Side. 85 VAC, 2 A Load. Ambient = 27 ºC. Figure 16 Transformer Side. 110 VAC, 2 A Load. Ambient = 26.2 ºC. Figure 17 InnoSwitch-CH Side. 110 VAC, 2 A Load. Ambient = 25 ºC. Page 29 of 51

Figure 20 Transformer Side. 265 VAC, 2 A Load. Ambient = 26.5 ºC.

30 Figure 18 Transformer Side. 230 VAC, 2 A Load. Ambient = 26.5 ºC. Figure 19 InnoSwitch-CH Side. 230 VAC, 2 A Load. Ambient = 25.4 ºC. Figure 20 Transformer Side. 265 VAC, 2 A Load. Ambient = 26.5 ºC. Figure 21 InnoSwitch-CH Side. 265 VAC, 2 A Load. Ambient = 25.3 ºC., Inc. Page 30 of 51

11 파형 11.1 부하과도응답 ( 케이블끝 ) Results were measured with 47 µf at end of cable which is the typical specified measurement condition for mobile phone chargers.

Upper: I LOAD, 1 A / div. Lower: V OUT, 500 mv, 50 ms / div. Figure 24 Transient Response (4.6 V MIN ). 230 VAC, 0-2 A Load Step. Upper: I LOAD, 1 A / div.

31 11 파형 11.1 부하과도응답 ( 케이블끝 ) Results were measured with 47 µf at end of cable which is the typical specified measurement condition for mobile phone chargers. Figure 22 Transient Response (4.5 V MIN ). 85 VAC, 0-2 A Load Step. Upper: I LOAD, 1 A / div. Lower: V OUT, 500 mv, 50 ms / div. Figure 23 Transient Response (4.5 V MIN ). 110 VAC, 0-2 A Load Step. Upper: I LOAD, 1 A / div. Lower: V OUT, 500 mv, 50 ms / div. Figure 24 Transient Response (4.6 V MIN ). 230 VAC, 0-2 A Load Step. Upper: I LOAD, 1 A / div. Lower: V OUT, 500 mv, 50 ms / div. Figure 25 Transient Response (4.6 V MIN ). 265 VAC, 0-2 A Load Step. Upper: I LOAD, 1 A / div. Lower: V OUT, 500 mv, 50 ms / div. Page 31 of 51

Lower: V OUT, 500 mv, 50 ms / div. Figure 28 Transient Response (4.85 V MIN ). 230 VAC, 0-2 A Load Step. Upper: I LOAD, 1 A / div.

32 11.2 부하과도응답 (USB 소켓 ) Figure 26 Transient Response (4.75 V MIN ). 85 VAC, 0-2 A Load Step. Upper: I LOAD, 1 A / div. Lower: V OUT, 500 mv, 50 ms / div. Figure 27 Transient Response (4.75 V MIN ). 110 VAC, 0-2 A Load Step. Upper: I LOAD, 1 A / div. Lower: V OUT, 500 mv, 50 ms / div. Figure 28 Transient Response (4.85 V MIN ). 230 VAC, 0-2 A Load Step. Upper: I LOAD, 1 A / div. Lower: V OUT, 500 mv, 50 ms / div. Figure 29 Transient Response (4.86 V MIN ). 265 VAC, 0-2 A Load Step. Upper: I LOAD, 1 A /div. Lower: V OUT, 500 mv, 50 ms / div., Inc. Page 32 of 51

11.3 스위칭파형 11.3.1 InnoSwitch-CH 파형 Figure 30 Drain Voltage and Current Waveforms. 85 VAC, 2 A load, Lower: I DRAIN, 500 ma / div.

Lower: I DRAIN, 500 ma / div. Upper: V DRAIN, 200 V, 20 µs / div. 11.3.2 SR FET 파형 Figure 32 SR FET Voltage Waveforms.

33 11.3 스위칭파형 InnoSwitch-CH 파형 Figure 30 Drain Voltage and Current Waveforms. 85 VAC, 2 A load, Lower: I DRAIN, 500 ma / div. Upper: V DRAIN, 100 V, 20 µs / div. Figure 31 Drain Voltage and Current Waveforms. 265 VAC, 2 A Load, 545 V MAX. Lower: I DRAIN, 500 ma / div. Upper: V DRAIN, 200 V, 20 µs / div SR FET 파형 Figure 32 SR FET Voltage Waveforms. 85 VAC Input, 2 A Load. V DRAIN, 10 V, 20 µs / div. Figure 33 SR FET Voltage Waveforms. 265 VAC Input, 2 A Load. V DRAIN, 20 V, 20 µs / div. (45.4 V MAX ). Page 33 of 51

11.4 출력리플측정 11.4.1 리플측정기술 For DC output ripple measurements, a modified oscilloscope test probe must be utilized in order to reduce spurious signals due to pick-up.

1 µf/50 V ceramic type and one (1) 47 µf/50 V aluminum electrolytic. The aluminum electrolytic type capacitor is polarized, so proper polarity across DC outputs must be maintained (see below).

34 11.4 출력리플측정 리플측정기술 For DC output ripple measurements, a modified oscilloscope test probe must be utilized in order to reduce spurious signals due to pick-up. Details of the probe modification are provided in the Figures below. The 4987BA probe adapter is affixed with two capacitors tied in parallel across the probe tip. The capacitors include one (1) 0.1 µf/50 V ceramic type and one (1) 47 µf/50 V aluminum electrolytic. The aluminum electrolytic type capacitor is polarized, so proper polarity across DC outputs must be maintained (see below). Probe Ground Probe Tip Figure 34 Oscilloscope Probe Prepared for Ripple Measurement. (End Cap and Ground Lead Removed) Figure 35 Oscilloscope Probe with Probe Master ( 4987A BNC Adapter. (Modified with wires for ripple measurement, and two parallel decoupling capacitors added), Inc. Page 34 of 51

35 측정결과 Measured at the end of cable V 115 V 230 V 265 V 0.10 Ripple (mv PK-PK) Current (ma) Figure 36 Output Ripple Voltage. RIPPLE (mv PK-PK) 85 V RIPPLE (mv PK-PK) 115 V RIPPLE (mv PK-PK) 230 V RIPPLE (mv PK-PK) 265 V Page 35 of 51

36 12 전도성 EMI A 저항부하, 플로우팅출력 (PK / AV) After running 5 minutes. Freq (MHz) QP Limit Margin Figure 37 Floating Ground EMI at 115 VAC., Inc. Page 36 of 51

37 Figure 38 Floating Ground at 230 VAC. Page 37 of 51

38 12.2 2A 저항부하, 인공핸드접지 (PK / AV) FREQ (MHZ) QP LIMIT MARGIN Figure 39 Artificial Ground at 115 VAC., Inc. Page 38 of 51

39 FREQ (MHZ) QP LIMIT MARGIN Figure 40 Artificial Ground at 230 VAC. Page 39 of 51

40 12.3 모니터설정 (HDMI) 이있는스마트폰 (QP / AV) Phone is connected to charger and LCD monitor. The monitor connection increases capacitance to earth ground. Figure 41 HDMI at 115 VAC., Inc. Page 40 of 51

41 Figure 42 HDMI at 230 VAC. Page 41 of 51

42 13 방사 EMI Maximized quasi-peak readings (NO manipulation of EUT interface cables) Frequency Level Pol Class B Detector Azimuth Height Comments MHz dbµv/m v/h Limit Margin Pk/QP/Avg degrees meters V QP QP (1.00s) H QP QP (1.00s) Figure 43 Radiation at 110 VAC., Inc. Page 42 of 51

43 Maximized quasi-peak readings (NO manipulation of EUT interface cables) Frequency Level Pol Class B Detector Azimuth Height Comments MHz dbµv/m v/h Limit Margin Pk/QP/Avg degrees meters V QP QP (1.00s) H QP QP (1.00s) Figure 44 Radiation at 230 VAC. Page 43 of 51

44 14 가청노이즈 Test performed inside case with microphone placed 3 mm from case surface on long side of case, transformer facing towards microphone. Figure 45 Audible Noise Spectrum: No-load, V IN Swept from 85 VAC to 264 VAC., Inc. Page 44 of 51

45 Figure 46 Audible Noise Spectrum: 85 VAC, I OUT Swept from 0 A to 2.0 A. Page 45 of 51

46 Figure 47 Audible Noise Spectrum: 110 VAC, I OUT Swept from 0 A to 2.0 A., Inc. Page 46 of 51

47 Figure 48 Audible Noise Spectrum: 220 VAC, I OUT Swept from 0 A to 2.0A. Page 47 of 51

48 Figure 49 Audible Noise Spectrum: 265 VAC, I OUT Swept from 0 A to 2.0 A., Inc. Page 48 of 51

49 15 조명서지및 ESD 테스트 15.1 디퍼렌셜모드테스트 Passed ±1 kv, 500 A surge test 15.2 커먼모드테스트 Passed ±6 KV, 500 A ring wave test. Need to install plastic barrier for >5 kv ring wave common mode surge test ESD 테스트 Passed ±16.5 kv air, 8 kv contact. Need to install plastic barrier to pass ESD test. Page 49 of 51

50 16 개정내역 날짜작성자개정설명및변경사항검토대상 2014 년 11 월 11 일 DK 1.0 최초출시 Mktg & Apps, Inc. Page 50 of 51

51 최신업데이트에대한자세한내용은당사웹사이트 () 를참고하십시오. 파워인테그레이션스 () 는안정성또는생산성향상을위하여언제든지당사제품을변경할수있는권한이있습니다. 파워인테그레이션스 () 는여기서설명하는디바이스나회로사용으로인해발생하는어떠한책임도지지않습니다. 파워인테그레이션스 () 는어떠한보증도제공하지않으며모든보증 ( 상품성에대한묵시적보증, 특정목적에의적합성및타사권리의비침해를포함하되이에제한되지않음 ) 을명백하게부인합니다. 특허정보여기에설명한제품및애플리케이션 ( 제품의외장트랜스포머구성및회로포함 ) 은하나이상의미국및해외특허의대상이되거나파워인테그레이션스 () 에서출원중인미국및해외특허신청의대상이될수있습니다. 파워인테그레이션스 () 의전체특허목록은 에서확인할수있습니다. 파워인테그레이션스 () 는고객에게 에명시된특정특허권에따라라이센스를부여합니다. PI 로고, TOPSwitch, TinySwitch, LinkSwitch, DPA-Switch, PeakSwitch, CAPZero, SENZero, LinkZero, HiperPFS, HiperTFS, HiperLCS, Qspeed, EcoSmart, Clampless, E-Shield, Filterfuse, StackFET, PI Expert 및 PI FACTS 는, Inc 의상표입니다. 다른상표는각회사고유의자산입니다. Copyright 2014, Inc. 전세계판매지원지역 세계본사 5245 Hellyer Avenue San Jose, CA 95138, USA. Main: 고객서비스 : 전화 : 팩스 : 전자메일 : usasales@powerint.com 독일 Lindwurmstrasse , Munich Germany 전화 : 팩스 : 전자메일 : eurosales@powerint.com 일본 Kosei Dai-3 Building , Shin-Yokohama, Kohoku-ku, Yokohama-shi, Kanagawa Japan 전화 : 팩스 : 전자메일 : japansales@powerint.com 한국 RM 602, 6FL Korea City Air Terminal B/D, Samsung-Dong, Kangnam-Gu, Seoul, Korea 전화 : 팩스 : 전자메일 : koreasales@powerint.com 싱가포르 51 Newton Road, #19-01/05 Goldhill Plaza Singapore, 전화 : 팩스 : 전자메일 : singaporesales@powerint.com 대만 5F, No. 318, Nei Hu Rd., Sec. 1 Nei Hu District Taipei 11493, Taiwan R.O.C. 전화 : 팩스 : 전자메일 : taiwansales@powerint.com 중국 ( 상하이 ) Rm 2410, Charity Plaza, No. 88 North Caoxi Road, Shanghai, PRC 전화 : 팩스 : 전자메일 : chinasales@powerint.com 인도 #1, 14 th Main Road Vasanthanagar Bangalore 인도전화 : 팩스 : 전자메일 : indiasales@powerint.com 영국 First Floor, Unit 15, Meadway Court, Rutherford Close, Stevenage, Herts. SG1 2EF United Kingdom 전화 : +44 (0) 팩스 : +44 (0) 전자메일 : eurosales@powerint.com 중국 ( 센젠 ) 17/F, Hivac Building, No. 2, Keji Nan 8th Road, Nanshan District, Shenzhen, China, 전화 : 팩스 : 전자메일 : chinasales@powerint.com 이탈리아 Via Milanese 20, 3 rd. Fl Sesto San Giovanni (MI) Italy 전화 : 팩스 : 전자메일 : eurosales@powerint.com 애플리케이션문의전화전세계통합번호 애플리케이션문의팩스전세계통합번호 Page 51 of 51

Microsoft Word - 71855.doc

Microsoft Word - 71855.doc Qspeed 제품군 1V, 4 A 커먼-캐소드 다이오드 제품 요약 다이오드당 I F(AVG) 2 A V RRM 1 V Q RR(12 C 일반) 33.6 nc I RRM(12 C 일반) 1.86 A Softness t b/t a(12 C 일반).7 TO-22AB LQA4T1C 핀 지정 A1 A2 TO-263AB K LQA4B1C RoHS 준수 본 패키지는 IEC