W5300 Datasheet

Transcription

1 High-Performance Internet Connectivity Solution W5300 Version WIZnet Co., Inc. All Rights Reserved. For more information, visit our website at Copyright 2008 WIZnet Co., Inc. All rights reserved. 1

2 Document History Information Version Date Descriptions Ver Mar. 11, 2008 Release with W5300 launching Copyright 2008 WIZnet Co., Inc. All rights reserved. 2

3 WIZnet s online Technical Support If you have something to ask about WIZnet Products, write down your question on Q&A Board of Support menu in WIZnet website ( WIZnet Engineer will give an answer as soon as possible. Click Copyright 2008 WIZnet Co., Inc. All rights reserved. 3

4 W5300 W5300 은위즈네트의 Hardware TCP/IP 기술을이용한임베디드시스템을위한인터넷솔루션중멀티미디어서비스에적합한고성능에목적을둔제품이다. 기존의위즈네트칩에비해서메모리및데이터처리부분을개선하여성능을향상시켰으며, 최근각광을받고있는 IPTV, IP-STB 등의대용량멀티미디어데이터전송에대응할수있도록개발된제품이다. W5300 하나의칩으로 TCP/IP 프로토콜처리및 10/100 Ethernet PHY 와 MAC 을구현하여개발하고자하는 Application 에 Internet Connectivity 를손쉽게구현할수있도록지원한다. High-Performance Hardware TCP/IP single chip solutions 위즈네트에서는 TCP, UDP, IPv4, ICMP, IGMP, ARP, PPPoE 등의통신프로토콜을 Full hardware logic으로개발하여여러제품에서사용하고있다. W5300에서는보다고성능의데이터통신을제공하기위해서 data communication memory를 128Kbyte로확장하고, 16bit bus interface를지원한다. 이에사용자는 W5300의하드웨어로처리되는 8개의독립적인고속의하드웨어 SOCKET을사용할수있다. More flexible memory allocation for various applications W5300의 data communication memory는사용자의설정에따라각 SOCKET별로 0~64Kbytes 범위에서조절할수있으므로사용하고자하는 application에맞춰자유롭게사용할수있다. 따라서사용자는고성능이요구되는 application에자원을집중하여보다효율적으로시스템을구성할수있도록유연한메모리사이즈할당기능을제공한다. Easy to implements for beginners W5300의 Host Interface 방식은 SRAM 메모리등과같은 System bus interface를제공하며 Direct address access 방식과 Indirect address access방식을지원하여메모리를사용하듯쉽게사용할수있도록한다. 또한 W5300의 Data communication memory는각 SOCKET별로존재하는송신 FIFO Register와수신 FIFO Register를통해서간단히 Access 할수있도록하여보다쉽고간단히 W5300을사용할수있도록하여네트워크를처음접하는엔지니어도쉽게 Internet connectivity를구현할수있도록지원한다. Copyright 2008 WIZnet Co., Inc. All rights reserved. 4

5 Target Applications W5300은다음과같은 Embedded application에적합하다. - Home Network Devices: Set-Top Boxes, PVRs, Digital Media Adapters - Serial-to-Ethernet: Access Controls, LED displays, etc. - Parallel-to-Ethernet: POS / Mini Printers, Copiers - USB-to-Ethernet: Storage Devices, Network Printers - GPIO-to-Ethernet: Home Network Sensors - Security Systems: DVRs, Network Cameras, Kiosks - Factory and Building Automation - Medical Monitoring Equipment - Embedded Servers Features - Supports hardwired TCP/IP protocols : TCP,UDP, ICMP, IPv4, ARP, IGMPv2, PPPoE, Ethernet - Supports 8 independent SOCKETs simultaneously - High network performance : Up to 50Mbps - Supports hybrid TCP/IP stack(software and hardware TCP/IP stack) - Supports PPPoE connection (with PAP/CHAP Authentication mode) - IP Fragmentation is not supported - Internal 128Kbytes memory for data communication(internal TX/RX memory) - More flexible allocation internal TX/RX memory according to application throughput - Supports memory-to-memory DMA (only 16bit Data bus width & slave mode) - Embedded 10BaseT/100BaseTX Ethernet PHY - Supports auto negotiation (Full-duplex and half duplex) - Supports auto MDI/MDIX(Crossover) - Supports network Indicator LEDs (TX, RX, Full/Half duplex, Collision, Link, Speed) - Supports a external PHY instead of the internal PHY - Supports 16/8 bit data bus width - Supports 2 host interface mode(direct address mode & Indirect address mode) - External 25MHz operation frequency (For internal PLL logic, period=40ns) - Internal 150MHz core operation frequency (PLL_CLK, period=about 6.67ns) - Network operation frequency (NIC_CLK : 25MHz(100BaseTX) or 2.5MHz(10BaseT)) - 3.3V operation with 5V I/O signal tolerance - Embedded power regulator for 1.8V core operation µm CMOS technology - 100LQFP 14X14 Lead-Free Package Copyright 2008 WIZnet Co., Inc. All rights reserved. 5

6 Block Diagram 150MHz 25MHz PLL PPPoE Host Host Host Interface Manager TCP Register Manager ARP TCP/IP Core Host Bus Interface ICMP IP UDP IGMP V1/V2 Memory Manager 128KB TX/RX DPRAM 3.3V 1.8V Power Regulator Ethernet MAC MII Manager (CSMA/CD) Ethernet PHY External MII Media Interface 3rd Party Transformer Ethernet PHY RJ45 Copyright 2008 WIZnet Co., Inc. All rights reserved. 6

7 PLL(Phase-Locked Loop) 25MHz의 Clock source를 6배빠른 150MHz clock으로생성한다. 생성된 150MHz clock은 TCP/IP core block, Host Interface Manager, Register Manager와같은내부 Block의 Operation clock으로사용된다. PLL은 Reset 후 Lock-in되어안정된 clock을공급한다. Power Regulator 3.3V Power를입력받아 1.8V/150mA의 Power를생성한다. 이 Power Regulator는 W5300의 Core operation power를공급한다. 외부에다른 Power regulator 장착이필요없다. 보다안정적인 1.8V Power 공급을위해외부에 Recommended capacitor를장착한다. Host Interface Manager Host bus signal을감지하고, Data bus width나 Host interface mode 설정에따라 Host의 Read/Write operation을관리한다. Register Manager Mode register, COMMON register, SOCKET register등의주요 Register들을관리한다. Memory Manager 128Kbytes의 Internal data memory를관리하고, Host에의해할당된각 SOCKET의 TX/RX memory를관리한다. Host는각 SOCKET의 TX/RX FIFO Register을통해서만이 Memory를 Access할수있다. 128KB TX/RX DPRAM 128Kbytes 의 Data memory 로, 8Kbytes DPRAM(Dual-Port RAM) 16 개로구성된다. Host 에의해 각 SOCKET 별로 flexible 하게할당된다. MII(Media Independent Interface) Manager MII interface 를관리한다. MII interface 은 TEST_MODE[3:0] 의설정에따라 Internal PHY 나 External PHY(3 rd Party PHY) 로 Switching 된다. Internal Ethernet PHY 10BaseT/100BaseTX Ethernet PHY로, Half-duplex/Full-duplex, Auto-negotiation, Auto MDI/MDIX를지원한다. 또한 Link status, Speed, Duplex와같은 6개의 Network Indicator LED output signal을지원한다. TCP/IP Core WIZnet 의 Network protocol processing 기술로, TCP/IP stack 이 Fully hardwired logic 으로구 Copyright 2008 WIZnet Co., Inc. All rights reserved. 7

8 현된다 Ethernet MAC(Media Access Control) CSMA/CD(Carrier Sense Multiple Access with Collision Detect) 방식의 Ethernet 접근을제어한다. 48bits의 Source/Destination MAC address를기반으로하는 Protocol 기술이다. Hardware TCP/IP stack뿐만아니라, 0번째 SOCKET을이용해 Host가직접적으로 MAC layer를 Control할수있게하여 Software TCP/IP stack을구현할수있다. - PPPoE(Point-To-Point Protocol over Ethernet) Ethernet상에서 PPP service를이용하게하는 Protocol 기술이다. 이는 Ethernet frame의 Payload(Data) 부분을 PPP frame으로 Encapsulation하여전송하며, PPP frame을 De-capsulation하여수신한다. PPPoE는 PPPoE server와의 PPP 통신을지원하며 PAP/CHAP 방식의 Authentication만을지원한다. - ARP(Address Resolution Protocol) IP address를이용한 MAC address를 Resolution하는 Protocol 기술이다. Peer로부터수신한 ARP-request에대한 ARP-reply를전송하며, Peer의 MAC address를찾는 ARPrequest를전송하며, 그에대한 ARP-reply를수신하여처리한다. - IP(Internet Protocol) IP layer의 Data 통신을지원하는 Protocol 기술이다. IP fragmentation은지원하지않는다. Fragmentation이발생한모든 Packet은수신할수없다. TCP나 UDP를제외한모든 protocol number를지원한다. TCP나 UDP는이미구현되어있는 Hardwired Stack을이용한다. - ICMP(Internet Control Message Protocol) Ethernet상의 Fragment MTU와 Unreachable destination의 ICMP packet들을수신하고이를 Host에게알리며, Ping-request ICMP packet을수신하여 Ping-reply ICMP packet을전송한다. Ping-request size는 119Byte 이상지원하지않는다. - IGMPv1/v2(Internet Group Management Protocol version 1/2) UDP에서 Multicasting 통신을할경우 IGMP Join/Leave, Report와같은 IGMP를처리한다. IGMP logic은 Version 1과 2만을지원한다. 상위버전의 IGMP를사용하고자할경우 IP layer를이용하여직접구현한다. - UDP(User Datagram Protocol) UDP layer의 Data 통신을지원하는 Protocol 기술이다. Unicast, Multicast, Broadcast 방식의 User datagram을지원한다. - TCP(Transmission Control Protocol) TCP layer의 Data 통신을지원하는 Protocol 기술이다. TCP SERVER 와 TCP CLIENT 통신을지원한다. W5300은모든 Protocol 처리를 Host 개입없이순수 Hardware logic으로만처리하여, TCP/IP stack 처리에대한 Host overhead를줄여, Host의자원을보다효율적으로활용할수있도록해주는 TOE(TCP/IP Offload Engine) 기술을기반으로하고있다. Copyright 2008 WIZnet Co., Inc. All rights reserved. 8

9 Table of Contents 1. PIN Description PIN Layout Configuration Signals Host Interface Signals Media Interface Signals MII Interface signal for External PHY Clock Signals Power Supply Signals System Memory Map W5300 Registers Mode Register Indirect Mode Registers Common Registers Socket Registers Register Description Mode Register Indirect Mode Registers Common Registers Socket Registers Functional Description Initialization Data Communication TCP UDP IPRAW MACRAW External Interface Direct Address Mode Bit Data Bus Width Bit Data Bus Width Indirect Address Mode Bit Data Bus Width Bit Data Bus Width Internal PHY Mode External PHY Mode Copyright 2008 WIZnet Co., Inc. All rights reserved. 9

10 7. Electrical Specifications IR Reflow Temperature Profile (Lead-Free) Package Descriptions List of Figures Fig 1. PIN Layout Fig 2. Power Design Fig 3. Memory Map Fig 4. BRDYn Timing Fig 5. SOCKETn Status Transition Fig 6. Access to Internal TX Memory Fig 7. Access to Internal RX Memory Fig 8. Allocation Internal TX/RX memory of SOCKETn Fig 9. TCP SERVER & TCP CLIENT Fig 10. TCP SERVER Operation Flow Fig 11. The received TCP data format Fig 12. TCP CLIENT Operation Flow Fig 13. UDP Operation Flow Fig 14. The received UDP data format Fig 15. IPRAW Operation Flow Fig 16. The received IPRAW data format Fig 17. MACRAW Operation Flow Fig 18. The received MACRAW data format Fig 19. Internal PHY & LED Signals Fig 20. External PHY Interface with MII Copyright 2008 WIZnet Co., Inc. All rights reserved. 10

11 1. PIN Description Type Description Type Description I Input D Internal pulled-down with 75KΩ resistor O Output M Multi-function IO Input/Output (Bidirectional) H Active high U Internal pulled-up with 75KΩ resistor L Active low <Notation> IUL : Input PIN with 75KΩ pull-up resistor. Active low OM : Multi-functional output PIN 1.1 PIN Layout Fig 1. PIN Layout Copyright 2008 WIZnet Co., Inc. All rights reserved. 11

12 1.2 Configuration Signals Symbol Type Description TEST_MODE[3:0] ID W5300 MODE SELECT W5300의 PHY mode 및 Factory test mode를설정한다. TEST_MODE Description Internal PHY mode Normal operation mode, Auto-negotiation enable with all capabilities External PHY mode with crystal clock External PHY mode with oscillator clock Others Reserved (Factory test mode) External PHY mode에서 Clock source에따라사용되는 Clock input pin이달라진다. 1.7 Clock Signals 참조. OP_MODE[2:0] ID Internal PHY Operation Control Mode Internal PHY 의여러가지동작 Mode 를설정한다. OP_MODE Description Normal operation mode, 권장 Auto-negotiation enable with all capabilities Auto-negotiation with 100 BASE-TX FDX/HDX ability Auto-negotiation with 10 BASE-T FDX/HDX ability Reserved Manual selection of 100 BASE-TX FDX Manual selection of 100 BASE-TX HDX Manual selection of 10 BASE-T FDX Manual selection of 10 BASE-T HDX cf> FDX : Full-duplex, HDX : Half-duplex 설정값은 Hardware reset 이후 Latch 된다. Copyright 2008 WIZnet Co., Inc. All rights reserved. 12

13 1.3 Host Interface Signals Symbol Type Description /RESET IL RESET Hardware reset signal. W5300을초기화한다. RESET은 Low assert 이후최소 2us 이상유지해야하고, High de-assert 이후내부 PLL logic이안정화될때까지최소 10ms 이상대기해야한다. 7 Electrical Specification 의 RESET Timing 참조. W5300은 Power-On-Reset을지원하지않는다. 따라서 Power-On-Reset Circuit를 Target system에설계해야한다. BIT16EN IU 16/8 BIT DATA BUS SELECT High : 16 bit data bus Low : 8 bit data bus Data bus width를결정한다. 이 Signal은 Reset 시내부적으로 Mode register(mr) 의 15번째 Bit( BW ) 로 Latch되며, Reset 이후의 Signal 변화는무시된다. 즉 Reset 이후 Data bus width를변경할수없다. 8bit data bus를사용할경우반드시 Ground 처리한다. ADDR9-0 ID ADDRESS System address bus. W5300의 Host interface mode와 Data bus width에따라선택적으로사용될수있다. 16 Bit Data bus를사용할경우 ADDR0은내부적으로무시된다. 6. External Interface 참조. DATA[15:8] IO DATA System high data bus. W5300 register의 Read/Write에사용된다. 8bit data bus를사용할경우 High-Z 상태가된다.(High-Z driven) DATA[7:0] IO DATA System low data bus. W5300 register 의 Read/Write 에사용된다. Copyright 2008 WIZnet Co., Inc. All rights reserved. 13

14 /CS IL CHIP SELECT Chip Select Signal. Host는 W5300 Read/Write operation시 W5300을선택한다. /CS signal이 High de-assert된경우 DATA[15:0] 은 High-Z 가된다. /WR IL WRITE ENABLE Write Enable Signal. Host에서 ADDR[9:0] 으로선택한 W5300 register에 DATA[15:0] 값을 Write하도록한다. DATA[15:0] 은 W5300 Write data fetch timing 설정에따라 W5300으로 Latch 된다. (MR의 13-11번째 bit(wdf[2:0]) 참조 ) /RD IL READ ENABLE Read Enable Signal. Host에서 ADDR[9:0] 으로선택한 W5300 register를 DATA[15:0] 를통해 Read하도록한다. /INT OL INTERRUPT Interrupt Request Signal. W5300이동작중 Interrupt (Connected, Disconnected, Data Received, Data Sent, or Timeout) 가발생할경우 Low assert되며, Host의 Interrupt service가완료되고 Interrupt register(ir) 가 Clear될때 High de-assert된다. IR, Interrupt Mask Register(IMR), SOCKETn Interrupt Register(Sn_IR), SOCKETn Interrupt Mask Register(Sn_IMR) 참조. BRDY[3:0] O Buffer Ready Indicator 각 PIN들은사용자에의해 SOCKET Number, Memory Type, Buffer Depth등을설정되고, 설정된 SOCKET의 Memory가 Buffer Depth보다크거나같을경우 High나 Low로 Signal된다. 4.2 COMMON Registers 의 Pn_BRDYR과 Pn_DPTHR 참조. Copyright 2008 WIZnet Co., Inc. All rights reserved. 14

15 1.4 Media Interface Signals W5300의 Internal PHY mode(test_mode[3:0] = 0000, 1.2 Configuration Signals 참조 ) 를 사용할경우, Network media(10mbps/10mbps) 와 Interface하기위한 Signals이다. Symbol Type Description RXIP RXIN I I RXIP/RXIN Signal Pair Differential receive Input signal pair. Media로부터 Data을수신한다. 이 Signal pair는더좋은 Impedance matching을위해 2개의 Termination resistor 50Ω(±1%) 과 1개의 Capacitor 0.1uF이 필요하며, 이 Resistor/Capacitor pair는 Magnetic(Transformer) 에보다가깝게위치시킨다. 사용하지않을경우 Ground 처리한다. TXOP TXON O O TXOP/TXON Signal Pair Differential transmit output signal pair. Media로 Data를송신한다. 이 Signal pair는더좋은 Impedance matching을위해 2개의 Termination resistor 50Ω(±1%) 과 1개의 Capacitor 0.1uF이필요하며, 이 Resistor/Capacitor pair는 W5300에보다가깝게위치시킨다. 사용하지않을경우 Float시킨다. RSET_BG O Off-chip Resistor 이 PIN 은 12.3 kω (±1%) Resistor 을통해 Ground 로반드시연결한다. 안정적인동작을위한권장사항이다. 1. RXIP/RXIN signal pair(rx) 의길이를가능한같게한다. 2. TXOP/TXON signal pair(tx) 의길이를가능한같게한다. 3. RXIP와 RXIN signal은최대한가깝게위치시킨다. 4. TXOP와 TXON signal은최대한가깝게위치시킨다. 5. RX와 TX signal pair는 bias resistor나 crystal 같은 noisy signals과는최대한멀리떨어지도록한다. 자세한내용은 W5100 Layout Guide.pdf 를참조하라. Copyright 2008 WIZnet Co., Inc. All rights reserved. 15

16 1.5 MII Interface signal for external PHY MII interface signal들은 W5300의 Internal PHY를사용하지않고, External PHY를사용할경 우 External PHY와 Interface를위한 Signal들이다. External PHY Mode(TEST_MODE[3:0] = 0001 or 0010 ) 일때사용된다. 1.2 Configuration Signals 참조. Internal PHY mode를사용할경우 Multi-function PIN들을제외한나머지 PIN 들은 Internal pulled-down 되어있으므로 float 시켜도무방하다. Symbol Type Description /TXLED(MII_TXEN) OMH Transmit Act LED / Transmit Enable MII_TXD[3:0] 으로출력되는 Transmit packet이 Valid 함을알리는 signal이다. Transmit packet이 MII_TXD[3:0] 를통해 MII_TXC clock에동기화되어 Nibble 단위로출력될때 High assert되며, Transmit packet의마지막 Nibble data가출력된후 Low de-assert된다. /RXLED(MII_TXD3) OM /RXLED,/COLLED,/FDXLED,/SPDLED / Transmit data output /COLLED(MII_TXD2) /FDXLED(MII_TXD1) /SPDLED(MII_TXD0) MII_TXC ID MII_TXEN이 High일때, Transmit packet이 Nibble 단위로 MII_TXC clock에동기화되어출력된다. MII_TXD3가 Most Significant Bit(MSB) 이다. Transmit Clock Input External PHY로부터입력되는연속적인 Transmit clock으로 100BaseTX일때 25MHz, 10BaseT일때 2.5MHz이다. Transmit clock은 MII_TXD[3:0] 의 Timing reference로사용되며, W5300 의 Network operation을위한 Clock(NIC_CLK) 으로사용된다. Rising edge sensitive. MII_CRS IDH Carrier Sense MII_COL IDH Collision Detect Media 의 Link traffic 을알려주는 Signal 로 Media 의 Carrier 가 Idle 이아닐경우 (Carrier present) High assert 된다. Media 상에서 Collision 이검출되면 High assert 된다. Half-duplex 에서만유효하며, Full-duplex 는무시된다. Asynchronous signal. Copyright 2008 WIZnet Co., Inc. All rights reserved. 16

17 MII_RXD3 ID Receive Data Input MII_RXD2 MII_RXD1 MII_RXD0 MII_RXDV IDH MII_RXDV가 High일때, Receive packet이 Nibble 단위로 MII_RXC에동기화되어입력된다. MII_RXD3가 MSB이다. Receive Data Valid MII_RXD[3:0] 으로부터입력되는 Receive packet이 Valid 함을알리는 signal이다. Receive packet이 MII_RXD[3:0] 으로부터 MII_RXC clock에동기화되어 Nibble 단위로입력될때 High assert되며, Receive packet의마지막 Nibble data가입력된후 Low de-assert된다. MII_RXC가 Rising edge일때 Valid하다. MII_RXC ID Receive Clock Input External PHY로부터입력되는 Continuous receive clock으로 100BaseTX일때 25MHz, 10BaseT일때 2.5MHz이다. Receive clock은 MII_RXD[3:0] 와 MII_RXDV의 Timing reference로사용. Rising edge sensitive. /FDX IDL Full-Duplex Select 0 : Full-duplex 1 : Half-duplex External PHY의현재 Link된상태 (Full-duplex/Half-duplex) 를입력받는 Signal이다. 대부분의 External PHY는 Autonegotiation을지원하고그결과를 Network Indicator LED나그외의 Signals을통해알려준다. /FDX는이런 Signal과연결될수있으며, 또한 High나 Low를직접입력하여 Manually 설정이가능하다. 안정적인동작을위한권장사항이다. 1. MII Interface Signal의길이는 25cm를가능한넘지않도록한다. 2. MII_TXD[3:0] Signal의길이는가능한같게한다. 3. MII_RXD[3:0] Signal의길이는가능한같게한다. 4. MII_TXD[3:0] 와 MII_TXC에서, MII_TXC의길이는 MII_TXD[3:0] 의길이보다 2.5cm를초과하지않도록한다. 5. MII_RXD[3:0] 와 MII_RXC에서, MII_RXC의길이는 MII_RXD[3:0] 의길이보다 2.5cm를초과하지않도록한다. Copyright 2008 WIZnet Co., Inc. All rights reserved. 17

18 1.6 Network Indicator LED Signals LINKLED를제외한나머지 Signal은 TEST_MODE[3:0] 의설정에따라 Multi-function PIN으로 사용된다. 이 Signal을 Network indicator signal로사용할경우 Internal PHY mode (TEST_MODE[3:0]= 0000 ) 로설정해야된다. Symbol Type Description LINKLED OML Link LED Media(10/100M) 의연결상태를알려준다. /TXLED(MII_TXEN) OML Transmit activity LED/Transmit Enable TXOP/TXON을통한 Transmit Data의출력 (Transmit Activity) 을알린다. /RXLED(MII_TXD3) OML Receive activity LED/Transmit Data RXIP/RXIN로부터의 Receive Data의입력 (Receive activity) 을알린다. cf> /TXLED와 /RXLED signal을 AND gate로연결하여 Network activity LED로사용할수있다. /COLLED(MII_TXD2) OML Collision LED/Transmit Data Collision 발생을알린다. Half-duplex에서만유효하며, Full-duplex이면 High를유지한다. /FDXLED(MII_TXD1) OML Full duplex LED/Transmit Data Auto-negotiation 이나 OP_MODE[2:0] 의 Manual 설정에따라, Full-duplex 이면 Low, Half-duplex 이면 High. /SPDLED(MII_TXD0) OML Link speed LED/Transmit Data Auto-negotiation 이나 OP_MODE[2:0] 의 Manual 설정에따라, 100Mbps 이면 Low, 10Mbps 이면 High. Copyright 2008 WIZnet Co., Inc. All rights reserved. 18

19 1.7 Clock Signals W5300은 Crystal과 Oscillator를 Clock source로사용할수있으나, 보다안정적인동작을위 해 Crystal clock 사용을권장한다. Clock source로부터입력되는 25MHz frequency는 W5300의 PLL logic을거쳐생성된 150MHz frequency로생성된다. PLL logic을거쳐생성된 150MHz frequency는 PLL_CLK(Period 6.67ns) 으로 W5300 core operation clock으로사용된다. Symbol Type Description XTLP XTLN I O 25MHz crystal input/output 25MHz parallel-resonant crystal은 Internal oscillator stabilization을위해 Matching capacitor와함께연결되어사용된다. 7.Electrical Specifications 의 Clock Characteristics 참조. 이 Signal은 Internal PHY mode(test_mode[3:0]= 0000 ) 나 External PHY mode with crystal clock (TEST_MODE[3:0] = 0001 ) 일때만사용된다. Internal PHY mode에서 Oscillator를사용할경우, 반드시 1.8V Level의 Oscillator를사용하며, Clock source를 XTLP에만연결하고 XTLN은 float 시킨다. OSC25I I 25MHz Oscillator input External PHY mode with oscillator clock(test_mode[3:0]= 0010 ) 일때만사용된다. 이때 XTLP는 leakage current를방지하기위해반드시 High 로유지하고 XPLN을 Float 시키며, 1.8V Level의 oscillator를사용해야한다. 1.8 Power Supply Signals Symbol Type Description VCC3A3 Power 3.3V power supply for Analog part VCC3A3 과 GNDA 사이에는 Power compensation 을위한 10uF Tantalum capacitor 을반드시연결한다. VCC3V3 Power 3.3V power supply for Digital part 각각의 VCC3V3 과 GND 사이에는 0.1uF Decoupling capacitor 를 선택적으로연결한다. VCC3V3 는 1uH Ferrite bead 로분리되어 Copyright 2008 WIZnet Co., Inc. All rights reserved. 19

20 VCC3A3으로연결할수있다. VCC1A8 Power 1.8V power supply for Analog part VCC1A8과 GNDA사이에는 Core power noise filtering을위한 10uF Tantalum capacitor와 0.1uF Capacitor을반드시연결한다. VCC1V8 Power 1.8V power supply for Digital part 각각의 VCC1V8과 GND사이에는 0.1uF Decoupling capacitor를선택적으로연결한다. GNDA Ground Analog ground PCB layout 시 Analog ground plane을가능한넓게한다. GND Ground Digital ground PCB layout 시 Digital ground plane을가능한넓게한다. 1V8O O 1.8V regulator output voltage Internal Power regulator에서생성되는 1.8V/150mA Power로 Core operation power(vcc1a8, VCC1V8) 로사용된다. 1V8O와 GND사이에 Output frequency compensation을위한 3.3uF Tantalum capacitor는반드시연결하고, High frequency noise decoupling을위한 0.1uF Capacitor는선택적으로연결한다. 1V8O은 VCC1V8와연결되고 1uH ferrite bead로분리되어 VCC1A8로연결된다. <Notice> 1V8O 는 W5300 의 Core operation 을위한 Power 이므로 다른 Device 의 Power 로연결해서는안된다. Copyright 2008 WIZnet Co., Inc. All rights reserved. 20

21 3.3V Power Source VCC3V3 10uF 0.1uF VCC1V8 1V8O 3.3uF 10uF VCC3A3 Ferrite Bead 0.1uF 10uF Ferrite Bead 0.1uF VCC1A8 Ferrite Bead 0.1uF 10uF 0.1uF Ferrite Bead 0.1uF Fig 2. Power Design VCC3V3 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF VCC1V8 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF Power 설계를위한권장사항이다. 1. Decoupling capacitor는가능한 W5300에가깝게위치. 2. Ground plane은가능한넓게사용. 3. Ground plane이충분히넓다면 Analog ground plane과 Digital ground plane를분리. Ground plane 이충분히넓지않다면, Analog ground plane 과 Digital ground plane 을분리하는 것보다 Single ground plane 으로설계하는것이더좋다. Copyright 2008 WIZnet Co., Inc. All rights reserved. 21

22 2. System Memory Map W5300은 Host interface 방식으로 Direct address mode와 Indirect address mode를지원한다. Direct address mode란, Target host system이 W5300 register들을 T.M.S(Target host system의 Memory-mapped I/O Space) 에 Mapping한후, Mapping된 W5300 register들을직접적으로 Access하는 Mode를말한다. W5300에서의 Direct address mode memory map은 Mode register(mr), COMMON registers, SOCKET registers들로구성되며, 이 Register들은 T.M.S의 BA(Base Address) 에서부터 2Byte씩증가하며순차적으로 Mapping된다. Target host system은 Mapping된 Address로 W5300의 MR, COMMON registers, SOCKET registers을직접적으로 Access할수있다. 따라서, Target host system이 W5300을 Direct address mode로사용할경우총 0x400 Bytes의 Memory space가필요하게된다. Indirect address mode란, Target host system이 W5300의 MR, Indirect mode address register(idm_ar), Indirect mode data register(idm_dr) 만을 T.M.S에 Mapping한후, Mapping된 IDM_AR과 IDM_DR register만을직접적으로 Access하여, COMMON registers와 SOCKET registers를간접적으로 Access하는 Mode를말한다. W5300에서의 Indirect address mode memory map은 Host가직접적으로 Access할수있는 MR, IDM_AR, IDM_DR과, 간접적으로 Access할수있는 COMMON registers, SOCKET registers 들로구성된다. MR, IDM_AR, IDM_DR만 T.M.S의 BA(Base Address) 에서부터 2Byte씩증가하며순차적으로 Mapping되고, COMMON & SOCKET registers들은 IDM_AR & IDM_DR을이용하여간접적으로 Access되기때문에 T.M.S에 Mapping되지않는다. 따라서, Target host system이 Indirect address mode로사용할경우 0x06 Bytes의 Memory space만필요하게된다. 예로, Target host system이 Indirect mode로 COMMON registers의 Interrupt register(ir) 를 Access할경우 Host Write : IDM_AR를 IR의주소 0x0002 설정 (IDM_AR = 0x0002) IDM_DR에 0xFFFF로설정 (IDM_DR = 0xFFFF) Host Read : IDM_AR를 IR의주소 0x0002 설정 (IDM_AR = 0x0002) IDM_DR을 Read하여 Value로저장 (Value = IDM_DR) W5300 의 Host interface mode 는 MR 의 IND bit (0 번째 Bit) 의값에따라결정된다. MR(0) = 0 이면, Direct address mode MR(0) = 1 이면, Indirect address mode 각 Host interface 방식에따른 Target host system memory Map 은다음과같다. Copyright 2008 WIZnet Co., Inc. All rights reserved. 22

23 Target Host System Memory- Mapped I/O Space (T.M.S) BA + 0x000 MR (Mode Reg) Mode Register BA + 0x002 IR (Interrupt Reg) BA + 0x004 IMR (Interrupt Mask Reg). Common Registers. BA + 0x0FE IDR (ID Reg) BA + 0x100 Reserved BA + 0x1FE BA + 0x200 BA + 0x240 BA + 0x280 BA + 0x2C0 BA + 0x300 BA + 0x340 BA + 0x380 S0_MR (SOCKET0 Mode Reg) S1_MR S2_MR S3_MR S4_MR S5_MR S6_MR BA + 0x3C0 S7_MR BA + 0x3FF Direct Address Mode (MR(0) = 0 ) Socket Registers BA + 0x002 MR 0x000 Reserved T.M.S BA + 0x002 IDM_AR 0x002 IR BA + 0x004 IDM_DR 0x004 IMR 0x0FE IDR 0x100 Reserved 0x1FE 0x200 S0_MR W5300 0x240 0x280 0x2C0 0x300 0x340 0x380 S1_MR S2_MR S3_MR S4_MR S5_MR S6_MR Internal Memory-Mapped Space (W.M.S) 0x3C0 S7_MR 0x3FF Indirect Address Mode (MR(0) = 1 ) Fig 3. Memory Map Copyright 2008 WIZnet Co., Inc. All rights reserved. 23

24 3. W5300 Registers W5300 register은 Direct/Indirect address mode를결정하는 MR와, Indirect address mode로설정시사용되는 IDM_AR & IDM_DR와, Address mode에상관없이사용되는 COMMON registers, SOCKET registers로구성된다. MR, IDM_AR, IDM_DR은 Target host system의 T.M.S에 Mapping되며, COMMON registers와 SOCKET registers는 Address mode에따라 T.M.S 혹은 W.M.S(W5300 Internal Memory Space) 에 Mapping된다. 모든 W5300 register는 1Byte, 2Bytes, 4Bytes, 6Bytes로구성되어있으며, Target host system 의 Data bus width에따라 16Bit data bus인경우 2 bytes address offset으로, 8Bit data bus인경우 1 byte address offset으로 Access 할수있다. W5300의 register가 T.M.S에 Mapping될경우, W5300 register의 Physical T.M.S address는 Physical Address of W5300 Reg = Base Address of T.M.S + Address offset of W5300 Reg 로구성된다. 또한, 모든 W5300 register의 Byte ordering은 Low address byte가 Most significant byte로사용되는 Big-endian을사용한다. [Register Notation] MR : MR register MR0 : Low address register of MR (Address offset - 0x000 ), Most significant byte MR1 : High address register of MR (Address offset 0x001), Least significant byte MR(15:5) : MR register의 15번 bit부터 5번 bit까지 11 bit MR(0) : MR register의 0번째 bit, MR1의 0번째 bit MR(13) : MR register의 13번째 bit, MR0의 5번째 Bit MR0(7) : MR register의 15번째 bit, Most significant bit of MR0 MR(DWB) : MR의 DWB bit (DWB : Bit Symbol) SHAR : Source Hardware Address Register SHAR0 : 1 ST address register of SHAR (Address offset 0x008) SHAR1 : 2 nd address register of SHAR (Address offset 0x009) SHAR2 : 3 rd address register of SHAR (Address offset 0x00A) SHAR3 : 4 th address register of SHAR (Address offset 0x00B) SHAR4 : 5 th address register of SHAR (Address offset 0x00C) SHAR5 : 6 th address register of SHAR (Address offset 0x00D) Copyright 2008 WIZnet Co., Inc. All rights reserved. 24

25 3.1 Mode Register Address offset Symbol 16Bit 8Bit 16Bit 8Bit 0x000 MR0 0x000 MR 0x001 MR1 3.2 Indirect Mode Registers Address offset Symbol 16Bit 8Bit 16Bit 8Bit 0x002 0x002 IDM_AR0 IDM_AR 0x003 IDM_AR1 0x004 0x004 IDM_DR0 IDM_DR 0x005 IDM_DR1 3.3 COMMON registers Address offset Symbol 16Bit 8Bit 16Bit 8Bit Description Mode Register Description Indirect Mode Address Register Indirect Mode Data Register Description 0x002 0x002 IR0 IR 0x003 IR1 Interrupt Register 0x004 0x004 IMR0 IMR 0x005 IRM1 Interrupt Mask Register 0x006 0x006 0x007 Reserved 0x008 0x008 SHAR0 Source Hardware Address Register SHAR 0x009 SHAR1 0x00A 0x00A SHAR2 SHAR2 0x00B SHAR3 0x00C 0x00C SHAR4 SHAR4 0x00D SHAR5 0x00E 0x00E Reserved 0x00F 0x010 0x010 GAR0 Gateway Address Register GAR 0x011 GAR1 0x12 0x012 GAR2 GAR2 0x013 GAR3 Copyright 2008 WIZnet Co., Inc. All rights reserved. 25

26 Address offset Symbol Description 16Bit 8Bit 16Bit 8Bit 0x014 0x016 0x018 0x01A 0x01C 0x01E 0x020 0x022 0x24 0x26 0x028 0x02A 0x02C 0x02E 0x030 0x032 0x014 SUBR0 Subnet Mask Register SUBR 0x015 SUBR1 0x016 SUBR2 SUBR2 0x017 SUBR3 0x018 SIPR0 Source IP Address Regsiter SIPR 0x019 SIPR1 0x01A SIPR2 SIPR2 0x01B SIPR3 0x01C RTR0 Retransmission Timeout-value Register RTR 0x01D RTR1 0x01E RCR0 Reserved RCR 0x01F RCR1 Retransmission Retry-count Register 0x020 TMSR0 Transmit Memory Size Register of SOCKET0 TMS01R 0x021 TMSR1 Transmit Memory Size Register of SOCKET1 0x022 TMSR2 Transmit Memory Size Register of SOCKET2 TMS23R 0x023 TMSR3 Transmit Memory Size Register of SOCKET3 0x024 TMSR4 Transmit Memory Size Register of SOCKET4 TMS45R 0x025 TMSR5 Transmit Memory Size Register of SOCKET5 0x026 TMSR6 Transmit Memory Size Register of SOCKET7 TMS67R 0x027 TMSR7 Transmit Memory Size Register of SOCKET 8 0x028 RMSR0 Receive Memory Size Register of SOCKET0 RMS01R 0x029 RMSR1 Receive Memory Size Register of SOCKET1 0x02A RMSR2 Receive Memory Size Register of SOCKET2 RMS23R 0x02B RMSR3 Receive Memory Size Register of SOCKET3 0x02C RMSR4 Receive Memory Size Register of SOCKET4 RMS45R 0x02D RMSR5 Receive Memory Size Register of SOCKET5 0x02E RMSR6 Receive Memory Size Register of SOCKET6 RMS67R 0x02F RMSR7 Receive Memory Size Register of SOCKET7 0x030 MTYPER0 Memory Block Type Register MTYPER 0x031 MTYPER1 0x032 PATR0 PPPoE Authentication Register PATR 0x033 PATR1 Copyright 2008 WIZnet Co., Inc. All rights reserved. 26

27 Address offset Symbol Description 16Bit 8Bit 16Bit 8Bit 0x034 0x036 0x038 0x03A 0x03C 0x03E 0x040 0x042 0x044 0x046 0x048 0x04A 0x04C 0x04E 0x050 : : 0x5E 0x034 Reserved 0x035 0x036 PTIMER0 Reserved PTIMER 0x037 PTIMER1 PPP LCP Request Time Register 0x038 PMAGICR0 PMAGICR 0x039 PMAGICR1 PPP LCP Magic Number Register 0x03A Reserved 0x03B 0x03C PSIDR0 PPP Session ID Register PSIDR 0x03D PSIDR1 0x03E Reserved 0x03F 0x040 PDHAR0 PPP Destination Hardware Address Register PDHAR 0x041 PDHAR1 0x042 PDHAR2 PDHAR2 0x043 PDHAR3 0x044 PDHAR4 PDHAR4 0x045 PDHAR5 0x046 Reserved 0x047 0x048 UIPR0 Unreachable IP Address Register UIPR 0x049 UIPR1 0x04A UIPR2 UIPR2 0x04B UIPR3 0x04C UPORT0 Unreachable Port Number Register UPORTR 0x04D UPORT1 0x04E FMTUR0 Fragment MTU Register FMTUR 0x04F FMTUR1 0x050 Reserved 0x051 : : 0x05E Reserved 0x060 Copyright 2008 WIZnet Co., Inc. All rights reserved. 27

28 Address offset Symbol Description 16Bit 8Bit 16Bit 8Bit 0x060 0x062 0x064 0x066 0x068 0x06A 0x06C 0x06E 0x070 : : 0xFC 0xFE 0x060 P0_BRDYR0 Reserved P0_BRDYR 0x061 P0_BRDYR1 PIN "BRDY0" Configure Register 0x062 P0_BDPTHR0 PIN "BRDY0" Buffer Depth Register P0_BDPTHR 0x063 P0_BDPTHR1 0x064 P1_BRDYR0 Reserved P1_BRDYR 0x065 P1_BRDYR1 PIN "BRDY1" Configure Register 0x066 P1_BDPTHR0 PIN "BRDY1" Buffer Depth Register P1_BDPTHR 0x067 P1_BDPTHR1 0x068 P1_BRDYR0 Reserved P2_BRDYR 0x069 P2_BRDYR1 PIN "BRDY2" Configure Register 0x06A P2_BDPTHR0 PIN "BRDY2" Buffer Depth Register P2_BDPTHR 0x06B P2_BDPTHR1 0x06C P3_BRDYR0 Reserved P3_BRDYR 0x06D P3_BRDYR1 PIN "BRDY3" Configure Register 0x06E P3_BDPTHR0 PIN "BRDY3" Buffer Depth Register P3_BDPTHR 0x06F P3_BDPTHR1 0x070 Reserved 0x071 : : 0x0FC Reserved 0x0FD 0x0FE IDR0 W5300 ID Register IDR 0x0FF IDR1 Copyright 2008 WIZnet Co., Inc. All rights reserved. 28

29 3.4 SOCKET registers Address offset Symbol Description 16Bit 8Bit 16Bit 8Bit 0x200 0x202 0x204 0x206 0x208 0x20A 0x20C 0x20E 0x210 0x212 0x214 0x216 0x218 0x21A 0x21C 0x21E 0x200 S0_MR0 SOCKET0 Mode Register S0_MR 0x201 S0_MR1 0x202 S0_CR0 Reserved S0_CR 0x203 S0_CR1 SOCKET0 Command Register 0x204 S0_IMR0 Reserved S0_IMR 0x205 S0_IMR1 SOCKET0 Interrupt Mask Register 0x206 S0_IR0 Reserved S0_IR 0x207 S0_IR1 SOCKET0 Interrupt Register 0x208 S0_SSR0 Reserved S0_SSR 0x209 S0_SSR1 SOCKET0 Socket Status Register 0x20A S0_PORTR0 SOCKET0 Source Port Register S0_PORTR 0x20B S0_PORTR1 0x20C S0_DHAR0 SOCKET0 Destination Hardware S0_DHAR 0x20D S0_DHAR1 Address Register 0x20E S0_DHAR2 S0_DHAR2 0x20F S0_DHAR3 0x210 S0_DHAR4 S0_DHAR4 0x211 S0_DHAR5 0x212 S0_DPORTR0 SOCKET0 Destination Port Register S0_DPORTR 0x213 S0_DPORTR1 0x214 S0_DIPR0 SOCKET0 Destination IP Address S0_DIPR 0x215 S0_DIPR1 Register 0x216 S0_DIPR2 S0_DIPR2 0x217 S0_DIPR3 0x218 S0_MSSR0 SOCKET0 Maximum Segment Size S0_MSSR 0x219 S0_MSSR1 Register 0x21A S0_KPALVTR SOCKET0 Keep Alive Time Register S0_PORTOR 0x21B S0_PROTOR SOCKET0 Protocol Number Register 0x21C S0_TOSR0 Reserved S0_TOSR 0x21D S0_TOSR1 SOCKET0 TOS Register 0x21E S0_TTLR0 Reserved S0_TTLR 0x21F S0_TTLR1 SOCKET0 TTL Register Copyright 2008 WIZnet Co., Inc. All rights reserved. 29

30 Address offset Symbol Description 16Bit 8Bit 16Bit 8Bit 0x220 0x222 0x224 0x226 0x228 0x22A 0x22C 0x22E 0x230 0x232 : : 0x23E 0x220 S0_TX_WRSR0 Reserved S0_TX_WRSR 0x221 S0_TX_WRSR1 SOCKET0 TX Write Size Register 0x222 S0_TX_WRSR2 S0_TX_WRSR2 0x223 S0_TX_WRSR3 0x224 S0_TX_FSR0 Reserved S0_TX_FSR 0x225 S0_TX_FSR1 SOCKET0 TX Free Size Register 0x226 S0_TX_FSR2 S0_TX_FSR2 0x227 S0_TX_FSR3 0x228 S0_RX_RSR0 Reserved S0_RX_RSR 0x229 S0_RX_RSR1 SOCKET0 RX Receive Size Register 0x22A S0_RX_RSR2 S0_RX_RSR2 0x22B S0_RX_RSR3 0x22C S0_FRAGR0 Reserved S0_FRAGR 0x22D S0_FRAGR1 SOCKET0 FLAG Register 0x22E S0_TX_FIFOR0 SOCKET0 TX FIFO Register S0_TX_FIFOR 0x22F S0_TX_FIFOR1 0x230 S0_RX_FIFOR0 SOCKET0 RX FIFO Register S0_RX_FIFOR 0x231 S0_RX_FIFOR1 0x232 Reserved 0x233 : : 0x23E Reserved 0x23F Copyright 2008 WIZnet Co., Inc. All rights reserved. 30

31 Address offset Symbol Description 16Bit 8Bit 16Bit 8Bit 0x240 0x242 0x244 0x246 0x248 0x24A 0x24C 0x24E 0x250 0x252 0x254 0x256 0x258 0x25A 0x25C 0x25E 0x240 S1_MR0 SOCKET1 Mode Register S1_MR 0x241 S1_MR1 0x242 S1_CR0 Reserved S1_CR 0x243 S1_CR1 SOCKET1 Command Register 0x244 S1_IMR0 Reserved S1_IMR 0x245 S1_IMR1 SOCKET1 Interrupt Mask Register 0x246 S1_IR0 Reserved S1_IR 0x247 S1_IR1 SOCKET1 Interrupt Register 0x248 S1_SSR0 Reserved S1_SSR 0x249 S1_SSR1 SOCKET1 Socket Status Register 0x24A S1_PORTR0 SOCKET1 Source Port Register S1_PORTR 0x24B S1_PORTR1 0x24C S1_DHAR0 SOCKET1 Destination Hardware S1_DHAR 0x24D S1_DHAR1 Address Register 0x24E S1_DHAR2 S1_DHAR2 0x24F S1_DHAR3 0x250 S1_DHAR4 S1_DHAR4 0x251 S1_DHAR5 0x252 S1_DPORTR0 SOCKET1 Destination Port Register S1_DPORTR 0x253 S1_DPORTR1 0x254 S1_DIPR0 SOCKET1 Destination IP Address S1_DIPR 0x255 S1_DIPR1 Register 0x256 S1_DIPR2 S1_DIPR2 0x257 S1_DIPR3 0x258 S1_MSSR0 SOCKET1 Maximum Segment Size S1_MSSR 0x259 S1_MSSR1 Register 0x25A S1_KPALVTR SOCKET1 Keep Alive Time Register S1_PORTOR 0x25B S1_PROTOR SOCKET1 Protocol Number Register 0x25C S1_TOSR0 Reserved S1_TOSR 0x25D S1_TOSR1 SOCKET1 TOS Register 0x25E S1_TTLR0 Reserved S1_TTLR 0x25F S1_TTLR1 SOCKET1 TTL Register Copyright 2008 WIZnet Co., Inc. All rights reserved. 31

32 Address offset Symbol Description 16Bit 8Bit 16Bit 8Bit 0x260 0x262 0x264 0x266 0x268 0x26A 0x26C 0x26E 0x270 0x272 : : 0x27E 0x260 S1_TX_WRSR0 Reserved S1_TX_WRSR 0x261 S1_TX_WRSR1 SOCKET1 TX Write Size Register 0x262 S1_TX_WRSR2 S1_TX_WRSR2 0x263 S1_TX_WRSR3 0x264 S1_TX_FSR0 Reserved S1_TX_FSR 0x265 S1_TX_FSR1 SOCKET1 TX Free Size Register 0x266 S1_TX_FSR2 S1_TX_FSR2 0x267 S1_TX_FSR3 0x268 S1_RX_RSR0 Reserved S1_RX_RSR 0x269 S1_RX_RSR1 SOCKET1 RX Receive Size Register 0x26A S1_RX_RSR2 S1_RX_RSR2 0x26B S1_RX_RSR3 0x26C S1_FRAGR0 Reserved S1_FRAGR 0x26D S1_FRAGR1 SOCKET1 IP FLAG Field Register 0x26E S1_TX_FIFOR0 SOCKET1 TX FIFO Register S1_TX_FIFOR 0x26F S1_TX_FIFOR1 0x270 S1_RX_FIFOR0 SOCKET1 RX FIFO Register S1_RX_FIFOR 0x271 S1_RX_FIFOR1 0x272 Reserved 0x273 : : 0x27E Reserved 0x27F Copyright 2008 WIZnet Co., Inc. All rights reserved. 32

33 Address offset Symbol Description 16Bit 8Bit 16Bit 8Bit 0x280 0x282 0x284 0x286 0x288 0x28A 0x28C 0x28E 0x290 0x292 0x294 0x296 0x298 0x29A 0x29C 0x29E 0x280 S2_MR0 SOCKET2 Mode Register S2_MR 0x281 S2_MR1 0x282 S2_CR0 Reserved S2_CR 0x283 S2_CR1 SOCKET2 Command Register 0x284 S2_IMR0 Reserved S2_IMR 0x285 S2_IMR1 SOCKET2 Interrupt Mask Register 0x286 S2_IR0 Reserved S2_IR 0x287 S2_IR1 SOCKET2 Interrupt Register 0x288 S2_SSR0 Reserved S2_SSR 0x289 S2_SSR1 SOCKET2 Socket Status Register 0x28A S2_PORTR0 SOCKET2 Source Port Register S2_PORTR 0x28B S2_PORTR1 0x28C S2_DHAR0 SOCKET2 Destination Hardware S2_DHAR 0x28D S2_DHAR1 Address Register 0x28E S2_DHAR2 S2_DHAR2 0x28F S2_DHAR3 0x290 S2_DHAR4 S2_DHAR4 0x291 S2_DHAR5 0x292 S2_DPORTR0 SOCKET2 Destination Port Register S2_DPORTR 0x293 S2_DPORTR1 0x294 S2_DIPR0 SOCKET2 Destination IP Address S2_DIPR 0x295 S2_DIPR1 Register 0x296 S2_DIPR2 S2_DIPR2 0x297 S2_DIPR3 0x298 S2_MSSR0 SOCKET2 Maximum Segment Size S2_MSSR 0x299 S2_MSSR1 Register 0x29A S2_KPALVTR SOCKET2 Keep Alive Time Register S2_PORTOR 0x29B S2_PROTOR SOCKET2 Protocol Number Register 0x29C S2_TOSR0 Reserved S2_TOSR 0x29D S2_TOSR1 SOCKET2 TOS Register 0x29E S2_TTLR0 Reserved S2_TTLR 0x29F S2_TTLR1 SOCKET2 TTL Register Copyright 2008 WIZnet Co., Inc. All rights reserved. 33

34 Address offset Symbol Description 16Bit 8Bit 16Bit 8Bit 0x2A0 0x2A2 0x2A4 0x2A6 0x2A8 0x2AA 0x2AC 0x2AE 0x2B0 0x2B2 : : 0x2BE 0x2A0 S2_TX_WRSR0 Reserved S2_TX_WRSR 0x2A1 S2_TX_WRSR1 SOCKET2 TX Write Size Register 0x2A2 S2_TX_WRSR2 S2_TX_WRSR2 0x2A3 S2_TX_WRSR3 0x2A4 S2_TX_FSR0 Reserved S2_TX_FSR 0x2A5 S2_TX_FSR1 SOCKET2 TX Free Size Register 0x2A6 S2_TX_FSR2 S2_TX_FSR2 0x2A7 S2_TX_FSR3 0x2A8 S2_RX_RSR0 Reserved S2_RX_RSR 0x2A9 S2_RX_RSR1 SOCKET2 RX Receive Size Register 0x2AA S2_RX_RSR2 S2_RX_RSR2 0x2AB S2_RX_RSR3 0x2AC S2_FRAGR0 Reserved S2_FRAGR 0x2AD S2_FRAGR1 SOCKET2 IP FLAG Field Register 0x2AE S2_TX_FIFOR0 SOCKET2 TX FIFO Register S2_TX_FIFOR 0x2AF S2_TX_FIFOR1 0x2B0 S2_RX_FIFOR0 SOCKET2 RX FIFO Register S2_RX_FIFOR 0x2B1 S2_RX_FIFOR1 0x2B2 Reserved 0x2B3 : : 0x2BE Reserved 0x2BF Copyright 2008 WIZnet Co., Inc. All rights reserved. 34

35 Address offset Symbol Description 16Bit 8Bit 16Bit 8Bit 0x2C0 0x2C2 0x2C4 0x2C6 0x2C8 0x2CA 0x2CC 0x2CE 0x2D0 0x2D2 0x2D4 0x2D6 0x2D8 0x2DA 0x2DC 0x2DE 0x2C0 S3_MR0 SOCKET3 Mode Register S3_MR 0x2C1 S3_MR1 0x2C2 S3_CR0 Reserved S3_CR 0x2C3 S3_CR1 SOCKET3 Command Register 0x2C4 S3_IMR0 Reserved S3_IMR 0x2C5 S3_IMR1 SOCKET3 Interrupt Mask Register 0x2C6 S3_IR0 Reserved S3_IR 0x2C7 S3_IR1 SOCKET3 Interrupt Register 0x2C8 S3_SSR0 Reserved S3_SSR 0x2C9 S3_SSR1 SOCKET3 Socket Status Register 0x2CA S3_PORTR0 SOCKET3 Source Port Register S3_PORTR 0x2CB S3_PORTR1 0x2CC S3_DHAR0 SOCKET3 Destination Hardware S3_DHAR 0x2CD S3_DHAR1 Address Register 0x2CE S3_DHAR2 S3_DHAR2 0x2CF S3_DHAR3 0x2D0 S3_DHAR4 S3_DHAR4 0x2D1 S3_DHAR5 0x2D2 S3_DPORTR0 SOCKET3 Destination Port Register S3_DPORTR 0x2D3 S3_DPORTR1 0x2D4 S3_DIPR0 SOCKET3 Destination IP Address S3_DIPR 0x2D5 S3_DIPR1 Register 0x2D6 S3_DIPR2 S3_DIPR2 0x2D7 S3_DIPR3 0x2D8 S3_MSSR0 SOCKET3 Maximum Segment Size S3_MSSR 0x2D9 S3_MSSR1 Register 0x2DA S3_KPALVTR SOCKET3 Keep Alive Time Register S3_PORTOR 0x2DB S3_PROTOR SOCKET3 Protocol Number Register 0x2DC S3_TOSR0 Reserved S3_TOSR 0x2DD S3_TOSR1 SOCKET3 TOS Register 0x2DE S3_TTLR0 Reserved S3_TTLR 0x2DF S3_TTLR1 SOCKET3 TTL Register Copyright 2008 WIZnet Co., Inc. All rights reserved. 35

36 Address offset Symbol Description 16Bit 8Bit 16Bit 8Bit 0x2E0 0x2E2 0x2E4 0x2E6 0x2E8 0x2EA 0x2EC 0x2EE 0x2F0 0x2F2 : : 0x2FE 0x2E0 S3_TX_WRSR0 Reserved S3_TX_WRSR 0x2E1 S3_TX_WRSR1 SOCKET3 TX Write Size Register 0x2E2 S3_TX_WRSR2 S3_TX_WRSR2 0x2E3 S3_TX_WRSR3 0x2E4 S3_TX_FSR0 Reserved S3_TX_FSR 0x2E5 S3_TX_FSR1 SOCKET3 TX Free Size Register 0x2E6 S3_TX_FSR2 S3_TX_FSR2 0x2E7 S3_TX_FSR3 0x2E8 S3_RX_RSR0 Reserved S3_RX_RSR 0x2E9 S3_RX_RSR1 SOCKET3 RX Receive Size Register 0x2EA S3_RX_RSR2 S3_RX_RSR2 0x2EB S3_RX_RSR3 0x2EC S3_FRAGR0 Reserved S3_FRAGR 0x2ED S3_FRAGR1 SOCKET3 IP FLAG Field Register 0x2EE S3_TX_FIFOR0 SOCKET3 TX FIFO Register S3_TX_FIFOR 0x2EF S3_TX_FIFOR1 0x2F0 S3_RX_FIFOR0 SOCKET3 RX FIFO Register S3_RX_FIFOR 0x2F1 S3_RX_FIFOR1 0x2F2 Reserved 0x2F3 : : 0x2FE Reserved 0x2FF Copyright 2008 WIZnet Co., Inc. All rights reserved. 36

37 Address offset Symbol Description 16Bit 8Bit 16Bit 8Bit 0x300 0x302 0x304 0x306 0x308 0x30A 0x30C 0x30E 0x310 0x312 0x314 0x316 0x318 0x31A 0x31C 0x31E 0x300 S4_MR0 SOCKET4 Mode Register S4_MR 0x301 S4_MR1 0x302 S4_CR0 Reserved S4_CR 0x303 S4_CR1 SOCKET4 Command Register 0x304 S4_IMR0 Reserved S4_IMR 0x305 S4_IMR1 SOCKET4 Interrupt Mask Register 0x306 S4_IR0 Reserved S4_IR 0x307 S4_IR1 SOCKET4 Interrupt Register 0x308 S4_SSR0 Reserved S4_SSR 0x309 S4_SSR1 SOCKET4 Socket Status Register 0x30A S4_PORTR0 SOCKET4 Source Port Register S4_PORTR 0x30B S4_PORTR1 0x30C S4_DHAR0 SOCKET4 Destination Hardware S4_DHAR 0x30D S4_DHAR1 Address Register 0x30E S4_DHAR2 S4_DHAR2 0x30F S4_DHAR3 0x310 S4_DHAR4 S4_DHAR4 0x311 S4_DHAR5 0x312 S4_DPORTR0 SOCKET4 Destination Port Register S4_DPORTR 0x313 S4_DPORTR1 0x314 S4_DIPR0 SOCKET4 Destination IP Address S4_DIPR 0x315 S4_DIPR1 Register 0x316 S4_DIPR2 S4_DIPR2 0x317 S4_DIPR3 0x318 S4_MSSR0 SOCKET4 Maximum Segment Size S4_MSSR 0x319 S4_MSSR1 Register 0x31A S4_KPALVTR SOCKET4 Keep Alive Time Register S4_PORTOR 0x31B S4_PROTOR SOCKET4 Protocol Number Register 0x31C S4_TOSR0 Reserved S4_TOSR 0x31D S4_TOSR1 SOCKET4 TOS Register 0x31E S4_TTLR0 Reserved S4_TTLR 0x31F S4_TTLR1 SOCKET4 TTL Register Copyright 2008 WIZnet Co., Inc. All rights reserved. 37

38 Address offset Symbol Description 16Bit 8Bit 16Bit 8Bit 0x320 0x322 0x324 0x326 0x328 0x32A 0x32C 0x32E 0x330 0x332 : : 0x33E 0x320 S4_TX_WRSR0 Reserved S4_TX_WRSR 0x321 S4_TX_WRSR1 SOCKET4 TX Write Size Register 0x322 S4_TX_WRSR2 S4_TX_WRSR2 0x323 S4_TX_WRSR3 0x324 S4_TX_FSR0 Reserved S4_TX_FSR 0x325 S4_TX_FSR1 SOCKET4 TX Free Size Register 0x326 S4_TX_FSR2 S4_TX_FSR2 0x327 S4_TX_FSR3 0x328 S4_RX_RSR0 Reserved S4_RX_RSR 0x329 S4_RX_RSR1 SOCKET4 RX Receive Size Register 0x32A S4_RX_RSR2 S4_RX_RSR2 0x32B S4_RX_RSR3 0x32C S4_FRAGR0 Reserved S4_FRAGR 0x32D S4_FRAGR1 SOCKET4 IP FLAG Field Register 0x32E S4_TX_FIFOR0 SOCKET4 TX FIFO Register S4_TX_FIFOR 0x32F S4_TX_FIFOR1 0x330 S4_RX_FIFOR0 SOCKET4 RX FIFO Register S4_RX_FIFOR 0x331 S4_RX_FIFOR1 0x332 Reserved 0x333 : : 0x33E Reserved 0x33F Copyright 2008 WIZnet Co., Inc. All rights reserved. 38

39 Address offset Symbol Description 16Bit 8Bit 16Bit 8Bit 0x340 0x342 0x344 0x346 0x348 0x34A 0x34C 0x34E 0x350 0x352 0x354 0x356 0x358 0x35A 0x35C 0x35E 0x340 S5_MR0 SOCKET5 Mode Register S5_MR 0x341 S5_MR1 0x342 S5_CR0 Reserved S5_CR 0x343 S5_CR1 SOCKET5 Command Register 0x344 S5_IMR0 Reserved S5_IMR 0x345 S5_IMR1 SOCKET5 Interrupt Mask Register 0x346 S5_IR0 Reserved S5_IR 0x347 S5_IR1 SOCKET5 Interrupt Register 0x348 S5_SSR0 Reserved S5_SSR 0x349 S5_SSR1 SOCKET5 Socket Status Register 0x34A S5_PORTR0 SOCKET5 Source Port Register S5_PORTR 0x34B S5_PORTR1 0x34C S5_DHAR0 SOCKET5 Destination Hardware S5_DHAR 0x34D S5_DHAR1 Address Register 0x34E S5_DHAR2 S5_DHAR2 0x34F S5_DHAR3 0x350 S5_DHAR4 S5_DHAR4 0x351 S5_DHAR5 0x352 S5_DPORTR0 SOCKET5 Destination Port Register S5_DPORTR 0x353 S5_DPORTR1 0x354 S5_DIPR0 SOCKET5 Destination IP Address S5_DIPR 0x355 S5_DIPR1 Register 0x356 S5_DIPR2 S5_DIPR2 0x357 S5_DIPR3 0x358 S5_MSSR0 SOCKET5 Maximum Segment Size S5_MSSR 0x359 S5_MSSR1 Register 0x35A S5_KPALVTR SOCKET5 Keep Alive Time Register S5_PORTOR 0x35B S5_PROTOR SOCKET5 Protocol Number Register 0x35C S5_TOSR0 Reserved S5_TOSR 0x35D S5_TOSR1 SOCKET5 TOS Register 0x35E S5_TTLR0 Reserved S5_TTLR 0x35F S5_TTLR1 SOCKET5 TTL Register Copyright 2008 WIZnet Co., Inc. All rights reserved. 39

40 Address offset Symbol Description 16Bit 8Bit 16Bit 8Bit 0x360 0x362 0x364 0x366 0x368 0x36A 0x36C 0x36E 0x370 0x372 : : 0x37E 0x360 S5_TX_WRSR0 Reserved S5_TX_WRSR 0x361 S5_TX_WRSR1 SOCKET5 TX Write Size Register 0x362 S5_TX_WRSR2 S5_TX_WRSR2 0x363 S5_TX_WRSR3 0x364 S5_TX_FSR0 Reserved S5_TX_FSR 0x365 S5_TX_FSR1 SOCKET5 TX Free Size Register 0x366 S5_TX_FSR2 S5_TX_FSR2 0x367 S5_TX_FSR3 0x368 S5_RX_RSR0 Reserved S5_RX_RSR 0x369 S5_RX_RSR1 SOCKET5 RX Receive Size Register 0x36A S5_RX_RSR2 S5_RX_RSR2 0x36B S5_RX_RSR3 0x36C S5_FRAGR0 Reserved S5_FRAGR 0x36D S5_FRAGR1 SOCKET5 IP FLAG Field Register 0x36E S5_TX_FIFOR0 SOCKET5 TX FIFO Register S5_TX_FIFOR 0x36F S5_TX_FIFOR1 0x370 S5_RX_FIFOR0 SOCKET5 RX FIFO Register S5_RX_FIFOR 0x371 S5_RX_FIFOR1 0x372 Reserved 0x373 : : 0x37E Reserved 0x37F Copyright 2008 WIZnet Co., Inc. All rights reserved. 40

41 Address offset Symbol Description 16Bit 8Bit 16Bit 8Bit 0x380 0x382 0x384 0x386 0x388 0x38A 0x38C 0x38E 0x390 0x392 0x394 0x396 0x398 0x39A 0x39C 0x39E 0x380 S6_MR0 SOCKET6 Mode Register S6_MR 0x381 S6_MR1 0x382 S6_CR0 Reserved S6_CR 0x383 S6_CR1 SOCKET6 Command Register 0x384 S6_IMR0 Reserved S6_IMR 0x385 S6_IMR1 SOCKET6 Interrupt Mask Register 0x386 S6_IR0 Reserved S6_IR 0x387 S6_IR1 SOCKET6 Interrupt Register 0x388 S6_SSR0 Reserved S6_SSR 0x389 S6_SSR1 SOCKET6 Socket Status Register 0x38A S6_PORTR0 SOCKET6 Source Port Register S6_PORTR 0x38B S6_PORTR1 0x38C S6_DHAR0 SOCKET6 Destination Hardware S6_DHAR 0x38D S6_DHAR1 Address Register 0x38E S6_DHAR2 S6_DHAR2 0x38F S6_DHAR3 0x390 S6_DHAR4 S6_DHAR4 0x391 S6_DHAR5 0x392 S6_DPORTR0 SOCKET6 Destination Port Register S6_DPORTR 0x393 S6_DPORTR1 0x394 S6_DIPR0 SOCKET6 Destination IP Address S6_DIPR 0x395 S6_DIPR1 Register 0x396 S6_DIPR2 S6_DIPR2 0x397 S6_DIPR3 0x398 S6_MSSR0 SOCKET6 Maximum Segment Size S6_MSSR 0x399 S6_MSSR1 Register 0x39A S6_KPALVTR SOCKET6 Keep Alive Time Register S6_PORTOR 0x39B S6_PROTOR SOCKET6 Protocol Number Register 0x39C S6_TOSR0 Reserved S6_TOSR 0x39D S6_TOSR1 SOCKET6 TOS Register 0x39E S6_TTLR0 Reserved S6_TTLR 0x39F S6_TTLR1 SOCKET6 TTL Register Copyright 2008 WIZnet Co., Inc. All rights reserved. 41

42 Address offset Symbol Description 16Bit 8Bit 16Bit 8Bit 0x3A0 0x3A2 0x3A4 0x3A6 0x3A8 0x3AA 0x3AC 0x3AE 0x3B0 0x3B2 : : 0x3BE 0x3A0 S6_TX_WRSR0 Reserved S6_TX_WRSR 0x3A1 S6_TX_WRSR1 SOCKET6 TX Write Size Register 0x3A2 S6_TX_WRSR2 S6_TX_WRSR2 0x3A3 S6_TX_WRSR3 0x3A4 S6_TX_FSR0 Reserved S6_TX_FSR 0x3A5 S6_TX_FSR1 SOCKET6 TX Free Size Register 0x3A6 S6_TX_FSR2 S6_TX_FSR2 0x3A7 S6_TX_FSR3 0x3A8 S6_RX_RSR0 Reserved S6_RX_RSR 0x3A9 S6_RX_RSR1 SOCKET6 RX Receive Size Register 0x3AA S6_RX_RSR2 S6_RX_RSR2 0x3AB S6_RX_RSR3 0x3AC S6_FRAGR0 Reserved S6_FRAGR 0x3AD S6_FRAGR1 SOCKET6 IP FLAG Field Register 0x3AE S6_TX_FIFOR0 SOCKET6 TX FIFO Register S6_TX_FIFOR 0x3AF S6_TX_FIFOR1 0x3B0 S6_RX_FIFOR0 SOCKET6 RX FIFO Register S6_RX_FIFOR 0x3B1 S6_RX_FIFOR1 0x3B2 Reserved 0x3B3 : : 0x3BE Reserved 0x3BF Copyright 2008 WIZnet Co., Inc. All rights reserved. 42

43 Address offset Symbol Description 16Bit 8Bit 16Bit 8Bit 0x3C0 0x3C2 0x3C4 0x3C6 0x3C8 0x3CA 0x3CC 0x3CE 0x3D0 0x3D2 0x3D4 0x3D6 0x3D8 0x3DA 0x3DC 0x3DE 0x3C0 S7_MR0 SOCKET7 Mode Register S7_MR 0x3C1 S7_MR1 0x3C2 S7_CR0 Reserved S7_CR 0x3C3 S7_CR1 SOCKET7 Command Register 0x3C4 S7_IMR0 Reserved S7_IMR 0x3C5 S7_IMR1 SOCKET7 Interrupt Mask Register 0x3C6 S7_IR0 Reserved S7_IR 0x3C7 S7_IR1 SOCKET7 Interrupt Register 0x3C8 S7_SSR0 Reserved S7_SSR 0x3C9 S7_SSR1 SOCKET7 Socket Status Register 0x3CA S7_PORTR0 SOCKET7 Source Port Register S7_PORTR 0x3CB S7_PORTR1 0x3CC S7_DHAR0 SOCKET7 Destination Hardware S7_DHAR 0x3CD S7_DHAR1 Address Register 0x3CE S7_DHAR2 S7_DHAR2 0x3CF S7_DHAR3 0x3D0 S7_DHAR4 S7_DHAR4 0x3D1 S7_DHAR5 0x3D2 S7_DPORTR0 SOCKET7 Destination Port Register S7_DPORTR 0x3D3 S7_DPORTR1 0x3D4 S7_DIPR0 SOCKET7 Destination IP Address S7_DIPR 0x3D5 S7_DIPR1 Register 0x3D6 S7_DIPR2 S7_DIPR2 0x3D7 S7_DIPR3 0x3D8 S7_MSSR0 SOCKET7 Maximum Segment Size S7_MSSR 0x3D9 S7_MSSR1 Register 0x3DA S7_KPALVTR SOCKET7 Keep Alive Time Register S7_PORTOR 0x3DB S7_PROTOR SOCKET7 Protocol Number Register 0x3DC S7_TOSR0 Reserved S7_TOSR 0x3DD S7_TOSR1 SOCKET7 TOS Register 0x3DE S7_TTLR0 Reserved S7_TTLR 0x3DF S7_TTLR1 SOCKET7 TTL Register Copyright 2008 WIZnet Co., Inc. All rights reserved. 43

44 Address offset Symbol Description 16Bit 8Bit 16Bit 8Bit 0x3E0 0x3E2 0x3E4 0x3E6 0x3E8 0x3EA 0x3EC 0x3EE 0x3F0 0x3F2 : : 0x3FE 0x3E0 S7_TX_WRSR0 Reserved S7_TX_WRSR 0x3E1 S7_TX_WRSR1 SOCKET7 TX Write Size Register 0x3E2 S7_TX_WRSR2 S7_TX_WRSR2 0x3E3 S7_TX_WRSR3 0x3E4 S7_TX_FSR0 Reserved S7_TX_FSR 0x3E5 S7_TX_FSR1 SOCKET7 TX Free Size Register 0x3E6 S7_TX_FSR2 S7_TX_FSR2 0x3E7 S7_TX_FSR3 0x3E8 S7_RX_RSR0 Reserved S7_RX_RSR 0x3E9 S7_RX_RSR1 SOCKET7 RX Receive Size Register 0x3EA S7_RX_RSR2 S7_RX_RSR2 0x3EB S7_RX_RSR3 0x3EC S7_FRAGR0 Reserved S7_FRAGR 0x3ED S7_FRAGR1 SOCKET7 IP FLAG Field Register 0x3EE S7_TX_FIFOR0 SOCKET7 TX FIFO Register S7_TX_FIFOR 0x3EF S7_TX_FIFOR1 0x3F0 S7_RX_FIFOR0 SOCKET7 RX FIFO Register S7_RX_FIFOR 0x3F1 S7_RX_FIFOR1 0x3F2 Reserved 0x3F3 : : 0x3FE Reserved 0x3FF Copyright 2008 WIZnet Co., Inc. All rights reserved. 44

45 4. Register Description [Notation] 1. Symbol(Name)[R/W,RO,WO][AO1/AO2][Reset] Symbol : Register symbol Name : Register name R/W : Read/Write RO : Read Only WO : Write Only AO1 : Physical address of W5300 reg. in T.M.S (For Direct address mode) AO2 : Address Offset of W5300 reg. in W.M.S (For Indirect address mode) Reset : Reset value 편의상 T.M.S의 Base Address(BA) 는 0x08000라가정하고, 앞으로설명될 W5300 register 의 Physical address는 0x08000을 BA로한다. 2. Pn_ : Buffer ready PIN n("brdyn") register prefix Pn_BRDYR(BRDYn configure register, 0 <= n <= 3) 3. Sn_ : SOCKETn register prefix Sn_MR ( SOCKETn Mode Register, 0 <= n <= 7) 4. Symbol of low address Reg. Bit Physical Address Symbol Address offset Reset Value X U(R) 0 0 Symbol of high address Reg. Bit Physical Address Symbol Address offset Reset Value : Reserved Bit 1 : Logical High 0 : Logical Low X : Don t Care U : 1 or 0 (R) : Read Only Bit 16 bit Register Symbol(AO1/AO2) 8bit Register Symbol (AO1/AO2) MSB(Value) 8bit Register Symbol (AO1/AO2) LSB(Value) Copyright 2008 WIZnet Co., Inc. All rights reserved. 45

46 4.1 Mode Register MR (Mode Register) [R/W] [0x08000/----][0x3800 or 0xB800] MR은전반적인 W5300 mode(host I/F, Sn_TX_FIFOR & Sn_RX_FIFOR의 MSB/LSB swap, S/W reset, Internal TX/RX memory test, Data bus의 MSB/LSB swap, address mode 등 ) 을설정한다. MR x08000 DBW MPF WDF2 WDF1 WDF0 RDH - FS ---- U(R) 0(R) MR x08001 RST - MT PB PPPoE DBS - IND MR(15:8)/MR0(7:0) Bit Symbol Description Data Bus Width 0 : 8 bit Data Bus 1 : 16 bit Data Bus 15 DBW W5300의 Reset시, 이 bit는 PIN BIT16EN 의 Logic level에따라결정되며, Reset 이후변경되지않는다. 1.1 PIN Layout 의 PIN BIT16EN 참조. 14 MPF MAC Layer Pause Frame 0 : Normal frame 1 : Pause frame 13 WDF2 12 WDF1 11 WDF0 10 RDH Router나 Switch 장비로부터 Pause frame을수신할경우 1 로설정된다. 1 로설정되었을경우, 0 으로바뀔때까지모든 Data전송은 Pause된다. Write Data Fetch Time Host-Write 동작시, W5300은 /CS 가 Low assert된시점부터 WRF X PLL_CLK 후에 Write-Data를 Fetch한다. WRF X PLL_CLK 이전에 Host-Write operation이끝날경우 ( /CS 이 High로 de-assert된경우 ) 는, /CS 가 High로 de-assert된그시점에서 Write-Data 를 Fetch한다. Read Data Hold Time 0 : No use data hold time Copyright 2008 WIZnet Co., Inc. All rights reserved. 46

47 1 : Use data hold time (2 X PLL_CLK) Host-Read 동작시, W5300은 Host-Read operation이끝난후 ( /CS 가 High로 de-assert 된후 ) 에도 2 X PLL_CLK 동안 Read-Data를 Hold한다. 이경우 Data bus 충돌이발생할수있기때문에주의해서사용한다. 9 - Reserved FIFO Swap Bit 0 : Disable swap 1 : Enable swap 8 FS Sn_TX_FIFOR/Sn_RX_FIFOR의 Most significant byte(msb) 와 Least significant byte(lsb) 를 서로 Swap한다. 기본적으로 W5300의 Byte ordering은 Big-endian이다. 만약 Target host system이 Little-endian이라 면, 이 Bit을 1 로설정하여 Sn_TX_FIFOR/Sn_RX_FIFOR의 Byte ordering 을바꾸어마치 Little-endian처럼사용할수있다. MR(7:0)/MR1(7:0) Bit Symbol Description S/W Reset 7 RST 1 이면, W5300을 Reset시킨다. 이 Bit는 Reset이후자동으로 Clear된다. 6 - Reserved Memory Test Bit 0 : Disable internal TX/RX memory test 1 : Enable internal TX/RX memory test 5 MT 4 PB 기본적으로 W5300의 Internal TX memory는 Sn_TX_FIFOR을통한 Host- Write operation만지원하고, Internal RX memory는 Sn_RX_FIFOR을통한 Host-Read operation만지원한다. 그러나, 이 Bit를 1 로설정할경우, Internal TX/RX memory는 Sn_TX_FIFOR/Sn_RX_FIFOR을통해 Host Read/Write operation을모두지원하여, Internal TX/RX memory을검증할수있다. W5300의 Internal TX/RX memory test 이후, 반드시 Reset이나해당 SOCKET을 Close해야한다. 자세한내용은 How to test internal TX/RX memory 를참조하라. Ping Block Mode 0 : Disable Ping Block 1 : Enable Ping Block Copyright 2008 WIZnet Co., Inc. All rights reserved. 47

48 이 Bit이 1 로설정될경우, W5300 ICMP logic block의 Auto-ping-replyprocess가 Disable되어상대방의 Ping-request(ICMP echo request) 에대한 Ping-reply(ICMP echo reply) 를하지않는다. cf> Ping block mode가 0 이라할지라도, User가 ICMP SOCKET (Sn_MR (P3:P0)=Sn_MR_IPRAW and Sn_PROTOR1=0x01) 을사용 (User가 ICMP Packet 을직접처리 ) 하고자할경우, Auto Ping-reply를하지않는다. Auto-ping-reply는 119Bytes까지만지원한다. 3 PPPoE PPPoE Mode 0 : Disable PPPoE mode 1 : Enable PPPoE mode Router나기타장비없이 PPPoE server에접속할경우, 이 bit를 1 로설정한다. 자세한내용은 How to use PPPoE in W5300 를참조하라. 2 DBS Data Bus Swap 앞서설명한 FS bit가 Sn_TX_FIFOR/Sn_RX_FIFOR만 MSB와 LSB를 Swap하는반면, 이비트는 Sn_TX_FIFOR/Sn_RX_FIFOR를포함한모든 Register의 MSB와 LSB를 Swap한다. 단, 이 bit는 DBW bit가 1 일때만적용된다. 1 - Reserved 0 IND Indirect Bus I/F mode 0 : Direct address mode 1 : Indirect address mode W5300 의 Host interface mode 를설정한다. 4.2 Indirect Mode Registers MR(IND) = 1 일경우 W5300은 Indirect address mode로동작하게된다. 이때 Target host system은 MR, IDM_AR, IDM_DR만을사용하여 ( 즉 MR, IDM_AR, IDM_DR만 T.M.S에 Mapping하여이들 register만 Direct로 Access하여 ), COMMON registers와 SOCKET registers를 Access하게된다. IDM_AR(Indirect Mode Address Register) [R/W] [0x08002/----][0x0000] Indirect 로 Access 할 COMMON registers 나 SOCKET registers 의 Address offset 을설정한다. Copyright 2008 WIZnet Co., Inc. All rights reserved. 48

49 IDM_AR의최하위 Bit인 IDM_AR(0) 혹은 IDM_AR1(0) 은무시된다. Ex) S4_RX_FIFOR(0x330) 를 Access할경우다음과같다. IDM_AR0 = S4_RX_FIFOR의 Address offset의 MSB (0x03) IDM_AR1 = S4_RX_FIFOR의 Address offset의 LSB (0x30) IDM_AR(0x08002/----) IDM_AR0(0x08002/----) IDM_AR1(0x08003/----) 0x03 0x30 IDM_DR(Indirect Mode Data Register) [R/W] [0x08004/-----][0x0000] IDM_AR로지정된 COMMON registers나 SOCKET registers의실제 Data 값을 Access한다. IDM_AR에지정된 Register의 MSB와 LSB값은 DM_DR0와 IDM_DR1으로각각대응된다. 8 bit data bus width를사용하는경우, 지정한 Register의 LSB값을 Access하고자한다면, IDM_DR1을사용하고, MSB값을 Access하고자한다면 IDM_DR0을사용한다. Ex1) IR(0x002) 에 0x80F0 값을 Host-Write하는동작 16 bit data bus width ( MR(DBW) = 1 ) 8 bit data bus width ( MR(DBW) = 0 ) IDM_AR = 0x0002 IDM_AR0 = 0x00 IDM_DR = 0x80F0 IDM_AR1 = 0x02 IDM_DR0 = 0x80 IDM_DR1 = 0xF0 Ex2) IR(0x0FE) 의값을 Host-Read해서변수 val 에저장하는동작 16 bit data bus width ( MR(DBW) = 1 ) 8 bit data bus width ( MR(DBW) = 0 ) IDM_AR = 0x0002 IDM_AR0 = 0x00 val = IDM_DR IDM_AR1 = 0x02 val = IDM_DR0 val = (val << 8) + IDM_DR1 IDM_AR(0x08002/----) IDM_AR0(0x08002/----) 0x00 IDM_AR1(0x08003/----) 0x02 IDM_DR(0x08004/----) IDM_DR0(0x08004/----) IR 의 MSB(IR0) IDM_DR1(0x08005/----) IR 의 LSB(IR1) Copyright 2008 WIZnet Co., Inc. All rights reserved. 49

50 4.3 COMMON Registers IR (Interrupt Register) [R/W] [0x08002/0x002] [0x0000] IR은 Host에게 W5300에서발생한 Interrupt 종류를알려주기위한 Register이다. Interrupt 발생시, IR의해당 Interrupt bit가 1 로설정되고 IMR의해당 Interrupt mask bit이 1 일경우, /INT signal은 Low로 Assert된다. /INT signal은 IR의모든 Bit가 0 이될때까지 Low를유지하며, IR의모든 Bit가 0 이되 었다면 High로 De-assert된다. 1 로설정된 IR0의 Bit를 Clear하기위해서는그 Bit를 1 로 Host-Write 해야한다. 1 로설정된 IR1의 Bit는그 Bit에해당하는 Sn_IR를 Clear할경우자 동으로 Clear된다. IR x08002 IPCF DPUR PPPT FMTU x IR x08003 S7_INT S6_INT S5_INT S4_INT S3_INT S2_INT S1_INT S0_INT 0x IR(15:8)/IR0(7:0) Bit Symbol Description IP Conflict 15 IPCF 14 DPUR 13 PPPT 12 FMTU W5300의 IP address가충돌할경우 (Source IP address와동일한 IP address 를갖는 ARP-request packet을수신할경우 ) 1 로설정된다. 1 로설정된경우, Network상에동일 IP address를사용하는 Network 장비가있음을의미하고, 이는통신장애의원인이되므로이를해결해야한다. Destination Port unreachable W5300은 ICMP(Destination port unreachable) packet을수신할경우 1 로설정된다. UIPR과 UPORTR를참조하라. PPPoE Terminate PPPoE mode에서, PPPoE server와 Connection이 Close되었을때 1 로설정된다. Fragment MTU ICMP(Fragment MTU) packet을수신할경우 1 로설정된다. Copyright 2008 WIZnet Co., Inc. All rights reserved. 50

51 FMTUR 참조를참조하라 Reserved 10 - Reserved 9 - Reserved 8 - Reserved IR(7:0)/IR1(7:0) Bit Symbol Description 7 S7_INT Occurrence of SOCKET7 Interrupt SOCKET7에서 Interrupt가발생할경우 1 로설정된다. 이때발생한 Interrupt 정보는 S7_IR1에반영되며, S7_IR1이 Host에의해 0x00으로 Clear될경우이 Bit는자동으로 Clear된다. 6 S6_INT Occurrence of SOCKET6 Interrupt SOCKET6에서 Interrupt가발생할경우 1 로설정된다. 이때발생한 Interrupt 정보는 S6_IR1에반영되며, S6_IR1이 Host에의해 0x00으로 Clear될경우이 Bit는자동으로 Clear된다. Occurrence of SOCKET5 Interrupt 5 S5_INT SOCKET5에서 Interrupt가발생할경우 1 로설정된다. 이때발생한 Interrupt 정보는 S5_IR1에반영되며, S5_IR1이 Host에의해 0x00으로 Clear될경우이 Bit는자동으로 Clear된다. Occurrence of SOCKET4 Interrupt 4 S4_INT SOCKET4에서 Interrupt가발생할경우 1 로설정된다. 이때발생한 Interrupt 정보는 S4_IR1에반영되며, S4_IR1이 Host에의해 0x00으로 Clear될경우이 Bit는자동으로 Clear된다. Occurrence of SOCKET3 Interrupt 3 S3_INT 2 S2_INT SOCKET3에서 Interrupt가발생할경우 1 로설정된다. 이때발생한 Interrupt 정보는 S3_IR1에반영되며, S3_IR1이 Host에의해 0x00으로 Clear될경우이 Bit는자동으로 Clear된다. Occurrence of SOCKET2 Interrupt SOCKET2에서 Interrupt가발생할경우 1 로설정된다. 이때발생한 Copyright 2008 WIZnet Co., Inc. All rights reserved. 51

52 Interrupt 정보는 S2_IR1에반영되며, S2_IR1이 Host에의해 0x00으로 Clear될경우이 Bit는자동으로 Clear된다. 1 S1_INT Occurrence of SOCKET1 Interrupt SOCKET1에서 Interrupt가발생할경우 1 로설정된다. 이때발생한 Interrupt 정보는 S1_IR1에반영되며, S1_IR1이 Host에의해 0x00으로 Clear될경우이 Bit는자동으로 Clear된다. 0 S0_INT Occurrence of SOCKET0 Interrupt SOCKET0에서 Interrupt가발생할경우 1 로설정된다. 이때발생한 Interrupt 정보는 S0_IR1에반영되며, S0_IR1이 Host에의해 0x00으로 Clear될경우이 Bit는자동으로 Clear된다. IMR (Interrupt Mask Register) [R/W] [0x08004/0x004] [0x0000] Host로알려줄 W5300의 Interrupt를설정한다. IMR의 Interrupt mask bit들은 IR의 Interrupt bit들과각각대응되며, IR의임의의 bit가 1 로설정되고 IMR의대응 Bit가 1 로설정되었 을경우, Host에게 Interrupt가 Issue( /INT signal은 High에서 Low로 Assert) 된다. 만약 IMR의대응 bit가 0 으로설정되었다면, IR의그 bit가 1 로설정되었다할지라도, Host에게 Interrupt는 Issue( /INT pin이 High를계속유지 ) 되지않는다. IMR x08004 IPCF DPUR PPPT FMTU x IMR x08005 S7_INT S6_INT S5_INT S4_INT S3_INT S2_INT S1_INT S0_INT 0x IMR(15:8)/IMR0(7:0) Bit Symbol Description 15 IPCF IR(IPCF) Interrupt Mask 14 DPUR IR(DPUR) Interrupt Mask 13 PPPT IR(PPPT) Interrupt Mask 12 FMTU IR(FMTU) Interrupt Mask 11 - Reserved 10 - Reserved Copyright 2008 WIZnet Co., Inc. All rights reserved. 52

53 9 - Reserved 8 - Reserved IMR(7:0)/IMR1(7:0) Bit Symbol Description 7 S7_INT IR(S7_INT) Interrupt Mask 6 S6_INT IR(S6_INT) Interrupt Mask 5 S5_INT IR(S5_INT) Interrupt Mask 4 S4_INT IR(S4_INT) Interrupt Mask 3 S3_INT IR(S3_INT) Interrupt Mask 2 S2_INT IR(S2_INT) Interrupt Mask 1 S1_INT IR(S1_INT) Interrupt Mask 0 S0_INT IR(S0_INT) Interrupt Mask SHAR (Source Hardware Address Register) [R/W] [0x08008/0x008] [ ] Source hardware address(mac address) 를설정한다. Ex) SHAR = DC SHAR(0x08008/0x008) SHAR0(0x08008/0x008) 0x00 SHAR1(0x08009/0x009) 0x08 SHAR2(0x0800A/0x00A) SHAR2(0x0800A/0x00A) 0xDC SHAR3(0x0800B/0x00B) 0x01 SHAR4(0x0800C/0x00C) SHAR4(0x0800C/0x00C) 0x02 SHAR5(0x0800D/0x00D) 0x03 GAR (Gateway IP Address Register) [R/W] [0x08010/0x010] [ ] Gateway IP address 를설정한다. Ex) GAR = GAR(0x08010/0x010) GAR2(0x08012/0x012) GAR0(0x08010/0x010) GAR1(0x08011/0x011) GAR2(0x08012/0x012) GAR3(0x08013/0x013) 192(0xC0) 168(0xA8) 0(0x00) 1(0x01) Copyright 2008 WIZnet Co., Inc. All rights reserved. 53

54 SUBR (Subnet Mask Register) [R/W] [0x08014/0x014] [ ] Subnet mask address를설정한다. Ex) SUBR = SUBR(0x08014/0x014) SUBR2(0x08016/0x016) SUBR0(0x08014/0x014) SUBR1(0x08015/0x015) SUBR2(0x08016/0x016) SUBR3(0x08017/0x017) 255 (0xFF) 255 (0xFF) 255 (0xFF) 0 (0x00) SIPR (Source IP Address Register) [R/W] [0x08018/0x018] [ ] Source IP address를설정하거나, W5300 내의 PPPoE-process를통해설정된 Source IP address를알려준다. Ex) SIPR = SIPR(0x08018/0x018) SIPR2(0x0801A/0x01A) SIPR0(0x08018/0x018) SIPR1(0x08019/0x019) SIPR2(0x0801A/0x01A) SIPR3(0x0801B/0x01B) 192(0xC0) 168(0xA8) 0(0x00) 3(0x03) RTR (Retransmission Timeout-period Register) [R/W] [0x0801C/0x01C] [0x07D0] Retransmission timeout-period(data 재전송시간 ) 를설정한다. RTR 의기본의단위는 100us 이 고, Reset 시 2000(0x07D0) 으로초기화되어 200ms 의 Timeout-period 를갖는다. Timeout-period = RTR X 0.1ms RTR = (Timeout-period / 1ms) X 10 Ex) Timeout-period 400ms 설정, RTR = (400ms / 1ms) X 10 = 4000(0x0FA0) RTR(0x0801C/0x01C) RTR0(0x0801C/0x01C) 0x0F RTR1(0x0801D/0x01D) 0xA0 RCR (Retransmission Retry-Count Register) [R/W] [0x0801E/0x001E] [0x--08] Retransmission count(data 재전송회수 ) 를설정한다. RCR + 1 개의 Retransmission이발생할경우, Timeout interrupt(sn_ir의 TO bit가 1 로설정 ) 된다. TCP 통신인경우, Sn_IR(TIMEOUT)= 1 과동시에 Sn_SSR의값이 SOCK_CLOSED 로변경된다. TCP 통신이아닌경우, Sn_IR(TIMEOUT) = 1 만된다. Copyright 2008 WIZnet Co., Inc. All rights reserved. 54

55 Ex) RCR = 0x0007 RCR(0x0801E/0x01E) RCR0(0x0801E/0x01C) RCR1(0x0801F/0x01F) Reserved 0x07 W5300에서의 Timeout은 RTR과 RCR로 Data 재전송의시간과횟수를설정할수있다. W5300의 Timeout에대해좀더살펴보면, ARP retransmission timeout과 TCP retransmission timeout 2가지가있다. 먼저 ARP( RFC 826 참조, retransmission timeout 살펴보면, W5300은 IP, UDP, TCP를이용한통신시상대방의 IP address로 MAC address를알기위해자동으로 ARP-request를전송한다. 이때상대방의 ARP-response 수신을기다리는데, RTR의설정대기시간동안 ARP-response의수신이없으면, Timeout이발생하고 ARP-request를 Retransmission한다. 이와같은작업은 RCR + 1 만큼반복하게된다. RCR + 1 개의 ARP-request retransmission이일어나고, 그에대한 ARP-response가없다면, Final timeout이발생하게되고, Sn_IR(TIMEOUT) = 1 된다. ARP-request의 Final timeout(arp TO ) 값은다음과같다. ARP TO = ( RTR X 0.1ms ) X ( RCR + 1 ) TCP packet retransmission timeout을살펴보면, W5300은 TCP packet (SYN, FIN, RST, DATA packet) 을전송하고그에대한 Acknowledgment(ACK) 을 RTR과 RCR에의해설정된대기시간동안기다리게된다. 이때상대방으로부터 ACK가없으면 Timeout이발생하고이전에보냈던 TCP packet을 Retransmission한다. 이와같은작업은 RCR + 1 만큼반복하게된다. RCR + 1 개의 TCP packet retransmission이일어나고, 그에대한 ACK 수신이없다면, Final timeout이발생하게되고, Sn_IR(TIMEOUT) = 1 과동시에 Sn_SSR이 SOCK_CLOSED 로변경된다. TCP packet retransmission의 Final timeout(tcp TO ) 값은다음과같다. M TCP TO = ( Σ(RTR X 2 N ) + ((RCR-M) X RTR MAX ) ) X 0.1ms N=0 N : Retransmission count, 0 <= N <= M M : RTR X 2 (M+1) > and 0 <= M <= RCR를만족하는최소값 RTR MAX : RTR X 2 M Ex) RTR = 2000(0x07D0), RCR = 8(0x0008) 일때, ARP TO = 2000 X 0.1ms X 9 = 1800ms = 1.8s TCP TO = (0x07D0 + 0x0FA0 + 0x1F40 + 0x3E80 + 0x7D00 + 0xFA00 + 0xFA00 + 0xFA00 + 0xFA00) X 0.1ms = ( ((8-4) X 64000)) X 0.1ms = X 0.1ms = 31.8s Copyright 2008 WIZnet Co., Inc. All rights reserved. 55

56 TMSR(TX Memory Size Register) [R/W] [0x08020/0x020] [ ] 각 SOCKET의 Internal TX memory size를 1Kbytes 단위로설정한다. 각 SOCKET의 TX memory size는 0Kbyte에서 64Kbytes내에서설정이가능하며, Reset시 8Kbytes로설정된다. 각 SOCKET의 TX memory size의총합 (TMS SUM ) 은반드시 8의배수가되도록설정하며, 또한 TMS SUM 과각 SOCKET의 RX memory size의총합 (RMS SUM ) 의합이 128Kbytes가되도록설정한다. TMS01R(TX Memory Size of SOCKET0/1 Register) [R/W] [0x08020/0x020] [0x0808] SOCKET0과 SOCKET1의 Internal TX memory size를결정한다. Ex1) SOCKET0 : 4KB, SOCKET1 : 16KB TMS01R(0x08020/0x020) TMSR0(0x08020/0x020) TMSR1(0x08021/0x021) 4 (0x04) 16 (0x10) TMS23R(TX Memory Size of SOCKET2/3 Register) [R/W] [0x08022/0x022] [0x0808] SOCKET2과 SOCKET3의 Internal TX memory size를결정한다. Ex2) SOCKET2 : 1KB, SOCKET3 : 20KB TMS23R(0x08020/0x020) TMSR2(0x08022/0x022) TMSR3(0x08023/0x023) 1 (0x01) 20 (0x14) TMS45R(TX Memory Size of SOCKET4/5 Register) [R/W] [0x08024/0x024] [0x0808] SOCKET4과 SOCKET5의 Internal TX memory size를결정한다. Ex3) SOCKET4 : 0KB, SOCKET5 : 7KB TMS45R(0x08024/0x024) TMSR4(0x08024/0x024) TMSR5(0x08025/0x025) 0 (0x00) 7 (0x07) TMS67R(TX Memory Size of SOCKET6/7 Register) [R/W] [0x08024/0x024] [0x0808] SOCKET6과 SOCKET7의 Internal TX memory size를결정한다. Ex4) SOCKET6 : 12KB, SOCKET7 : 12KB TMS67R(0x08026/0x026) TMSR6(0x08026/0x026) TMSR7(0x08027/0x027) 12 (0x0C) 12 (0x0C) 상기 Ex1)~Ex4) 에서, TMS SUM (TMSR0 + TMSR1 + TMSR2 + TMSR3 + TMSR4 + TMSR5 + TMSR6 + TMSR7) 은 72 로, 8 의배수로설정되었다 (72 % 8 = 0). Copyright 2008 WIZnet Co., Inc. All rights reserved. 56

57 RMSR(RX Memory Size Register) [R/W] [0x08028/0x028] [ ] 각 SOCKET의 Internal RX memory size를 1Kbytes 단위로설정한다. 각 SOCKET의 RX memory size는 0Kbyte에서 64Kbytes내에서설정이가능하며, Reset시 8Kbytes로설정된다. 각 SOCKET의 RMS SUM 은 TMS SUM 과각 RMS SUM 의합이 128KB가되도록설정하여야한다. RMS01R(RX Memory Size of SOCKET0/1 Register) [R/W] [0x08028/0x028] [0x0808] SOCKET0과 SOCKET1의 Internal RX memory size를결정한다. Ex5) SOCKET0 : 17KB, SOCKET1 : 3KB RMS01R(0x08028/0x028) RMSR0(0x08028/0x028) RMSR1(0x08029/0x029) 17 (0x11) 3 (0x03) RMS23R(RX Memory Size of SOCKET2/3 Register) [R/W] [0x0802A/0x02A] [0x0808] SOCKET2과 SOCKET3의 Internal RX memory size를결정한다. Ex6) SOCKET2 : 5KB, SOCKET3 : 16KB RMS23R(0x0802A/0x02A) RMSR2(0x0802A/0x02A) RMSR3(0x0802B/0x02B) 5 (0x05) 16 (0x10) RMS45R(RX Memory Size of SOCKET4/5 Register) [R/W] [0x0802C/0x02C] [0x0808] SOCKET4과 SOCKET5의 Internal RX memory size를결정한다. Ex7) SOCKET4 : 3KB, SOCKET5 : 4KB RMS45R(0x0802C/0x02C) RMSR4(0x0802C/0x02C) RMSR5(0x0802D/0x02D) 3 (0x03) 4 (0x04) RMS67R(TX Memory Size of SOCKET6/7 Register) [R/W] [0x0802E/0x02F] [0x0808] SOCKET6과 SOCKET7의 Internal RX memory size를결정한다. Ex8) SOCKET6 : 4KB, SOCKET7 : 4KB RMS67R(0x0802E/0x02E) RMSR6(0x0802E/0x02E) RMSR7(0x0802F/0x02F) 4 (0x04) 4 (0x04) 상기 Ex1)~Ex8) 에서, RMS SUM (RMSR0 + RMSR1 + RMSR2 + RMSR3 + RMSR4 + RMSR5 + RMSR6 + RMSR7) 은 56 로설정되었다. 또한 TMS SUM 와 RMS SUM 의합은 128 이다. Copyright 2008 WIZnet Co., Inc. All rights reserved. 57

58 MTYPER(Memory Type Register) [R/W] [0x08030/0x030] [0x00FF] W5300의 128Kbytes data memory(internal TX/RX memory) 는 8Kbytes의 Memory block 16개 로구성된다. MTYPER은 8KB의 Memory block들이 TX memory로사용될지, RX memory로사 용될지를설정한다. 8KB memory block의 Type은 MTYPER의각 Bit로대응되며그값이 1 인경우 TX memory, 0 인경우 RX memory로사용된다. MTYPER는반드시하위 Bit부터 TX memory type으로설정하며, TX memory로설정하지않은나머지 Bit는 0 으로설정한다. MTYPER x08030 MB15 MB14 MB13 MB12 MB11 MB10 MB9 MB8 0x MTYPER x08031 MB7 MB6 MB5 MB4 MB3 MB2 MB1 MB0 0x MTYPER(15:8)/MTYPER0(7:0) Bit Symbol Description 15 MB15 16 th Memory Block Type 14 MB14 15 th Memory Block Type 13 MB13 14 th Memory Block Type 12 MB12 13 th Memory Block Type 11 MB11 12 th Memory Block Type 10 MB10 11 th Memory Block Type 9 MB9 10 th Memory Block Type 8 MB8 9 th Memory Block Type MTYPER(7:0)/MTYPER1(7:0) Bit Symbol Description 7 MB7 8 th Memory Block Type 6 MB6 7 th Memory Block Type 5 MB5 6 th Memory Block Type 4 MB4 5 th Memory Block Type 3 MB3 4 th Memory Block Type 2 MB2 3 rd Memory Block Type 1 MB1 2 nd Memory Block Type 0 MB0 1 st Memory Block Type Ex1) TMS SUM = 72, RMS SUM = 56 Copyright 2008 WIZnet Co., Inc. All rights reserved. 58

59 72 / 8 = 9 이므로 MB0부터 MB8까지 TX Memory로설정한다. MTYPER(0x08030/0x030) MTYPER0(0x08030/0x030) MTYPER1(0x08031/0x031) 0x01 0xFF Ex2) TMS SUM = 128, RMS SUM = 0 MTYPER(0x08030/0x030) MTYPER0(0x08030/0x030) MTYPER1(0x08031/0x031) 0xFF 0xFF Ex3) TMS SUM = 0, RMS SUM = 128 MTYPER(0x08030/0x030) MTYPER0(0x08030/0x030) MTYPER1(0x08031/0x031) 0x00 0x00 PATR (PPPoE Authentication Type Register) [R] [0x08032/0x032] [0x0000] PPPoE server와의통신에서협의된 Authentication method을알려준다. W5300 2가지의 Authentication method를지원한다. Value Authentication method 0xC023 PAP 0xC223 CHAP Ex) PATR = CHAP PATR(0x08032/0x032) PATR0(0x08032/0x032) 0xC2 PATR1(0x08033/0x033) 0x23 PTIMER(PPP Link Control Protocol Request Timer Register)[R/W][0x08036/0x036][0x--28] Link control protocol(lcp) echo request 의전송 Timer 를설정한다. Value 1 은약 25ms 에해당한다. Ex) PTIMER = 200 (200 * 25ms = 5000ms = 5s) PTIMER(0x08036/0x037) PTIMER0(0x08036/0x036) Reserved PTIMER1(0x08037/0x037) 200 (0xC8) Copyright 2008 WIZnet Co., Inc. All rights reserved. 59

60 PMAGICR(PPP LCP Magic number Register)[R/W][0x08038/0x038][0x--00] PPPoE server와 LCP negotiation 동안사용하게될 4bytes Magic number 로사용될 Byte 값을설정한다. How to use PPPoE in W5300 문서를참조하라. Ex) PMACICR = 0x01 PMAGICR(0x08036/0x037) PMAGICR0(0x08038/0x038) PMAGICR1(0x08039/0x039) Reserved 0x01 Magic number = 0x PSIDR(PPPoE Session ID Register)[R][0x0803C/0x03C][0x0000] W5300 내의 PPPoE-process를통해획득한 PPPoE server와의통신에서사용하게될 PPP session ID를알려준다. Ex) PSIDR = 0x0017 PSIDR(0x0803C/0x03C) PSIDR0(0x0803C/0x03C) PSIDR1(0x0803D/0x03D) 0x00 0x17 PDHAR(PPPoE Destination Hardware Address Register)[R][0x08040/0x040] [ ] W5300 내의 PPPoE-process 를통해획득한 PPPoE server 의 Hardware address 를알려준다. Ex) PDHAR = PDHAR(0x08040/0x040) PDHAR0(0x08040/0x040) 0x00 PDHAR1(0x08041/0x041) 0x01 PDHAR2(0x08042/0x042) PDHAR2(0x08042/0x042) 0x02 PDHAR3(0x08043/0x043) 0x03 PDHAR4(0x08044/0x044) PDHAR4(0x08044/0x044) 0x04 PDHAR5(0x08045/0x045) 0x05 Copyright 2008 WIZnet Co., Inc. All rights reserved. 60

61 UIPR (Unreachable IP Address Register) [R] [0x08048/0x048] [ ] UPORTR (Unreachable Port Register) [R] [0x0804C/0x04C] [0x0000] 열려있지않는 Destination port number로 UDP data 전송을시도할때, W5300은 ICMP(Destination port unreachable) packet를수신할수있다. 이경우 IR(DPUR) = 1 이되고, 수신된 ICMP packet의 Destinaton IP address와 Unreachable port number는각각 UIPR와 UPORTR을통해알수있다. Ex1) UIPR = UIPR(0x08048/0x048) UIPR2(0x0804A/0x04A) UIPR0(0x08048/0x048) UIPR1(0x08049/0x049) UIPR2(0x0804A/0x04A) UIPR3(0x0804B/0x04B) 192 (0xC0) 168 (0xA8) 0 (0x00) 11 (0x0B) Ex2) UPORTR = 5000(0x1388) UPORTR(0x0804C/0x04C) UPORTR0(0x0804C/0x04C) UPORTR1(0x0804D/0x04D) 0x13 0x18 FMTUR (Fragment MTU Register) [R] [0x0804E/0x04E] [0x0000] MTU가서로다른상대방과통신을시도할경우, W5300은 ICMP(Fragment MTU) packet을수신할수있다. 이경우 IR(FMTU)= 1 이되며, 수신된 ICMP packet의 Destination IP address와 Fragment MTU값은각각 UIPR과 FMTUR을통해알수있다. Fragment MTU가발생한상대방과통신을계속시도할경우, 그 FMTUR 값을해당통신 SOCKET의 Sn_MSSR에설정한후다시통신을시도해야한다. Ex) FMTUR = 512(0x200) FMTUR(0x0804E/0x04E) FMTUR0(0x0804E/0x04E) 0x02 FMTUR1(0x0804F/0x04F) 0x00 Pn_BRDYR (PIN "BRDYn" Configure Register) [R/W] [0x n/0x060+4n] [0x--00] SOCKET의 TX/RX memory 상태를 Monitoring하는 PIN "BRDYn" 을설정한다. Pn_BRDYR의설정에따라, SOCKET의 TX memory의 Free buffer size가 Pn_BDPTHR에설정된 Buffer depth보다같거나클경우, 혹은 RX memory의 Received buffer size가 Pn_BDPTHR보다같거나클경우에 PIN "BRDYn" 은 signal된다. Copyright 2008 WIZnet Co., Inc. All rights reserved. 61

62 Pn_BRDYR x n x n Pn_BRDYR x08061 PEN PMT PPL - - SN2 SN1 SN0 0x Pn_BRDYR(7:0)/Pn_BRDYR1(7:0) Bit Symbol Description 7 PEN PIN BRDYn Enable 0 : Disable BRDYn 1 : Enable BRDYn PIN BRDYn 을사용하고자할경우 1 로설정한다. 6 PMT PIN Memory Type 0 : RX memory 1 : TX memory Monitoring 할 SOCKET 의 Memory 를설정한다. 5 PPL PIN Polarity 0 : Low sensitive 1 : High sensitive TX/RX memory의 Free/Received buffer size가 Pn_DPTHR보다같거나클경우, Host에게 Signal 될 PIN BRDYn 의 Logic level을설정한다. 4 - Reserved 3 - Reserved 2 SN2 SOCKET Number PIN BRDYn 으로 Monitoring할 SOCKET Number를설정한다. 1 SN1 0 SN0 SN2 SN1 SN0 SN2 SN1 SN Copyright 2008 WIZnet Co., Inc. All rights reserved. 62

63 P0_BRDYR (PIN "BRDY0" Configure Register) [R/W] [0x08060/0x060] [0x--00] PIN "BRDY0" 을설정한다. P1_BRDYR (PIN "BRDY1" Configure Register) [R/W] [0x08064/0x064] [0x--00] PIN "BRDY1" 을설정한다. P2_BRDYR (PIN "BRDY2" Configure Register) [R/W] [0x08068/0x068] [0x--00] PIN "BRDY2" 을설정한다. P3_BRDYR (PIN "BRDY3" Configure Register) [R/W] [0x0806C/0x06C] [0x--00] PIN "BRDY3" 을설정한다. Pn_BDPTHR (PIN "BRDYn" Buffer Depth Register) [R/W] [0x08062/0x062] [0xUUUU] PIN "BRDYn" 의 Buffer depth를설정한다. TX memory를 Monitoring할경우, Sn_TX_FSR이 Pn_DPTHR보다같거나클경우 PIN "BRDYn" 은 signal된다. RX memory를 Monitoring할경우, Sn_RX_RSR이 Pn_DPTHR보다같거나클경우에 PIN "BRDYn" 은 signal된다. Pn_BDPTHR은 TMSR이나 RMSR에의해설정된 SOCKET의 TX/RX memory 할당크기를초과하여설정할수없다. P0_BDPTHR (PIN "BRDY0" Buffer Depth Register) [R/W] [0x08062/0x062] [0xUUUU] PIN "BRDY0" 의 Buffer depth 를설정한다. P1_BDPTHR (PIN "BRDY1" Buffer Depth Register) [R/W] [0x08066/0x066] [0xUUUU] PIN "BRDY1" 의 Buffer depth 를설정한다. P2_BDPTHR (PIN "BRDY2" Buffer Depth Register) [R/W] [0x0806A/0x06A] [0xUUUU] PIN "BRDY2" 의 Buffer depth 를설정한다. P3_BDPTHR (PIN "BRDY3" Buffer Depth Register) [R/W] [0x0806E/0x06E] [0xUUUU] PIN "BRDY3" 의 Buffer depth 를설정한다. Ex) PIN "BRDY3" 로 SOCKET5의 TX memory Free size가 2048 이상인지를 High sensitive로 Monitoring 할경우, P3_BRDYR = 0x00E5 P3_BRDYR(0x0806C/0x06C) P3_BRDYR0(0x0806C/0x06C) Reserved P3_BRDYR1(0x0806D/0x06D) 0xE5 Copyright 2008 WIZnet Co., Inc. All rights reserved. 63

64 P3_BDPTHR = 2048(0x0800) P3_BDPTHR(0x0806E/0x06E) P3_BDPTHR0(0x0806E/0x06E) P3_BDPTHR1(0x0806F/0x06F) 0x08 0x00 다음은 SOCKETn의 RX memory를 Monitoring할때의 PIN BRDYRn 의 Signal 변화를보여준다. a. Sn_RX_RSR > Sn_BDPTHR 감지 b. 1 NIC_CLK 후, PIN BRDYn High Assert c. Host의 RX memory Read에의해 Sn_RX_RSR가감소, Sn_RX_RSR < Sn_BDPTHR 감지 d. 1 NIC_CLK 후, PIN BRDYn Low De-assert Assert Time : BRDYRn 의 Active Time. 최소 80ns 이상 Sn_RX_RSR > Sn_BDPTHR 인동안유지. Fig 4. BRDYn Timing IDR (Identification Register) [R] [0x080FE/0x0FF] [0x5300] W5300 의 ID 값을알려준다. IDR(0x080FE/0x0FE) IDR0(0x080FE/0x0FE) 0x53 IDR1(0x080FF/0x0FF) 0x00 Copyright 2008 WIZnet Co., Inc. All rights reserved. 64

65 4.4 SOCKET Registers Sn_MR (SOCKETn Mode Register) [R/W] [0x x40n/0x200+0x40n] [0x0000] SOCKETn의 Protocol type이나 Option을설정한다. Sn_MR x x40n ALIGN 0x x40n Sn_MR x x40n MULTI - ND/MC - P3 P2 P1 P0 0x x40n Sn_MR(15:8)/Sn_MR0(7:0) Bit Symbol Description 15 - Reserved 14 - Reserved 13 - Reserved 12 - Reserved 11 - Reserved 10 - Reserved 9 - Reserved Alignment 0 : No use alignment 1 : Use alignment 8 ALIGN 이 Bit는 TCP(P3~P0 : 0001 ) 일때만유효하다. TCP 통신에있어서, 모든수신 Data의크기가짝수 (Even) 일때 1 로설정하면, 매수신 Data마다붙는 PACKET-INFO(Data size) 를제거하여, Data 수신성능을향상시킬수있다 TCP SERVER 참조. Sn_MR(7:0)/Sn_MR1(7:0) Bit Symbol Description 7 MULTI Multicasting 0 : Disable multicasting 1 : Enable multicastting Copyright 2008 WIZnet Co., Inc. All rights reserved. 65

66 6 MF 5 ND/MC 이 Bit는 UDP(P3~03 : 0010 ) 일경우에만유효하다. Multicasting을위해, Sn_CR의 OPEN command 이전에 Multicast-group의 IP address와 Port number를 Sn_DIPR과 Sn_DPORTR에각각설정한다. MAC Filter 0 : Disable MAC filter 1 : Enable MAC filter 이 Bit는 MACRAW(P3~P0 : 0100 ) 일경우에만유효하다. 1 로설정될경우, W5300은 Broadcasting packet이나자신에게전송되는 Packet만을수신하게된다. 0 으로설정될경우, W5300은 Ethernet 상의모든 Packet을수신하게된다. Hybrid TCP/IP stack을구현하고자하는경우, Host의수신 Overhead를감소시키기위해이 Bit를 1 로설정할것을권장한다. Use No Delayed ACK 0 : Disable no delayed ACK option 1 : Enable no delayed ACK option 이 Bit는 TCP(P3~P0 : 0001 ) 일때만유효하다. 1 로설정된경우, ACK packet은상대방으로부터 DATA packet을수신할때마다즉시 ACK packet을전송한다. 이 Bit는 TCP의성능향상을위해 1 로설정하는것을권장한다. 0 으로설정된경우, ACK packet은상대방의 DATA packet 수신에상관없이 RTR에설정된시간이후전송된다. Multicast 0 : using IGMP version 2 1 : using IGMP version 1 이 Bit는 MULTI= 1 이고, UDP(P3~P0 : 0010 ) 일때만유효하다. Multicast-group에 Join/Leave/Report와같은 IGMP message를전송할 IGMP version을설정한다. 4 - Reserved 3 P3 Protocol 각 SOCKET별로사용할통신 Protocol(TCP, UDP, IP RAW, MAC RAW) 을설정하거나, PPPoE server와의연동에사용할 PPPoE SOCKET을설정한다. Copyright 2008 WIZnet Co., Inc. All rights reserved. 66

67 Symbol P3 P2 P1 P0 Meaning 2 P2 Sn_MR_CLOSE Closed Sn_MR_TCP TCP Sn_MR_UDP UDP Sn_MR_IPRAW IP RAW 1 P1 S0_MR_MACRAW MAC RAW S0_MR_PPPoE P0 S0_MR_MACRAW와 S0_MR_PPPoE는오직 SOCKET0에서만유효하다. S0_MR_PPPoE는 PPPoE server connection/termination을위해일시적으로사용되는것으로연결후다른 Protocol로활용될수있다. Sn_CR (SOCKETn Command Register) [R/W] [0x x40n/0x202+0x40n] [0x--00] SOCKETn에대한 Open, Close, Connect, Listen, Send, Recv와같은 Command를설정한다. W5300이그 Command를인지하게되면 Sn_CR은자동으로 Clear된다. Sn_CR이 0x00으로 Clear되었다할지라도, 해당 Command는수행중일수있으며, Command의완료는 Sn_IR 이나 Sn_SSR 등을통해 Check할수있다. Sn_CR(0x x40n/0x202+0x40n) Sn_CR0(0x x40n/0x202+0x40n) Reserved Sn_CR1(0x x40n/0x203+0x40n) Command Sn_CR(7:0)/Sn_CR1(7:0) Value Command Description 0x01 OPEN SOCKETn을초기화하고, Sn_MR(P3:P0) 에서설정한 Protocol에따라 Open한다. 다음은 Sn_MR(P3:P0) 에따른 Sn_SSR 값의변화이다. Sn_MR(P3:P0) Sn_SSR Sn_MR_CLOSE - Sn_MR_TCP SOCK_INIT Sn_MR_UDP SOCK_UDP Sn_MR_IPRAW SOCK_IPRAW S0_MR_MACRAW SOCK_MACRAW S0_MR_PPPoE SOCK_PPPoE Copyright 2008 WIZnet Co., Inc. All rights reserved. 67

68 0x02 LISTEN TCP mode(sn_mr(p3:p0)=sn_mr_tcp) 일때만유효하다. SOCKETn을 TCP SERVER 로동작시킨다. 이것은임의의 TCP CLIENT 의 Connect-request(SYN packet) 을기다리기위해 Sn_SSR을 SOCK_INIT 에서 SOCK_LISTEN으로변경시킨다. Sn_SSR = SOCK_LISTEN이고 TCP CLIENT 의 Connect-request를성공적으로처리했을경우, Sn_IR(0)= 1 로되고 Sn_SSR은 SOCK_ ESTABLISHED 로변경된다. Connect-request 처리를실패했을경우 (SYN/ACK 전송실패 ), TCP TO 가발생하고 (Sn_IR(3)= 1 ), Sn_SSR은 SOCK_CLOSED로변경된다. cf> TCP CLIENT 의 TCP connect-request port number가존재하지않을경우, W5300은 RST packet을전송하며, Sn_SSR은변경되지않는다. TCP mode일때만유효하다. SOCKETn을 TCP CLIENT 로동작시킨다. 이것은 Sn_DIPR와 Sn_DPORTR로설정된 TCP SERVER 에게 Connect- request(syn packet) 를전송한다. 0x04 CONNECT Connect-request가성공했을경우 (SYN/ACK packet을수신했을경우 ), Sn_IR(0)= 1 로되고 Sn_SSR은 SOCK_ESTABLISHED로변경된다. Connect-request 가실패했을경우는 3 가지가있다. - ARP-process 를통해 Destination hardware address 를얻지못하여 ARP TO 가발생 (Sn_IR(3)= 1 ) 한경우 - SYN/ACK packet 를수신못하고 TCP TO 가발생 (Sn_IR(3)= 1 ) 한경우 - SYN/ACK packet 대신 RST packet 을수신했을경우. 이런경우 Sn_SSR 은 SOCK_CLOSED 로변경된다. TCP mode 일때만유효하다. TCP SERVER 와 TCP CLIENT 에상관없이, 접속중인상대방에게 Disconnect-request(FIN packet) 를전송하거나 (Active close), 상대방으로 0x08 DISCON 부터 Disconnect-request(FIN packet) 을수신했을때 (Passive close), FIN packet 을전송한다 (Disconnect-process). Disconnect-request 가성공했다면 (FIN/ACK packet 을수신했을경우 ), Sn_SSR 은 SOCK_CLOSED 로변경된다. Copyright 2008 WIZnet Co., Inc. All rights reserved. 68

69 0x10 CLOSE Disconnect-request가실패했다면, TCP TO 가발생 (Sn_IR(3)= 1 ) 하고 Sn_SSR은 SOCK_CLOSED로변경된다. cf> DISCON 대신 CLOSE를사용할경우, Disconnect-process(disconnectrequest 전송 ) 없이, 단지 Sn_SSR만 SOCK_CLOSED로변경된다. 그리고통신중상대방으로부터 RST packet을수신할경우, 무조건 Sn_SSR은 SOCK_CLOSED로변경된다. SOCKETn을 close한다. Sn_SSR은 SOCK_CLOSED로변경된다. 상대방에게 Sn_TX_WRSR으로설정된크기의 Data를전송한다. TCP나 UDP mode에서, Sn_TX_WRSR이 Maximum segment size(mss) 보다클경우 W5300은자동으로 Data를 MSS 단위로나누고, 나누어진 Data(DATA packet) 을전송하게된다. 그러나 IPRAW나 MACRAW Mode에서는이와같은기능은지원되지않고 Host가전송 Data를직접 MSS 단위로나누어전송해야한다. SEND에대한처리가완료되었을경우 Sn_IR (SENDOK)= 1 로된다. Host는 Sn_IR(SENDOK)= 1 를확인후그다음 Data에대한 SEND command 를내릴수있다. 0x20 SEND SEND 에의해 DATA packet 를상대방에게성공적으로전송한경우 ( 상대 방으로부터 DATA/ACK packet 을수신한경우 ) Sn_TX_FSR 은전송 DATA packet size 만큼증가한다. 그렇지못한경우 (DATA/ACK packet 을수신 하지못했을경우 ), TCP TO 가발생 (Sn_IR(3)= 1 ) 하고 Sn_SSR 은 SOCK_CLOSED 로변경된다. cf> SEND 이전에, Host 는전송할 Data 를 Sn_TX_FIFOR 을통해 SOCKETn 의 Internal TX memory 로 copy 하고, Data size 를 Sn_TX_WRSR 에설정해 야한다. UDP(Sn_MR(P3:P0)=Sn_MR_UDP) 나 IPRAW((Sn_MR(P3:P0)=Sn_MR_IPRAW) mode 일때만유효하다. 0x21 SEND_MAC 기본동작은 SEND 와같다. SEND 는자동으로 ARP-process 를통해 Destination hardware address 를 얻은후 Data 를전송하는반면, SEND_MAC 은 Host 가설정한 Sn_DHAR 을 Destination hardware address 로하여 Data 를전송한다. SEND_MAC Copyright 2008 WIZnet Co., Inc. All rights reserved. 69

70 0x22 SEND_KEEP 은 Hardware address를이미알고있는 Destination으로 UDP나 IPRAW data를전송할때불필요한 ARP-process를없애 Network traffic을감소시킬수있다. TCP mode일때만유효하다. 상대방의 TCP 접속상태를 Check하기위해 KEEP ALIVE(KA) packet을전송한다. SEND_KEEP은 Sn_KPALVTR = 0 일때만동작하며, Sn_KPALVTR > 0 일경우무시된다. Sn_KPALVTR > 0 인경우, Sn_KPALVTR 의설정시간동안 Data 송수신이없을때자동으로상대방에게 KA packet을전송한다. KA packet을성공적으로전송했다면 (KA/ACK packet을상대방으로부터수신했다면 ), Sn_SSR은 SOCK_ESTABLISHED를계속유지한다. 실패했을경우 ( 상대방이이미접속을종료했거나, KA/ACK를전송하지않을때 ) 는 TCP TO 가발생 (Sn_IR(3)= 1 ) 하고 Sn_SSR은 SOCK_CLOSED로변경된다. cf> KA packet은접속이후한번이상의 Data 송신이나수신이후에 전송될수있다. Host 가 SOCKETn 의수신 DATA packet 을수신했음을알린다. 0x40 RECV cf> RECV 이전에, Host는 SOCKETn의 Internal RX memory에서수신 DATA packet를 Sn_RX_FIFOR을통해 Host memory로 Copy해야한다. 아래 command들은 SOCKET0이고 S0_MR(P3:P0)=S0_MR_PPPoE일때만유효하다. How to use PPPOE 를참조하라. 0x23 PCON PPPoE discovery packet 전송을시작으로 PPPoE connection을시작한다. 0x24 PDISCON PPPOE connection을종료한다. 0x25 PCR 각 Phase에서, REQ message를전송한다. 0x26 PCN 각 Phase에서, NAK message를전송한다. 0x27 PCJ 각 Phase에서 REJECT message를전송한다. Sn_IMR (SOCKETn Interrupt Mask Register)[R/W] [0x x40n/0x204+0x40n] [0x--FF] Host로알려줄 SOCKETn의 Interrupt를설정한다. Sn_IMR의 Interrupt mask bit들은 Sn_IR의 Interrupt bit들과각각대응된다. 임의의 SOCKET interrupt가발생하고 Sn_IMR의그 bit가 1 로설정되어있을경우 Sn_IR의대응 Bit가 1 로 Copyright 2008 WIZnet Co., Inc. All rights reserved. 70

71 설정된다. Sn_IMR과 Sn_IR의임의 bit가모두 1 일때 IR(n)= 1 된다. 이때 IMR(n)= 1 이라면 Host에게 Interrupt가 Issue( /INT signal low assert) 된다. Sn_IMR x x40n x x40n Sn_IMR x x40n PRECV PFAIL PNEXT SENDOK TIMEOUT RECV DISCON CON 0x x40n Sn_IMR(15:8)/Sn_IMR0(7:0) : All Reserved Sn_IMR(7:0)/Sn_IMR1(7:0) Bit Symbol Description 7 PRECV Sn_IR(PRECV) Interrupt Mask SOCKET=0 이고 S0_MR(P3:P0)=S0_MR_PPPoE일때만유효하다. 6 PFAIL Sn_IR(PFAIL) Interrupt Mask SOCKET=0 이고 S0_MR(P3:P0)=S0_MR_PPPoE일때만유효하다. 5 PNEXT Sn_IR(PNEXT) Interrupt Mask SOCKET=0 이고 S0_MR(P3:P0)=S0_MR_PPPoE일때만유효하다. 4 SENDOK Sn_IR(SENDOK) Interrupt Mask 3 TIMEOUT Sn_IR(TIMEOUT) Interrupt Mask 2 RECV Sn_IR(RECV) Interrupt Mask 1 DISCON Sn_IR(DISCON) Interrupt Mask 0 CON Sn_IR(CON) Interrupt Mask Sn_IR (SOCKETn Interrupt Register) [R/W] [0x x40n/0x206+0x40n] [0x--00] Sn_IR은 Host에게 Establishment, Termination, Receiving data, Timeout과같은 SOCKETn의 Interrupt 종류를알려주기위한 Register이다. 임의의 Interrupt가발생하고 Sn_IMR의해당 Mask bit이 1 인경우 Sn_IR의그 Interrupt bit 가 1 이된다. 1 로설정된 Sn_IR의 Bit를 Clear하기위해서는그 Bit를 1 로 Host-Write한다. Sn_IR의모든 Bit이 0 으로 Clear될때, IR(n) 은자동으로 Clear된다. Copyright 2008 WIZnet Co., Inc. All rights reserved. 71

72 Sn_IR x x40n x x40n Sn_IR x x40n PRECV PFAIL PNEXT SENDOK TIMEOUT RECV DISCON CON 0x x40n Sn_IR(15:8)/Sn_IR0(7:0) : All Reserved Sn_IR(7:0)/Sn_IR1(7:0) Bit Symbol Description 7 PRECV PPP Receive Interrupt 지원하지않는 Option data를수신하였을경우설정 6 PFAIL PPP Fail Interrupt PAP authentication이실패했을경우설정 5 PNEXT PPP Next Phase Interrupt PPPoE connection 처리과정에서 Phase 변경시설정 4 SENDOK SEND OK Interrupt SEND command가완료되었을경우설정 3 TIMEOUT TIMEOUT Interrupt ARP TO 나 TCP TO 가발생했을경우설정 2 RECV Receive Interrupt 상대방으로부터 DATA packet을수신할때마다설정 1 DISCON Disconnect Interrupt 상대방으로부터 FIN packet이나 FIN/ACK Packet을수신하였을경우설정 0 CON Connect Interrupt 상대방과의접속이성공적으로이루어졌을경우설정 Sn_SSR (SOCKETn SOCKET Status Register) [R] [0x x40n/0x208+0x40n] [0x--00] SOCKETn 의 SOCKET status 를알려준다. SOCKET status 는 Sn_CR 의 Command 나, Packet 송수 신에의해변경될수있다. Sn_SSR(0x x40n/0x208+0x40n) Sn_SSR0(0x x40n/0x208+0x40n) Reserved Sn_SSR1(0x x40n/0x209+0x40n) Socket stauts Copyright 2008 WIZnet Co., Inc. All rights reserved. 72

73 Sn_SSR(15:8)/Sn_IR0(7:0) : All Reserved Sn_SSR(7:0)/Sn_SSR1(7:0) Value Symbol Description 0x00 SOCK_CLOSED SOCKETn의 Resource가 Release된상태. DISCON, CLOSE command가수행되거나 ARP TO,TCP TO 가발생했을경우이전값에관계없이전이된다. 이상태에서는오직 OPEN command만수행가능하다. 0x13 SOCK_INIT SOCKETn이 TCP mode로 Open된상태. Sn_MR(P3:P0)=Sn_MR_TCP이고, OPEN command가수행되었을때전이되며, TCP connection establishment의초기단계이다. TCP SERVER 로동작할경우 LISTEN, TCP CLIENT 로동작할경우 CONNECT command가수행가능하다. 0x14 SOCK_LISTEN SOCKETn이 TCP SERVER 로동작하며, TCP CLIENT 의 connection-request(syn packet) 를기다리는상태. LISTEN command가수행되었을때전이된다. SOCK_LISTEN에서 TCP CLIENT 의 Connect-request(SYN packet) 처리를성공했을경우 SOCK_ESTABLISHED로전이된다. 실패했을경우 TCP TO 가발생 (Sn_IR(TIMEOUT)= 1 ) 하고 SOCK_CLOSED로전이된다. 0x17 SOCK_ESTABLISHED TCP connection이 established 상태. SOCK_LISTEN에서 TCP CLIENT 의 SYN packet 처리를성공했을경우나 CONNECT command에수행이성공했을경우전이된다. 이상태에서 DATA packet 송수신이가능하다. 즉 SEND 나 RECV command를수행할수있다. 0x1C SOCK_CLOSE_WAIT 상대로부터 Disconnect-request(FIN packet) 를수신한상태. TCP connection이완전히 Disconnect된것이아닌 Half close 상태이므로 DATA packet 송수신이가능하다. TCP connection을완전히 Disconnect 하기위해선 DISCON command를수행한다. 하지만단순히 SOCKET을 Close하기원한다면 CLOSE command를수행한다. Copyright 2008 WIZnet Co., Inc. All rights reserved. 73

74 0x22 SOCK_UDP SOCKETn이 UDP mode로 Open된상태. Sn_MR(P3:P0)=Sn_MR_UDP이고, OPEN command가수행되었을때전이되며, TCP mode SOCKET과같은 Connection-process없이 DATA packet을직접송수신할수있다. 0x32 SOCK_IPRAW SOCKETn이 IPRAW mode로 Open된상태. Sn_MR(P3:P0)=Sn_MR_IPRAW이고, OPEN command가수행되었을때전이되며, UDP mode SOCKET처럼 Connection-process없이 IP packet을 packet을직접송수신할수있다. 0x42 SOCK_MACRAW SOCKET0이 MACRAW mode로 Open된상태. S0_MR(P3:P0)=S0_MR_MACRAW이고, S0_CR=OPEN 일때전이되며, UDP mode SOCKET처럼 Connection-process없이 MAC packet(ethernet frame) 을직접송수신할수있다. 0x5F SOCK_PPPoE SOCKET0이 PPPoE mode로 Open된상태 S0_MR(P3:P0)=S0_MR_PPPoE이고, S0_CR=OPEN 일때전이되며, PPPoE connection에서일시적으로사용된다. How to use PPPoE in W5300 을참조. 아래의 SOCKET status 은 Sn_SSR 의전이과정에서관찰될수있는 temporary Status 들이다. 0x15 SOCK_SYNSENT TCP SERVER 에게 Connect-request(SYN packet) 를전송한상 태. 이 Status는 CONNECT command에 의한 SOCK_INIT에서 SOCK_ESTABLISEHD로의전이과정에서나타난다. 이 Status에서 TCP SEVER 로부터 Connect-accept(SYN/ACK packet) 을수신할경우자동으로 SOCK_ESTABLISHED로전이된다. TCP SEVER 로부터 TCP TO 발생 (Sn_IR(TIMEOUT)= 1 ) 이전까지 SYN/ACK packet을수신하지못할경우 SOCK_CLOSED로전이한다. 0x16 SOCK_SYNRECV TCP CLIENT 로부터 Connect-request(SYN packet) 를수신한상태. W5300 이 Connect-request 에대한응답으로 Connect-accept (SYN/ACK packet) 을 TCP CLIENT 에게성공적으로전송하였 Copyright 2008 WIZnet Co., Inc. All rights reserved. 74

75 을경우자동으로 SOCK_ESTABLISHED로전이한다. 전송에실 패하였을 경우 TCP TO 가 발생 (Sn_IR(TIMEOUT)= 1 ) 하고 SOCK_CLOSED로전이된다. 0x18 SOCK_FIN_WAIT SOCKETn이 Closing되는상태 0X1B SOCK_TIME_WAIT Active close나 Passive close시, Disconnect-process에서관찰된 0X1D SOCK_LAST_ACK 다. Disconnect-process 과정이성공적으로완료되거나, TCP TO 가발생 (Sn_IR(TIMEOUT)= 1 ) 하면 SOCK_CLOSED로전이된다. 0x01 SOCK_ARP Destination hardware address를찾기위해 ARP-request를전송하는상태이상태는 SOCK_UDP나 SOCK_IPRAW에서 SEND command를수행할경우관찰되거나, SOCK_INIT에서 CONNECT command 를수행할경우관찰되는 Status이다. Destination으로부터 Hardware address를성공적으로얻은경우 (ARP-response을수신한경우 ), SOCK_UDP, SOCK_IPRAW, SOCK_SYNSENT로각각전이된다. 실패할경우 ARP TO 가발생 (Sn_IR(TIMEOUT)= 1 ) 하고, UDP나 IPRAW mode일경우이전 Status인 SOCK_UDP나 SOCK_IPRAW로되돌아가며, TCP인경우 SOCK_CLOSED로전이된다. cf> SOCK_UDP나 SOCK_IPRAW에서, 이전 SEND command에대한 Sn_DIPR와현재 SEND command의 Sn_DIPR이다를경우에만 ARP-process가동작한다. Sn_DIPR이같을경우 ARPprocess 없이이전에획득한 Destination hardware address를그대로사용한다. Copyright 2008 WIZnet Co., Inc. All rights reserved. 75

76 Fig 5. SOCKETn Status Transition Sn_PORTR(SOCKETn Source Port Register)[R/W][0x0820A+0x40n/0x20A+0x40A] [0x0000] Source port number를설정한다. SOCKETn을 TCP나 UDP mode로사용할때만유효하며, 그외 mode에서는무시된다. OPEN Command 이전에반드시설정한다. Ex) Sn_PORTR = 5000(0x1388) Sn_PORTR(0x0820A+0x40n/0x20A+0x40n) Sn_PORTR0(0x0820A+0x40n/0x20A+0x40n) 0x13 Sn_PORTR1(0x0820B+0x40n/0x20B+0x40n) 0x88 Copyright 2008 WIZnet Co., Inc. All rights reserved. 76

77 Sn_DHAR (SOCKETn Destination Hardware Address Register) [R/W] [0x0820C+0x40n/0x20C+0x40n] [FF.FF.FF.FF.FF.FF] SOCKETn의 Destination hardware address를설정하거나설정된다. 또한 SOCKET0이 PPPoE mode로사용될경우 S0_DHAR은이미알고있는 PPPoE server hardware address로설정한다. UDP나 IPRAW mode에서 SEND_MAC command를사용할경우 SOCKETn의 Destination hardware address를설정한다. 또한 TCP, UDP, IPRAW mode에서 Sn_DHAR은 CONNECT나 SEND command에의한 ARP-process를통해획득한 Destination hardware address로설정된다. Host는 CONNECT나 SEND command 성공이후 Sn_DHAR을통해 Destination hardware address를알수있다. PPPoE mode에서, W5300의 PPPoE-process를이용할경우 PPPoE server hardware address를따로설정할필요는없다. 하지만 W5300의 PPPoE-process를이용하지못하고 MACRAW mode로 PPPoE-process를직접구현하여처리한경우라할지라도, PPPoE packet을송수신하기위해서는, 직접구현한 PPPoE-process를통해획득한 PPPoE server hardware address, PPPoE server IP address, PPP session ID를설정하고 MR(PPPoE) 를 1 로반드시설정한다. S0_DHAR는이미알고있는 PPPoE server hardware address를설정하며, OPEN command 이전에설정한다. S0_DHAR을통해설정된 PPPoE server hardware address는 OPEN command 이후 PDHAR에반영된다. 설정된 PPPoE information은 CLOSE command 이후에도내부적으로계속유효하다. Ex) Sn_DHAR = DC Sn_DHAR(0x0820C+0x40n/0x20C+0x040n) Sn_DHAR0(0x0820C+0x40n/0x20C+0x040n) 0x00 Sn_DHAR1(0x0820D+0x40n/0x20D+0x040n) 0x08 Sn_DHAR2(0x0820E+0x40n/0x20E+0x040n) Sn_DHAR2(0x0820E+0x40n/0x20E+0x040n) 0xDC Sn_DHAR3(0x0820F+0x40n/0x20F+0x040n) 0x01 Sn_DHAR4(0x x40n/0x210+0x040n) Sn_DHAR4(0x x40n/0x210+0x040n) 0x02 Sn_DHAR5(0x x40n/0x211+0x040n) 0x10 Sn_DPORTR (SOCKETn Destination Port Register) [R/W] [0x x40n/0x212+0x40n] [0x0000] SOCKETn의 Destination port number를설정하거나설정되며, SOCKET0이 PPPoE mode로사용될경우 S0_DPORTR은이미알고있는 PPP Session ID로설정한다. TCP, UDP, PPPoE mode에서만유효하고, 그외의 mode에서는무시된다. TCP mode에서, TCP CLIENT 로동작할경우접속하기위한 TCP SERVER 의 Listen port number로설정하고, CONNECT command 이전에설정한다. TCP SERVER 로동작할경우 TCP CLIENT 와접속성공이후 TCP CLIENT 의 Port number로설정된다. Copyright 2008 WIZnet Co., Inc. All rights reserved. 77

78 UDP mode에서, Sn_DPORTR은 UDP DATA packet 전송에사용될 Port number로 SEND나 SEND_MAC command 이전에설정한다. PPPoE mode에서, S0_PDHAR과같은경우로 S0_DPORTR는이미알고있는 PPP Session ID를설정한다. S0_DPORTR을통해설정된 PPP Session ID는 OPEN command 이후 PSIDR에반영된다. Ex) Sn_DPORTR = 5000(0x1388) Sn_DPORTR(0x x40n/0x212+0x40n) Sn_DPORTR0(0x x40n/0x212+0x40n) Sn_DPORTR1(0x x40n/0x213+0x40n) 0x13 0x88 Sn_DIPR (SOCKETn Destination IP Address Register) [R/W] [0x x40n/0x214+0x40n] [ ] SOCKETn의 Destination IP address를설정하거나설정되며, SOCKET0이 PPPoE mode로사용될경우 S0_DIPR은이미알고있는 PPPoE server IP address로설정한다. TCP, UDP, PPPoE mode에서만유효하고, 그외의 mode에서는무시된다. TCP mode에서, TCP CLIENT 로동작할경우접속하기위한 TCP SERVER 의 IP address로설정하고, CONNECT command 이전에설정한다. TCP SERVER 로동작할경우 TCP CLIENT 와접속성공이후내부적으로 TCP CLIENT 의 IP address로설정된다. UDP mode에서, Sn_DIPR은 UDP DATA packet 전송에사용될 Destination IP address로 SEND나 SEND_MAC command 이전에설정한다. PPPoE mode에서, S0_DHAR과같은경우로 S0_DIPR는이미알고있는 PPPoE server IP address를설정한다. Ex) Sn_DIPR = Sn_DIPR(0x x40n/0x214+0x040n) Sn_DIPR0(0x x40n/0x214+0x040n) Sn_DIPR1(0x x40n/0x215+0x040n) 192 (0xC0) 168 (0xA8) Sn_DHAR2(0x x40n/0x216+0x040n) Sn_DIPR2(0x x40n/0x216+0x040n) Sn_DIPR3(0x x40n/0x217+0x040n) 0 (0x00) 11 (0x0B) Sn_MSSR (SOCKETn Maximum Segment Size Register) [R/W] [0x x40n/0x218+0x40n] [0x0000] SOCKETn의 MTU(Maximum Transfer Unit) 를설정하거나, 설정된 MTU를알려준다. Copyright 2008 WIZnet Co., Inc. All rights reserved. 78

79 Host가 Sn_MSSR를설정하지않을경우는 Default MTU로설정된다. TCP나 UDP mode만지원하며, PPPoE를사용할경우 (MR(PPPoE)= 1 ) PPPoE의 MTU내에서 TCP나 UDP mode의 MTU가결정된다. IPRAW나 MACRAW는내부적으로 MTU를처리하지않고 Default MTU가적용되므로, Host는 Default MTU보다큰 Data를전송할때 Data를 Default MTU 단위로직접 (Manually) 나누어전송해야한다. TCP나 UDP mode에서는 Host가전송할 Data가설정된 MTU보다클경우, W5300은설정된 MTU 단위로 Data를내부적으로 (Automatically) 나누어전송한다. MTU는 TCP mode에서 MSS라불리며, MSS는 TCP connection 과정을통해 Host-Written- Value(Host 설정값 ) 와상대방의 MSS 값중작은값으로자동으로설정된다. UDP mode에서는 TCP mode와같은 Connection-process가없고 Host-Written-Value를그대로사용한다. MTU가서로다른상대방과통신할경우, W5300은 ICMP(Fragment MTU) packet을수신할수있다. 이경우 IR(FMTU)= 1 가되고 Host는 FMTUR과 UIPR을통해 Fragment MTU 와 Destination IP address를알수있다. IR(FMTU)= 1 일경우그상대방과는 UDP 통신이불가능하므로, 해당 SOCKET을 close하고알아낸 FMTU를 Sn_MSSR로설정한후 OPEN command로 open하여다시통신을시도한다. Normal (MR(PPPoE)= 0 ) PPPoE (MR(PPPoE)= 1 ) Mode Default MTU Range Default MTU Range TCP ~ ~ 1452 UDP ~ ~ 1464 IPRAW MACRAW Ex) Sn_MSSR = 1460 (0x05B4) Sn_MSSR(0x x40n/0x218+0x040n) Sn_MSSR0(0x x40n/0x218+0x040n) 0x05 Sn_MSSR1(0x x40n/0x219+0x040n) 0xB4 Sn_KPALVTR(SOCKETn Keep Alive Time Register)[R/W] [0x0821A+40n/0x21A+0x40n][0x00] 1 byte register로 SOCKETn의 KEEP ALIVE(KA) packet의전송 Time을설정한다. TCP mode만유효하며, 그외 mode는무시된다. 단위는 5s이다. KA packet은 Sn_SSR이 SOCK_ESTABLISHED로전이되고한번이상의 DATA packet 송신이나수신이후전송이가능하다. Sn_KPALVTR > 0일경우, 설정된 Time-period가지나게되면 W5300은내부적으로 (automatically) KA packet을전송하여 TCP connection을 Check한다 Copyright 2008 WIZnet Co., Inc. All rights reserved. 79

80 (Auto-Keep-Alive-process). Sn_KPALVTR = 0 일경우는 Auto-Keep-Alive-process는동작하지않으며, Host의 SEND_KEEP command에의해 KA packet이전송할수있다 (Manual-Keep- Alive-process). Manual-Keep-Alive-process는 Sn_KPALVTR > 0 일경우무시된다. Ex) Sn_KPALVTR = 10, 매 50s마다 KA packet을전송 Sn_PROTOR(0x0821A+0x40n/0x21A+0x040n) Sn_KPALVTR(0x0821A+0x40n/0x21A+0x040n) Sn_PROTOR (0x0821B+0x40n/0x21B+0x040n) 10 (0x0A) Sn_PROTOR Sn_PROTOR (SOCKETn Protocol Number Register)[R/W] [0x0821B+40n/0x21B+0x40n] [0x00] 1 byte register로 IP layer에서 IP header의 Protocol number field를설정한다. IPRAW mode에서만유효하며, 그외 mode는무시된다. Sn_PROTOR은 OPEN command 이전에설정한다. IPRAW mode로 Open된 SOCKETn은 Sn_PROTOR에설정된 Protocol number의 Data만을송수신한다. Sn_PROTOR은 0x00 ~ 0xFF 의범위내에서설정가능하나, W5300은 TCP(0x06), UDP(0x11) protocol number은지원하지않는다. Protocol number는 IANA(Internet Assigned Numbers Authority) 에서정의하고있으며, IANA의 online document( 를참조하라. Ex) Sn_PROTOR = 0x01 (ICMP) Sn_PROTOR(0x0821A+0x40n/0x21A+0x040n) Sn_KPALVTR(0x0821A+0x40n/0x21A+0x040n) Sn_KPALVTR Sn_PROTOR (0x0821B+0x40n/0x21B+0x040n) 0x01 Sn_TOSR (SOCKETn TOS Register) [R/W] [0x0821C+40n/0x21C+40n] [0x00] IP layer에서 IP header의 TOS(Type of service) field를설정한다. OPEN command 이전에설정한다. 참조. Ex) Sn_TOSR = 0x00 Sn_TOSR(0x0821C+0x40n/0x21C+0x040n) Sn_TOSR0(0x0821C+0x40n/0x21C+0x040n) Reserved Sn_TOSR1(0x0821D+0x40n/0x21D+0x040n) 0x00 Sn_TTLR (SOCKETn TTL Register) [R/W] [0x0821E+40n/0x21E+40n] [0x80] IP layer에서 IP header의 TTL(Time to live) field를설정한다. OPEN command 이전에설정한다. 참조. Copyright 2008 WIZnet Co., Inc. All rights reserved. 80

81 Ex) Sn_TTLR = 128 (0x80) Sn_TTLR(0x0821E+0x40n/0x21E+0x040n) Sn_TTLR0(0x0821E+0x40n/0x21E+0x040n) Sn_TTLR1(0x0821F+0x40n/0x21F+0x040n) Reserved 0x80 Sn_TX_WRSR (SOCKETn TX Write Size Register) [R/W] [0x n/0x220+40n] [0x ] Sn_TX_FIFOR을통해 Internal TX memory에 Write한 Data의 Byte size를설정한다. SEND나 SEND_MAC command 이전에설정하며, TMSRn에의해설정된 Internal TX memory size보다크게설정할수없다. TCP나 UDP mode이고 Sn_TX_WRSR > Sn_MSSR 인경우, W5300은내부적으로 (Automatically) Sn_MSSR 단위로 Data를나누어전송한다. 그외 Mode에서는 Sn_TX_WRSR을 Sn_MSSR보다크게설정해선안된다. Ex1) Sn_TX_WRSR = 64KB = = 0x Sn_TX_WRSR(0x x40n/0x220+0x040n) Sn_TX_WRSR0(0x x40n/0x220+0x040n) Sn_TX_WRSR1(0x x40n/0x221+0x040n) Reserved Sn_TX_WRSR2(0x x40n/0x222+0x040n) Sn_TX_WRSR2(0x x40n/0x222+0x040n) 0x00 Sn_TX_WRSR3(0x x40n/0x21D+0x040n) 0x00 Ex2) Sn_TX_WRSR = 2017 = 0x000007E1 Sn_TX_WRSR(0x x40n/0x220+0x040n) Sn_TX_WRSR0(0x x40n/0x220+0x040n) Sn_TX_WRSR1(0x x40n/0x221+0x040n) Reserved Sn_TX_WRSR2(0x x40n/0x222+0x040n) Sn_TX_WRSR2(0x x40n/0x222+0x040n) 0x07 Sn_TX_WRSR3(0x x40n/0x223+0x040n) 0xE1 Sn_TX_FSR (SOCKETn TX Free Size Register) [R] [0x n/0x224+40n] [0x ] SOCKETn 의 Internal TX memory 의 Free size( 전송가능한 Data 의 Byte size) 를알려준다. Copyright 2008 WIZnet Co., Inc. All rights reserved. 81

82 Sn_TX_FSR보다크게 Sn_TX_FIFOR을 Host-Write하면안된다. 따라서 Data 전송전에 Sn_TX_FSR를반드시확인하고, 전송할 Data의크기가 Sn_TX_FSR보다작거나같으면 SEND 나 SEND_MAC command로 Data를전송한다. TCP mode에서는상대방으로부터 Data 수신이확인 (DATA/ACK packet 수신 ) 되면, Sn_TX_FSR 은상대방이수신한 DATA packet 크기만큼내부적으로증가하게된다. 그외 mode에서는 IR(SENDOK) = 1 인경우 Sn_TX_FSR은전송한 Data size만큼내부적으로증가하게된다. Ex1) Sn_TX_FSR = 64KB = = 0x Sn_TX_FSR(0x x40n/0x224+0x040n) Sn_TX_FSR0(0x x40n/0x214+0x040n) Sn_TX_FSR1(0x x40n/0x225+0x040n) Reserved Sn_TX_FSR2(0x x40n/0x226+0x040n) Sn_TX_FSR2(0x x40n/0x226+0x040n) Sn_TX_FSR3(0x x40n/0x227+0x040n) 0x00 0x00 Ex2) Sn_TX_FSR = = 0x Sn_TX_FSR(0x x40n/0x224+0x040n) Sn_TX_FSR0(0x x40n/0x224+0x040n) Sn_TX_FSR1(0x x40n/0x225+0x040n) Reserved Sn_TX_FSR2(0x x40n/0x226+0x040n) Sn_TX_FSR2(0x x40n/0x226+0x040n) 0x82 Sn_TX_FSR3(0x x40n/0x227+0x040n) 0x34 Sn_RX_RSR (SOCKETn RX Received Size Register) [R] [0x n/0x228+40n] [0x ] SOCKETn의 Internal RX memory의 Received data의 Byte size를알려준다. Sn_RX_RSR보다크게 Sn_RX_FIFOR을 Host-Read하면안된다. 따라서 Data 수신전에 Sn_RX_RSR를반드시확인하고, Sn_RX_RSR보다같거나작게 Sn_RX_FIFOR을 Host-Read하여 Host system memory로 Copy한다. Memory copy 후에는 RECV command를수행하여수신 Data copy를완료했음을 W5300에게알린다. Sn_RX_RSR은 Sn_RX_FIFOR를 Host-Read 할때마다, 2 bytes씩내부적으로감소한다. Sn_RX_RSR > 0 일경우하나이상의 DATA packet이존재할수있고 DATA packet 단위로처리되어야한다. Sn_RX_FIFOR을참조하라. Ex1) Sn_RX_RSR = 64KB = = 0x Copyright 2008 WIZnet Co., Inc. All rights reserved. 82

83 Sn_RX_RSR(0x x40n/0x228+0x040n) Sn_RX_RSR0(0x x40n/0x21C+0x040n) Sn_RX_RSR1(0x x40n/0x229+0x040n) Reserved Sn_RX_RSR2(0x0822A+0x40n/0x22A+0x040n) Sn_RX_RSR2(0x0822A+0x40n/0x22A+0x040n) Sn_RX_RSR3(0x0822B+0x40n/0x22B+0x040n) 0x00 0x00 Ex2) Sn_RX_RSR = 3800 = 0x00000ED8 Sn_TX_RSR(0x x40n/0x228+0x040n) Sn_RX_RSR0(0x x40n/0x21C+0x040n) Sn_RX_RSR1(0x x40n/0x229+0x040n) Reserved Sn_RX_RSR2(0x0822A+0x40n/0x22A+0x040n) Sn_RX_RSR2(0x0822A+0x40n/0x22A+0x040n) Sn_RX_RSR3(0x0822B+0x40n/0x22B+0x040n) 0x0E 0xD8 Sn_FRAGR (SOCKETn Fragment Register) [R/W] [0x0822C+40n/0x22C+40n] [0x40] IP layer에서 IP header의 Fragment field를설정한다. W5300은 IP layer의 Packet fragment는 지원하지않는다. Sn_FRAGR를설정하더라도 IP data는 Fragment되지않으며이를설정하는 것은권장하지않는다. OPEN command 이전에설정한다. Ex) Sn_FRAGR = 0x40 (Don t Fragment) Sn_FRAGR(0x0822C+0x40n/0x22C+0x040n) Sn_FRAGR0(0x0822C+0x40n/0x22C+0x040n) Reserved Sn_FRAGR1(0x0822D+0x40n/0x22D+0x040n) 0x40 Sn_TX_FIFOR (SOCKETn TX FIFO Register) [R/W] [0x0822E+40n/0x22E+40n] [0xUUUU] SOCKETn의 Internal TX memory를간접적으로접근한다. SOCKETn의 Internal TX memory는 Host에의해직접적으로접근될수없으며, Sn_TX_FIFOR 을통해서만접근이허용된다. MR(MT) = 0 인경우 Internal TX memory는 Sn_TX_FIFOR을통해 Host-Write만허용된다. MR(MT) = 1 인경우 Host-Write와 Host-Read 모두허용되며, Target host system과 W5300간의 Interface 검증후에는반드시 0 으로설정한다.( How to Test Internal TX/RX Memory 참조 ). Target host system이 8bit data bus width를사용한다면반드시 Sn_TX_FIFOR0와 Sn_TX_FIFOR1를한쌍 (pair) 으로접근해야한다. 1byte 크기의 Data를 Internal TX memory로 Copyright 2008 WIZnet Co., Inc. All rights reserved. 83

84 Copy할지라도, 그 1byte data는 Sn_TX_FIFOR0에 Host-Write하고, Sn_TX_FIFOR1은 dummy data로 Host-Write해야한다. Sn_TX_FIFOR은반드시 2bytes 크기로접근해야하며, Low address register인 Sn_TX_FIFOR0를먼저접근한후 high address register인 Sn_TX_FIFOR1을접근해야한다. Sn_TX_FIFOR0을접근후 Sn_TX_FIFOR1 이외에다른 W5300 Register의접근은허용되지않는다. 임의의 Data를 2bytes씩 Sn_TX_FIFOR을통해 Host-Write할경우그 Data는 Internal TX memory로순차적으로 Copy된다. Sn_TX_FIFOR0과 Sn_TX_FIFOR1의값들은 Internal TX memory의 low address와 high address로각각저장된다. Internal TX memory에저장된 Data 들은 SEND나 SEND_MAC command에의해 Low address부터순서대로전송된다. Ex1) Sn_TX_FIFOR = 0x1122 Sn_TX_FIFOR(0x0822E+0x40n/0x22E+0x040n) Sn_TX_FIFOR0(0x0822E+0x40n/0x22E+0x040n) Sn_TX_FIFOR1(0x0822F+0x40n/0x22F+0x040n) 0x11 0x22 Ex2) 5bytes의 String data abcde 를전송할경우 (abcde - 0x61 0x62 0x63 0x64 0x65) 16 Bit Data Bus Width ( MR(DBW) = 1 ) 8 Bit Data Bus Width ( MR(DBW) = 0 ) Sn_TX_FIFOR = 0x6162 Sn_TX_FIFOR0 = 0x61 Sn_TX_FIFOR = 0x6364 Sn_TX_FIFOR1 = 0x62 Sn_TX_FIFOR = 0x6500 Sn_TX_FIFOR0 = 0x63 Sn_TX_WRSR0 = 0x0000 Sn_TX_FIFOR1 = 0x64 Sn_TX_WRSR1 = 0x0005 Sn_TX_FIFOR0 = 0x65 Sn_CR = 0x0020 (SEND command) Sn_TX_FIFOR1 = 0x00 Sn_TX_WRSR0 = 0x00 Sn_TX_WRSR1 = 0x00 Sn_TX_WRSR2 = 0x00 Sn_TX_WRSR2 = 0x05 Sn_CR1 = 0x20 (SEND command) Fig 6. Access to Internal TX Memory Copyright 2008 WIZnet Co., Inc. All rights reserved. 84

85 Sn_RX_FIFOR (SOCKETn RX FIFO Register) [R/W] [0x n/0x230+40n] [0xUUUU] SOCKETn의 Internal RX memory를간접적으로접근한다. SOCKETn의 Internal RX memory는 Host에의해직접적으로접근될수없으며, Sn_RX_FIFOR 을통해서만접근이허용된다. MR(MT) = 0 인경우 Internal RX memory는 Sn_RX_FIFOR을통해 Host-Read만허용된다. MR(MT) = 1 인경우 Host-Read와 Host-Write 모두허용되며, Target host system과 W5300간의 Interface 검증후에는반드시 0 으로설정한다.( How to Test Internal TX/RX Memory 참조 ). Target host system이 8bit data bus width를사용한다면 Sn_TX_FIFOR과마찬가지로 Sn_RX_FIFOR0와 Sn_RX_FIFOR1를한쌍 (pair) 으로접근해야하고, 또한 Sn_TX_FIFOR0과 Sn_TX_FIFOR1을접근한바로직후 Sn_RX_FIFOR0과 Sn_RX_FIFOR0을접근할수없다. 이럴경우 Sn_RX_FIFOR0과 Sn_RX_FIFOR1의값을제대로읽을수가없다. 이를방지하기위해서 Sn_TX_FIFOR0과 Sn_TX_FIFOR1을읽은후 Sn_MR와같은임의의 Register를먼저 Host-Read 한다음 Sn_RX_FIFOR을접근한다. Internal RX memory에수신된 DATA packet을 2bytes씩 Sn_RX_FIFOR을통해 Host-Read할경우 Internal RX memory의 Low address와 High address에위치한 Data는각각 Sn_RX_FIFOR0 와 Sn_RX_FIFOR1를통해알수있다. Host는 Internal RX memory의수신된 DATA packet 처리를완료했을경우 RECV command를수행한다. Internal RX memory에수신된 Data들은 Sn_MR(P3:P0) 에따라 DATA packet에대한 PACKET- INFO가앞에추가된다. 추가된 PACKET-INFO는그 DATA packet에대한 Size를포함한기타정보를가지고있으며, Host는 PACKET-INFO를먼저처리한후 DATA packet을처리해야한다. 수신된 DATA packet이홀수크기일경우 1byte dummy data가추가되며, Host는이 Dummy data를읽은후무시해야한다. DATA packet의마지막 Byte가 Dummy data인지아닌지는, PACKET-INFO의 Size 정보로판단할수있다. Host는 Internal RX memory에수신된 PACKET-INFO와 DATA packet 쌍들을 Sn_RX_FIFOR을통해 2bytes씩 Host-Read하여순차적으로처리한다. PACKET-INFO는 TCP나 MACRAW mode인경우 2bytes, UDP mode인경우 8bytes, IPRAW mode 인 6bytes의고정길이를갖는다. PACKET-INFO 처리에대한자세한설명은 Chapter 5. Functional Description 의각 mode 별설명을참조하라. Ex1) Sn_RX_FIFOR = 0x3344 Sn_RX_FIFOR(0x x40n/0x230+0x040n) Sn_RX_FIFOR0(0x x40n/0x230+0x040n) 0x33 Sn_RX_FIFOR1(0x x40n/0x231+0x040n) 0x44 Copyright 2008 WIZnet Co., Inc. All rights reserved. 85

86 Ex2) TCP mode에서 5bytes의 String data abcde 를수신하여 str 변수에저장할경우 16 Bit Data Bus Width ( MR(DBW) = 1 ) 8 Bit Data Bus Width ( MR(DBW) = 0 ) INT16 pack_size, idx,temp INT16 pack_size, idx,temp INT8 str[5] INT8 str[5], dummy pack_size = Sn_RX_FIFOR pack_size = Sn_RX_FIFOR0 idx = 0 pack_size = (pack_size << 8) LOOP pack_size/2 pack_size = pack_size + Sn_RX_FIFOR1 temp = Sn_RX_FIFOR idx = 0 str[idx] = (INT8)(temp >> 8) LOOP pack_size/2 idx = idx + 1 str[idx] = Sn_RX_FIFOR0 str[idx] = (INT8)(temp & 0x00FF) idx = idx + 1 idx = idx + 1 str[idx] = Sn_RX_FIFOR1 END LOOP idx = idx + 1 IF pack_size is odd? THEN END LOOP temp = Sn_RX_FIFOR IF pack_size is odd? THEN str[idx] = (INT8)(temp >> 8) str[idx] = Sn_RX_FIFOR0 END IF dummy = Sn_RX_FIFOR1 Sn_CR = 0x0040 (RECV command) END IF Sn_CR1 = 0x40 (RECV command) Fig 7. Access to Internal RX Memory Copyright 2008 WIZnet Co., Inc. All rights reserved. 86

87 5. Functional Description W5300은간단한 Register 조작만으로 Internet connectivity를제공한다. 이 Chapter에서는 W5300의초기화와각 Protocol(TCP, UDP, IPRAW, MACRAW) 에따른 Data 통신방법에대하여각단계별로 Pseudo code를기반으로살펴본다. 5.1 Initialization W5300의초기화는 Host interface 설정, Network 정보설정, Internal TX/RX memory 설정과같이 3단계로이루어진다. STEP 1 : Setting host interface 1. Data bus width, Host interface mode & timing 설정 (MR 참조 ) 2. Host interrupt 설정 (IMR 참조 ) STEP 2 : Setting network information 1. 통신을위한기본 Network 정보설정 (SHAR, GAR, SUBR, SIPR 참조 ) 2. Packet 전송을실패시사용하게될재전송 time & count 설정 (RTR, RCR 참조 ) SHAR에의해설정되는 Source hardware address는모든 Device에대해유일한 Hardware address(ethernet MAC address) 값을 Ethernet MAC layer에서사용하도록정해져있다. 이 MAC address의할당은 IEEE에서관장하고있으며, Network device를생산하는 Manufacture는생산된 Network device에 IEEE로부터할당받은 MAC address를부여하여야한다. STEP 3 : Allocation internal TX/RX memory for SOCKETn 1. Internal TX/RX memory 크기를각각결정 (MTYPER 참조 ) 2. SOCKETn의 TX/RX memory를각각결정 (TMSR, RMSR 참조 ) W5300은 8Kbytes의 Memory Block 16개를내부적으로포함하고있다. 16개의 Memory Block은 128Kbytes의 Address space에순차적으로 Mapping되어있다. 128Kbytes의 Memory는크게 Transmission(TX) memory, Reception(RX) memory로구분된다. Internal TX memory와 Internal RX memory는 128Kbytes 범위내에서 8Kbytes 단위로할당될수있다. Internal TX/RX memory는각할당된크기내에서또다시 SOCKET 별로최소 0Kbyte에서최대 64Kbytes 내에서 1Kbytes 단위로각각할당될수있다. 다음은예로 Internal TX memory로 72Kbytes, Internal RX memory로 56Kbytes를각각할당한것이다. SOCKET0에서 SOCKET7까지의 TX memory는 72Kbytes 범위내에서각각 4, 16, 1, 20, 0, 7, 12, 12KBytes로할당되고, RX Memory는 56Kbytes 범위내에서각각 17, 3, 5, 16, 3, 4, 4, 4Kbytes로된다. 이때 0Kbyte로설정된 SOCKET4은 Data 전송이불가능함에유의하라. Copyright 2008 WIZnet Co., Inc. All rights reserved. 87

88 Fig 8. Allocation Internal TX/RX memory of SOCKETn Copyright 2008 WIZnet Co., Inc. All rights reserved. 88

89 3단계에걸친 W5300 initialization 과정을성공적으로마쳤다면, W5300은 Ethernet을통해 Data communication이가능하다. 이시점부터 W5300은 Network으로부터수신한 Pingrequest packet에대한 Ping-reply를전송할수있게된다 (Auto-ping-reply). 5.2 Data Communication Initialization 과정후, W5300은 TCP, UDP, IPRAW, MACRAW mode의 SOCKET을 open하여상대방과 Data를송수신할수있게된다. W5300은독립적으로동시에사용가능한 SOCKET을총 8개까지지원한다. 이 Chapter에서는각 Mode에따른통신방법에대해서설명한다 TCP TCP는 Connection-oriented protocol이다. TCP는자신의 IP address와 Port number 그리고상대방의 IP address와 Port number를한쌍으로 Connection SOCKET을형성하게되고, 형성된 Connection SOCKET을통해 Data를송수신한다. Connection SOCKET의형성방법에는 TCP SERVER 와 TCP CLIENT 2가지가있다. 이는누가 connect-request(syn packet) 을전송하느냐에따라구분된다. TCP SERVER 은상대방의 connect-request 전송을대기하며, 전송된 connect-request을 accept하여 Connection SOCKET을형성하게된다 (Passive-open). TCP CLIENT 는자신이 connect-request를상대방에게전송하여 Connection SOCKET 형성을먼저요구하게된다 (Active-open). Fig 9. TCP SERVER & TCP CLIENT Copyright 2008 WIZnet Co., Inc. All rights reserved. 89

90 TCP SERVER Fig 10. TCP SERVER Operation Flow SOCKET Initialization TCP Data communication을위해 SOCKET Initialization 과정이필요하다. 이는 SOCKET을 open하는일이다. SOCKET open 과정은 W5300의 8개의 SOCKET 중하나를선택하여선택된 SOCKET의 Protocol mode(sn_mr(p3:p0)) 와 Source port number( TCP SERVER 에서는 Listen port number라고함 ) 인 Sn_PORTR을설정한후, OPEN command를수행함으로써이루어진다. OPEN command 이후 Sn_SSR이 SOCK_INIT으로변경되면 SOCKET initialization 과정은완료된다. SOCKET initialization 과정은 TCP SEVER 와 TCP CLIENT 의구분없이동일하게적용된다. 다음은 SOCKETn을 TCP mode의 Initialization 과정을보여준다. { START: Copyright 2008 WIZnet Co., Inc. All rights reserved. 90

91 } { } Sn_MR = 0x0001; /* sets TCP mode */ Sn_PORTR = source_port; /* sets source port number */ Sn_CR = OPEN; /* sets OPEN command */ /* wait until Sn_SSR is changed to SOCK_INIT */ if (Sn_SSR!= SOCK_INIT) Sn_CR = CLOSE; goto START; 만약상대방으로부터수신한 Data size가모두짝수크기로이루어진다면, Sn_MR(ALIGN) 을 1 로설정할수있다. Sn_MR(ALIGN) = 1 인경우 W5300은 TCP mode의 PACKET- INFO을추가하지않고, DATA packet만을 SOCKETn의 Internal RX Memory로저장하게된다. 이방법은 Host의 PACKET-INFO 처리 Overhead를줄여수신성능을향상시킬수있다. ( 위의 Code에서 Sn_MR = 0x0001 대신 Sn_MR = 0x0101를사용 ) LISTEN LISTEN command를수행하여 TCP SERVER 로동작시킨다. /* listen socket */ Sn_CR = LISTEN; /* wait until Sn_SSR is changed to SOCK_LISTEN */ if (Sn_SSR!= SOCK_LISTEN) Sn_CR = CLOSE; goto START; ESTABLISHED? Sn_SSR이 SOCK_LISTEN일때상대방으로부터 SYN packet을수신하게되면 Sn_SSR은 SOCK_SYNRECV로변경되고 SYN/ACK packet을전송후 SOCKETn은 Connection을형성하게된다. SOCKETn의 Connection이형성된이후부터 Data communication은가능해진다. SOCKETn의 Connection 형성을확인하는방법은 2가지가있다. First method : { if (Sn_IR(CON) == 1 ) Sn_IR(CON) = 1 ; goto ESTABLISHED stage; /* In this case, if the interrupt of SOCKETn is activated, interrupt occurs. Refer to IR, IMR Sn_IMR and Sn_IR. */ } Second method : { if (Sn_SSR == SOCK_ESTABLISHED) goto ESTABLISHED stage; } Copyright 2008 WIZnet Co., Inc. All rights reserved. 91

92 ESTABLISHED : Received Data? 상대방으로부터의 TCP data 수신을확인한다. First method : { if (Sn_IR(RECV) == 1 ) Sn_IR(RECV) = 1 ; goto Receiving Process stage; /* In this case, if the interrupt of SOCKETn is activated, interrupt occurs. Refer to IR, IMR Sn_IMR and Sn_IR. */ } Second Method : { if (Sn_RX_RSR!= 0x ) goto Receiving Process stage; } First method는매수신 DATA packet 마다 Sn_IR(RECV) 이 1 로설정된다. Host가이전에수신한 DATA packet의 Sn_IR(RECV) 를미처처리못하고 W5300이다음 DATA packet을수신할경우, 이전 Sn_IR(RECV) 에중복설정되어 Host는그다음의수신 DATA packet에대한 Sn_IR(RECV) 를인지할수가없게된다. 따라서 Host가각 Sn_IR(RECV) 에대한 DATA packet을완벽하게처리하지못한다면이방법은권장되지않는다. ESTABLISHED : Receiving Process Internal RX memory 에수신된 TCP data 를처리한다. 수신된 TCP data 의구조는아래와 같다. Fig 11. The received TCP data format 수신된 TCP data는 Sn_MR(ALIGN)= 0 일경우 PACKET-INFO와 DATA packet로이루어지며, Sn_MR(ALIGN)= 1 일경우 PACKET-INFO는제거되어 DATA packet으로만이루어진다. TCP mode에서상대방이전송한 Data 크기가 SOCKETn의 RX memory free size보다클경우 W5300은그 Data를수신할수없으며, RX memory free size가클때까지 Connection을유지한체기다린다. { /* first, check Sn_MR(ALIGN) */ if (Sn_MR(ALIGN) == 0 ) Copyright 2008 WIZnet Co., Inc. All rights reserved. 92

93 } { pack_size = Sn_RX_FIFOR; /* extract size of DATA packet from internal RX memory */ } else { pack_size = Sn_RX_RSR; /* check the total received data size */ } /* calculate the read count of Sn_RX_FIFOR */ if (pack_size is odd?) read_cnt = (pack_size + 1) / 2; read_cnt = pack_size / 2; /* extract DATA packet from internal RX memory */ for( i = 0; i < read_cnt; i++) { data_buf[i] = Sn_RX_FIFOR; /* data_buf is array of 16bit */ } /* set RECV command */ Sn_CR = RECV; <Notice> SOCKETn을송신없이수신전용으로사용하고자할경우 Host의 Internal RX memory 처리가늦어져 Internal RX memory가 Full에도달할수있다. 이럴경우, W5300의 Window size(tcp에서수신가능한최대 Data 크기 ) 가 0이아님에도불구하고상대방은 W5300의 Window size를 0으로오인하여, 더이상 Data를전송하지않고 Window size가증가할때까지기다리게된다. 이런현상은 W5300의 Data 수신성능을급감시키는원인이된다. 이를해결하기위해서 Internal RX memory에수신된 Data를처리한후, 처리한수신 Data size만큼 W5300의 Window size가증가했음을상대방에게알려야한다. 상기 code에서 RECV command 이후다음과같은 Code를추가함으로써간단히해결할수있다. /* set RECV command */ Sn_CR = RECV; /* Add the code that notifies the update of window size to the peer */ Sn_TX_WRSR = 0; /* set 0 to the transmit data size */ Sn_CR = SEND; /* set SEND command */ while(sn_ir(sendok)== 0 ); /* check previous SEND command completion */ Sn_IR(SENDOK)= 1 ; /* clear the SENDOK bit of Sn_IR */ Copyright 2008 WIZnet Co., Inc. All rights reserved. 93

94 ESTABLISHED : Send DATA? / Sending Process 전송할 Data를 Sn_TX_FIFOR을통해 Internal TX memory에저장한후상대방에게전송을시도한다. 전송할 Data 크기는할당된 SOCKETn의 Internal TX memory보다클수없으며, 전송할 Data 크기가설정된 MSS보다클경우 MSS 단위로나뉘어져전송된다. 다음 Data를전송하기위해선반드시이전의 SEND command가완료되었는지확인해야한다. 이전 SEND command 완료전에다시 SEND command를수행할경우오류가발생할수있다. Data의크기가클수록 SEND command 완료시간도길어지므로, 전송 Data 를적정한크기로나누어전송하는것이유리하다. { /* first, get the free TX memory size */ FREESIZE: get_free_size = Sn_TX_FSR; if (Sn_SSR!= SOCK_ESTABLISHED && Sn_SSR!= SOCK_CLOSE_WAIT) goto CLOSED state; if (get_free_size < send_size) goto FREESIZE; /* calculate the write count of Sn_TX_FIFOR */ if (send_size is odd?) write_cnt = (send_size + 1) / 2; else write_cnt = send_size / 2; /* copy data to internal TX memory */ for (i = 0; i < write_cnt; i++) { Sn_TX_FIFOR = data_buf[i]; /* data_buf is array of 16bit */ } /* check previous SEND command completion */ if (is first send?) ; /* skip check Sn_IR(SENDOK) */ else { while(sn_ir(sendok)== 0 ) { if(sn_ssr == SOCK_CLOSED) goto CLOSED state; /* check connection establishment */ } Sn_IR(SENDOK) = 1 ; /* clear previous interrupt of SEND completion */ } Copyright 2008 WIZnet Co., Inc. All rights reserved. 94

95 /* sets transmission data size to Sn_TX_WRSR */ Sn_TX_WRSR = send_size; /* set SEND command */ Sn_CR = SEND; } ESTABLISHED : Received FIN? 상대방으로부터 Disconnect-request(FIN packet) 를수신했는지확인한다. FIN packet 수신은다음과같이확인할수있다. First method : { if (Sn_IR(DISCON) == 1 ) Sn_IR(DISCON)= 1 ; goto CLOSED stage; /* In this case, if the interrupt of SOCKETn is activated, interrupt occurs. Refer to IR, IMR Sn_IMR and Sn_IR. */ } Second method : { if (Sn_SSR == SOCK_CLOSE_WAIT) goto CLOSED stage; } { } ESTABLISHED : Disconnect? / Disconnecting Process 더이상상대방과의 Data communication이필요가없는경우나상대방으로부터 FIN packet을수신했을경우는 Connection SOCKET을 Disconnect한다. /* set DISCON command */ Sn_CR = DISCON; ESTABLISHED : CLOSED? DISCON이나 CLOSE command에의해 SOCKETn이 Disconnect 혹은 Close 되었는지확인한다. First method : { if (Sn_IR(DISCON) == 1 ) goto CLOSED stage; /* In this case, if the interrupt of SOCKETn is activated, interrupt occurs. Refer to IR, IMR Sn_IMR and Sn_IR. */ Copyright 2008 WIZnet Co., Inc. All rights reserved. 95

96 } Second method : { if (Sn_SSR == SOCK_CLOSED) goto CLOSED stage; } ESTABLISHED : Timeout Timeout은 Connect-request(SYN packet) 나그것에대한응답 (SYN/ACK packet), DATA packet이나그것의응답 (DATA/ACK packet), Disconnect-request(FIN packet) 나그것의응답 (FIN/ACK packet) 등, 모든 TCP packet을전송할때발생할수있다. RTR과 RCR에설정된 Timeout 시간동안상기 packet들을전송하지못하면 TCP final timeout(tcp TO ) 이발생하게되고 Sn_SSR은 SOCK_CLOSED로전이한다. TCP TO 의확인은다음과같이할수있다. First method : { if (Sn_IR(TIMEOUT bit) == 1 ) Sn_IR(TIMEOUT)= 1 ; goto CLOSED stage; /* In this case, if the interrupt of SOCKETn is activated, interrupt occurs. Refer to IR, IMR Sn_IMR and Sn_IR. */ } Second method : { if (Sn_SSR == SOCK_CLOSED) goto CLOSED stage; } { } SOCKET Close Disconnect-process에의해이미 Disconnection된 SOCKETn이나 TCP TO 에의해 Close된 SOCKETn을완전히 Close하거나, Host가 Disconnect-process없이필요에의해 SOCKETn 을 Close할경우사용될수있다. /* clear the remained interrupts of SOCKETn*/ Sn_IR = 0x00FF; IR(n) = 1 ; /* set CLOSE command */ Sn_CR = CLOSE; Copyright 2008 WIZnet Co., Inc. All rights reserved. 96

97 TCP CLIENT CONNECT state 를제외한모든 state 는 TCP SEVER 와동일하다 TCP SERVER 를참조. Fig 12. TCP CLIENT Operation Flow { } CONNECT TCP SERVER 에게 connect-request(syn packet) 를 전송한다. TCP SERVER 와의 Connection SOCKET 형성과정에서 ARP TO, TCP TO 와같은 Timeout이발생할수있다. Sn_DIPR = server_ip; /* set TCP SERVER IP address*/ Sn_DPORTR = server_port; /* set TCP SERVER listen port number*/ Sn_CR = CONNECT; /* set CONNECT command */ Copyright 2008 WIZnet Co., Inc. All rights reserved. 97

98 5.2.2 UDP UDP는 Connection-less protocol이다. UDP는 TCP와달리 Connection SOCKET을형성하지않고 Data를송수신한다. TCP는신뢰성있는 Data 통신을보장하는반면, UDP는 Data 통신의신뢰성을보장하지않는 Datagram 통신을하는 protocol이다. UDP는 Connection SOCKET을사용하지않기때문에자신의 IP address와 Port number를알고있는많은상대방과의통신이허락된다. 이와같은 Datagram 통신은하나의 SOCKET을이용하여많은상대방과통신을할수있는이점이있는반면, 전송된 Data의손실이나원치않는상대방으로부터의 Data 수신과같은여러문제가발생할수있다. 이와같은문제를해결하고신뢰성을보장하기위해서, Host가직접손실된 Data를재전송하거나, 원치않는상대방으로부터의수신 Data를무시해야한다. UDP 통신은 unicast, broadcast, multicast 통신을지원하며, 다음과같은통신 flow를따른다. Fig 13. UDP Operation Flow Unicast & Broadcast Unicast 통신은가장일반적인 UDP 통신으로, 한번에하나의상대방에게 Data를전송한다. 반면, Broadcast 통신은 Broadcast IP address( ) 을이용하여한번의통신으로수신가능한모든상대방에게 Data를전달한다. 예로 A,B,C 에게 Data를전송할경우, Unicast 통신은 A, B, C 각각에대해서한번씩 Data를전송을한다. 이때 A, B, C에대한 Destination hardware address를획득하는과정 (ARP-process) 에서 ARP TO 가발생할수있으며, ARP TO 가발생한상대방에게는 Data를전송할수가없다. Broadcast 통신은 IP address로한번의 Data 전송을통하여 A, B, C 모두 Copyright 2008 WIZnet Co., Inc. All rights reserved. 98

99 에게동시에 Data를전달한다. 이때 A, B, C에대한 Destination hardware address를획득할필요가없으며, ARP TO 역시발생하지않는다. SOCKET Initialization UDP data communication을위해 SOCKET initialization 과정이필요하다. 이는 SOCKET을 open하는일이다. SOCKET open 과정은 W5300의 8개의 SOCKET 중하나를선택하고, 선택된 SOCKET의 Protocol mode(sn_mr(p3:p0)) 와상대방과의통신에사용할 Source port number인 Sn_PORTR을설정한후, OPEN command를수행한다. OPEN command 이후 Sn_SSR이 SOCK_UDP으로변경되면 SOCKET initialization 과정은완료된다. { START: Sn_MR = 0x02; /* sets UDP mode */ Sn_PORTR = source_port; /* sets source port number */ Sn_CR = OPEN; /* sets OPEN command */ /* wait until Sn_SSR is changed to SOCK_UDP */ if (Sn_SSR!= SOCK_UDP) Sn_CR = CLOSE; goto START; } Received DATA? 상대방으로부터의 UDP data 수신을확인한다. TCP 통신과동일한방법으로확인이가능하다. 물론 TCP와같은이유로 Second method를권장한다 TCP SERVER 의해당절을참조하라. First method : { if (Sn_IR(RECV) == 1 ) Sn_IR(RECV) = 1 ; goto Receiving Process stage; /* In this case, if the interrupt of SOCKETn is activated, interrupt occurs. Refer to IR, IMR Sn_IMR and Sn_IR. */ } Second Method : { if (Sn_RX_RSR!= 0x ) goto Receiving Process stage; } Receiving Process Internal RX memory 에수신된 UDP Data 를처리한다. 수신된 UDP data 의구조는아래와 같다. Copyright 2008 WIZnet Co., Inc. All rights reserved. 99

100 { Fig 14. The received UDP data format 수신된 UDP data는 8bytes의 PACKET-INFO와 DATA packet으로이루어지며, PACKET-INFO 는송신자의정보 (IP address, Port number) 와 DATA packet의길이가포함된다. UDP는많은송신자로부터 UDP data를수신할수가있다. 송신자의구분은 PACKET-INFO의송신자정보를통해확인할수있다. 송신자가 IP address를이용하여 broadcast한경우도수신된다. Host는 PACKET-INFO의송신자정보를분석하여필요없는수신 DATA packet은무시해야한다. 송신자의 Data 크기가 SOCKETn의 Internal RX memory free size보다클경우그 Data는수신할수없으며, 또한 Fragment된 Data 역시수신할없다. /* process PACKET-INFO read from internal RX memory */ temp = Sn_RX_FIFOR; /* extract destination IP address from internal RX memory */ dest_ip[0] = ((temp & 0xFF00) >> 8); dest_ip[1] = (temp & 0x00FF); temp = Sn_RX_FIFOR; dest_ip[2] = ((temp & 0xFF00) >> 8); dest_ip[3] = (temp & 0x00FF); dest_port = Sn_RX_FIFOR; /* extract destination port number from internal RX memory */ pack_size = Sn_RX_FIFOR; /* extract length of DAT packet from internal RX memory */ /* calculate the read count of Sn_RX_FIFOR */ if (pack_size is odd?) read_cnt = (pack_size + 1) / 2; read_cnt = pack_size / 2; for ( i = 0 ; i < read_cnt ; i++ ) { data_buf[i] = Sn_RX_FIFOR; /* data_buf is array of 16bit */ } } /* set RECV command */ Sn_CR = RECV; Copyright 2008 WIZnet Co., Inc. All rights reserved. 100

101 Send Data? / Sending Process 상대방의 IP address와 Port number를설정하고전송할 Data를 Sn_TX_FIFOR을통해 Internal TX memory에저장한후상대방에게전송을시도한다. 전송할 Data크기는할당된 SOCKETn의 Internal TX memory보다클수없으며, 전송할 Data 크기가 MTU보다클경우 MTU 단위로자동으로나누어져전송된다. Broadcast할경우 Sn_DIPR을 로설정한다. { /* first, get the free TX memory size */ FREESIZE: get_free_size = Sn_TX_FSR; if (get_free_size < send_size) goto FREESIZE; /* Set the destination information */ Sn_DIPR0 = dest_ip[0]; //or 255; /* Set the 4 bytes destination IP address to Sn_DIPR */ Sn_DIPR1 = dest_ip[1]; //or 255; Sn_DIPR2 = dest_ip[2]; //or 255; Sn_DIPR3 = dest_ip[3]; //or 255; Sn_DPORTR = dest_port; /* Set the 2 bytes destination port number to Sn_DPORTR */ /* calculate the write count of Sn_TX_FIFOR */ if (send_size is odd?) write_cnt = (send_size + 1) / 2; else write_cnt = send_size / 2; /* copy data to internal TX memory */ for (i = 0; i < write_cnt; i++) { Sn_TX_FIFOR = data_buf[i]; /* data_buf is array of 16bit */ } /* sets transmission data size to Sn_TX_WRSR */ Sn_TX_WRSR = send_size; } /* set SEND command */ Sn_CR = SEND; Copyright 2008 WIZnet Co., Inc. All rights reserved. 101

102 { } { } Complete Sending? & Timeout 다음 Data를전송하기위해선반드시이전 SEND command가완료되었는지확인해야한다. Data의크기가클수록 SEND command 완료시간도길어지므로, 전송 Data를적정한크기로나누어전송하는것이유리하다. UDP data 전송시 ARP TO 가발생할수있고, ARP TO 가발생할경우 UDP data 전송은실패한다. /* check SEND command completion */ while(sn_ir(sendok)== 0 ) /* wait interrupt of SEND completion */ { /* check ARP TO */ if (Sn_IR(TIMEOUT)== 1 ) Sn_IR(TIMEOUT)= 1 ; goto Next stage; } Sn_IR(SENDOK) = 1 ; /* clear previous interrupt of SEND completion */ Finished? / Socket Close 더이상통신이필요없을경우 SOCKETn을 close한다. /* clear remained interrupts */ Sn_IR = 0x00FF; IR(n) = 1 ; /* set CLOSE command */ Sn_CR = CLOSE; Multicast Broadcast 통신이불특정다수와통신하는반면, Multicast 통신은특정 Multicast-group에등록된다수와통신을한다. A, B, C가특정 Multicast-group에등록되어있고, A가등록된 Mutlicast-group으로 Data를전송할경우 B, C 역시 A의전송 Data를수신할수있다. Multicast 통신을하기위해선 IGMP protocol을이용하여 Multicast-group에등록하여야한다. Multicast-group은 Group hardware address, Group IP address, Group port number로구분된다. Group hardware address와 IP address는이미지정되어있는 Address를사용하고, Group port number는임의로사용할수있다. Group hardware address는지정범위 ( 01:00:5e:00:00:00 에서부터 01:00:5e:7f:ff:ff ) 내에서선택되며, Group IP address는 D-class IP address 범위 ( 에서 까지, ) 내에서선택된다. 이때 Copyright 2008 WIZnet Co., Inc. All rights reserved. 102

103 6bytes의 Group hardware address와 4bytes의 IP address의하위 23bit는같도록선택해야한다. 예로, Group IP address를 로선택할경우 Group hardware address는 01:00:5e:01:01:0b 로선택된다. RFC1112 참조 ( W5300에서는 Multicast-group 등록에필요한 IGMP 처리는내부적으로 (Automatically) 이루어진다. SOCKETn을 Multicast mode로 Open할경우 IGMP의 Join message, Close할경우 Leave message가내부적으로전송된다. SOCKET open 이후통신시주기적으로 Report message가내부적으로전송된다. W5300은 IGMP version 1과 version 2만을지원하며상위 version을사용하고자한다면, IPRAW mode SOCKET을이용하여 Host가직접 IGMP를처리해야한다. SOCKET Initialization Multicast 통신을위해 8개의 SOCKET 중하나를선택하고, Sn_DHAR을 Multicast-group hardware address로 Sn_DIPR을 Multicast-group IP address로설정한다. Sn_PORTR과 Sn_DPORTR을 Multicast-group port number로설정한다. Sn_MR(P3:P0) 를 UDP로 Sn_MR (MULTI) 를 1 로설정한후 OPEN command를수행한다. OPEN command 이후 Sn_SSR이 SOCK_UDP으로변경되면 SOCKET initialization 과정은완료된다. { START: /* set Multicast-Group information */ Sn_DHAR0 = 0x01; /* set Multicast-Group H/W address(01:00:5e:01:01:0b) */ Sn_DHAR1 = 0x00; Sn_DHAR2 = 0x5E; Sn_DHAR3 = 0x01; Sn_DHAR4 = 0x01; Sn_DHAR5 = 0x0B; Sn_DIPR0 = 211; /* set Multicast-Group IP address( ) */ Sn_DIPR1 = 1; Sn_DIPR2 = 1; Sn_DIRP3 = 11; Sn_DPORTR = 0x0BB8; /* set Multicast-Group Port number(3000) */ Sn_PORTR = 0x0BB8; /* set Source Port number(3000) */ Sn_MR = 0x0002 0x0080; /* set UDP mode & Multicast on SOCKETn Mode Register */ Sn_CR = OPEN; /* set OPEN command */ Copyright 2008 WIZnet Co., Inc. All rights reserved. 103

104 /* wait until Sn_SSR is changed to SOCK_UDP */ if (Sn_SSR!= SOCK_UDP) Sn_CR = CLOSE; goto START; } Received DATA? Receiving Process Unicast & Broadcast 참조. Send Data? / Sending Process SOCKET initialization에서이미 Multicast-group에대한정보를설정하였으므로, Unicast 통신처럼상대방의 IP address와 Port number를설정할필요가없다. 따라서전송할 Data를 internal TX memory로 copy한후 SEND command를수행한다. { /* first, get the free TX memory size */ FREESIZE: get_free_size = Sn_TX_FSR; if (get_free_size < send_size) goto FREESIZE; /* calculate the write count of Sn_TX_FIFOR */ if (send_size is odd?) write_cnt = (send_size + 1) / 2; else write_cnt = send_size / 2; /* copy data to internal TX memory */ for (i = 0; i < write_cnt; i++) { Sn_TX_FIFOR = data_buf[i]; /* data_buf is array of 16bit */ } /* sets transmission data size to Sn_TX_WRSR */ Sn_TX_WRSR = send_size; } /* set SEND command */ Sn_CR = SEND; Complete Sending? & Timeout 이미설정된 Multicast-group 과의통신이므로, ARP-process 가필요없고 ARP TO 는발생하 Copyright 2008 WIZnet Co., Inc. All rights reserved. 104

105 지않지않는다. { /* check SEND command completion */ while(sn_ir(sendok)== 0 ); /* wait interrupt of SEND completion */ Sn_IR(SENDOK) = 1 ; /* clear previous interrupt of SEND completion */ } Finished? / Socket Close Unicast & Broadcast 참조 IPRAW IPRAW는 TCP와 UDP의하위 protocol 계층인 IP layer를이용한 Data 통신이다. IPRAW는 protocol number에따라 ICMP(0x01), IGMP(0x02) 와같은 IP layer의 protocol을지원한다. ICMP의 ping이나 IGMP v1/v2는 W5300에서 Hardware logic으로이미구현되어있다. 하지만필요에따라 Host는 SOCKETn을 IPRAW mode로 open하여이를직접구현하여처리할수있다. IPRAW mode SOCKET을사용할경우, 어떤 protocol을사용할지반드시 IP header의 protocol number field를설정하여야한다. Protocol number는 IANA에의해이미정의되어있다. 참조. Protocol number는 SOCKET Open 이전에 Sn_PROTOR에반드시설정한다. W5300은 IPRAW mode에서 TCP(0x06) 나 UDP(0x11) protocol number는지원하지않는다. IPRAW mode SOCKET의통신은지정된 protocol number만의통신을허용한다. ICMP로설정된 SOCKET은 IGMP와같이설정되지않은그외의 Protocol Data를수신할수없다. Fig 15. IPRAW Operation Flow Copyright 2008 WIZnet Co., Inc. All rights reserved. 105

106 SOCKET Initialization SOCKET을선택하고 Protocol number를설정한다. Sn_MR(P3:P0) 를 IPRAW mode로설정하고 OPEN command를수행한다. OPEN command 이후 Sn_SSR이 SOCK_IPRAW로변경되면 SOCKET initialization 과정은완료된다. { START: /* sets Protocol number */ /* The protocol number is used in Protocol Field of IP Header. */ Sn_PROTOR = protocol_num; /* sets IP raw mode */ Sn_MR = 0x03; /* sets OPEN command */ Sn_CR = OPEN; /* wait until Sn_SSR is changed to SOCK_IPRAW */ if (Sn_SSR!= SOCK_IPRAW) Sn_CR = CLOSE; goto START; } Received DATA? Unicast & Broadcast 참조. Receiving Process Internal RX Memory 에수신된 IPRAW Data 를처리한다. 수신된 IPRAW Data 의구조는아 래와같다. Fig 16. The received IPRAW data format IPRAW Data는 6 bytes의 PACKET-INFO와 DATA packet으로이루어지며, PACKET-INFO는송신자의정보 (IP address) 와 DATA packet의길이가포함된다. IPRAW mode의 Data 수신은 UDP의 PACKET-INFO에서송신자의 Port number 처리를제외하고는 UDP data 수신과모두동일하다 Unicast & Broadcast 참조. 송신자의 Data 크기가 SOCKETn의 RX memory free size보다클경우그 Data는수신할수없으며, 또한 Fragmented data 역시수신할없다. Send DATA? / Sending Process Copyright 2008 WIZnet Co., Inc. All rights reserved. 106

107 전송할 Data 크기는할당된 SOCKETn의 Internal TX memory보다클수없고, Default MTU보다클수없다. IPRAW data 전송은 UDP data 전송에서 Destination port number를설정하는것을제외하고모두동일하다 Unicast & Broadcast 참조. Complete Sending & Timeout Finished? / Socket Closed UDP 통신과동일하다 UDP 참조 MACRAW MACRAW 통신은 Ethernet MAC을기반으로그상위 Protocol을 Host가목적에맞게유연하게사용할수있도록하는통신방법이다. MACRAW mode는오직 SOCKET0만사용가능하다. SOCKET0을 MACRAW로사용할경우 SOCKET1에서 7까지는 Hardwired TCP/IP stack을그대로사용할뿐만아니라, SOCKET0을마치 NIC(Network Interface Controller) 처럼사용할수있어 Software TCP/IP stack을구현할수있다. 이와같이 W5300은 Hardwired TCP/IP와 Software TCP/IP를모두구현할수있는 Hybrid TCP/IP stack을지원한다. W5300이지원하는 8개의 SOCKET보다더많은 SOCKET들이요구될경우, 높은성능을요구하는 SOCKET들은 Hardwired TCP/IP Stack으로구현하고, 그외는 MACRAW mode를이용하여 Software TCP/IP로구현하여 SOCKET 수의한계를극복할수있다. MACRAW mode의 SOCKET0은 SOCKET1에서 7까지사용되고있는 protocol들을제외한모든 protocol를처리할수있다. MACRAW 통신은아무런처리없이순수 Ethernet packet만의통신이므로 MACRAW 설계자는이러한 protocol을분석하고처리할있는 Software TCP/IP stack를직접구현해야한다. MACRAW data는 Ethernet MAC을기반으로하기때문에 6bytes의 Source hardware address, 6bytes의 destination hardware address, 2 bytes의 Ethernet type 총 14bytes을기본적으로포함해야한다. Fig 17. MACRAW Operation Flow Copyright 2008 WIZnet Co., Inc. All rights reserved. 107

108 SOCKET Initialization SOCKET을선택하고 Sn_MR(P3:P0) 를 MACRAW mode로설정한후 OPEN command를수행한다. OPEN command 이후 Sn_SSR이 SOCK_MACRAW로변경되면 SOCKET initialization 과정은완료된다. 이때통신에필요한모든정보 (Source hardware address, Source IP address, Source port number, Destination hardware address, Destination IP address, Destination port number, 각종 Protocol header, ETC) 는 MACRAW Data의일부분이므로이와관련된 Register 설정은필요없다. { START: /* sets MAC raw mode */ S0_MR = 0x04; /* sets OPEN command */ S0_CR = OPEN; /* wait until Sn_SSR is changed to SOCK_MACRAW */ if (Sn_SSR!= SOCK_MACRAW) S0_CR = CLOSE; goto START; } Received DATA? Unicast & Broadcast 참조. Receiving Process SOCKET0 의 Internal RX Memory 에수신된 MACRAW Data 를처리한다. MACRAW Data 의구 조는아래와같다. Fig 18. The received MACRAW data format MACRAW data는 2 bytes의 PACKET-INFO, DATA packet, 4bytes의 CRC로이루어진다. PACKET-INFO는 DATA packet의길이이며, DATA packet은 6bytes destination MAC address, 6bytes source MAC address, 2bytes type, 46~1500 bytes payload로이루어진다. DATA packet의 Payload는 Type에따라 ARP, IP와같은 Internet protocol로이루어진다. Type에관한정보는 MACRAW data의 CRC는반드시 S0_RX_FIFOR을통해 Host-Read한후무시해야한다. Copyright 2008 WIZnet Co., Inc. All rights reserved. 108

109 { } /* extract size of DATA packet from internal RX memory */ pack_size = S0_RX_FIFOR; /* calculate the read count of Sn_RX_FIFOR */ if (pack_size is odd?) read_cnt = (pack_size + 1) / 2; read_cnt = pack_size / 2; /* extract DATA packet from internal RX memory */ for( i = 0; i < read_cnt; i++) { data_buf[i] = S0_RX_FIFOR; /* data_buf is array of 16bit */ } /* extract 4 bytes CRC from internal RX memory and then ignore it */ dummy = S0_RX_FIFOR; dummy = S0_RX_FIFOR; /* set RECV command */ S0_CR = RECV; <Notice> Internal RX memory의 Free size가 W5300이수신해야할 MACRAW data의크기보다작을경우, 실제수신되어선안될그 MACRAW data의 PACKET-INFO와 DATA packet의일부가 Internal RX memory에저장되는문제가간혹발생할수있다. 이는상기 Sample code에서 PACKET-INFO 분석의오류를야기시켜올바른 MACRAW data 수신처리를할수없게된다. 이문제는 Internal RX memory가 Full에가까울수록발생할확률이높아진다. 이문제는 MACRAW data의소실을어느정도감안한다면해결될수있다. 해결방법은, Internal RX memory의처리를최대한빨리하여 Full에도달하는것을방지한다. 자신에해당하는 MACRAW data만을수신하도록하여수신부하를줄인다. SOCKET Initialization 과정의 Sample code에서 S0_MR의 MF bit를설정한다. { START: /* sets MAC raw mode with enabling MAC filter */ S0_MR = 0x44; /* sets OPEN command */ S0_CR = OPEN; Copyright 2008 WIZnet Co., Inc. All rights reserved. 109

110 /* wait until Sn_SSR is changed to SOCK_MACRAW */ if (Sn_SSR!= SOCK_MACRAW) S0_CR = CLOSE; goto START; } Internal RX memory의 Free size가 Default MTU(1514)+PACKET-INFO(2) + DATA packet(8) + CRC(2) - 보다작을경우 SOCKET0을 Close한후지금까지수신한모든 MACRAW data를처리하고다시 SOCKET0을 Open하여정상처리한다. 이때 SOCKET0 Close이후수신되는 MACRAW data는소실될수있다. { /* check the free size of internal RX memory */ if((tmsr0 * 1024) - Sn_RX_RSR < 1526) { recved_size = Sn_RX_RSR; /* backup Sn_RX_RSR */ Sn_CR = CLOSE; /* SOCKET0 Closed */ while(sn_ssr!= SOCK_CLOSED); /* wait until SOCKET0 is closed */ /* process all data remained in internal RX memory */ while(recved_size > 0) { /* extract size of DATA packet from internal RX memory */ pack_size = S0_RX_FIFOR; /* calculate the read count of Sn_RX_FIFOR */ if (pack_size is odd?) read_cnt = (pack_size + 1) / 2; read_cnt = pack_size / 2; /* extract DATA packet from internal RX memory */ for( i = 0; i < read_cnt; i++) { data_buf[i] = S0_RX_FIFOR; /* data_buf is array of 16bit */ } /* extract 4 bytes CRC from internal RX memory and then ignore it */ dummy = S0_RX_FIFOR; dummy = S0_RX_FIFOR; /* calculate the size of remained data in internal RX memory*/ recved_size = recved_size 2 pack_size 4; } /* Reopen the SOCKET0 */ /* sets MAC raw mode with enabling MAC filter */ S0_MR = 0x44; /* or S0_MR = 0x04 */ /* sets OPEN command */ Copyright 2008 WIZnet Co., Inc. All rights reserved. 110

111 S0_CR = OPEN; /* wait until Sn_SSR is changed to SOCK_MACRAW */ while (Sn_SSR!= SOCK_MACRAW); } else /* process normally the DATA packet from internal RX memory */ { /* This block is same as the code of Receiving process stage*/ } } Send DATA? / Sending Process 전송할 Data 크기는할당된 SOCKET0의 Internal TX memory보다클수없고, 또한 Default MTU보다클수없다. Host는 Receiving process 절의 DATA packet 형식과동일한 MACRAW data를생성하고그 Data를전송한다. 이때생성된 Data의크기가 60 bytes 미만일경우실제 Ethernet으로전송되는 Packet은내부적으로 60bytes가되도록 Zero padding 되어전송된다. { /* first, get the free TX memory size */ FREESIZE: get_free_size = S0_TX_FSR; if (get_free_size < send_size) goto FREESIZE; /* calculate the write count of Sn_TX_FIFOR */ if (send_size is odd?) write_cnt = (send_size + 1) / 2; else write_cnt = send_size / 2; /* copy data to internal TX memory */ for (i = 0; i < write_cnt; i++) { S0_TX_FIFOR = data_buf[i]; /* data_buf is array of 16bit */ } /* sets transmission data size to Sn_TX_WRSR */ S0_TX_WRSR = send_size; /* set SEND command */ S0_CR = SEND; Copyright 2008 WIZnet Co., Inc. All rights reserved. 111

112 } { } Complete Sending? Data 통신에필요한모든 Protocol 처리는 Host가관장하므로 Timeout은발생하지않지않는다. /* check SEND command completion */ while(s0_ir(sendok)== 0 ); /* wait interrupt of SEND completion */ S0_IR(SENDOK) = 1 ; /* clear previous interrupt of SEND completion */ Finished? / Socket Close Unicast & Broadcast 참조. Copyright 2008 WIZnet Co., Inc. All rights reserved. 112

113 6. External Interface W5300의 Host interface는 Direct/Indirect address mode와 16/8 bit data bus width에따라결정된다. 또한 PIN TEST_MODE[3:0] 설정에따라 W5300은 Internal PHY 혹은 External PHY 와 Interface 된다. 6.1 Direct Address Mode Bit Data Bus Width 16bit data bus width를사용할경우, ADDR[9:1] 만사용되며, ADDR0은 Float나 Ground 처리한다. BIT16EN 은내부적으로 Pull-up 처리되어있어 Float 시켜도무방하다 Bit Data Bus Width 8bit data bus width 를사용할경우, ADDR[9:0] 모두사용되며, BIT16EN 은반드시 Logical LOW(Ground) 처리한다. 사용하지않는 DATA[15:8] 은모두 Float 시킨다. Copyright 2008 WIZnet Co., Inc. All rights reserved. 113

114 6.2 Indirect Address Mode Bit Data Bus Width 16bit data bus width를사용할경우, ADDR[2:1] 만사용되며, ADDR[9:3] 과 ADDR0은 Float나 Ground 처리한다. BIT16EN 은내부적으로 Pull-up 처리되어있어 Float 시켜도무방하다 Bit Data Bus Width 8bit data bus width 를사용할경우, ADDR[2:0] 만사용되며, ADDR[9:3] 은 Float 나 Ground 처리 한다. BIT16EN 은반드시 Ground 처리한다. 사용하지않는 DATA[15:8] 은모두 Float 시킨다. Copyright 2008 WIZnet Co., Inc. All rights reserved. 114

115 6.3 Internal PHY Mode W5300의 Internal PHY를사용하는 Mode로 TEST_MODE[3:0] 은 Float 시키거나, Ground 처리한다. OP_MODE[2:0] 은 Internal PHY의동작을설정하는 PIN으로, 각 PIN의 Logical value에따라 Internal PHY의동작 Mode가결정된다. 1.1 Configuration Signals 참조. Internal PHY와 Transformer간의 Interface에서보다좋은 Impedance matching을위한 Termination resistor와 Capacitor가필요하다. Resister는 50ohm( 오차1%), Capacitor는 0.1uF 을사용한다. Internal PHY는 LINK, SPEED와같은 6가지의 Network indicator LED를지원한다. 사용하지않는 Network indicator LED는 float 시킨다. /RXLED와 /TXLED를 Logical AND로묶어사용하면 ACT LED(Active LED) 를구현할수있다. 1.6 Network Indicator LED Signals 참조. Fig 19. Internal PHY & LED Signals Copyright 2008 WIZnet Co., Inc. All rights reserved. 115

116 6.4 External PHY Mode W5300의 Internal PHY 특성이맞지않을경우 External PHY를사용할수있다. External PHY 를사용할경우, W5300의 Clock source를결정해주어야한다. TEST_MODE0이 Logical HIGH일경우 Crystal을, TEST_MODE1이 Logical HIGH일경우 Oscillator를사용한다. 1.1 Configuration Signals 와 1.7 Clock Signals 를참조하라. External PHY와 Transformer간의 Impedance matching 회로는각제조사의문서를참조하라. W5300의 /FDX Pin은 External PHY의 Duplex indicator signal과연결할수있다. Fig 20. External PHY Interface with MII Copyright 2008 WIZnet Co., Inc. All rights reserved. 116

117 7. Electrical Specifications Absolute Maximum Ratings Symbol Parameter Rating Unit V DD DC Supply voltage -0.5 to 3.6 V V IN DC input voltage -0.5 to 5.5 (5V tolerant) V V OUT DC output voltage -0.5 to 3.6 V I IN DC input current 5 ma I OUT DC output current 2 to 8 ma T OP Operating temperature 0 to 80 C T STG Storage temperature -55 to 125 C *COMMENT: Stressing the device beyond the Absolute Maximum Ratings may cause permanent damage. DC Characteristics Symbol Parameter Test Condition Min Typ Max Unit V DD DC Supply voltage Junction V temperature is from -55 C to 125 C V IH High level input voltage V V IL Low level input voltage V V OH High level output voltage IOH = 2, 4, 8, 12, 16, V 24 ma V OL Low level output voltage IOL = -2, -4, -8, -12, V 16, -24 ma I I Input Current V IN = V DD 5 A I O Output Current V OUT = V DD 2 8 ma POWER DISSIPATION Symbol Parameter Test Condition Min Typ Max Unit P IA Power consumption when using the auto-negotiation of internal PHY mode Vcc 3.3V Temperature 25 C ma Copyright 2008 WIZnet Co., Inc. All rights reserved. 117

118 P IM P E Power consumption when using manual configuration of internal PHY mode Power consumption when using external PHY mode AC Characteristics Reset Timing Vcc 3.3V Temperature 25 C Vcc 3.3V Temperature 25 C ma ma Description Min Max 1 Reset Cycle Time 2 us - 2 PLL Lock-in Time 50 us 10 ms Register READ Timing Copyright 2008 WIZnet Co., Inc. All rights reserved. 118

119 Description Min Max taddrs Address Setup Time after /CS and /RD low - 7 ns taddrh Address Hold Time after /CS or /RD high - - tcs /CS Low Time 65 ns - tcsn /CS Next Assert Time 28 ns - trd /RD Low Time 65 ns - tdatas DATA Setup Time after /RD low 42 ns - tdatah DATA Hold Time after /RD and /CS high - 7 ns tdatahe DATA Hold Extension Time after /CS high - 2XPLL_CLK <Note> tdatahe 는 MR(RDH)= 1 일때만적용되는 Data Hold Time이다. MR(RDH) = 1 은 /CS 가 High로 De-assert된후에도 2XPLL_CLK 동안 Data bus가 Driven되기때문에 Data bus collision이발생할수있다. 이는사용에있어주의를요한다. Register WRITE Timing Description Min Max taddrs Address Setup Time after /CS and /WR low - 7 ns taddrh Address Hold Time after /CS or /RD high - - tcs /CS low Time 50 ns - tcsn /CS next Assert Time 28 ns twr /WR low time 50 ns tdatas Data Setup Time after /WR low 7 ns 7ns + 7XPLL_CLK tdataf Data Fetch Time 14 ns twr-tdatas tdatah Data Hold Time after /WR high 7 ns - Copyright 2008 WIZnet Co., Inc. All rights reserved. 119

120 <Note> tdatas 는 MR(WDF2-WDF0) 의설정값에따라최대 7 PLL_CLK동안 Host-Write data 의 Fetch를지연시키는시간이다. tdataf 는 Host-Write data를 Fetch할수있는시간으로, 이시간보다먼저 /WR가 High로 De-assert될경우 tdataf 와상관없이 /WR High-De-assert시점에 Host-Write data를 Fetch한다. 이때유효한 data를 Fetch하기위해 Host는 tdatah 를보장해야한다. Crystal Characteristics Parameter Range Frequency 25 MHz Frequency Tolerance (at 25 ) ±30 ppm Shunt Capacitance 7pF Max Drive Level 1 ~ 500uW (100uW typical) Load Capacitance 27pF Aging (at 25 ) ±3ppm / year Max Transformer Characteristics Parameter Transmit End Receive End Turn Ratio 1:1 1:1 Inductance 350 uh 350 uh Internal PHY mode 에서 Auto MDI/MDIX(Crossover) 을지원하기위해서는반드시 Symmetric transformer 를사용해야한다. External PHY mode 에서는 External PHY 의 Spec 에맞는 Transformer 를선택하여사용한다. Copyright 2008 WIZnet Co., Inc. All rights reserved. 120

121 8. IR Reflow Temperature Profile (Lead-Free) Moisture Sensitivity Level : 3 Dry Pack Required : Yes Average Ramp-Up Rate 3 C/second max. (Ts max to Tp) Preheat Temperature Min (Ts min ) 150 C Temperature Max (Ts max ) 200 C Time (ts min to ts max ) seconds Time maintained above: Temperature (TL) 217 C Time (tl) seconds Peak/Classification Temperature (Tp) C Time within 5 C of actual Peak Temperature (tp) seconds Ramp-Down Rate 6 C/second max. Time 25 C to Peak Temperature 8 minutes max. Copyright 2008 WIZnet Co., Inc. All rights reserved. 121