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1 SMK-V0_USER S MNUL_REV 0.0 Preliminary User s Manual (SMK SPV0 Rev0.0) evelopment Kit for SPV0 ec 0, 00 REV 0.0

2 SMK-V0_USER S MNUL_REV 0.0 Important Notice The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. Samsung assumes no responsibility, however, for possible errors or omissions, or for any consequences resulting from the use of the information contained herein. Samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes. This publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of Samsung or others. Samsung makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation any consequential or incidental damages. "Typical" parameters can and do vary in different applications. ll operating parameters, including "Typicals" must be validated for each customer application by the customer's technical experts. Samsung products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, for other applications intended to support or sustain life, or for any other application in which the failure of the Samsung product could create a situation where personal injury or death may occur. Should the uyer purchase or use a Samsung product for any such unintended or unauthorized application, the uyer shall indemnify and hold Samsung and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, expenses, and reasonable attorney fees arising out of, either directly or indirectly, any claim of personal injury or death that may be associated with such unintended or unauthorized use, even if such claim alleges that Samsung was negligent regarding the design or manufacture of said product SPV0 RIS Microprocessor SMK SPV0 User s manual, Revision 0.0 opyright 00 Samsung Electronics o.,ltd. ll rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written consent of Samsung Electronics o.,ltd. Samsung Electronics o., Ltd. San # Nongseo-ong, Giheung-Gu Yongin-ity Gyeonggi-o, Korea - Home Page: mobilesol.cs@samsung.com Printed in the Republic of Korea

3 SMK-V0_USER S MNUL_REV 0.0 Revision History Rev. No 0.00 escription of hange Refer to uthor(s) - Initial Release (SMK SPV0 Rev0.00) P development Effective ate (MM//YY) ec, 0, 00

4 SMK-V0_USER S MNUL_REV 0.0 Table of ontents INTROUTION.... SYSTEM OVERVIEW.... SMK SPV0 FETURES... SMK SPV0 REL VIEW.... SMK SPV0 PU OR REL VIEW.... SMK SPV0 SE OR REL VIEW.... SMK SPV0 L OR REL VIEW... IRUIT ESRIPTION.... POWER ISTRIUTION TREE.... FUNTIONL LOK IGRM... SMK SPV0 SYSTEM ONFIGURTIONS.... PLL LOK SOURE SELETION...0. OOT MOE SELETION Switch onfiguration...0. ONFIGURTION SWITH ESRIPTION IN PU OR..... FG: SELETION FOR S#,#..... J: SELETION for Interrupt of Ext. OneNN..... FG: onfiguration of MM slot FG: TSI I/F..... J: PSHOL selection..... JP: JIG ON selection.... ONFIGURTION SWITH ESRIPTION IN SE OR..... FG: SROM NK0 HIP SELETOR..... FG: SROM NK HIP SELETOR..... FG: SROM NK HIP SELETOR..... FG: SROM NK HIP SELETOR..... FG: SROM NK HIP SELETOR..... FG: SROM NK HIP SELETOR..... F,MOEM,M_,KEY,MHL,SROM R SWITHING..... FG0: udio Port..... FG: udio odec(wm0) Master clock selection FG: udio evice Input/Output onnection..... FG: URT/Ir onnection.... LE & SWITH escription..... LE description..... Switch description... SMK aughter oard.... External OneNN..... Real view..... Schematic.... SI aughter oard..... Real view..... Schematic...0. SI aughter oard Real view..... Schematic... SMK SHEMTI REVISION HISTORY... SMK SHEMTI...

5 SMK-V0_USER S MNUL_REV 0.0 Figure List Figure SPV0 Functional lock iagram... Figure SPV0 PU OR TOP VIEW... Figure SPV0 PU OR OTTOM VIEW... 0 Figure SPV0 SE OR OTTOM VIEW... Figure SPV0 L OR TOP VIEW... Figure SPV0 SE OR POWER ISTRIUTION TREE... Figure SPV0 PU OR POWER ISTRIUTION TREE... Figure SPV0 SMK FUNTIONL LOK IGRM... Figure 0 External OneNN... Figure SI aughter oard... 0 Figure SI aughter oard... Figure amera module... 오류! 책갈피가정의되어있지않습니다.

6 SMK-V0_USER S MNUL_REV 0.0 INTROUTION. SYSTEM OVERVIEW SMK SPV0 ( SPV0 evelopment Kit) is a platform for code development of SMSUNG's SPV0 /-bit RIS microcontroller (RM-ORTEX ). SPV0 is used in hand-held devices and general applications. The SPV0 is a -bit RIS cost-effective, low power, high performance microprocessor solution for mobile phones and general applications, and integrates an RM ortex- which implements the RM architecture V- with supporting numerous peripherals. To provide optimized Hardware (H/W) performance for the G and.g communication services, SPV0 adopts -bit internal bus architecture and includes many powerful hardware accelerators for tasks such as motion video processing, display control and scaling. Integrated Multi Format odec (MF) supports encoding and decoding of MPEG-//, H., H. and decoding of V, ivx. This Hardware accelerators support realtime video conferencing and nalog TV out, HMI for NTS and PL mode The SPV0 has an optimized interface to external memory capable of sustaining the demanding memory bandwidths required in high-end communication services. The memory system has Flash/ ROM external memory ports for parallel access and RM port for high bandwidth. RM port can be configured to support LPR(=mobile R), R or LPR. Flash/ROM Port supports NN Flash, NOR-Flash, OneNN, SRM and ROM type external memory. To reduce total system cost and enhance overall functionality, SPV0 includes many hardware peripherals such as TFT -bit true color L controller, amera Interface, MIPI SI, SI-, System Manager for power management, T I/F, URT, -channel M, Timers, General I/O Ports, IIS, S/PIF, II-US interface, HS-SPI, US Host.0, US OTG.0 operating at high speed (0Mbps), S Host & High Speed Multi-Media ard Interface and PLLs for clock generation. Package on Package (POP) option with MP is available for small form factor applications.

7 SMK-V0_USER S MNUL_REV 0.0 System Peripheral RT PLL x Timer with PWM (ch) Watchdog Timer M (ch) Keypad (x) TS- (bit/0ch) PU ore ortex K/K I/ cache K L cache NEON Multimedia MP amera IF / MIPI SI- 00p 0fps MF odec H./H./MPEG ecoder MPEG/V-/ivx VG / Graphics engine onnectivity NTS / PL TV out & HMI udio IF IIS x / PM x K RM K ROM JPEG odec S/PIF / Storage IF HSMM/S x T onnectivity US Host.0 / OTG.0 URT x II x HS-SPI x Modem IF GPIO Multi layer H/XI us rypto Engines Power Management lock gating / Power gating / ynamic Voltage Frequency Scaling udio SP TFT L controller XG resolution Memory Interface SRM / ROM (Flex) OneNN SL / ML NN with bit E LPR / OneRM LPR / R Figure SPV0 Functional lock iagram

8 SMK-V0_USER S MNUL_REV 0.0. SMK SPV0 FETURES The SMK SPV0 (SPV0 evelopment Kit) highlights the basic system-based hardware design which uses the SPV0. It can evaluate the basic operations of the SPV0 and assist in developing codes. The features of SMK SPV0 include: - Microcontroller : SPV0 (/ bit RIS microcontroller, RM-ORTEX ) - External memory. M Mbit NOR Flash (Socket E). SMSUNG NN Flash (Socket E). SMSUNG OneNN (External oard, Optional). SMSUNG Mbit SRM E. ram port 0 : SMSUNG x Gb R SRM(x). ram port : SMSUNG x Gb R SRM(x) or SMSUNG x Gb R SRM(x) - TFT L & Touch panel interface (External oard, default:. WVG LMS0KF0) - T interface ( F card sockets) - S/SIO/MM interface ( S Sockets) - igital Video & udio : HMI. Video(0p) & S/PIF. hannel udio I/F - TV Out interface (omposite) - US Host, US OTG.0 interface - High Speed SPI interface - IIS//PM Interface : WM, WM0 udio OE on board - General amera Interface : port - MIPI amera Interface : MIPI-SI (Gbps/Lane Serial ommunication) - High Speed Serial MIPI Interface L : MIPI-SI (Gbps/Lane Serial ommunication) - Keypad interface - Ethernet Interface : M000(0/00Mbps Ethernet controller) on board - port URT interface - JTG port - Module onnector (M ~ M). M (Module): For GPS aughter oard (URT, SPI) : Samsung GP0 (SiRFSTR III GS) (Optional). M (Module): For Mobile TV aughter oard (SPI, II) or H Radio (SPI, IIS) Mobile TV: Samsung SPF (T, Optional) H Radio: SiPORT S00 (T, Optional), Samsung (T, Optional). M (Module): For luetooth aughter oard (URT, PM for PMI udio odec). M (Module): For udio aughter oard (, IIS, II)

9 SMK-V0_USER S MNUL_REV 0.0 SMK SPV0 REL VIEW. SMK SPV0 PU OR REL VIEW V/ US OTG US HOST JTG HMI MER-Port MIPI-SI FG(OM) SPV0 MIPI-SI FG(S) L I/F POWER Figure SPV0 PU OR TOP VIEW External OneNN RESET

10 SMK-V0_USER S MNUL_REV 0.0 ONNETOR To ase oard S/MM SLOT S/MM SLOT S/MM SLOT 0 Figure SPV0 PU OR OTTOM VIEW

11 SMK-V0_USER S MNUL_REV 0.0. SMK SPV0 SE OR REL VIEW UIO omposite Ir M M MOEM & MHL I/F ONNETOR For PU oard amera -Port NN M NOR ROM us onnector M Figure SPV0 SE OR TOP VIEW

12 SMK-V0_USER S MNUL_REV 0.0 URT // omposite LN S/PIF URT 0 udio OE QWERTY KEYP ompact Flash Socket Figure SPV0 SE OR OTTOM VIEW

13 SMK-V0_USER S MNUL_REV 0.0. SMK SPV0 L OR REL VIEW. 00 x 0 WVG. 0 x 00 WVG OLE Figure SPV0 L OR TOP VIEW IRUIT ESRIPTION The SMK SPV0 is designed to test SPV0 and develop software while hardware is being developed. Figure 0 highlights the SMK SPV0's block diagram.. POWER ISTRIUTION TREE SMK SPV0 is operated by.v for Internal,.V for Memory and.v for Input/Output pad and several peripherals. SMK SPV0 is supplied by V/ daptor Power. The SMK SPV0 has distributed power plane, with power going separately to the MU and the main power plane.

14 SMK-V0_USER S MNUL_REV 0.0 SE oard Power TREE (SPV0) onnector For ase oard V_SYS V_EXT V_ V_U V_MSM V_V V_V V V_V Regulator V_V PWROn_OR (.V) V_M_EXT Regulator V PWROn_OR Figure SPV0 SE OR POWER ISTRIUTION TREE

15 SMK-V0_USER S MNUL_REV 0.0 Figure SPV0 PU OR POWER ISTRIUTION TREE

16 SMK-V0_USER S MNUL_REV 0.0. FUNTIONL LOK IGRM PLL HMI RT US Figure SPV0 SMK FUNTIONL LOK IGRM

17 SMK-V0_USER S MNUL_REV 0.0 SMK SPV0 SYSTEM ONFIGURTIONS Perform the following steps to use SMK SPV0 board. - FG is on PU board and FG is on ase board. - onfiguration value meaning - X: don t care, : ON 0: OFF onfiguration Switch (IP Switch) Off(Switch Open) On (Switch Short). Select the lock source(fg) Please refer to PLL LOK SOURE SELETION. Select the oot evice(storage) and set oot Mode configuration switches (FG) Please refer to OOT MOE SELETION. Set the FG switch or Jumper for each booting device. External OneNN - heck If OneNN daughter card is connected on ON(on PU board). - Set FG[:] to X0X00. (Xm0Sn) FG S S [] [] [] [] [] [] X OFF X OFF ON OFF - Set J(on PU board) to - SHORT. J - S/MM or emm - Insert a ard to HS-MM slot0 (ON on PU board).

18 SMK-V0_USER S MNUL_REV Set FG[:] to X0. (to use SMM channel 0 of SPV0) FG escription [] OFF NN Flash - Insert a NN Flash to NN socket (U on aseboard). - Set FG[:] to 0. (Xm0Sn) FG [] [] ON OFF NOR Flash - Insert a NOR Flash to NOR socket (U on aseboard). - Set FG[:] to 0. (Xm0Sn0) FG [] [] OFF ON - Set FG[:] to 00 and FG[:] to and FG[:] to 00. ( to use SROM ddr [:]) FG [] [] OFF OFF FG [] [] ON ON

19 SMK-V0_USER S MNUL_REV 0.0 FG [] [] OFF OFF. Set FG for debugging message channel. URT ch is for default debugging message channel and booting channel.(ch in case of EVT0) - onnect to URT cable to OM(ON on ase board) - Set FG[:] to 000 FG [] [] [] [] URT OFF OFF OFF ON. heck default Jumper setting. <PU oard> - JP~0 Short - J - short - J - short - J - short - JP Open <SE oard> - JP Short - J,J Open. onnect V power adapter and push the power button.. heck the Power LE if it is operating normally. Refer to LE description section.

20 SMK-V0_USER S MNUL_REV 0.0. PLL LOK SOURE SELETION Main input clock for the SPV0 system can be selected by setting the XOM[0] values. escription MHz X-tal lock (XXTI) MHz X-tal lock (XusbXTI) FG[], (XOM[0]) OFF ON (default). OOT MOE SELETION.. Switch onfiguration escription FG[:] FG[] FG[:] FG[] FG[] FG[] FG[] FG[] ess Nand K, cycle (Nand bit E) Nand K, cycle (Nand bit E) Nand K, cycle (Nand bit E) OFF OFF OFF ON OFF ON OFF ON OnenandMux OFF OFF I-ROM ooting sequence: Storage Onenandemux S/MM OFF ON ON OFF ON emm(-bit) ON Reserved ON Nand K, cycle (Nand bit E) ON OFF OFF ON NOR boot OFF ON emm(-bit) ON I-ROM ess ON OFF OFF OFF OFF ooting sequence: Nand K, cycle ON

21 SMK-V0_USER S MNUL_REV 0.0 URT ->US ->Storage Nand K, cycle Nand K, cycle (Nand bit E) ON OFF ON OnenandMux(udi) OFF OFF Onenandemux(udi) ON ON S/MM OFF ON emm(-bit) ON Note) If FG[] is set to, It is used for debug mode that URT boot is first and US boot is second. URT boot has some kind of error case. In case of URT error, the irom boot sequence moves to US boot. US boot also has some kind of error case like URT. If US boot is fail, boot sequence move to main storage boot. Please refer to irom application note which is more detail about error case.. ONFIGURTION SWITH ESRIPTION IN PU OR.. FG: SELETION FOR S#,# FG escription S S [] [] [] [] [] [] ON External OneNand onnect to ase S# External OneNand onnect to ase S#.. J: SELETION for Interrupt of Ext. OneNN J escription - short onnect to ONXL_INT0 - short onnect to ONXL_INT(default)

22 SMK-V0_USER S MNUL_REV FG: onfiguration of MM slot 0 FG [] [] escription ON : MM port bit ata Width OFF : MM port 0 bit ata Width (default) ON : HMI I uffer isable OFF : HMI I uffer Enable.. FG: TSI I/F FG [] [] escription ON : TSI I/F uffer Enable OFF : TSI I/F uffer isable ON : TSI RX OFF : TSI TX.. J: PSHOL selection J escription - short Not using PSHOL - short Using PSHOL. PSHOL should be programmed Output-HIGH during pressing the power button,... JP: JIG ON selection JIG ON is used to turn on board without pressing power button. JP short open Turn on system power always. escription Turn on system power by pressing power button.

23 SMK-V0_USER S MNUL_REV 0.0

24 SMK-V0_USER S MNUL_REV 0.0. ONFIGURTION SWITH ESRIPTION IN SE OR.. FG: SROM NK0 HIP SELETOR FG component is used to select devices as SROM US I/F 0(_Xm0Sn0). escription FG [] [] NOR (M) Flash OFF ON SRM ON OFF.. FG: SROM NK HIP SELETOR FG component is used to select devices as SROM US I/F (_Xm0Sn). escription FG [] [] NOR (M) Flash OFF ON SRM ON OFF.. FG: SROM NK HIP SELETOR FG component is used to select devices as SROM US I/F (_Xm0Sn/NFSn0). escription FG [] [] SRM OFF ON Nand S 0 ON OFF.. FG: SROM NK HIP SELETOR FG component is used to select devices as SROM US I/F (_Xm0Sn/NFSn). escription FG [] [] SRM OFF ON

25 SMK-V0_USER S MNUL_REV 0.0 Nand S ON OFF.. FG: SROM NK HIP SELETOR FG component is used to select devices as SROM US I/F (_Xm0Sn/NFSn). escription FG [] [] [] [] SRM OFF OFF OFF ON NN S OFF OFF ON OFF External Rom us onnector OFF ON OFF OFF Ethernet ON OFF OFF OFF.. FG: SROM NK HIP SELETOR FG component is used to select devices as SROM US I/F (_Xm0Sn/NFSn). escription FG [] [] [] [] SRM OFF OFF OFF ON NN S OFF OFF ON OFF External Rom us onnector OFF ON OFF OFF Ethernet ON OFF OFF OFF.. F,MOEM,M_,KEY,MHL,SROM R SWITHING FG,, component is used to switching Xmsm signals which are muxed following signals. (F ard I/F, Modem I/F, amera I/F, Keypad I/F, MHL I/F, SROM ddr[:] ) escription FG FG FG

26 SMK-V0_USER S MNUL_REV 0.0 [] [] [] [] [] [] F ard OFF OFF ON ON ON/OFF OFF SROM ddr [:] OFF OFF ON ON ON/OFF OFF MHL I/F OFF ON ON OFF ON/OFF OFF MOEM I/F OFF OFF ON OFF ON/OFF OFF amera port ON OFF OFF OFF ON/OFF OFF Keypad muxed with Xmsm signals OFF OFF ON ON ON ON Keypad muxed with XEINT signals ON OFF.. FG0: udio Port FG0 component is used to select devices as udio I/F,. escription udio udio [] [] OFF SPIF Out (WM) ON IIS/PM(WM0) IIS/PM(WM0).. FG: udio odec(wm0) Master clock selection FG Mater lock source [] IS0 LK [] IS, LK [] External LK [] External Voice LK [] External HMI udio LK [] P LKOUT

27 SMK-V0_USER S MNUL_REV FG: udio evice Input/Output onnection FG [] : Speaker [] : MI [] : Line In escription OFF: IIS (WM0) ON: (WM) [] : WM0 OFF: Line In ON: MI.. FG: URT/Ir onnection FG component is used to select OM(ON) Port connection. FG [] [] [] [] URT OFF X X X URT ON OFF X X URT ON ON OFF X Ir X X ON X. LE & SWITH escription.. LE description <PU oard>. LE: V Power(adapter) Status. LE: System power(from PMI) Status

28 SMK-V0_USER S MNUL_REV 0.0. LE: ard Insertion status of MM slot 0. LE: ard Insertion status of MM slot. LE: ard Insertion status of MM slot <ase oard>. LE: F card Power status. LE,,: Ethernet status. LE: For debugging (GPH_). LE: For debugging (GPH_) 0. LE: For debugging (GPH_). LE: For debugging (GPH_). LE0: V Power(adapter) Status.. Switch description <PU oard>. SW : Warm reset switch. SW: System reset switch. SW: Power On switch <ase oard>. SW : For EINT test (XEINT). SW : For EINT test (XEINT)

29 SMK-V0_USER S MNUL_REV 0.0 SMK aughter oard Each aughter board can be connected on SMK connector.. External OneNN External OneNN can be mounted on ON... Real view Figure 0 External OneNN.. Schematic EXTERNL_ONE NN.pdf. SI aughter oard SI aughter oard can be mounted on ON... Real view

30 SMK-V0_USER S MNUL_REV 0.0 Figure SI aughter oard.. Schematic SI_daughter_O R.pdf. SI aughter oard SI aughter oard can be mounted on ON.

31 SMK-V0_USER S MNUL_REV Real view Figure SI aughter oard.. Schematic MIPI-LM&LN SHEMTI_R

32 SMK-V0_USER S MNUL_REV 0.0 SMK SHEMTI REVISION HISTORY This document contains information of corrected points on the schematic of SMK SPV0. oards Page ontents orrected points (EN) PU oard ase oard L oard SMK SHEMTI There are parts of SMK Schematic.. PU & ase oard Rev0.. L oard Rev0. SMKV0_PU_ REV0_.pdf SMKV0_SE SH_REV0.p SPV0_SMK_L _SHEMTI_V

33 SMK_SPV0_PU 'd (SPV0 Evaluation oard) Schematics Revision ate escription Rev Preliminary Version Table of ontents Part Reference Page Function Revision History 0 SPV0 (SYS&onnectivity)/ oot Option 0 SPV0 (MP & SROM Memory) 0 SPV0 (Media) 0 SPV0 (Gen_Power) 0 XM R(Gbit *) #0, 0 XM R(Gbit *) #, 0 XM R(Gbit *) #0, 0 XM R(Gbit *) #, 0 Power Jumper shunt Power ( jack & Regulator) Reset/ lock Source/ JTG Power (PMI) Memory (SROM EI IF) OneNN / L I/F(NonMIPI) MM #0 MM #/#/ HS-SPI amera -Port I/F HMI/ MIPI-SI/ MIPI-HSI/ US 0 MIPI-SI onnector(pu) <omponent><number> U : omponent or Regurator I : apacitor : apacitor ypass T : apacitor Tantal T : apacitor Tantal ypass J : Jumper J : PU To ase connector JP : Jumper Power R : Resistor R : Resistor rray RP : Resistor Power VR : Variable Resistor L : Inductor F : Ferrite ead OS : Oscillator X : X-tal (rystal) Q : Transistor or FET : iode Z : Zener iode LE : LE iode SW : SWitch Tact/Push ON : ONnector FG : onfigure switch (IP/Slide) TP : Test Point (SM) TPH : Test Point Hole (Through Hole) MTH: Mount Through Hole MO : MOule Interface connector SMSUNG ELETRONIS O.,LT SMK_SPV0_PU oard (Evaluation oard) Size ocument Number Rev Revision History 0.0 ate: Monday, October, 00 Sheet of

34 [] [] [] [] [] [] [] [] XuRX0 XuTX0 XuTSn0 XuRTSn0 XuRX XuTX XuTSn XuRTSn [,] XuRX/URT_UIO_RX [,] XuTX/URT_UIO_TX [] XuRX/TSn/URT_UIO_TSn [] XuTX/RTSn/URT_UIO_RTSn [] [] [] [] [] [] [] [] XspiLK0 XspiSn0 XspiMISO0 XspiMOSI0 XspiLK XspiSn XspiMISO XspiMOSI [] XuhP [] XuhN [] XuhREXT [] XuhPWREN [] XuhOVERUR [] XuoP [] XuoM [] XuoREXT [] XuoI [] XuoVUS [] XuoRVVUS [] XisSLK0/PM_SLK [] XisLK0/PM_EXTLK [] XisLRK0/PM_FSYN [] XisSI0/PM_SIN [] XisSO0_0/PM_SOUT [] XisSO0_ [] XisSO0_ [] XisSLK/PM_SLK/_ITLK [] XisLK/PM_EXTLK/_RESETn [] XisLRK/PM_FSYN/_SYN [] XisSI/PM_SIN/_SI [] XisSO/PM_SOUT/_SO [] XpcmSLK0/SPIF_OUT0/XisSLK [] XpcmEXTLK0/SPIF_EXTLK/XisLK [] XpcmFSYN0/L_FRM/XisLRK [] XpcmSIN0/XisSI [] XpcmSOUT0/XisSO [] Xmmc0LK [] Xmmc0M [] Xmmc0n [] Xmmc0T0 [] Xmmc0T [] Xmmc0T [] Xmmc0T [] XmmcLK [] XmmcM [] Xmmcn [] XmmcT0/MM0_T [] XmmcT/MM0_T [] XmmcT/MM0_T [] XmmcT/MM0_T [] XmmcLK/SPI LK [] XmmcM/SPI nss [] Xmmcn/SPI MISO [] XmmcT0/SPI MOSI [] XmmcT [] XmmcT [] XmmcT [] XmmcLK [] XmmcM [] Xmmcn [] XmmcT0/MM_T [] XmmcT/MM_T [] XmmcT/MM_T [] XmmcT/MM_T XuRX0/GP0_0 XuTX0/GP0_ XuTSn0/GP0_ XuRTSn0/GP0_ G0 XuRX/GP0_ F0 XuTX/GP0_ XuTSn/GP0_ E0 XuRTSn/GP0_ (V_EXT0) (V_EXT0) URT/Ir 0 XuRX/URT_UIO_RX/GP_0 XuTX/URT_UIO_TX/GP_ (V_EXT) XuRX/TSn/URT_UIO_TSn/GP_ (V_SYS0) XuTX/RTSn/URT_UIO_RTSn/GP_ SYSTEM XspiLK0/GP0 E XspiSn0/GP J XspiMISO0/GP J XspiMOSI0/GP G XspiLK/GP XspiSn/GP G XspiMISO/GP XspiMOSI/GP E XuhP XuhM XuhREXT XuhPWREN XuhOVERUR HS-SPI (V_EXT) US HOST.0 U (V_UHOST_) SPV0 (V_SYS0) XuoP E XuoM E XuoREXT US OTG.0 XuoI (V_UOTG_) XuoVUS XuoRWUS (V_SYS0) XisSLK0/PM_SLK XisLK0/PM_EXTLK E XisLRK0/PM_FSYN E XisSI0/PM_SIN XisSO0_0/PM_SOUT XisSO0_ XisSO0_ Xmmc0LK/GPG0_0 E Xmmc0M/GPG0_ F Xmmc0n/GPG0_ Xmmc0T0/GPG0_ Xmmc0T/GPG0_ Xmmc0T/GPG0_ Xmmc0T/GPG0_ XmmcLK/GPG_0 F XmmcM/GPG_ Xmmcn/GPG_ XmmcT0/Xmmc0T/GPG_ E XmmcT/Xmmc0T/GPG_ XmmcT/Xmmc0T/GPG_ F XmmcT/Xmmc0T/GPG_ IS/PM/ (V_U) XisSLK/PM_SLK/ITLK/GP0_0 XisLK/PM_EXTLK/RESETn/GP0_ XisLRK/PM_FSYN/SYN/GP0_ XisSI/PM_SIN/SI/GP0_ XisSO/PM_SOUT/SO/GP0_ XpcmSLK0/SPIF_OUT0/XisSLK/GP_0 XpcmEXTLK0/SPIF_EXTLK/XisLK/GP_ XpcmFSYN0/L_FRM/XisLRK/GP_ XpcmSIN0/XisSI/GP_ XpcmSOUT0/XisSO/GP_ HS-MM (V_EXT0) Y XmmcLK/SPI_LK/GPG_0 W XmmcM/SPI_Sn/GPG_ Xmmcn/SPI_MISO/GPG_ Y XmmcT0/SPI_MOSI/GPG_ (V_EXT) Y XmmcT/GPG_ Y XmmcT/GPG_ W XmmcT/GPG_ XmmcLK/GPG_0 0 XmmcM/GPG_ E Xmmcn/GPG_ 0 XmmcT0/XmmcT/GPG_ 0 XmmcT/XmmcT/GPG_ XmmcT/XmmcT/GPG_ 0 XmmcT/XmmcT/GPG_ (V_EXT) XpwmTOUT0/GP0_0 E PWM Timer XpwmTOUT/GP0_ XpwmTOUT/GP0_ (V_EXT0) XpwmTOUT/PWM_MIE/GP0_ F (V_SYS0) (V_SYS) EINT KEYP (V_KEY) I (V_EXT0) (V_EXT) (V_RT) XrtcXTI T XrtcXTO T RT LOK (V_KO) XRTLKO R EPLL Filter XjTRSTn P XjTMS R XjTK JTG U XjTI T XjTO W XjGSEL P XOM0 T XOM T SYSTEM XOM V OPTION XOM U XOM V XOM V XXTI U XXTO U XusbXTI 0 XusbXTO LOK E0 XLKOUT E XhdmiXTI Y XhdmiXTO Y XnWRESET T RESET XnRESET U XnRSTOUT T0 XPWRRGTON XefFSOURE U XEINT0/GPH0_0 Y XEINT/GPH0_ W XEINT/GPH0_ W XEINT/GPH0_ Y XEINT/GPH0_ XEINT/GPH0_ W XEINT/GPH0_ W XEINT/GPH0_ XEINT/GPH_0 V0 XEINT/GPH_ V XEINT0/GPH_ Y XEINT/GPH_ W XEINT/HMI_E/GPH_ XEINT/HMI_HP/GPH_ XEINT/GPH_ XEINT/GPH_ W0 XEINT/KP_OL0/GPH_0 U0 XEINT/KP_OL/GPH_ Y XEINT/KP_OL/GPH_ V XEINT/KP_OL/GPH_ XEINT0/KP_OL/GPH_ XEINT/KP_OL/GPH_ XEINT/KP_OL/GPH_ XEINT/KP_OL/GPH_ Y0 XEINT/KP_ROW0/GPH_0 XEINT/KP_ROW/GPH_ XEINT/KP_ROW/GPH_ XEINT/KP_ROW/GPH_ Y XEINT/KP_ROW/GPH_ XEINT/KP_ROW/GPH_ 0 XEINT0/KP_ROW/GPH_ Y XEINT/KP_ROW/GPH_ XicS0/GP_0 F XicSL0/GP_ XicS/GP_ E XicSL/GP_ XicS/IEM_SLK/GP_ XicSL/IEM_SPWI/GP_ E N/EPLL(evt) R XjTRSTn [] XjTMS [] XjTK [] XjTI [] R0 XjTO 00K [] XOM0 XOM XOM XOM XOM XOM XXTI [] XXTO [] XusbXTI [] XusbXTO [] XhdmiXTI [] XhdmiXTO [] XnWRESET [] XnRESET [,] XPWRRGTON [] XrtcXTI [] XrtcXTO [] R 0 XpwmTOUT0 [] XpwmTOUT [] XpwmTOUT [] XpwmTOUT/PWM_MIE [,0,] XEINT0/PSHOL [] XEINT [,] XEINT [,] XEINT [,] XEINT [,] XEINT [,] XEINT [,0] XEINT [] XEINT [] XEINT [] XEINT0 [,] XEINT [] XEINT/HMI_E [] XEINT/HMI_HP [] XEINT [,] XEINT [,] XEINT/KP_OL0 [] XEINT/KP_OL [0,] XEINT/KP_OL [] XEINT/KP_OL [] XEINT0/KP_OL [] XEINT/KP_OL [] XEINT/KP_OL [] XEINT/KP_OL [] XEINT/KP_ROW0 [,] XEINT/KP_ROW [,] XEINT/KP_ROW [] XEINT/KP_ROW [,] XEINT/KP_ROW [] XEINT/KP_ROW [] XEINT0/KP_ROW [] XEINT/KP_ROW [].nf XLKOUT [] TP XnRSTOUT TP XRTLKO TP [] [] [] [] [] [] Pin FFG XOM0 XOM XOM XOM XOM XOM ootingmode Option Selection OM[] oot Seq. 0: Storage : US-> URT-> Storage 0: Storage V_SYS OM[:] OM[0] : X-TL R K R K R0.K R.K R K R K 0 XicS0 [,,] XicSL0 [,,] XicS [,0,] XicSL [,0,] XicS/IEM_SLK [] XicSL/IEM_SPWI [] : X-TL (US) FG KHS0 R R R R R R V_EXT OM[:0] 00K 00K 00K 00K 00K 00K * OM can be tied V or GN directly. Storage NN -cycle NN K-cycle NN K-cycle -E NN K-cycle -E OneNN Mux(udi) OneNN emux(udi) S/MM emm(bit) Reserved NN Kyte Page, cycle irom NOR boot emm(bit) <I pull-up resistor> For High speed - Kohm For HMI -.Kohm SMSUNG ELETRONIS O.,LT SMK_SPV0_PU oard (Evaluation oard) Size ocument Number Rev SPV0 (SYS&onnectivity)/ oot Option 0.0 ate: Monday, October, 00 Sheet of

35 [,] Xm0R[:0] [,] Xm0T[:0] [,] XmR[:0] [,] Xm0 [,] Xm [,] XmSn [,] XmRSn [,] XmWEn [,] XmKE0 TP [,] XmSn0 [,] XmSn/ [] XmQS0 [] XmQSn0 [] XmQS [] XmQSn [] XmQS [] XmQSn [] XmQS [] XmQSn [] XmM0 [] XmM [] XmM [] XmM [,] XmSLK [,] XmSLKn [,] XmT[:0] V_MEM XM, MEMORY Interface K Xm0R0/MP0_0 Xm0Sn0/MP0_0 U OneNN Interface Xm0R0 Xm0R Xm0R Xm0R Xm0R Xm0R Xm0R Xm0R Xm0R Xm0R Xm0R0 Xm0R Xm0R Xm0R Xm0R Xm0R Xm0T0 Xm0T Xm0T Xm0T Xm0T Xm0T Xm0T Xm0T Xm0T Xm0T Xm0T0 Xm0T Xm0T Xm0T Xm0T Xm0T XmR0 XmR XmR XmR XmR XmR XmR XmR XmR XmR XmR0 XmR XmR XmR Xm0 Xm XmSn XmRSn XmWEn XmKE0 XmR XmSn0 XmSn/ XmQS0 XmQSn0 XmQS XmQSn XmQS XmQSn XmQS XmQSn XmM0 XmM XmM XmM XmSLK XmSLKn XmT0 XmT XmT XmT XmT XmT XmT XmT XmT XmT XmT0 XmT XmT XmT XmT XmT XmT XmT XmT XmT XmT0 XmT XmT XmT XmT XmT XmT XmT XmT XmT XmT0 XmT L Xm0R/MP0_ J Xm0R/MP0_ H Xm0R/MP0_ J Xm0R/MP0_ K Xm0R/MP0_ K Xm0R/MP0_ J Xm0R/MP0_ H Xm0R/MP0_0 G Xm0R/MP0_ J Xm0R0/MP0_ K Xm0R/MP0_ H Xm0R/MP0_ G Xm0R/MP0_ F Xm0R/MP0_ H Xm0R/MP0_ K Xm0T0/MP0_0 L Xm0T/MP0_ L Xm0T/MP0_ M Xm0T/MP0_ N Xm0T/MP0_ N Xm0T/MP0_ P Xm0T/MP0_ N Xm0T/MP0_ L Xm0T/MP0_0 L Xm0T/MP0_ L Xm0T0/MP0_ M Xm0T/MP0_ M Xm0T/MP0_ M Xm0T/MP0_ N Xm0T/MP0_ P Xm0T/MP0_ E XmR0 E0 XmR E XmR E XmR XmR F XmR XmR 0 XmR E XmR F XmR F XmR0 F XmR Memory Port E XmR F XmR R/mR/mR E Xm0 Xm (V_M) F XmSn E XmRSn G XmWEn G XmKE0 G XmKE/R G XmSn0 G XmSn XmQS0 XmQSn0 XmQS XmQSn XmQS XmQSn XmQS XmQSn XmM0 XmM XmM XmM XmSLK XmSLKn XmT0 XmT XmT XmT XmT XmT 0 XmT XmT XmT 0 XmT 0 XmT0 XmT XmT XmT XmT XmT XmT XmT XmT XmT E XmT0 E XmT F XmT XmT XmT XmT XmT XmT XmT XmT XmT0 XmT Xm0Sn/MP0_ T Xm0Sn/NFSn0/MP0_ J Xm0Sn/NFSn/MP0_ N Xm0Sn/NFSn/ONNXL_Sn0/MP0_ N Xm0Sn/NFSn/ONNXL_Sn/MP0_ N Xm0OEn/MP0_ R Xm0WEn/MP0_ P Xm0E0/MP0_0 T Xm0E/MP0_ N Xm0WITn/MP0_ W Xm0T_Rn/MP0_ M Xm0FLE/ONXL_V/MP0_0 K Xm0FLE/ONXL_SMLK/MP0_ K Xm0FWEn/ONXL_RPn/MP0_ J Xm0FREn/MP0_ M Memory Port0 Xm0FRn0/ONXL_INT0/MP0_ R Xm0FRn/ONXL_INT/MP0_ SROM/NN/ONENN Xm0FRn/MP0_ V Xm0FRn/MP0_ L (V_M0) U SPV0 XRSEL (V_SYS0) XmR0 L0 XmR L XmR L XmR R XmR F XmR F0 XmR H XmR J XmR G0 XmR H XmR0 K Memory Port XmR H XmR J R/mR/mR XmR H0 Xm0 J0 (V_M) Xm K0 XmSn J XmRSn J XmWEn P XmKE0 J XmKE/R G XmSn0 N XmSn K XmQS0 N XmQSn0 N XmQS L XmQSn L XmQS F XmQSn F XmQS XmQSn XmM0 P XmM L XmM H XmM E XmSLK G XmSLKn G XmT0 P XmT R XmT R XmT P XmT N XmT M XmT N XmT M XmT M XmT M XmT0 L XmT M XmT K XmT K XmT J XmT K XmT H XmT H XmT G XmT G XmT0 F XmT E XmT E XmT E XmT XmT XmT XmT F XmT XmT XmT0 XmT Xm0Sn0 [] Xm0Sn [] Xm0Sn/NFSn0 [,] Xm0Sn/NFSn [] Xm0Sn/NFSn/ONNXL_Sn0 [] Xm0Sn/NFSn/ONNXL_Sn [] Xm0OEn [,] Xm0WEn [,] Xm0E0 [] Xm0E [] Xm0T_Rn [,] Xm0FLE/ONXL_V [,] Xm0FLE/ONXL_SMLK [,] Xm0FWEn/ONXL_RPn [,] XmR0 XmR XmR XmR XmR XmR XmR XmR XmR XmR XmR0 XmR XmR XmR Xm0 Xm XmSn XmRSn XmWEn XmKE0 XmR XmSn0 XmSn/ XmQS0 XmQSn0 XmQS XmQSn XmQS XmQSn XmQS XmQSn XmM0 XmM XmM XmM XmSLK XmSLKn XmT0 XmT XmT XmT XmT XmT XmT XmT XmT XmT XmT0 XmT XmT XmT XmT XmT XmT XmT XmT XmT XmT0 XmT XmT XmT XmT XmT XmT XmT XmT XmT XmT0 XmT R.K R.K R.K R.K XmR[:0] [,] Xm0 [,] Xm [,] XmSn [,] XmRSn [,] XmWEn [,] XmKE0 [,] XmR [,] XmSn0 [,] XmSn/ [,] XmQS0 [] XmQSn0 [] XmQS [] XmQSn [] XmQS [] XmQSn [] XmQS [] XmQSn [] XmM0 [] XmM [] XmM [] XmM [] XmSLK [,] XmSLKn [,] XmT[:0] [,] R.K V_SYS Xm0WITn [] Xm0FREn [,] Xm0FRn0/ONXL_INT0 [,] Xm0FRn/ONXL_INT [,] Xm0FRn [] Xm0FRn [] R 00K R N SMSUNG ELETRONIS O.,LT SMK_SPV0_PU oard (Evaluation oard) Size ocument Number Rev SPV0 (RR & SROM Memory) 0.0 ate: Monday, October, 00 Sheet of

36 V P 00nF [] M LK [] TP SI_LK R.K/% [] XvHSYN/SYSS0/VENHSYN XvHSYN/SYSS0/VENHSYN/GPF0_0 [] XvVSYN/SYSS/VENVSYN Y0 XvVSYN/SYSS/VENVSYN/GPF0_ [] XvVEN/SYSR/VENHREF 0 XvVEN/SYSRS/VENHREF/GPF0_ [] XvVLK/SYSWE/V0LK 0 XvVLK/SYSWE/V0LK/GPF0_ [] XvV[:0] XvV0 XvV XvV0/SYS0/VEN0/GPF0_ XvV XvV/SYS/VEN/GPF0_ XvV XvV/SYS/VEN/GPF0_ XvV XvV/SYS/VEN/GPF0_ Y XvV XvV/SYS/VEN/GPF_0 XvV XvV/SYS/VEN/GPF_ E XvV XvV/SYS/VEN/GPF_ XvV XvV/SYS/VEN/GPF_ L XvV XvV/SYS/V0/GPF_ W XvV0 XvV/SYS/V/GPF_ E (V_L) XvV XvV0/SYS0/V/GPF_ XvV XvV/SYS/V/GPF_ Y XvV XvV/SYS/V/GPF_0 XvV XvV/SYS/V/GPF_ XvV XvV/SYS/V/GPF_ E XvV XvV/SYS/V/GPF_ XvV XvV/SYS/GPF_ XvV XvV/SYS/GPF_ XvV XvV/SYS/GPF_ XvV0 XvV/SYS/GPF_ XvV XvV0/SYS0/GPF_0 XvV XvV/SYS/GPF_ XvV XvV/SYS/GPF_ Y XvV/SYS/V_LK/GPF_ [] VSYN_LI W VSYN_LI/GPF_ [] SYS_OE/VEN_FIEL E SYS_OE/VEN_FIEL/GPF_ 0 00nF R 0 R 0 lose to P [] [] [] [] [] [] [] [] [] [] [] [] XadcIN0 XadcIN XadcIN XadcIN XadcIN XadcIN XadcIN XadcIN XadcIN XadcIN XdacOUT_0 XciPLK XciVSYN XciHREF XciYT0 XciYT XciYT XciYT XciYT XciYT XciYT XciYT XciFIEL XadcIN_0 XadcIN_ XadcIN_ 0 XadcIN_ Y XadcIN_ W XadcIN_ Y XadcIN_ XadcIN_ XadcIN_ XadcIN_ U XdacOUT_0 W XdacIREF V XdacVREF V XdacOMP XciPLK/GPE0_0 XciVSYN/GPE0_ XciHREF/GPE0_ XciYT0/GPE0_ XciYT/GPE0_ 0 XciYT/GPE0_ XciYT/GPE0_ XciYT/GPE0_ Y XciYT/GPE_0 XciYT/GPE_ XciYT/GPE_ XciLKenb/GPE_ XciFIEL/GPE_ TouchScreen (V_) TVOUT (V ) M (V_M) U SPV0 MIPI-SI/SI (V_MIPI_) HMI (V_HMI) XmipiMPLK E XmipiMNLK XmipiMP0 E XmipiMN0 XmipiMP E XmipiMN XmipiMP E XmipiMN XmipiMP E XmipiMN XmipiSPLK 0 XmipiSNLK E0 XmipiSP0 XmipiSN0 E XmipiSP XmipiSN E XmipiSP XmipiSN E XmipiSP XmipiSN E XmipiVREG_0PV XhdmiTX0P T XhdmiTX0N T XhdmiTXP U XhdmiTXN U XhdmiTXP V XhdmiTXN V XhdmiTXP R XhdmiTXN R XhdmiREXT W XmsmR0/M 0/F_R0/MIPI_YTE_LK/GPJ0_0 H XmsmR/M /F_R/MIPI_ES_LK/GPJ0_ G XmsmR/M /F_R/TS_LK/GPJ0_ E XmsmR/M /F_IORY/TS_SYN/GPJ0_ H XmsmR/M /F_INTRQ/TS_VL/GPJ0_ G XmsmR/M /F_MRQ/TS_T/GPJ0_ H XmsmR/M /F_RESETN/TS_ERROR/GPJ0_ F XmsmR/M /F_MKN/MHL_0/GPJ0_ XmsmR/M PLK/SROM_R/MHL_/GPJ_0 F XmsmR/M VSYN/SROM_R/MHL_/GPJ_ G XmsmR0/M HREF/SROM_R/MHL_/GPJ_ F XmsmR/M FIEL/SROM_R/MHL_/GPJ_ G XmsmR/M LKOUT/SROM_R0/MHL_/GPJ_ E XmsmR/KP_OL_0/SROM_R/MHL_/GPJ_ F Modem XmsmT0/KP_OL_/F_T0/MHL_/GPJ_0 F amera XmsmT/KP_OL_/F_T/MHL_/GPJ_ E XmsmT/KP_OL_/F_T/MHL_/GPJ_ F XmsmT/KP_OL_/F_T/MHL_0/GPJ_ MHL XmsmT/KP_OL_/F_T/MHL_/GPJ_ Key XmsmT/KP_OL_/F_T/MHL_/GPJ_ E XmsmT/KP_OL_/F_T/MHL_/GPJ_ SROM addr[:] XmsmT/KP_ROW_0/F_T/MHL_/GPJ_ XmsmT/KP_ROW_/F_T/MHL_/GPJ_0 (V_MOEM) XmsmT/KP_ROW_/F_T/MHL_/GPJ_ XmsmT0/KP_ROW_/F_T0/MHL_/GPJ_ XmsmT/KP_ROW_/F_T/MHL_/GPJ_ XmsmT/KP_ROW_/F_T/MHL_/GPJ_ XmsmT/KP_ROW_/F_T/MHL_0/GPJ_ XmsmT/KP_ROW_/F_T/MHL_/GPJ_ XmsmT/KP_ROW_/F_T/MHL_/GPJ_ XmsmSn/KP_ROW_/F_Sn0/MHL_/GPJ_0 G XmsmWEn/KP_ROW_0/F_Sn/MHL_HSYN/GPJ_ XmsmRn/KP_ROW_/F_IORN/MHL_IK/GPJ_ G XmsmIRQn/KP_ROW_/F_IOWN/MHL_VSYN/GPJ_ XmsmVN/KP_ROW_/SROM_R/MHL_E/GPJ_ XmipiMPLK [0] XmipiMNLK [0] XmipiMP0 [0] XmipiMN0 [0] XmipiMP [0] XmipiMN [0] XmipiMP [0] XmipiMN [0] XmipiMP [0] XmipiMN [0] XmipiSPLK [] XmipiSNLK [] XmipiSP0 [] XmipiSN0 [] XmipiSP [] XmipiSN [] XmipiSP [] XmipiSN [] XmipiSP [] XmipiSN [] XhdmiTX0P [] XhdmiTX0N [] XhdmiTXP [] XhdmiTXN [] XhdmiTXP [] XhdmiTXN [] XhdmiTXP [] XhdmiTXN [] XhdmiREXT [] nf XmsmR0/M 0/F_R0/MIPI_YTE_LK [0,] XmsmR/M /F_R/MIPI_ES_LK [0,] XmsmR/M /F_R/TS_LK [0,] XmsmR/M /F_IORY/TS_SYN [0,] XmsmR/M /F_INTRQ/TS_VL [0,] XmsmR/M /F_MRQ/TS_T [0,] XmsmR/M /F_RESETN/TS_ERROR [0,] XmsmR/M /F_MKN/MHL_0 [] XmsmR/M PLK/SROM_R/MHL_ [] XmsmR/M VSYN/SROM_R/MHL_ [] XmsmR0/M HREF/SROM_R/MHL_ [] XmsmR/M FIEL/SROM_R/MHL_ [] XmsmR/M LKOUT/SROM_R0/MHL_ [] XmsmR/KP_OL0/SROM_R/MHL_ [] XmsmT0/KP_OL/F_T0/MHL_ [] XmsmT/KP_OL/F_T/MHL_ [] XmsmT/KP_OL/F_T/MHL_ [] XmsmT/KP_OL/F_T/MHL_0 [] XmsmT/KP_OL/F_T/MHL_ [] XmsmT/KP_OL/F_T/MHL_ [] XmsmT/KP_OL/F_T/MHL_ [] XmsmT/KP_ROW0/F_T/MHL_ [] XmsmT/KP_ROW/F_T/MHL_ [] XmsmT/KP_ROW/F_T/MHL_ [] XmsmT0/KP_ROW/F_T0/MHL_ [] XmsmT/KP_ROW/F_T/MHL_ [] XmsmT/KP_ROW/F_T/MHL_ [] XmsmT/KP_ROW/F_T/MHL_0 [] XmsmT/KP_ROW/F_T/MHL_ [] XmsmT/KP_ROW/F_T/MHL_ [] XmsmSn/KP_ROW/F_Sn0/MHL_ [] XmsmWEn/KP_ROW0/F_Sn/MHL_HSYN [] XmsmREn/KP_ROW/F_IORN/MHL_IK [] XmsmIRQn/KP_ROW/F_IOWN/MHL_VSYN [] XmsmVN/KP_ROW/SROM_R/MHL_E [] XdacOUT_ REV0. R 00/% 00nF R V GN VIN U N NJMF POWER VOUT VSG V_ R.K/0 00nF T uf/.v T uf/.v T 0uF/.V R0 /% OUT0 [] Header XadcIN0 XadcIN XadcIN XadcIN XadcIN ON 0 -P-S R XadcIN XadcIN XadcIN XadcIN XadcIN R 0 0 TSYM0 [] TSYP0 [] TSXM0 [] TSXP0 [] lose to ON TSYM [] TSYP [] TSXM [] TSXP [] SMSUNG ELETRONIS O.,LT SMK_SPV0_ PU oard (Evaluation oard) Size ocument Number Rev SPV0 (Media) 0.0 ate: Monday, October, 00 Sheet of

37 V P V_MOEM_P V_MIPI P V_UHOST P V_UOTG P V_EXT_P V_M_P V P V_EXT0_P V_LIVE_P V_M0_P V_M_P V_INT_P V_EXT_P V_RT_P V_PLL_P V_MPLL_P V_MIPI_PLL_P V P V_MIPI P V_KEY_P V_L_P V_MIPI_PLL_P V_M_P V P V_HMI_P V_HMI_OS_P V_M_P V_VPLL_P V_EPLL_P V_HMI_PLL_P V_UOTG P V_MIPI P V_KEY_P V_U_P V_KO_P V_UHOST P V_SYS0_P V_SYS_P V_L_P V_RM_P V_KO_P V_MOEM_P V_MIPI P V_RM_P V_INT_P V_EXT_P V_EXT0_P V_RT_P V_LIVE_P V_M0_P V_M_P V_M_P V P V_U_P V_SYS_P V_SYS0_P V_EXT_P V_PLL_P V_VPLL_P V_MPLL_P V_EPLL_P V P V_HMI_P V_HMI_PLL_P V_HMI_OS_P V_UHOST P V_UOTG P V_UOTG P V_UHOST P Size ocument Number Rev ate: Sheet of SPV0 (Gen. Power) 0.0 SMK_SPV0_PU oard (Evaluation oard) Monday, October, 00 SMSUNG ELETRONIS O.,LT Size ocument Number Rev ate: Sheet of SPV0 (Gen. Power) 0.0 SMK_SPV0_PU oard (Evaluation oard) Monday, October, 00 SMSUNG ELETRONIS O.,LT Size ocument Number Rev ate: Sheet of SPV0 (Gen. Power) 0.0 SMK_SPV0_PU oard (Evaluation oard) Monday, October, 00 SMSUNG ELETRONIS O.,LT nf nf T 0uF/.V T 0uF/.V 00nF 00nF 00nF 00nF nf nf T 0uF/.V T 0uF/.V 00nF 00nF 0 nf 0 nf 00nF 00nF 00nF 00nF nf nf T 0uF/.V T 0uF/.V 00nF 00nF 00nF 00nF 00nF 00nF 00nF 00nF 0 00nF 0 00nF 00nF 00nF 00nF 00nF 0 00nF 0 00nF nf nf 0 00nF 0 00nF 00 00nF 00 00nF 00nF 00nF 0 00nF 0 00nF 0 00nF 0 00nF 0 00nF 0 00nF 0 nf 0 nf 00nF 00nF 0 00nF 0 00nF 00nF 00nF 00nF 00nF 00nF 00nF T 0uF/.V T 0uF/.V 00nF 00nF 00nF 00nF U SPV0 U SPV0 V_INT_ K V_SYS0_ U VSS_ J V_INT_ M V_PLL M0 VSS_ P V_INT_ R VSS_ G VSS_ N VSS_ R0 VSS_ T VSS_0 K V_RM_ M V_SYS0_0 P V_INT_ L VSS_ M V_RM_0 P VSS_ R V_SYS0_ U VSS_ K VSS_ P VSS_ T0 VSS_ R VSS_ W VSS_ R V_INT_ N0 VSS_ K V_INT_ R VSS_ E VSS_ K VSS_ V_RM_ P V_RM_ M VSS_ P VSS_0 P0 V_INT_ P VSS_ L VSS_ L VSS_ M VSS_ L V_RM_0 L V_RM_ L V_INT_ K VSS_ K0 VSS_ T V_INT_0 R VSS_ R V_RM_ N V_RM_ L V_RM_ N V_INT_ T VSS_ W VSS_ T V_INT_ L0 V_RT P VSS_ G V_INT_ N VSS_ E V_RM_ M V_LIVE_ W VSS_0 T VSS_ T V_RM_ N VSS_ M0 VSS_ N V_INT_0 K V_MPLL N0 VSS_0 V_LIVE_0 R V_M_0 J V_M_ J V_M_ J V_M_ J V_M_0 J V_M_ K V_M_ L V_M_ M V_EXT0 J0 V_EXT_0 T V_EXT_ W V_EXT G V_VPLL P0 V_SYS T V_EPLL R0 VSS_PLL M VSS_MPLL N VSS_EPLL R VSS_VPLL P V 0 W0 V_U_0 U V_U_ U V_M V V_KO P V_ V V_HMI P V_MOEM J V_KEY T V_L U0 V_MIPI 0 U V_MIPI U V_MIPI_PLL W V_MIPI_ Y V_UHOST_ Y V_UOTG_ W V U V_UHOST_ W V_UOTG_ U V_HMI_OS T V_HMI_PLL R V_M0_0 K V_M0_ M VSS 0 W VSS_ V VSS_HMI R VSS_MIPI_0 U VSS_MIPI_ U VSS U VSS_UHOST_ VSS_UOTG_ Y VSS_UHOST_ VSS_UOTG_ Y VSS_UHOST_ Y VSS_UOTG_ W VSS_HMI_OS T VSS_HMI_PLL P nf nf 00nF 00nF 00nF 00nF nf nf 00nF 00nF 00nF 00nF 0 00nF 0 00nF 0 nf 0 nf 00nF 00nF T 0uF/.V T 0uF/.V 00nF 00nF 00nF 00nF 00nF 00nF 00nF 00nF 00nF 00nF 00nF 00nF T 0uF/.V T 0uF/.V 00nF 00nF nf nf nf nf 00nF 00nF 00nF 00nF nf nf 0 nf 0 nf

38 [,] XmR[:0] [,] Xm0 [,] Xm [,] XmSn/ [] XmQSn0 [] XmQS0 [] XmM0 [,] XmSLKn [,] XmSLK [,] XmRSn [,] XmSn [,] XmSn0 [,] XmKE0 [,] XmWEn XmR0 XmR XmR XmR XmR XmR XmR XmR XmR XmR XmR0 XmR XmR XmR H H H J J J J K K K H K L L G G G F E F G G F F U 0 0/P 0 nqs QS M/RQS NU/nRQS nk K nrs ns ns KE nwe VSSQ0 VSSQ VSSQ VSSQ VSSQ VQ0 VQ VQ VQ VQ V0 V V V VL VSSL VREF OT Q0 Q Q Q Q Q Q Q N0 N E H L E E E F L L 00nF V_MEM 0uF/.V T XmOT [] XmT0 XmT XmT XmT XmT XmT XmT XmT 00nF V_MEM 00nF 0 00nF nf R 0K/% R 0K/% XmT[:0] [] nf [,] XmR[:0] [,] Xm0 [,] Xm [,] XmSn/ [] XmQSn [] XmQS [] XmM [,] XmSLKn [,] XmSLK [,] XmRSn [,] XmSn [,] XmSn0 [,] XmKE0 [,] XmWEn XmR0 XmR XmR XmR XmR XmR XmR XmR XmR XmR XmR0 XmR XmR XmR H H H J J J J K K K H K L L G G G F E F G G F F U 0 0/P 0 nqs QS M/RQS NU/nRQS nk K nrs ns ns KE nwe VSSQ0 VSSQ VSSQ VSSQ VSSQ VQ0 VQ VQ VQ VQ V0 V V V VL VSSL VREF OT Q0 Q Q Q Q Q Q Q N0 N E H L E E E F L L 00nF V_MEM 0uF/.V T XmOT [] XmT XmT XmT0 XmT XmT XmT XmT XmT 00nF 00nF nf nf V_MEM R 0K/% R 0K/% 00nF XmT[:] [] K J E VSS0 VSS VSS VSS K J E VSS0 VSS VSS VSS KTG0QQ-HE or HF (R, Gb) KTG0QQ-HE or HF (R, Gb) XM R(For Gbit x) SMSUNG ELETRONIS O.,LT SMK_SPV0_POP PU oard (Evaluation oard) Size ocument Number Rev R(Gbit*) XM #, 0.0 ate: Monday, October, 00 Sheet of

39 [,] XmR[:0] [,] Xm0 [,] Xm [,] XmSn/ [] XmQSn [] XmQS [] XmM [,] XmSLKn [,] XmSLK [,] XmRSn [,] XmSn [,] XmSn0 [,] XmKE0 [,] XmWEn XmR0 XmR XmR XmR XmR XmR XmR XmR XmR XmR XmR0 XmR XmR XmR H H H J J J J K K K H K L L G G G F E F G G F F K J E U 0 0/P 0 nqs QS M/RQS NU/nRQS nk K nrs ns ns KE nwe VSSQ0 VSSQ VSSQ VSSQ VSSQ VSS0 VSS VSS VSS VQ0 VQ VQ VQ VQ V0 V V V VL VSSL VREF OT Q0 Q Q Q Q Q Q Q N0 N E H L E E E F L L 00nF V_MEM 0uF/.V T XmOT [] XmT XmT XmT XmT XmT0 XmT XmT XmT 00nF 00nF nf nf V_MEM R 0K/% R 0K/% 00nF XmT[:] [] [] XmOT [,] XmR[:0] [,] Xm0 [,] Xm [,] XmSn/ [] XmQSn [] XmQS [] XmM [,] XmSLKn [,] XmSLK [,] XmRSn [,] XmSn V_MEM [,] XmSn0 [,] XmKE0 [,] XmWEn R0 0K R 0K/N XmR0 XmR XmR XmR XmR XmR XmR XmR XmR XmR XmR0 XmR XmR XmR H H H J J J J K K K H K L L G G G F E F G G F F K J E U 0 0/P 0 nqs QS M/RQS NU/nRQS nk K nrs ns ns KE nwe VSSQ0 VSSQ VSSQ VSSQ VSSQ VSS0 VSS VSS VSS VQ0 VQ VQ VQ VQ V0 V V V VL VSSL VREF OT Q0 Q Q Q Q Q Q Q N0 N E H L E E E F L L 00nF V_MEM 0uF/.V T0 XmT XmT XmT XmT XmT XmT XmT0 XmT 00nF XmOT [] 0 00nF nf V_MEM 00nF nf R 0K/% R 0K/% XmT[:] [] KTG0QQ-HE or HF (R, Gb) KTG0QQ-HE or HF (R, Gb) XM R(For Gbit x) SMSUNG ELETRONIS O.,LT SMK_SPV0_PU oard (Evaluation oard) Size ocument Number Rev R(Gbit*) XM #, 0.0 ate: Monday, October, 00 Sheet of

40 [,] XmR[:0] [,] XmR [,] Xm0 [,] Xm [,] XmSn/ [] XmQSn0 [] XmQS0 [] XmM0 [,] XmSLKn [,] XmSLK [,] XmRSn [,] XmSn [,] XmSn0 [,] XmKE0 [,] XmWEn XmR0 XmR XmR XmR XmR XmR XmR XmR XmR XmR XmR0 XmR XmR XmR M M M N N N N P P P M P R R R L L L E F F E K J K L L K K U 0 0/P 0 nqs QS M/RQS NU/nRQS nk K nrs ns ns KE nwe VQ0 VQ VQ VQ VQ V0 V V V VL VSSL VREF OT Q0 Q Q Q Q Q Q Q E G G G G E J M R J J J K G G H H H H F F 00nF V_MEM 0uF/.V T XmT0 XmT XmT XmT XmT XmT XmT XmT 00nF XmOT [] 00nF nf XmT[:0] [] V_MEM nf 00nF R 0K/% R 0K/% [,] XmR[:0] [,] XmR [,] Xm0 [,] Xm [,] XmSn/ [] XmQSn [] XmQS [] XmM [,] XmSLKn [,] XmSLK [,] XmRSn [,] XmSn [,] XmSn0 [,] XmKE0 [,] XmWEn XmR0 XmR XmR XmR XmR XmR XmR XmR XmR XmR XmR0 XmR XmR XmR M M M N N N N P P P M P R R R L L L E F F E K J K L L K K U0 0 0/P 0 nqs QS M/RQS NU/nRQS nk K nrs ns ns KE nwe VQ0 VQ VQ VQ VQ V0 V V V VL VSSL VREF OT Q0 Q Q Q Q Q Q Q E G G G G E J M R J J J K G G H H H H F F 00nF V_MEM 0uF/.V T XmOT [] XmT XmT XmT0 XmT XmT XmT XmT XmT 00nF V_MEM 00nF 0 00nF nf R 0K/% R 0K/% nf XmT[:] [] H H E F F P N J E VSSQ0 VSSQ VSSQ VSSQ VSSQ VSS0 VSS VSS VSS N0 N N N N N N N N W W W W R H H E F F P N J E VSSQ0 VSSQ VSSQ VSSQ VSSQ VSS0 VSS VSS VSS N0 N N N N N N N N W W W W R KTG0Q-HE or HF (R, Gb) KTG0Q-HE or HF (R, Gb) XM R(For Gbit x) SMSUNG ELETRONIS O.,LT SMK_SPV0_PU oard (Evaluation oard) Size ocument Number Rev R(Gbit*) XM #0, 0.0 ate: Monday, October, 00 Sheet of

41 [,] XmR[:0] [,] XmR [,] Xm0 [,] Xm [,] XmSn/ [] XmQSn [] XmQS [] XmM [,] XmSLKn [,] XmSLK [,] XmRSn [,] XmSn [,] XmSn0 [,] XmKE0 [,] XmWEn XmR0 XmR XmR XmR XmR XmR XmR XmR XmR XmR XmR0 XmR XmR XmR M 0 M M N N N N P P P M 0/P P R R R L 0 L L E nqs F QS U F M/RQS E NU/nRQS K nk J K K nrs L ns L ns K KE K nwe H VSSQ0 H VSSQ E VSSQ F VSSQ F VSSQ P VSS0 N VSS J VSS E VSS VQ0 E VQ G VQ G VQ G VQ G V0 E V J V M V R VL VSSL VREF OT J J J K Q0 G Q G Q H Q H Q H Q H Q F Q F N0 N N N N W N W N W N W N R KTG0Q-HE or HF (R, Gb) 0 00nF V_MEM 0uF/.V T XmOT [] XmT XmT XmT XmT XmT0 XmT XmT XmT V_MEM 00nF 00nF 00nF nf R 0K/% R 0K/% XmT[:] [] [] nf XmOT V_MEM R0 0K R 0K/N [,] XmR[:0] [,] XmR [,] Xm0 [,] Xm [,] XmSn/ [] XmQSn [] XmQS [] XmM [,] XmSLKn [,] XmSLK [,] XmRSn [,] XmSn [,] XmSn0 [,] XmKE0 [,] XmWEn XmR0 XmR XmR XmR XmR XmR XmR XmR XmR XmR XmR0 XmR XmR XmR M 0 M M N N N N P P P M 0/P P R R R L 0 L L E nqs F QS U F M/RQS E NU/nRQS K nk J K K nrs L ns L ns K KE K nwe H VSSQ0 H VSSQ E VSSQ F VSSQ F VSSQ P VSS0 N VSS J VSS E VSS VQ0 E VQ G VQ G VQ G VQ G V0 E V J V M V R VL VSSL VREF OT J J J K Q0 G Q G Q H Q H Q H Q H Q F Q F N0 N N N N W N W N W N W N R KTG0Q-HE or HF (R, Gb) 00nF V_MEM 0uF/.V T XmOT [] XmT XmT XmT XmT XmT XmT XmT0 XmT 00nF V_MEM 00nF 00nF nf R 0K/% R 0K/% XmT[:] [] nf XM R(For Gbit x) SMSUNG ELETRONIS O.,LT SMK_SPV0_POP PU oard (Evaluation oard) Size ocument Number Rev R(Gbit*) XM #, 0.0 ate: Monday, October, 00 Sheet of

42 .V 0m PV_LO PV_LO.V 0m R PV_LO.0V 0m [,,] PWRRGTON_INV R JP N/R0 -P-S (Pitch :.0mm) JP -P-S R R 0 JP0 N/R0 -P-S LO should be OFF in SLEEP mode T 0uF/.V R 0 R N/R0 R0 K V_L V_L_P V_UOTG P V_UHOST P REV0. hange JP -P-S R N/R0 JP -P-S R N/R0 JP -P-S Q SIS N/R0 00nF R N V_SYS R K V_SYS0_P V_SYS_P V P R0 JP -P-S R0 JP0 -P-S R 0 R U IN nen.v 00m PV_LO R N/R0 JP -P-S JP -P-S R0 N/R0 R 0 V P N/R0 V P N OUT TPS0V R R R 0 GN no JP -P-S JP R 0 JP -P-S R JP -P-S R00 0 V_ -P-S R V_KO_P N/R0 N/R0 V_KEY_P V_KEY N/R0 N/R0 N/R0 R V_U_P V_U V_EXT0_P V_EXT_P V_EXT_P V_MM V_EXT V_HMI_OS_P R N/R0 JP F LMPGSN -P-S V_MOEM_P N/R0 R -P-S J V_MSM R 0/R0 R.0V 0m PV_LO V_V V_V should be OFF in SLEEP mode N/R0 N/R0.V 0m PV_LO PV_LO.uF/XR V R JP -P-S.V PV_RM PV_RT R 0/R0 V_PLL_P V_MPLL_P V_EPLL_P V_VPLL_P V_RM_P V_RT_P N/R0.V 00m PV_MEM N/R0 V_M0_P R N/R0 V_HMI_PLL_P -P-S JP F.V 0m V_LIVE_P LMPGSN R0 N/R0 -P-S PV_LO R N/R0 V_MEM R N/R0 V_MIPI P JP JP JP -P-S -P-S -P-S R0 N/R0 V_MIPI_PLL_P.V JP PV_INT V_INT_P -P-S R0 N/R0 V_MEM_V LO should be OFF in SLEEP mode R0 JP JP -P-S V_M_IO_V R0 V_UOTG P V_UHOST P Vout=.V(R/R) VIN GN EN N/R0 00nF N/R0 -P-S R N/R0 U VOUT J MIM 0 JP -P-S T N/R0 0pF R R R JP -P-S V_HMI_P F LMPGSN 0uF/.V/T0 V_M_P V_M_IO_V R0 0K R 00K N/R0 R N/R0.uF/XR R0 0 R 0 R 0 R 0 JP -P-S R0 JP -P-S R JP -P-S N/R REV0. hange LO should be OFF in SLEEP mode.v 0m PV_LO R0 JP SMSUNG ELETRONIS O.,LT SMK_SPV0_ PU oard (Evaluation oard) R N/R0 V_M_P JP -P-S R0 N/R0 V_M_P JP -P-S R N/R0 V_MEM JP -P-S R N/R0 V_MEM JP -P-S R N/R0 V_MIPI P JP0 -P-S R 0/R0 V_MIPI_ Size ocument Number Rev Power Jumper 0.0 ate: Monday, October, 00 Sheet 0 of

43 uf,.v PV_LO R 00K V Vout=0.0(R/R) R=R(Vout/0.0V-) U LMXMY VIN SW VIN GN GN F EN GN P L RH (0uH) 0K,% Z MRS0T 0K,% R R R R (.V) uf,.v V_MEM_V uf,.v Vout =.V@.0 PV_INT V T0 0uF/0V R0 0 Vout=0.(R/R)-Iadj(R) U IN N PGN N0 OUT J LT0ES(J) nshn GN R K,%/R0 R R R 0K,%/R0 (.V) V_V T 0uF/.V V_V PV_LO R T 00K 0uF/.V Vout=.(R/R) R=R(Vout/.V-) U0 IN POK OUT SET nshn GN MXEUT R R R.K,%/R0 R 00K,%/R0 00nF/0 (.V) V_V T 0uF/.V V V_SYS V PV_LO R 00K T 0uF/0V Vout=0.(R/R) R=R(Vout/0.V-) U VIN RUN GN SW VF LT0ES R L.uH (LQHNRM) R R K,%/R0 R 00K,%/R0 pf (.V) V_V T 0uF/.V R 0 LE LE-Red (SM 0) -IN R 0 LE LE-GREEN (SM 0) SYS_ON REV0. hange V/ JK P G G POWER JK (-JK, -00) F MicroSM0- (., SM, Poly Switch) Z Onsemi SM0TG (.V) 0 00nF U V OUT GN R K R 0K U SIY V R 0K IN- IN MX R.K SMSUNG ELETRONIS O.,LT SMK_SPV0_PU oard (Evaluation oard) Size ocument Number Rev Power(jack&Regulator) 0.0 ate: Monday, October, 00 Sheet of

44 X MHz (SM,SX-) (L: pf) X R pf.m REV0. hange MHz (SM,SX-) (L: pf) R pf.m pf R N R N XXTI [] XXTO [] For PLL XhdmiXTI [] R V_SYS 00K OE GN R MHz (SM,SO-0) N.KHz (H-0) (L: pf) 0 X V OS OUT R 0M R: lose to X R N R N R: lose to X XrtcXTI [] XrtcXTO [] XXTI [] XusbXTI [] X MHz (SM,SX-) (L: pf) R0.M For US pf pf REV0. hange XusbXTI [] XusbXTO [] [] [] [] [] XjTRSTn XjTI XjTMS XjTK [] XjTO [] EXT_nRESET R N R N R N R 0 R N V_SYS ON JTG JTG V_SYS HIFF-0P-.S (ox,male,right ngle) *Pull-up, Pull-down resistors are embeded For HMI REV0. hange XhdmiXTO [] pf For RT 0pF 0pF X-Tal lock Source [,] XuTX/URT_UIO_TX [,] XuRX/URT_UIO_RX V_V J -P-.S (HR-.-MLE) URT nwreset SW SW-TT (Red) V_V R0 N XnWRESET [] 00nF nreset SW SW-TT (Red) V R 00K [] PMI_nRST_OUT [] EXT_nRESET 00nF V R 00K U V SNLVG0V 00nF XnRESET [,] TP V.uF/XR U VIN VOUT GN EN YP MI-. 00nF V.uF/XR Reset ircuitry SMSUNG ELETRONIS O.,LT SMK_SPV0_POP PU oard (Evaluation oard) Size ocument Number Rev Reset / lock source / JTG 0.0 ate: Monday, October, 00 Sheet of

45 PV_RM PV_INT PV_MEM [] XEINT0/PSHOL [,,0,] PWROn_OR J -P-S PWRON [,] XEINT [,] XEINT [,] XEINT R 0 R 0 R 0.uF/XR.uF/XR PWRRGTON V.uF/XR F G G F U IN IN IN IN IN IN SET SET SET PWREN PWRHOL LX UK LX UK LX UK GN GN PGN PGN PGN E E G F G F E G G L.uH (LQH_) L0.uH (LQH_) L.uH (LQH_).uF/XR.uF/XR 0 PV_RT PV_LO PV_LO PV_LO PV_LO PV_LO PV_LO PV_LO PV_LO 0 R.uF/XR V POWER_KEY [,] XEINT R 0 JIG_ON E PWRON JIGON ONOn V_OIN LO F F R N V_V R 00K [] PMI_nRST_OUT TP [] XicSL/IEM_SPWI [] XicS/IEM_SLK TP R E RSOn MRn SL S SR LO REFP LO LO LO LO LO LO LO LO E 0 00nF MX T R_IV0N(N).uF/XR.uF/XR.uF/XR.uF/XR.uF/XR 0.uF/XR.uF/XR.uF/XR.uF/XR V JP R0 JIG_ON -P-S 00K nf V_V U V SNLVG0V PWRRGTON_INV [0,,] V R 0K/R00 U IN GN 00nF V OUT PWRON [] XPWRRGTON R 0 PWRRGTON LER nout POWER 00nF MX0ZT V SW SW-TT (Red) R U 0 SNLVG0V POWER_KEY SMSUNG ELETRONIS O.,LT SMK_SPV0_PU oard (Evaluation oard) Size ocument Number Rev Power - PMI Socket 0.0 ate: Monday, October, 00 Sheet of

46 [,] Xm0R[:0] V_MEM V_V 00nF 00nF V0 V0 V V Xm0R0 Xm0R Xm0R Xm0R Xm0R Xm0R 0 Xm0R Xm0R Xm0R Xm0R Xm0R0 Xm0R Xm0R 0 Xm0R Xm0R Xm0R OE OE U 0 IR IR GN0 GN GN GN 0 GN GN GN GN SNVGG _Xm0R0 _Xm0R _Xm0R _Xm0R _Xm0R _Xm0R _Xm0R _Xm0R _Xm0R _Xm0R _Xm0R0 _Xm0R _Xm0R _Xm0R _Xm0R _Xm0R R 00K V_MEM _Xm0R[:0] [] [,] Xm0Sn/NFSn0 R N [] [] R 0 Xm0Sn0 Xm0Sn [] Xm0Sn/NFSn M0Sn/NFSn M0Sn/NFSn V_MEM V_MEM U SNLVGV U 00nF 00nF SNLVGV V_MEM 0 00nF V_MEM Xm0T0 Xm0T Xm0T Xm0T Xm0T Xm0T Xm0T Xm0T V_V 00nF 00nF V0 V0 V V [,] Xm0T[:0] _Xm0T[:0] [] U0 SNLVG0V Xm0T Xm0T Xm0T0 Xm0T Xm0T 0 Xm0T Xm0T Xm0T 0 OE OE GN0 GN GN GN U SNVGG 0 IR IR GN GN 0 GN GN _Xm0T0 _Xm0T _Xm0T _Xm0T _Xm0T _Xm0T _Xm0T _Xm0T _Xm0T _Xm0T _Xm0T0 _Xm0T _Xm0T _Xm0T _Xm0T _Xm0T Xm0T_Rn [,] [,] Xm0T_Rn TP V_MEM V_V 00nF [] Xm0Sn0 [] Xm0Sn [,] Xm0Sn/NFSn0 [] Xm0Sn/NFSn M0Sn/NFSn M0Sn/NFSn TP TP0 [] Xm0E0 [] Xm0E [,] Xm0OEn [,] Xm0WEn [,] Xm0FLE/ONXL_V [,] Xm0FLE/ONXL_SMLK [,] Xm0FWEn/ONXL_RPn [,] Xm0FREn 0 0 V0 V U V0 V 0 TP TP 00nF _Xm0Sn0 [] _Xm0Sn [] _Xm0Sn/NFSn0 [] _Xm0Sn/NFSn [] _M0Sn/NFSn [] _M0Sn/NFSn [] _Xm0E0 [] _Xm0E [] _Xm0OEn [] _Xm0WEn [] _Xm0FLE/ONV [] _Xm0FLE/ONSMLK [] _Xm0FWEn/ONRPn [] _Xm0FREn [] [] Xm0Sn/NFSn/ONNXL_Sn0 [] Xm0Sn/NFSn/ONNXL_Sn FG KHS0 0 V_MEM R 00K R 00K R0 00K M0Sn/NFSn M0ONSn [] M0Sn/NFSn S S ase 'd EXT. ON POP. ON OE OE IR IR GN0 GN GN GN 0 GN GN GN GN SNVGG R 00K V_MEM ONINT0 ONINT J -P-S Xm0FRn0/ONXL_INT0 [,] M0ONINT [] Xm0FRn/ONXL_INT [,] SMSUNG ELETRONIS O.,LT SMK_SPV0_PU oard (Evaluation oard) Size ocument Number Rev Level Shifter & uffer (SROM EI IF) 0.0 ate: Monday, October, 00 Sheet of

47 TFT L FP able Interface (MOULE oard) M 0uF/0V T [,] Xm0R[:0] 00nF [] M0ONSn [,] Xm0WEn [,] Xm0FLE/ONXL_V [,] Xm0FWEn/ONXL_RPn [,] Xm0FLE/ONXL_SMLK [,] Xm0T[:0] V_MEM Xm0R0 Xm0R Xm0R Xm0R Xm0R Xm0R0 Xm0R Xm0R M0ONSn OneNN onnector Xm0T0 Xm0T Xm0T Xm0T Xm0T Xm0T0 Xm0T Xm0T ON QSH-00-0-F-- V_MEM Xm0R Xm0R Xm0R Xm0R Xm0R Xm0R Xm0R Xm0R Xm0T Xm0T Xm0T Xm0T Xm0T Xm0T Xm0T Xm0T Xm0R[:0] [,] R Xm0T[:0] [,] N V_V Place resistors on Top. Xm0OEn [,] M0ONINT R [] N Xm0FREn [,] R0 N Xm0Sn/NFSn0 [,] V_L 00nF 00nF V 00nF T 0uF/0V T 0uF/.V V [] V_L [,0,] XpwmTOUT/PWM_MIE V_L XvV[:0] [,,] XicS0 [] TSYM [] TSYP [,,] XicSL0 [] XvVLK/SYSWE/V0LK [] XvHSYN/SYSS0/VENHSYN [] XvVSYN/SYSS/VENVSYN [] XvVEN/SYSR/VENHREF [,,0,] PWROn_OR [] TSXM [] TSXP [] VSYN_LI [] SYS_OE/VEN_FIEL [,0] XEINT [] [] [] [] TSYM0 TSYP0 TSXM0 TSXP0 R 0 R 0 R 0 R 0 [,] SPI_LK [,] SPI_MOSI [,] SPI_MISO [,] SPI_Sn XvV0 XvV XvV XvV XvV XvV XvV XvV XvV XvV XvV0 XvV XvV XvV XvV XvV XvV XvV XvV XvV XvV0 XvV XvV XvV L_L L_SU_LK L_RESET L_SPILK L_SPIMOSI L_SPIMISO L_NSS [] XvVLK/SYSWE/V0LK [] XvHSYN/SYSS0/VENHSYN [] XvVSYN/SYSS/VENVSYN [] XvVEN/SYSR/VENHREF XvV XvV XvV TP0 TP TP TP TP TP TP GF0-0S-LSS-P000 SMSUNG ELETRONIS O.,LT SMK_SPV0_PU oard (Evaluation oard) Size ocument Number Rev OneNN / L I/F(NonMIPI) 0.0 ate: Monday, October, 00 Sheet of

48 V_MM V_MM0 R 0K HS-MM Slot 0 slot0_n T uf/.v 00nF R 0K R 0K R 0K R00 0K R0 0K R0 0K R0 0K R0 0K R0 0K ON S_ N T P0/GN slot0_t [] XEINT [] XmmcT/MM0_T V_MM R0 0K R0 0 slot0_t [] XmmcT0/MM0_T slot0_m slot0_lk [] XmmcT/MM0_T [] XmmcT/MM0_T slot0_t0 slot0_t 0 0 T N T N0 M N T N VSS N N V N N0 LK N T N VSS N T T0 T S_WP P/GN [0,,] slot0_n PWRRGTON_INV 00nF V_MM U LVGV T 0uF/.V R0 K Q V_MM SIS 00nF V_MM0 R0 0 LE LE-lue (SM 0) MM SLOT 0(mmc ch0,) S/HSMM Socket (S ) FG SLOT0,HMI V_MM FG SW-IP R0 00K SLOT0_SEL HMI_I_EN [] [] [] [] [] [] [] Xmmc0M Xmmc0LK Xmmc0n XmmcM XmmcLK Xmmcn U 0 GN V S noe SNTLVPWR V_MM 0 00nF/0 slot0_m slot0_lk slot0_n SLOT0_SEL [] Xmmc0T [] Xmmc0T [] Xmmc0T [] Xmmc0T0 [] XmmcT/MM0_T [] XmmcT/MM0_T [] XmmcT/MM0_T [] XmmcT0/MM0_T U 0 GN V S noe SNTLVPWR S - L : port, H : port OE - L : Output enable H : all disconnect V_MM 00nF slot0_t slot0_t slot0_t slot0_t0 SLOT0_SEL [] Xmmc0T [] Xmmc0T [] Xmmc0T [] Xmmc0T0 [] Xmmc0M [] Xmmc0LK [] Xmmc0n [] [] R R R R R R R OFF:mmc0 ON: mmc ON: HMI isable N N N N N N N slot0_t slot0_t slot0_t slot0_t0 slot0_m slot0_lk slot0_n SMSUNG ELETRONIS O.,LT SMK_SPV0_PU oard (Evaluation oard) Size ocument Number Rev MM#0 0.0 ate: Monday, October, 00 Sheet of

49 [] Xmmcn/SPI MISO [,] XEINT/KP_ROW HS-MM Slot V_MM R 0K V_MM [] XmmcT [] XmmcT [] XmmcT0/MM_T [] XmmcM/SPI nss [] XmmcT/MM_T R 0 0 T uf/.v 00nF [] XmmcLK/SPI LK [] XmmcT/MM_T V_MM R 0K R 0K R 0K R 0K V_MM [] XmmcT/MM_T [] XmmcT0/SPI MOSI R [] XmmcT 0K MM SLOT (mmc ch) V_MM R 0K R 0K R 0K R0 0K R 0K ON N T T N T 0 N0 M N T N VSS N N V N 0 N0 LK N T N VSS N T T0 S_ T S_WP S/HSMM Socket (S ) HS-MM port P0/GN P/GN HS-MM Slot [] Xmmcn/SPI MISO [0,,] PWRRGTON_INV HS-SPI [] [] [] [] [] [] [] [] XspiLK0 XspiSn0 XspiMISO0 XspiMOSI0 XspiLK XspiSn XspiMISO XspiMOSI 00nF HS-SPI0 ON -P-S(x, mm pitch) V_MM U T0 0uF/.V LVGV V_MM R K HS-SPI ON0 00nF ON R 0 HS-SPI -P-S(x, mm pitch) -P-S(x, mm pitch) Q SIS R V_MM ON,, spacing : mm 0 R 0 LE SPI_LK0 [] SPI_Sn0 [] SPI_MISO0 [] SPI_MOSI0 [] SPI_LK [,] SPI_Sn [,] SPI_MISO [,] SPI_MOSI [,] LE-lue (SM 0) [] Xmmcn R 0K [] XmmcT/MM_T T uf/.v/t0 00nF R 0K R 0K R 0K R0 0K R 0K ON S_ N T P0/GN [] XmmcLK/SPI LK [] XmmcM/SPI nss [] Xmmcn/SPI MISO [] XmmcT0/SPI MOSI R 0 [] XEINT 0 R [] XmmcT/MM_T [] V_MM R 0K XmmcM [] XmmcLK [] XmmcT0/MM_T [] XmmcT/MM_T MM SLOT (mmc ch) T N T 0 N0 M N T N VSS N N V N 0 N0 LK N T N VSS N T T0 T S_WP S/HSMM Socket (S ) HS-MM port (bit) P/GN [0,,] [] Xmmcn PWRRGTON_INV 00nF V_MM U LVGV V_MM T 0uF/.V R K Q SIS 00nF SMSUNG ELETRONIS O.,LT V_MM SMK_SPV0_PU oard (Evaluation oard) R 0 LE LE-lue (SM 0) Size ocument Number Rev MM#/#/ HS-SPI 0.0 ate: Monday, October, 00 Sheet of