adStar-L - PDF 무료 다운로드

Preliminary Datasheet High-Performance Processor Advanced Digital Chips, Inc. adstar-l Hardware Manual December 5, 217 Subject to Change Without Notice. 215 Advanced Digital Chips, Inc. All right reserved. No part of this document may be reproduced in any form without written permission from Advanced Digital Chips, Inc. Advanced Digital Chips, Inc. reserves the right to change in its products or product specification to improve function or design at any time, without notice. Office Korea (Headquarters) 22F, Bldg A, Keumkang Penterium IT Tower, 81 Gwanyang-dong, Dongan-gu, Anyang-si, Gyeonggi-do, 431-6, Korea T : +82-31-463-75 / F : +82-31-463-7588 E-mail : eisc@adc.co.kr http://www.adc.co.kr China Peak Microtech Co., Ltd 北京芯首电子科技有限公司 E-mail : sales@peaktech.com.cn http://www.peaktech.com.cn

www.adc.co.kr Contents 1 DESCRIPTIONS AND FEATURES... 15 1.1 General Description... 15 1.2 Features... 16 2 BLOCK DIAGRAM & PIN DESCRIPTIONS... 18 2.1 Block Diagram... 18 2.2 Pin Layout... 19 2.3 Pin Definition... 2 2.4 Pin Description... 24 3 MEMORY ARCHITECTURE AND BOOTING MODES... 26 3.1 Memory Map... 26 3.2 Embedded Memories... 27 3.2.1 Internal SRAM for Instruction... 27 3.2.2 Internal SRAM for Data... 27 3.2.3 Internal SRAM Registers... 27 3.2.4 Internal SRAM Register Setting... 28 3.3 Peripheral Memory Map... 29 3.4 Boot Modes... 3 3.4.1 Debugger Mode... 3 3.4.2 Boot Mode... 3 3.4.3 Serial Flash Boot... 3 3.4.4 NAND Flash Boot... 3 3.4.5 SWD Seleciton... 3 4 SYSTEM CONTROL... 31 4.1 Reset Control... 31 4.1.1 System Reset... 31 4.1.2 Power On Start Time... 32 4.2 Clock control... 33 4.2.1 Main oscillator... 34 4.2.2 RTC oscillator (32KHz)... 34 4.2.3 PLL... 35 4.2.4 PLL1... 36 4.2.5 PLLx Clock Change... 36 4.2.6 Clock gating... 37 4.2.7 Additional Clock Divider... 37 4.2.8 USB Clock... 38 4.2.9 TFT LCD Clock... 38 4.2.1 Sound Mixer Clock... 39 4.2.11 Protection Mechanism... 39 4.3 Power modes... 4 4.3.1 RUN mode... 4 4.3.2 Sleep mode... 4 4.3.3 Stop mode... 41 4.3.4 Shutdown mode... 42 4.3.5 Static mode... 43 4.4 System Control Registers... 43 4.4.1 System Control Global Lock Register (GLOCK)... 43 4.4.2 System Control Write Enable Register (WREN)... 44 4.4.3 Halt Register... 44 4.4.4 Halt Status Register... 45 4.4.5 Interrupt Wake up Enable Register... 46 4.4.6 Event Wake up Enable Register... 47 4.4.7 PMC Status Register... 48 4.4.8 OSC Stable Counter Register... 48 4.4.9 Clock Control Register (CLKCON)... 48 4.4.1 PLL Control Register (PLLCON)... 49 4.4.11 Clock Divider Control Register (CLKDCON)... 5 4.4.12 AHB Clock Enable Register (HCLKEN)... 51 4.4.13 APB Clock Enable Register (PCLKEN)... 51 4.4.14 USB PHY Control Register (USBPHYCON)... 52 4.4.15 Boot mode status register(bmst)... 52 4.4.16 Boot mode config register(bmct)... 52 4.4.17 HCLK clock divide register(hclkdiv)... 53 4.4.18 CLK16_ clock divide register(clk16div)... 53 2 Contents Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr 4.4.19 4.4.2 4.4.21 4.4.22 CLK16_1 clock divide register(clk16div1)... 53 LCD clock divide register(lcddiv)... 53 Sound Mixer clock divide register(smdiv)... 54 PLL1 Control Register (PLLCON1)... 54 5 SPI FLASH MEMORY CONTROLLER... 55 5.1 Introduction... 55 5.2 Feature... 55 5.3 Functional Description... 56 5.3.1 Register Interface... 56 5.3.2 Memory Interface... 56 5.3.3 Internal Flash Memory... 56 5.3.4 Internal Flash Memory Commands... 57 5.3.5 Flash Status Register... 59 5.3.6 Chip Erasing Flash memory... 61 5.3.7 Sector/Block Erasing Flash memory... 61 5.3.8 Programing Flash memory... 61 5.3.9 Reading Flash memory... 62 5.3.1 Power Down and Release Power Down... 62 5.3.11 Flash Mode Register (FLMOD)... 62 5.3.12 Flash Baudrate Register (FLBRT)... 62 5.3.13 Flash Chip Select High Pulse Width Register (FLCSH)... 62 5.3.14 Flash WIP Check Period Register (FLWCP)... 63 5.3.15 Flash Clock Delay Register (FLCKDLY)... 63 5.4 Register Description... 64 5.4.1 Flash Mode Register (FLMOD)... 64 5.4.2 Flash Baudrate Register (FLBRT)... 65 5.4.3 Flash Chip Select High Pulse Width Register (FLCSH)... 65 5.4.4 Flash Performance Enhance Mode Register (FLPEM)... 65 5.4.5 Flash Command Register (FLCMD)... 65 5.4.6 Flash Status Register (FLSTS)... 65 5.4.7 Flash Sector Erase Address Register (FLSEA)... 65 5.4.8 Flash Block Erase Address Register (FLBEA)... 66 5.4.9 Flash Data Register (FLDAT)... 66 5.4.1 Flash WIP Check Period Register (FLWCP)... 66 5.4.11 Flash Clock Delay Register (FLCKDLY)... 66 5.4.12 Flash 2nd Status Register (FLSTS2)... 66 5.4.13 Flash ID Read Register (FLIDR)... 66 5.4.14 Flash Memory Size Write Register (SFMSIZE)... 67 6 GPIO (GENERAL PURPOSE I/O)... 68 6.1 Features... 68 6.2 Block Diagram... 68 6.3 Functional Description... 69 6.3.1 Port Control... 69 6.3.2 Port Edge Detect... 69 6.4 Register Description... 7 6.4.1 Port Direction Registers ( GPxDIR )... 7 6.4.2 Port Direction Output Mode Setting Registers ( GPxODIR )... 7 6.4.3 Port Direction Input Mode Setting Registers ( GPxIDIR )... 7 6.4.4 Port Output Data Level Registers ( GPxOLEV )... 7 6.4.5 Port Output Data Registers ( GPxDOUT )... 71 6.4.6 Port Output Data High Level Setting Registers ( GPxOHIGH )... 71 6.4.7 Port Output Data Low Level Setting Registers ( GPxOLOW )... 71 6.4.8 Port Input Data Level Registers ( GPxILEV )... 72 6.4.9 Port Pull-up Status Registers ( GPxPUS )... 72 6.4.1 Port Pull-up Enable Registers ( GPxPUEN )... 72 6.4.11 Port Pull-up Disable Registers ( GPxPUDIS )... 72 6.4.12 Port Rising Edge Detect Registers ( GPxRED )... 73 6.4.13 Port Falling Edge Detect Registers ( GPxFED )... 73 6.4.14 Port Edge Detect Status Registers ( GPxEDS )... 73 6.4.15 Port Open Drain Mode Control Registers ( GPxODM )... 74 6.4.16 Port Schmitt Input Enable Registers ( GPxSHMT )... 74 6.4.17 Port Pull-down Status Registers ( GPxPDS )... 74 6.4.18 Port Pull-down Enable Registers ( GPxPDEN )... 74 6.4.19 Port Pull-down Disable Registers ( GPxPDDIS )... 75 7 PIN MUX... 76 7.1 Pin Mux register... 76 8 INTERRUPT CONTROLLER... 77 8.1 Features... 77 Copyright 215, Advanced Digital Chips, Inc. 3 Contents

www.adc.co.kr 8.2 Functional Description... 77 8.2.1 Interrupt Vector and Priority... 78 8.2.2 External Interrupt (EIRQx)... 79 8.2.3 Internal Interrupt Mode... 79 8.2.4 Interrupt Pending and Interrupt Pending Clear... 8 8.2.5 Interrupt Enable... 8 8.2.6 Interrupt Mask Set/Clear Register... 8 8.3 Register Description... 81 8.3.1 Interrupt Pending Clear Register (INTPENDCLR)... 81 8.3.2 External Interrupt Mode and External PIN Level Register (EINTMOD)... 81 8.3.3 Internal Interrupt Mode Register (IINTMODn)... 82 8.3.4 Interrupt Pending Register (INTPENDn)... 83 8.3.5 Interrupt Enable Register (INTENn)... 84 8.3.6 Interrupt Mask Status Register (INTMASKn)... 85 8.3.7 Interrupt Mask Set Register (INTMASKSETn)... 85 8.3.8 Interrupt Mask Clear Register (INTMASKCLRn)... 86 9 CORE TIMER... 87 9.1 Features... 87 9.2 15-bit Pre-scaler with clock source selection... 87 9.3 Timer/Counter... 88 9.4 Timer Control Registers... 89 9.4.1 Timer Reset Control Register (TMRST)... 89 9.4.2 Timer Control Registers (TMCON)... 89 9.4.3 Timer Counter Registers (TMCNT )... 89 9.4.4 Timer Interrupt waveform... 89 1 WATCHDOG TIMER... 9 1.1 Register Description... 91 1.1.1 Watchdog Timer Control Register (WDTCTRL)... 91 1.1.2 Watchdog Timer Counter Value Register (WDTCNT)... 91 1.1.3 Watchdog Timer Lock Value Register (WDTLOCK)... 91 Operational Flow Diagrams... 92 11 TIMERS... 93 11.1 Features... 93 11.2 Functional Description... 93 11.2.1 15-bit Pre-scaler with clock source selection... 93 11.2.2 Timer/Counter... 94 11.2.3 Pulse Width Modulation (PWM)... 95 11.2.4 Capture... 97 11.3 Register Description... 99 11.3.1 Timer Pre-scale Control Registers ( TPxCTRL )... 99 11.3.2 Timer Control Registers ( TMxCTRL)... 99 11.3.3 Timer Counter / PWM Period Registers ( TMxCNT )... 1 11.3.4 Capture Counter Registers / PWM Duty Registers ( TMxDUT )... 1 11.3.5 PWM Pulse Count Registers ( TMxPUL )... 1 12 REAL TIMER CLOCK... 11 12.1 RTC Features... 11 12.2 RTC diagram... 12 12.3 RTC Calibration (function diagram)... 12 12.4 Real Time Counter Control Register... 13 12.4.1 Real Time Counter Control Register (RTCCON_1)... 13 12.4.2 Real Time Counter Control Register (RTCCON_2)... 13 12.5 Real Time Counter Register... 14 12.5.1 Real Time Counter Sec Register (RSEC)... 14 12.5.2 Real Time Counter Min Register (RMIN)... 14 12.5.3 Real Time Counter Hour Register (RHOUR)... 14 12.5.4 Real Time Counter Day Register (RDAY)... 14 12.5.5 Real Time Counter Week Register (RWEEK)... 14 12.5.6 Real Time Counter Month Register (RMONTH)... 14 12.5.7 Real Time Counter Year Register (RYEAR)... 14 12.6 Real Time Alarm Register... 15 12.6.1 Real Time Alarm Register (RALM_S)... 15 12.6.2 Real Time Alarm Register (RALM_M)... 15 12.6.3 Real Time Alarm Register (RALM_H)... 15 12.6.4 Real Time Alarm Register (RALM_D)... 15 12.6.5 Real Time Alarm Register (RALM_MO)... 15 12.7 Real Time Back up Register... 16 12.7.1 Real Time Back up Register (BACKUP_)... 16 12.7.2 Real Time Back up Register (BACKUP_1)... 16 4 Contents Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr 12.7.3 Real Time Back up Register (BACKUP_2)... 16 12.7.4 Real Time Back up Register (BACKUP_3)... 16 12.7.5 Real Time Back up Register (BACKUP1_)... 17 12.7.6 Real Time Back up Register (BACKUP1_1)... 17 12.7.7 Real Time Back up Register (BACKUP1_2)... 17 12.7.8 Real Time Back up Register (BACKUP1_3)... 17 12.7.9 Real Time Back up Register (BACKUP2_)... 18 12.7.1 Real Time Back up Register (BACKUP2_1)... 18 12.7.11 Real Time Back up Register (BACKUP2_2)... 18 12.7.12 Real Time Back up Register (BACKUP2_3)... 18 12.7.13 Real Time Back up Register (BACKUP3_)... 19 12.7.14 Real Time Back up Register (BACKUP3_1)... 19 12.7.15 Real Time Back up Register (BACKUP3_2)... 19 12.7.16 Real Time Back up Register (BACKUP3_3)... 19 12.8 Real Time PMU Controller Register (PMUCON)... 11 12.9 RTC interrupt timing diagram... 111 12.9.1 Alarm interrupt operation... 111 12.9.2 1sec interrupt operation... 111 12.9.3 1/2 interrupt operation... 112 12.9.4 1/4 interrupt operation... 112 13 COPROCESSOR... 113 13.1 Features... 113 13.2 Coprocessor Description... 113 13.3 Coprocessor Control Registers... 114 13.3.1 System Coprocessor Status Register (SCPR15)... 114 13.3.2 Master Command Register (SCPR15)... 114 13.3.3 Supervisor Stack Point Register (SCPR14)... 114 13.3.4 User Stack Point Register (SCPR13)... 114 13.3.5 Vector Base Register (SCPR12)... 114 13.3.6 Invalidate Cache Line and Lock Register (SCPR11)... 115 13.3.7 Memory Bank Configuration Register (SCPR9)... 115 13.3.8 General Access Point Data Register (SCPR4)... 116 13.3.9 General Access Point Index Register (SCPR3)... 116 14 UART... 117 14.1 Features... 117 14.2 Block Diagram... 117 14.3 Functional Description... 118 14.3.1 Serial Data Format... 118 14.3.2 UART Baud Rate... 12 14.4 Register Summery... 121 14.5 Register Description... 122 14.5.1 UART Channel Receiver Buffer Registers ( UxRB )... 122 14.5.2 UART Channel Transmitter Holding Registers ( UxTH )... 122 14.5.3 UART Channel Interrupt Enable Registers ( UxIE )... 122 14.5.4 UART Channel Interrupt Identification Register ( UxII )... 122 14.5.5 UART Channel FIFO Control Register ( UxFC )... 123 14.5.6 UART Channel Line Control Register ( UxLC )... 124 14.5.7 UART Channel Line Status Register ( UxLS )... 125 14.5.8 UART Channel Divisor Latch LSB Register ( UxDLL )... 126 14.5.9 UART Channel Divisor Latch MSB Register ( UxDLM )... 126 14.5.1 UART Channel Fractional Divider Register ( UxFDR )... 126 15 DMA... 127 15.1 Features... 127 15.2 Block Description... 128 15.3 Functional Description... 129 15.3.1 DMA Operation... 129 15.3.2 Linked List Operation... 13 15.3.3 Auto Reload Operation... 133 15.3.4 Peripheral Interface... 136 15.4 Register Description... 138 15.4.1 DMA Interrupt Status ( DMAIntStatus )... 138 15.4.2 DMA Terminal Count Interrupt Status ( DMATCIntStatus )... 138 15.4.3 DMA Terminal Count Interrupt Clear ( DMATCIntClr )... 138 15.4.4 DMA Error Interrupt Status ( DMAErrorIntStatus )... 138 15.4.5 DMA Error Interrupt Clear ( DMAErrorIntClr )... 138 15.4.6 DMA Block Interrupt Status ( DMABlockIntStatus )... 139 15.4.7 DMA Block Interrupt Clear ( DMABlockIntClr )... 139 15.4.8 DMA Raw Terminal Count Interrupt Status ( DMARawTCIntStatus )... 139 15.4.9 DMA Raw Error Interrupt Status ( DMARawErrorIntStatus )... 139 15.4.1 DMA Enabled Channel Status ( DMAEnbldChn )... 139 Copyright 215, Advanced Digital Chips, Inc. 5 Contents

www.adc.co.kr 15.4.11 DMA Software Burst Request ( DMASoftBReq )... 139 15.4.12 DMA Software Single Request ( DMASoftSReq )... 14 15.4.13 DMA Software Last Burst Request ( DMASoftLBReq )... 14 15.4.14 DMA Software Last Single Request ( DMASoftLSReq )... 14 15.4.15 Channel Source Address Register ( ChnSrcAddr )... 14 15.4.16 Channel Destination Address Register ( ChnDstAddr )... 141 15.4.17 Channel Linked List Item Register ( ChnLLI )... 141 15.4.18 Channel Control Register ( ChnCntl )... 141 15.4.19 Channel Configuration Register ( ChnCfg )... 143 15.4.2 Channel Source Gather Address Register ( ChnSrcGaAddr )... 144 15.4.21 Channel Destination Scatter Address Register ( ChnDstScaAddr )... 144 15.4.22 Channel Auto Reload Count Register ( ChnAutoReloadCnt )... 144 15.5 Program Guide... 145 15.5.1 Sumary of Register... 145 15.5.2 Programming Sequence... 145 15.5.3 Program Consideration... 146 16 LOCAL MEMORY CONTROLLER... 147 16.1 Register Description... 147 16.1.1 SDRAM Control Register (MEMCON)... 147 16.1.2 SDRAM Clock Delay Register (MEMCLKCON)... 147 16.1.3 SDRAM Refresh Control Register (MEMREFCON)... 148 17 NAND FLASH CONTROLLER... 149 17.1 Features... 149 17.2 Functional Description... 15 17.2.1 Data Read/Write... 15 17.2.2 DMA Operation... 15 17.3 ECC Operation... 15 17.3.1 ECC Encoding... 151 17.3.2 ECC Decoding by S/W... 151 17.3.3 ECC Decoding by H/W (Auto ECC Decoding)... 151 17.4 Register Description... 152 17.4.1 NAND Flash Memory Control Register (NFCTRL)... 152 17.4.2 NAND Flash Memory Command Set Register (NFCMD)... 152 17.4.3 NAND Flash Memory Address Register (NFADR)... 152 17.4.4 NAND Flash Memory Data Register (NFDATA)... 153 17.4.5 NAND Flash Memory Operation Status Register (NFSTAT)... 153 17.4.6 NAND Flash Memory ECC(Error Correction Code) Register (NFECC)... 153 17.4.7 NAND Flash Memory Configuration Register (NFCFG)... 154 17.4.8 NAND Flash Memory ECC Code for LSN data (NFECCL)... 154 17.4.9 NAND Flash Memory Error Corrected Data Register (NFECD)... 154 17.4.1 NAND Flash Memory Spare Address Register (NFSPADR)... 155 17.4.11 NAND Flash Memory MLC ECCn Register (NFECCn)... 155 17.4.12 NAND Flash Memory Error Location n Register (NFERRLOCn)... 155 17.4.13 NAND Flash Memory Error Pattern n Register (NFERRPTNn)... 155 17.4.14 NAND Flash Memory ID Register (NFMID)... 155 18 SD HOST CONTROLLER... 156 18.1 Features... 156 18.2 Block Diagram... 156 18.3 SD Card Protocol... 156 18.4 Register Description... 157 18.4.1 SDHC Control Register (SDHCCON)... 157 18.4.2 SDHC Status Register (SDHCSTAT)... 158 18.4.3 SDHC Clock Divide Register (SDHCCD)... 159 18.4.4 SDHC Response Time Out Register (SDHCRTO)... 159 18.4.5 SDHC Read Data Time Out Register (SDHCRDTO)... 16 18.4.6 SDHC Block Length Register (SDHCBL)... 16 18.4.7 SDHC Number of Block Register (SDHCNOB)... 16 18.4.8 SDHC Interrupt Enable Register (SDHCIE)... 161 18.4.9 SDHC Command Control Register (SDHCCMDCON)... 162 18.4.1 SDHC Command Argument Register (SDHCCMDA)... 162 18.4.11 SDHC Response FIFO Access Register (SDHCRFA)... 162 18.4.12 SDHC Data FIFO Access Register (SDHCDFA)... 162 19 SPI LCD CONTROLLER... 163 19.1 Features... 163 19.2 Register Description... 163 19.2.1 SPI LCD control Register (CTRL)... 163 19.2.2 SPI LCD Baud Rate Register (BAUD)... 163 19.2.3 SPI LCD DMA Configuration Register (SPI_LCD_DMA)... 163 6 Contents Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr 19.2.4 19.2.5 19.2.6 19.2.7 SPI LCD ChipSelect Register (CSx)... 164 SPI LCD Status Register (SPI_LCD_STAT)... 164 LCD Data Register (SPI_LCD_DATA)... 164 LCD Interrupt Mask Register (SPI_LCD_INT)... 164 2 SPI (SERIAL PERIPHERAL INTERFACE)... 165 2.1 Features... 165 2.2 Block Diagram... 165 2.3 Functional Description... 166 2.3.1 SPI Pins... 166 2.3.2 SPI Operating Modes... 167 2.3.3 Data Transfer Timing... 168 2.3.4 SCK Phase and Polarity Control... 169 2.3.5 SPI Serial Clock Baud Rate... 169 2.3.6 Open-Drain Output for Wired-OR... 17 2.3.7 Transfer Size and Direction... 17 2.3.8 Write Collision... 17 2.3.9 MODE Fault... 17 2.3.1 Interrupt... 171 2.4 Register Description... 172 2.4.1 SPI Control Register (SPICTRL)... 172 2.4.2 SPI Baud Rate Register (SPIBR)... 172 2.4.3 SPI Status Register (SPISTAT)... 173 2.4.4 SPI Data Register (SPIDATA)... 173 2.4.5 SPI nss Control Register (nssctrl)... 174 2.4.6 SPI Interrupt Mask Register (SPIINT)... 174 21 TWI (TWO WIRED INTERFACE)... 175 21.1 Features... 175 21.2 Block Diagram... 175 21.3 Functional Description... 176 21.3.1 DATA TRANSFER FORMAT... 176 21.3.2 START AND STOP CONDITION... 176 21.3.3 ACK SIGNAL TRANSMISSION... 177 21.3.4 READ-WRITE OPERATION... 177 21.3.5 BUS ARBITRATION PROCEDURES... 178 21.3.6 ABORT CONDITIONS... 179 21.3.7 Operational Flow Diagrams... 179 21.4 Register Description... 185 21.4.1 TWI Control Register (TWICTRL)... 185 21.4.2 TWI Status Register (TWISTAT)... 186 21.4.3 TWI Address Register(TWIADR)... 187 21.4.4 TWI Data Register (TWIDATA)... 187 21.4.5 TWI Baud-Rate Register (TWIBR)... 187 21.4.6 TWI Baud-Rate 1 Register (TWIBR1)... 187 22 SOUND MIXER... 189 22.1 Features... 189 22.2 Block Diagram... 189 22.3 Low Pass Filter for Digital Modulator... 19 22.4 Sound Mixer clock... 19 22.5 Mixer Block Diagram... 191 22.6 Register Description... 192 22.6.1 Mixer Control Register (MIXER_ CON)... 192 22.6.2 Mixer Volume Register (MIXER_VOL)... 193 22.6.3 Mixer Buffer Status Register (MIXER_BST)... 193 22.6.4 Mixer Data Register (MIXER_DAT)... 193 22.6.5 Mixer Out Register (MIXER_OUT)... 193 22.6.6 Mixer Interrupt Status Register (MIX_IST)... 193 23 ADC CONTROLLER... 194 23.1 Features... 194 23.2 Register Description... 195 23.2.1 ADC Control Register (ADCCTRL)... 195 23.2.2 ADC Data Register (ADCDATA)... 195 23.2.3 ADC FIFO Register (ADCFIFO)... 195 23.2.4 ADC Status Register (ADCSTAT)... 196 23.2.5 ADC Control Register2 (ADCCTRL2)... 196 24 TFT LCD CONTROLLER... 197 24.1 Introduction... 197 24.2 Features... 197 Copyright 215, Advanced Digital Chips, Inc. 7 Contents

www.adc.co.kr 24.3 Functional Description... 198 24.3.1 LCD clock source and divider... 198 24.3.2 Double buffering... 198 24.3.3 LCD Interrupt... 199 24.3.4 HSYNC, VSYNC... 199 24.3.5 DISPEN (Hor.active)... 2 24.3.6 VGA Timings... 2 24.3.7 Color Bar Test Pattern Generation Block... 22 24.4 Register Description... 22 24.4.1 LCD Horizontal Total Register(LCDHT)... 22 24.4.2 LCD Horizontal Sync. Start / End Register(LCDHS)... 23 24.4.3 LCD Horizontal Active Start / End Register(LCDHA)... 23 24.4.4 LCD Vertical Total Register(LCDVT)... 23 24.4.5 LCD Vertical Sync. Start / End Register(LCDVS)... 23 24.4.6 LCD Vertical Active Start / End Register(LCDVA)... 24 24.4.7 LCD Display Current X / Y Position Register(LCDXY)... 24 24.4.8 LCD Status Register(LCDSTAT)... 24 24.4.9 LCD Control Register(LCDCON)... 25 24.4.1 LCD Base Address Register (LCDBADR)... 25 24.4.11 LCD Base Address 1 Register (LCDBADR1)... 26 24.4.12 LCD Frame Sync. Count Register (LCDFRAMECNT)... 26 24.4.13 LCD Horizontal Width Register (LCDHWIDTH)... 26 24.4.14 LCD Flip Control Register (LCDFCTL)... 26 24.4.15 LCD Base Address 2 Register (LCDBADR2)... 26 24.4.16 LCD Base Address 3 Register (LCDBADR3)... 26 25 JPEG DECODER... 27 25.1 Features... 27 25.2 Block Description... 27 25.3 Functional Description... 29 25.4 Register Description... 21 25.4.1 JPEG Decoder Quantization Scale Control Register (JDQSC)... 21 25.4.2 JPEG Decoder Command Control Register (JDCC)... 21 25.4.3 JPEG Decoder Y DC Node Table (JDYDCNT)... 21 25.4.4 JPEG Decoder Y DC Leaf Table (JDYDCLT)... 21 25.4.5 JPEG Decoder Y AC Node Table (JDYACNT)... 21 25.4.6 JPEG Decoder Y AC Leaf Table (JDYACLT)... 211 25.4.7 JPEG Decoder UV DC Node Table (JDUVDCNT)... 211 25.4.8 JPEG Decoder UV DC Leaf Table (JDUVDCLT)... 211 25.4.9 JPEG Decoder UV AC Node Table (JDUVACNT)... 211 25.4.1 JPEG Decoder UV AC Leaf Table (JDUVACLT)... 211 25.4.11 JPEG Decoder Status Register (JDSTAT)... 211 25.4.12 JPEG Decoder IRQ Status Register (JDIRQSTAT)... 212 25.4.13 JPEG Decoder Data FIFO Status Register (JDDFSTAT)... 212 25.4.14 JPEG Decoder Enable Register (JDENA)... 212 25.4.15 JPEG Decoder FIFO Clear Register (JDFCLR)... 212 25.4.16 JPEG Decoder FIFO Control Register (JDFCON)... 213 25.4.17 JPEG Decoder Waite Control Register (JDWCON)... 213 25.4.18 JPEG Decoder Software Reset Register (JDSRST)... 213 25.4.19 JPEG Decoder Version Information Register (JDVERINFO)... 213 25.4.2 JPEG Decoder CSC Base Address Register (JDCSCBASEADDR)... 213 25.4.21 JPEG Decoder Stride Size Register (JDCSTRID)... 213 25.4.22 JPEG Decoder RGB565 mode and Timeout count enable (JDCRGBTIMEOUT)... 214 25.4.23 JPEG Decoder Timeout counter Register (JDCTIMEOUTCNT)... 214 25.4.24 JPEG Decoder Timeout counter clear (JDCTIMEOUTCLR)... 214 25.4.25 JPEG Decoder Input Data FIFO Register (JDIDF)... 214 26 USB DEVICE... 215 26.1 Features... 215 26.2 Register Summary... 215 26.2.1 USB Function Address Register... 216 26.2.2 USB Power Management Register... 216 26.2.3 USB Interrupt Registers... 216 26.2.4 USB Interrupt Enable Registers... 216 26.2.5 Frame Number Registers... 216 26.2.6 Index Register... 216 26.2.7 MAXP Register... 216 26.2.8 EP Control Register... 216 26.2.9 IN Control Registers... 216 26.2.1 Out Control Registers... 216 26.2.11 Out Write Count Registers... 216 26.2.12 Endpoint FIFO Access Registers... 216 26.3 Register Description... 217 8 Contents Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr 26.3.1 26.3.2 26.3.3 26.3.4 26.3.5 26.3.6 26.3.7 26.3.8 26.3.9 26.3.1 26.3.11 26.3.12 26.3.13 26.3.14 26.3.15 26.3.16 26.3.17 26.3.18 26.3.19 26.3.2 26.3.21 26.3.22 USB Function Address Register (USBFA)... 217 USB Power Management Register (USBPM)... 217 USB Endpoint Interrupt Register (USBEPI)... 218 USB Interrupt Register (USBINT)... 218 Endpoint Interrupt Enable Register (USBEPIEN)... 219 USB Interrupt Enable Register (USBINTEN)... 219 USB Low Byte Frame Number Register (USBLBFN)... 219 USB High Byte Frame Number Register (USBHBFN)... 219 USB Index Register (USBIND)... 219 USB MAXP Register (USBMP)... 219 USB EP Control Register (USBEPC)... 22 USB IN Control 1 Register (USBIC1)... 221 USB IN Control 2 Register (USBIC2)... 222 USB Out Control Register 1 (USBOC1)... 223 USB OUT Control Register 2 (USBOC2)... 223 USB Low Byte Out Write Count Register (USBLOWC)... 224 USB High Byte Out Write Count Register (USBHBOWC)... 224 EP FIFO Data Register (USBEP)... 224 EP1 FIFO Data Register (USBEP1)... 224 EP2 FIFO Data Register (USBEP2)... 224 EP3 FIFO Data Register (USBEP3)... 224 EP4 FIFO Data Register (USBEP4)... 224 27 USB HOST CONTROLLER... 225 27.1 Features... 225 27.2 Operational Registers... 225 28 ELECTRICAL CHARACTERISTIC... 226 28.1 DC Electrical Characteristic... 226 28.2 Operating Conditions... 226 28.3 LDO Electrical Specification... 226 28.4 POR Electrical Specification... 227 28.5 PLL Electrical Specification... 227 28.6 ADC Electrical Specification... 228 28.7 RTC Operation Voltage... 228 28.8 Power Consumption... 228 29 PACKAGE DIMENSION... 229 Copyright 215, Advanced Digital Chips, Inc. 9 Contents

www.adc.co.kr Figures Figure 2-1 adstar-l Block Diagram... 18 Figure 2-2 adstar-l Pin Layout... 19 Figure 3-1 Memory Map... 26 Figure 4-1 Reset... 31 Figure 4-2 Power On Start Time Diagram... 32 Figure 4-3 Clock Scheme... 33 Figure 4-4 Main Oscillator Circuit... 34 Figure 4-5 32.768-KHz Oscillator Circuit... 34 Figure 4-6 PLL with External Filter... 35 Figure 4-7 PLL1 with External Filter... 36 Figure 4-8 Additional Clock Divider... 37 Figure 4-9 USB Clock... 38 Figure 4-1 TFT LCD Clock... 38 Figure 4-11 Sound Mixer Clock... 39 Figure 4-12 Wake-up process from Sleep mode... 41 Figure 4-13 Wake-up process from Stop mode... 41 Figure 4-14 Power Off for Shutdown/Static mode... 42 Figure 4-15 Wake-up process from Standby mode... 42 Figure 4-16 Wake-up process from Static mode... 43 Figure 5-1 Flash Memory Controller Block Diagram... 55 Figure 5-2 Internal Serial Flash Memory... 56 Figure 5-3 Serial Flash Memory Status Register 1... 59 Figure 5-4 Serial Flash Memory Status Register 2... 59 Figure 5-5 SCK and CS timing... 62 Figure 5-6 Flash Clock Delay Timing... 63 Figure 5-7 Access Two Flash... 67 Figure 6-1 GPIO Block Diagram... 68 Figure 8-1 External Interrupt Mode... 79 Figure 9-1 Pre-scaler Block Diagram... 87 Figure 9-2 Timer Operation... 88 Figure 9-3 core timer interrupt waveform... 89 Figure 1-1 Operational flow... 92 Figure 11-1 Pre-scaler Block Diagram... 93 Figure 11-2 Timer Operation... 94 Figure 11-3 PWM Operation... 96 Figure 11-4 Capture Mode Operation... 97 Figure 12-1 RTC Block Diagram... 12 Figure 12-2 Calibration Function Diagram... 12 Figure 12-3 Alarm Interrupt Operation... 111 Figure 12-4 1sec Interrupt Operation... 111 Figure 12-5 1/2 Interrupt Operation... 112 Figure 12-6 1/4 Interrupt Operation... 112 Figure 14-1 UART Block Diagram... 117 Figure 14-2 UART LCR Register Setting and Serial Data Format... 119 Figure 15-1 DMA Block Diagram... 128 Figure 15-2 DMA Transfer hierarchy... 129 Figure 15-3 Linked list... 13 Figure 15-4 Multi Block Transfer... 131 Figure 15-5 Gathering by using LLI... 132 Figure 15-6 Auto Reload Operation Transfer Hierarchy... 133 Figure 15-7 Scatter with Auto Reload Operation... 134 Figure 15-8 Gather with Auto Reload Operation... 135 Figure 15-9 DMA Handshake Signals... 136 Figure 15-1 Time Diagram of DMA Request... 137 Figure 17-1 NAND Flash Controller Block Diagram... 149 Figure 17-2 Read/Write Timing Diagram of NAND Flash Memory... 15 Figure 18-1 SDHC Block Diagram... 156 Figure 2-1 SPI Block Diagram... 165 Figure 2-2 Transfer Timing when CPHA =... 168 Figure 2-3 Transfer Timing when CPHA = 1... 169 Figure 2-4 SCK Phase and Polarity... 169 Figure 2-5 1-Byte Transfer vs. Status and Interrupt... 171 Figure 2-6 n-bytes Transfer vs. Status and Interrupt... 171 Figure 21-1 TWI Block Diagram... 175 Figure 21-2 TWI-Bus Interface Data Format... 176 Figure 21-3 Data Transfer on the TWI-Bus... 176 Figure 21-4 Acknowledgement of TWI... 177 Figure 21-5 Bus arbitration 1 of TWI... 178 1 Figures Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr Figure 21-6 Bus arbitration 2... 178 Figure 21-7 TWI Initialization Flow Char... 179 Figure 21-8 Master Transmit Flow Char... 18 Figure 21-9 Master Receive Flow Char... 181 Figure 21-1 Master combined format Flow Char... 182 Figure 21-11 Slave Mode Flow Chart (Polling)... 183 Figure 21-12 Slave Mode Flow Chart (Interrupt)... 184 Figure 21-13 Tcf interrupt wave form... 188 Figure 21-14 SCL Hold wave form... 188 Figure 22-1 Mixer Block Diagram... 189 Figure 22-2 Low pass filter for digital modulator... 19 Figure 22-3 Sound Mixer Pre-Scaler... 19 Figure 22-4 Sound Mixer output diagram... 191 Figure 23-1 ADC Block Diagram... 194 Figure 24-1 LCD Controller Block Diagram... 197 Figure 24-2 LCD Clock... 198 Figure 24-3 Flipping Structure with double buffering... 198 Figure 24-4 LCDC Horizontal, Vertical Sync / Active Signal Timing... 199 Figure 24-5 Horizontal Timing... 21 Figure 24-6 Vertical Timing... 21 Figure 25-1 JPEG Decoder Block Diagram... 27 Figure 25-2 Decoder Core Block Diagram... 28 Figure 29-1 Package Dimension... 229 Copyright 215, Advanced Digital Chips, Inc. 11 Figures

www.adc.co.kr Tables Table 2-1 adstar-l Pin Definitions 1-Pin... 2 Table 3-1 Peripheral Memory Map... 29 Table 3-2 Signals for boot mode... 3 Table 5-1 Instruction Set Table 1 (Erase, Program Instructions)... 57 Table 5-2 Instruction Set Table 2 (Read Instructions)... 58 Table 5-3 Instruction Set Table 3 (ID, Security Instructions)... 58 Table 5-4 Serial Flash Memory Status Register Description... 6 Table 6-1 Internal Pull-up Resistance Characteristics... 69 Table 8-1 Interrupt Vector & Priority... 78 Table 13-1 Real Memory map... 113 Table 13-2 Coprocessor Register Description... 113 Table 14-1 UART Baud Rate... 12 Table 14-2 UART Fractional Baud Rate... 12 Table 14-3 UART Register Summery... 121 Table 14-4 UART Interrupt Control Function... 123 Table 2-1 SPI Pin Functions... 166 Table 24-1 Typical VGA Timings... 2 Table 24-2 Register Values for VGA timing... 21 Table 24-3 LCD Controller Registers Table... 22 Table 26-1 Endpoint List... 215 Table 26-2 USB Core Register List... 215 Table 27-1 USB Host Register List... 225 Table 28-1 I/O DC Electrical Characteristic... 226 Table 28-2 I/O Recommended Operating Conditions... 226 Table 28-3 LDO Electrical Specifications... 226 Table 28-4 POR Specification (Unless otherwise specified, Topr=25 C, VDD=1.8V)... 227 Table 28-5 PLL DC Characteristics (Unless otherwise specified, Topr=25 C, VDD=1.8V)... 227 Table 28-6 PLL Input Frequency (Unless otherwise specified, Topr=25 C, VDD=1.8V)... 227 Table 28-7 ADC Recommended operating conditions... 228 Table 28-8 ADC DC Characteristics (Unless otherwise specified, Topr=25 C, VDD=1.8V)... 228 Table 28-9 Power Consumption from different conditions... 228 12 Tables Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr History Ver 1. June 29, 217 Ver 1.1 December 5, 217 1st version released Correct the description of the ADC Copyright 215, Advanced Digital Chips, Inc. 13 History

www.adc.co.kr 14 History Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr 1 DESCRIPTIONS AND FEATURES 1.1 General Description adstar-l 은최대 12MHz 의빠른동작속도를가진 32 비트마이크로컨트롤러이며특히칩내부에 내장되는메모리가기존의플래시메모리뿐만아니라 SDRAM 까지내장되어다양한어플리케이션에적용할 수있다. PART NAME FLASH SDRAM adstar-l8m - 8MB adstar-l8mf512 512KB 8MB adstar-l16m - 16MB adstar-l16mf512 512KB 16MB adstar-l 은칩외부에연결되거나내부에내장된 Quad Flash 로동작하게된다. Flash 는프로그램코드와 데이터용도로같이사용가능하며, 설정에의해 Quad 데이터비트를사용하여매우빠른접근이가능하다. 또한 Serial Debugger 를통하여빠른프로그램다운로드가가능하다. CPU 는프로그램메모리와데이터메모리를액세스하기위한버스를독립적으로구현되어있으며 ( 하버드 구조 ), 5 단파이프라인의 EISC 구조로매우빠른명령처리를수행한다. 별도의하드웨어로구성된 LCD Controller 는 RGB888 또는 RGB565 출력을지원하며동급최대 8x6 의해상도를지원하고 Hardware JPEG Decoding 을지원한다. 그리고, Graphic Library 을제공함으로써 adstar-l 칩하나만으로도 LCD 를사용하는스마트어플리케이션에최적의솔루션이된다. 이외에제공되는 MP3 Decoding Library 와 Sound Mixer 는음성, 효과음, 배경음등으로활용할수있으며 4 채널 12 비트 ADC(1MSPS) 는센서나외부데이터를활용할수있게한다. 또한외부에 FLASH Memory, SD Card 를확장할수있고특히 NAND FLASH 의경우 SLC Type 뿐만 아니라 24bit ECC 채용으로 MLC Type 을사용할수있으므로전체적인시스템단가를낮출수있다. 다양한통신수단으로는 USB 1.1 Full-Speed Device/Host, 2 채널 UART, 1 채널 SPI_LCD, 1 채널 SPI, TWI 등을제공하며 6 채널 DMA 는보다빠른수행을할수있게한다. 또한, 파워다운모드를지원한다. adstar-l 는스마트가전등의스마트어플리케이션, LCD 를사용하여 G.U.I 환경의공장자동화시스템, 출입통제시스템, 스마트그리드, 사인패드, 각종프린터, POS, 바코드시스템, POP 모니터등에적용할수 있다. 개발환경으로는 GCC 기반의컴파일러와소스편집및다운로드, 디버깅환경을제공하는 EISC STUDIO, 레퍼런스회로도, 각종 Library, 예제소스코드를에이디칩스홈페이지 (http://www.adchips.co.kr) 자료실에서아무런제약없이다운로드할수있으며, 개발보드와다운로드 / 디버깅툴인 E-con 은저렴한가격에판매를하고있다. 양산툴로는조립전의칩을 8 개의소켓이있는갱라이터로 WRITE 하는방법과칩이조립된상태의타겟보드의전원을이용하여 stand alone 타입의 EISC HANDY 로하나씩다운로드하는방법을제공한다. 15 1.1 General Description 1 Descriptions and Features Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr 1.2 Features High-performance, Low-power 32-bit EISC Microprocessor 32-bit EISC Architecture AE32C-Lucida Harvard Architecture 5-Stage Pipelining 1 Cycle 32bit MAC Up to 12MIPS Throughput at 12MHz 8KB 2-way Instruction Cache 8KB 2-way Data Cache Serial Wire Debugger Embedded Memory 2KBytes Internal SRAM for Instruction 1KBytes Internal SRAM for Data 8/16Mbytes SDRAM Optional 512KBytes Flash (More than 1, erase/program cycles) External Memory Interface 8-bit NAND Flash Interface supports SLC and MLC (4/24-bit ECC) type Boot Modes NAND Flash Booting Serial Flash Booting SWD Interface Extensive On-chip Debug Support Programming of Serial Flash, other Ram LCD Controller RGB 888 or 565 output Supports up to 8 x 6 resolution display in RGB mode SPI_LCD Interface Support 9bit data transfer for lcd control USB 1.1 Full-Speed Device/Host Compatible Supports Full-speed Data Rate 12Mbps SD-Card Interface Supports single/quad Sound Mixer 4ch mixing 1-ch PWM output for Stereo or 2-ch PWM output for mono (1-CH Digital Modulator) RTC Support RTC counter (hour, minute, second) and calendar counter (year, month, day, week) Support Alarm counter (month, day, hour, minute, second) Support periodic time tick interrupt with 14 period options 1/4sec, 1/2sec, 1sec, 2sec, 4sec, 12sec, 1min, 2min,4min, 16min, 1hour, 2hour, 4hour, 24hour Support wake-up function 16 1 Descriptions and Features 1.2 Features Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr Other Peripherals 32-bit Watchdog Timer 6-ch DMA Interrupt Controller with 2 External IRQ 2 Channel 16-bit Timer/Counter with 15-bit Pre-scaler, Capture, PWM 2 Channel UART with 16Bytes FIFO, Functionally compatible with the 1655, with 1Channel IrDA 1 Channel Master/Slave SPI with 8Bytes FIFO 1 Channel TWI Auto ECC NAND Flash Controller: 4-bit/24-bit ECC Support, Auto Booting with ECC Support 55-Port In/Out with open drain mode 55-Port GPIO JPEG Decoder Analog IPs 12-bit 1MSPS SAR ADC with 4 analog input channels POR (Power On Reset) LDO PLL x 2 Operating frequency Up to 12MHz Power 3.V to 3.6V Operating Temperature -4 / +85 Package 1-Pin QFP (14mm x 14mm) 17 1.2 Features 1 Descriptions and Features Copyright 215, Advanced Digital Chips, Inc.

Bus 2 AHB Bus 3 APB Bus 4 APB adstar-l www.adc.co.kr 2 BLOCK DIAGRAM & PIN DESCRIPTIONS 2.1 Block Diagram INTC GPIO Core Timer Fast IO SWD AC32C I-SPM 2KB I Cache 2-Way 8KB D Cache 2-Way 8KB D-SPM 1KB Bus 1 AHB # 2 512K Flash L8M, L16M Serial Flash Cntl # 1 512K Flash L8M_F512, L16M_F512 APB Bridge Sound Mixer SPI CRTC 12-bit ADC 4 Memory (8MB, 16MB) AHB Bridge DMA Controller JPEG TWI NAND Flash Cntl Timer 2ch. SDHC SPI_LCD APB Bridge URAT 2ch. Watchdog Timer USB Host 1.1 PINMUX USB PHY RTC_Ctrl USB Dev 1.1 RTC Figure 2-1 adstar-l Block Diagram 18 2 Block Diagram & Pin Descriptions 2.1 Block Diagram Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr 2.2 Pin Layout 6 7 8 9 1 11 12 13 14 15 16 17 18 19 1 99 2 GP. 21 GP.1 22 23 24 25 98 97 96 95 94 93 92 91 9 89 88 87 86 85 84 QFP 1-pin 14mm x 14mm 83 82 81 GP3.6 7 69 68 GP3.5 67 GP3.4 66 GP3.3 65 GP3.2 64 GP3.1 63 GP3. 62 GP2.7 61 GP2.6 6 59 58 57 56 55 54 53 52 51 VDD18 G[4] G[3] G[2] G[1] / DBG_SDA G[] / DBG_SCK GND VDD33 R[7] R[6] R[5] R[4] R[3] R[2] R[1] R[] VBAT RTC_XOUT RTC_XIN PWR_DN WAKEUP GND (RTC, LDO, BOD) VIN VOUT VDD18 SPI_LCD_CS# NAND_D[7] / SPI_LCD_SDI NAND_D[6] / SPI_LCD_SDO NAND_D[5] / SPI_LCD_SCL SD_CLK / NAND_D[4] SD_D[3] / NAND_D[3] / SPI_MOSI SD_D[2] / NAND_D[2] / SPI_MISO SD_D[1] / NAND_D[1] / SPI_CS# SD_D[] / NAND_D[] / SPI_SCL VDD33 GND NAND_WE# / SF_HOLD# NAND_ALE / SF_CLK NAND_CLE / SF_DI NAND_CE# / SF_CS1# NAND_RE# / SF_WP# NAND_BUSY# / SF_DO GND TWI_SDA TWI_SCL TX RX VDD33 26 27 28 29 3 31 32 33 34 35 36 37 38 39 4 41 42 43 44 45 46 47 48 49 5 VDD33 PMW1_N PMW1_P PWM_N PWM_P GND DOTCLK_I / TM_O[1] HSYNC DOTCLK AGND33 AVDD33 USB_AVDD33 USB_DM USB_AGND33 PLL_AVDD18 PLL_VCTR PLL_AGND18 PLL1_AVDD18 PLL1_VCTR1 PLL1_AGND18 TEST# RESET# GND DISP_EN VDD33 GND B[7] B[6] B[5] B[4] B[3] B[2] B[1] / EIRQ[1] B[] / EIRQ[] G[7] G[6] G[5] GND VREF AIN[3] AIN[2] AIN[1] AIN[] USB_DP VDD18 VDD33 XIN 1 2 3 4 5 GP6.6 GP.2 GP6.5 GP6.4 GP.3 GP.4 GP6.3 GP.5 GP.6 GP6.2 GP.7 GP6.1 GP1. 8 79 78 77 76 75 GP4.2 74 GP4.1 73 GP4. 72 GP3.7 71 SD_CMD / SF_CS# VSYNC / TM_O[] CFG[] CFG[1] CAP[] / TX1 CAP[1] / RX1 XOUT GP6. GP1.1 GP5.7 GP1.2 GP5.6 GP1.3 GP5.5 GP1.4 GP5.4 GP1.5 GP5.3 GP1.6 GP5.2 GP1.7 GP5.1 GP2. GP5. GP2.1 GP4.7 GP4.6 GP2.2 GP4.5 GP2.3 GP4.4 CFG[2] CFG[3] CFG[4] GP2.4 GP4.3 GP2.5 USB_HOST_I USB_HOST_O Figure 2-2 adstar-l Pin Layout 19 2.2 Pin Layout 2 Block Diagram & Pin Descriptions Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr 2.3 Pin Definition No. Pin Name Alt CFG Table 2-1 adstar-l Pin Definitions 1-Pin Description. 1 AGND33 ADC power ground In 2 VREF ADC analog voltage input reference In 3 AIN[3] ADC analog voltage input channel 3 In 4 AIN[2] ADC analog voltage input channel 2 In 5 AIN[1] ADC analog voltage input channel 1 In 6 AIN[] ADC analog voltage input channel In 7 AVDD33 ADC power supply 3.3 V In 8 USB_AVDD33 USB power supply 3.3 V In 9 USB_DP USB DP - data+ pin Bidi 1 USB_DM USB DM - data- pin Bidi 11 USB_AGND33 USB power ground In 12 PLL_AVDD18 PLL power supply 1.8V In 13 PLL_VCTR Vco control voltage of pll, corresponding LPF should be connected here In 14 PLL_AGND1 8 Power ground In 15 PLL1_AVDD18 PLL1 power supply 1.8V In 16 PLL1_VCTR Vco control voltage of pll1, corresponding LPF should be connected here In 17 PLL1_AGND1 8 Power ground In 18 TEST# Test mode entrance active low In 19 RESET# Reset of system active low In UART_TX1 Uart tx [1] 2 CAP_IN 1 Timer capture [] CFG[] 3 Booting Mode Select [] Bidi GP. General Purpose I/O UART_RX1 Uart rx [1] 21 CAP_IN1 1 Timer capture [1] CFG[1] 3 Booting Mode Select [1] In GP.1 General Purpose I/O 22 VDD18 Core power supply 1.8V In 23 VDD33 IO power supply 3.3V In 24 XIN Oscillator xin In 25 XOUT Oscillator xout Out 26 GND Power gournd Out SPI_LCD_CS# SPI_LCD chip select signal [1] 27 CFG[2] 3 Booting mode Select [2] In GP.2 General purpose I/O SPI_LCD_SDI SPI data input [1] 28 NAND_D[7] 1 Nand flash data [7] GP.3 General purpose I/O SPI_LCD_SD O SPI_LCD data output [1] 29 NAND_D[6] 1 Nand flash data [6] CFG[3] 3 Booting mode Select [3] GP.4 General purpose I/O SPI_LCD_SCL SPI_LCD clock [1] 3 NAND_D[5] 1 Nand flash data [5] CFG[4] 3 Booting mode select [4] GP.5 General purpose I/O NAND_D[4] 1 Nand flash data [4] 31 SD_CLK 2 SD card clock GP.6 General purpose I/O SPI_MOSI When SPI is configured to Master, It used for Data output, otherwise, Data input 32 NAND_D[3] 1 Nand flash data [3] SD_DATA[3] 2 SD card data [3] GP.7 General purpose I/O 33 SPI_MISO When SPI is configured to Master, It used for Data input, otherwise, Data output Type Bidi Bidi Bidi Bidi Bidi Bidi Output Drive Current 8mA 8mA 8mA 8mA 8mA 8mA Pull-Up / Pull- Down up, down or disable up, down or disable up, down or disable up, down or disable up, down or disable up, down or 2 2 Block Diagram & Pin Descriptions 2.3 Pin Definition Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr NAND_D[2] 1 Nand flash data [2] disable SD_DATA[2] 2 SD card data [2] GP1. General purpose I/O 34 SPI_CS# SPI chip select signal [] up, NAND_D[1] 1 Nand flash data [1] Bidi 8mA down or SD_DATA[1] 2 SD card data [1] disable GP1.1 General purpose I/O 35 SPI_SCL SPI clock [] up, NAND_D[] 1 Nand flash data [] Bidi 8mA down or SD_DATA[] 2 SD card data [] disable GP1.2 General purpose I/O 36 VDD33 IO power supply 3.3V In 37 GND IO power ground In SF_HOLD# Serial flash hold signal 38 NAND_WE# 1 Nand write enable Bidi GP1.3 General purpose I/O SF_CLK Serial flash clock up, 39 NAND_ALE 1 Nand address latch enable Bidi 8mA down or GP1.4 General purpose I/O disable SF_DI Serial flash data Input up, 4 NAND_CLE 1 Nand command latch enable Bidi 8mA down or GP1.5 General purpose I/O disable SF_CS1# Serial flash chip select 1 up, 41 NAND_CE# 1 Nand chip enable down or GP1.6 General purpose I/O disable SF_WP Serial flash write protection signal up, 42 NAND_RE# 1 Nand read enable Bidi 8mA down or GP1.7 General purpose I/O disable SF_DO Serial flash data out. data output signal. up, 43 NAND_BUSY 1 Nand busy check Bidi down or GP2. General purpose I/O disable SF_CS# Serial flash chip select up, 44 SD_CMD 1 SD card command Bidi down or GP2.1 General purpose I/O disable 45 GND Power ground Bidi 46 TWI_SDA TWI data line up, USB_HOST_I 1 USB host input Bidi 8mA down or N disable GP2.2 General purpose I/O 47 TWI_SCL TWI clock line up, USB_HOST_O 1 USB host output Bidi down or UT disable GP2.3 General purpose I/O up, UART_TX Uart tx [] 48 Bidi 8mA down or GP2.4 General purpose I/O disable UART_RX Uart rx [] up, 49 Bidi 8mA down or GP2.5 General purpose I/O disable 5 VDD33 IO power supply 3.3V In 51 VDD18 Core power supply 1.8V In 52 VOUT LDO voltage output 1.8V Out 53 VIN LDO voltage input 3.3V In 54 GND Power ground In 55 WAKEUP System wake up signal In 56 PWR_DN System power down signal Out 57 RTC_XIN RTC oscillator xin In 58 RTC_XOUT RTC oscillator xout Out 59 VBAT Battery voltage input In up, R[] LCD red out [] 6 Bidi 8mA down or GP2.6 General purpose I/O disable up, R[1] LCD red out [1] 61 Bidi 8mA down or GP2.7 General purpose I/O disable up, R[2] LCD red out [2] 62 Bidi 8mA down or GP3. General purpose I/O disable 63 R[3] LCD red out [3] Bidi 8mA up, 21 2.3 Pin Definition 2 Block Diagram & Pin Descriptions Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr GP3.1 General purpose I/O down or disable up, R[4] LCD red out [4] 64 Bidi 8mA down or GP3.2 General purpose I/O disable up, R[5] LCD red out [5] 65 Bidi 8mA down or GP3.3 General purpose I/O disable R[6] LCD red out [6] up, 66 Bidi 8mA down or GP3.4 General purpose I/O disable up, R[7] LCD red out [7] 67 Bidi 8mA down or GP3.5 General purpose I/O disable 68 VDD33 IO power supply 3.3V In 69 GND Power ground In G[] LCD green out [] up, 7 DBG_SCK 1 Debugger clock Bidi 8mA down or GP3.6 General purpose I/O disable G[1] LCD green out [1] up, 71 DBG_SDA 1 Debugger data Bidi 8mA down or GP3.7 General purpose I/O disable up, G[2] LCD green out [2] 72 Bidi 8mA down or GP4. General purpose I/O disable up, G[3] LCD green out [3] 73 Bidi 8mA down or GP4.1 General purpose I/O disable G[4] LCD green out [4] up, 74 Bidi 8mA down or GP4.2 General purpose I/O disable 75 VDD18 Core power supply 1.8V In 76 GND Power ground In up, G[5] LCD green out [5] 77 Bidi 8mA down or GP4.3 General purpose I/O disable up, G[6] LCD green out [6] 78 Bidi 8mA down or GP4.4 General purpose I/O disable up, G[7] LCD green out [7] 79 Bidi 8mA down or GP4.5 General purpose I/O disable B[] LCD blue out [] up, 8 EIRQ 1 External interrupt [] Bidi 8mA down or GP4.6 General purpose I/O disable B[1] LCD blue out [1] up, 81 EIRQ1 1 External interrupt [1] Bidi 8mA down or GP4.7 General purpose I/O disable B[2] LCD blue out [2] up, 82 Bidi 8mA down or GP5. General purpose I/O disable up, B[3] LCD blue out [3] 83 Bidi 8mA down or GP5.1 General purpose I/O disable B[4] LCD blue out [4] up, 84 Bidi 8mA down or GP5.2 General purpose I/O disable up, B[5] LCD blue out [5] 85 Bidi 8mA down or GP5.3 General purpose I/O disable B[6] LCD blue out [6] up, 86 Bidi 8mA down or GP5.4 General purpose I/O disable up, B[7] LCD blue out [7] 87 Bidi 8mA down or GP5.5 General purpose I/O disable 88 GND Power ground In 89 VDD33 IO power 3.3V In 9 DOTCLK LCD clock output Bidi 8mA up, 22 2 Block Diagram & Pin Descriptions 2.3 Pin Definition Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr GP5.6 General purpose I/O DISP_EN Display enable 91 Bidi GP5.7 General purpose I/O HSYNC Signal for horizontally synchronization 92 Bidi GP6. General purpose I/O VSYNC Signal for vertically synchronization 93 TM_OUT 1 Timer pwm output [] Bidi GP6.1 General purpose I/O LCD_CLK_IN Clock input (lcd controller) 94 TM_OUT1 1 Timer pwm output [1] Bidi GP6.2 General purpose I/O 95 GND Power ground In PWM_P GP6.3 (sound pwm positive output channel ) 96 Bidi GP6.3 General purpose I/O PWM_N GP6.4 (sound pwm negative output channel ) 97 Bidi GP6.4 General purpose I/O PWM1_P GP6.5 (sound pwm positive output channel 1) 98 Bidi GP6.5 General purpose I/O PWM1_N GP6.6 (sound pwm negative output channel 1) 99 Bidi GP6.6 General purpose I/O 1 VDD33 IO power supply 3.3V In * Alt CFG 는 pin mux 설정값에해당하는숫자이다. 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA down or disable up, down or disable up, down or disable up, down or disable up, down or disable up, down or disable up, down or disable up, down or disable up, down or disable 23 2.3 Pin Definition 2 Block Diagram & Pin Descriptions Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr 2.4 Pin Description VDD33, AVDD33, USB_AVDD33 : 3.3V Supply voltage 에연결하며서로연결되지않는독립전원이어야한다. PLL_AVDD18, PLL1_AVDD18 : 1.8V Supply voltage VDD18 : 1.8v supply voltage AGND33 : ADC Power Ground USB_AGND : USB Power Ground PLL_AGND, PLL1_AGND : PLL Power Ground GND : Power Ground TEST# : Chip Test pin (Low active) Chip test를위한핀이다. 이핀이 이면모든핀들이 Pin Mux 의 3rd 핀으로할당되어 Test Mode로진입하게된다. TEST# 은 active-low 테스트핀이고, 정상적인동작동안 high를유지한다. CFG[4:] : Booting Mode Select (3.4 Boot Mode 참고 ) Flash Booting, NAND Flash Booting 등을선택할수있다. AIN[3:] : ADC 에입력되는아날로그전압레벨이며디지털값으로변환된다. 4 채널 VREF : AIN 입력레벨에대한 Reference 이다. USB Pins: USB Device 와 Host 가공유. (4.4.14 USB PHY Control Register 참고 ) USB_DP : USB Data+ I/O USB_DM : USB Data- I/O EIRQ, EIRQ1 : External Interrupt Request Input Pins (8 Interrupt Controller 참고 ) 외부에서인터럽트를요청해야할경우사용. Serial Flash (5 SPI Flash Memory Controller 참고 ) SF_CS#, SF_CS1# : Serial Flash Chip Select SF_CLK, : Serial Flash Clock SF_DI : Serial Flash Data Input. Command, Address, Data 를입력받는신호. SF_DO : Serial Flash Data Out. Data 를출력하는신호. SF_WP : Serial Flash write protection 신호. SF_HOLD : Serial Flash hold 신호. NAND Flash (17 NAND Flash Controller 참고 ) NAND_CE: NAND Flash Chips Enable. NAND Flash 를활성화할때사용 NAND_ALE : NAND Flash Address Latch Enable. NAND Flash 에 address 를전송할때사용 NAND_CLE: NAND Flash Command Latch Enable. NAND Flash 에 command 를전송할때사용 NAND_WE# : NAND Flash Write Enable. NAND Flash 에 data 를저장할때사용 NAND_RE# : NAND Flash Read Enable. NAND Flash 에서 data 를읽을때사용 NAND_BUSY# : NAND Flash Busy signal input pin. NAND Flash 가 Busy 상태일때. NAND_D[7:] : NAND Flash 8-bit Data I/O. 24 2 Block Diagram & Pin Descriptions 2.4 Pin Description Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr LCD Controller : RGB 최대 888 출력. 최대 8x6 지원 (24 TFT LCD Controller 참고 ) CRTC_CLK_IN : LCD Controller 에서사용하는 Clock Input VSYNC : 수직동기신호 HSYNC : 수평동기신호 DISP_EN : Display Enable CRTC_CLK_OUT : LCD Clock Output R[7:] : Red Output 8-bit G[7:] : Green Output 8-bit B[7:] : Blue Output 8-bit PWM/Capture : 2 channels. (11 Timer 참고 ) TM_OUT, TM_OUT1 : PWM Output. CAP_IN, CAP_IN1 : Capture Input. 외부신호의주기나펄스폭을측정하기위한입력핀 SPI : 1 channel. (2 SPI 참고 ) SPI_CS# : SPI Chip select signal SPI_SCK : SPI Clock pin SPI_SDI : SPI 가 Master 일때 Data input, Slave 일때 Data output 으로사용 SPI_SDO : SPI 가 Master 일때 Data output, Slave 일때 Data input 으로사용 SPI_LCD : 1 channel. (19 SPI_LCD 참고 ) 9bit SPI 인터페이스방식의 LCD 모듈제어 SPI_LCD_CS# : SPI Chip select signal SPI_LCD_SCK : SPI Clock pin SPI_LCD_SDI : SPI Data input SPI_LCD_SDO : SPI Data output TWI (21 TWI 참고 ) TWI_SCL : TWI Serial Clock TWI_SDA : TWI Serial Data UART : 2 channels. Channel 은 UART only. Channel 1 은 IrDA 를지원. UART_RX : UART RX UART_TX : UART TX UART_RX1 : UART RX with IrDA supported UART_TX1 : UART TX with IrDA supported Sound Mixer : Digital Modulator 2 channels. (22 Sound Mixer 참고 ) SPWM_P, SPWM_N, SPWM1_P, SPWM1_N : Sound Mixer Digital Modulator PWM 출력. Sound Mixer 의출력에할당되어 Mono 일때 2channel, Stereo 일때 1channel 에해당한다. XIN, XOUT : 외부에서 2Mhz crystal 을연결한다. 25 2.4 Pin Description 2 Block Diagram & Pin Descriptions Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr 3 MEMORY ARCHITECTURE AND BOOTING MODES 3.1 Memory Map 메모리영역은아래의표와같이할당되어있다. (figure 3-1) xffff3fff xffff xbfffffff FIO Bus Reserved 2nd Bus xa x9fffffff 1st Bus x8 x4fffffff x4 x2fffffff Reserved Serial Flash Reserved SDRAM 8MB/16MB x2 x183ff x18 x17ff x1 xfffffff x Reserved Internal SRAM 1KB for Data Reserved Internal SRAM 2KB for Instruction Boot Area (NAND Boot: Internal SRAM 2KB, Serial Flash Boot) Figure 3-1 Memory Map 26 3 Memory Architecture and Booting modes 3.1 Memory Map Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr 3.2 Embedded Memories 2KB Internal SRAM for Instruction 1KB Internal SRAM for Data 3.2.1 Internal SRAM for Instruction adstar-l 은 Instruction 을위한 2KB SRAM 메모리가내장되어있다. 명령어또는데이터를저장하는용도로사용할수있으며주로명령어를저장하게된다. 명령어를읽는경우 1cycle 접근이가능하며데이터를읽는경우는 3 cycle 이소요된다. 3.2.2 Internal SRAM for Data adstar-l 은 Data 를위한 1KB SRAM 메모리가내장되어있다. 주로데이터를저장하는데사용되며, 데이터를읽는경우 1cycle 접근이가능하다. 3.2.3 Internal SRAM Registers Internal SRAM 전체를관장하는 1 개의 Global Control Register 를갖는다. 또한 Internal SRAM 은내부에 여러개의 Bank 로구성될수있으므로 Global Register 의 Configuration 에의해결정되는 Bank 개수만큼 Local Register Set 을갖는다. Local Register Set 는다음과같은 3 개의 32bit Register 로구성된다. - Local Internal SRAM Control Register - Local Internal SRAM Start Address - Local Internal SRAM End Address Internal SRAM Global Control Register Address : x7 - Global Control Register Bit R/W Description Default 31 : 28 R Exception Status h 4 b1 : DATA Access Violation 4 b1 : Instruction Access Violation 27 : 24 R Reserved h 23 : 2 R ibank Size: isram에서각 bank의 physical Memory 크기 4 h : 1 KB 4 h1 : 2 KB 4 h2 : 4 KB 4 h3 : 8 KB 4 h4 : 16 KB 4 h5 : 32 KB 4 h6 : 64 KB 4 h7 : 128 KB 4 h8 : 256 KB 19 : 16 R/W isram Configuration 4 h : 사용자에게 1 개의메모리덩어리로보임 4 h1 : Reserved h 4 h2 : 사용자에게 4 개의메모리덩어리로보임 (4개를넘는경우는현재구현되어있지않음 ) 15 : 12 R isram Enable 4 b1 : SRAM Enable 4 b : SRAM Disable 11 : 8 R dbank Size: dsram에서각 bank의 physical Memory 4 h : 1 KB 4 h1 : 2 KB 4 h2 : 4 KB 4 h3 : 8 KB 4 h4 : 16 KB 4 h5 : 32 KB 4 h6 : 64 KB 4 h7 : 128 KB 4 h8 : 256 KB h 27 3.2 Embedded Memories 3 Memory Architecture and Booting modes Copyright 215, Advanced Digital Chips, Inc.

7 : 4 R/W dsram Configuration 4 h : 사용자에게 1 개의메모리덩어리로보임 4 h1 : Reserved 4 h2 : 사용자에게 4 개의메모리덩어리로보임 (4개를넘는경우는현재구현되어있지않음 ) 3 : R dsram Enable 4 b1 : SRAM Enable 4 b : SRAM Disable www.adc.co.kr h h Internal SRAM Local Control Register Address : x71, x711 - Local isram Control Register Address : x74 - Local dsram Control Register Bit R/W Description Default 31 : 12 R Reserved h 11 : 8 R External Access: BUS 접근권한 4 h : External Access Not Support 4 h1 : External Access Support 7 : 4 R/W Privilege Mode: 사용자권한 4 h : Supervisor only Access 4 h1 : Supervisor/User Access 3 : R Enable 4 b1 : Local SRAM Enable 4 b : Local SRAM Disable h h Internal SRAM Local Start Address Register Address : x72, x712 - Local isram Start Register Address : x75 - Local dsram Start Register Bit R/W Description Default 31 : R/W SRAM Start Address h Internal SRAM Local End Address Register ADDRESS : x73, x713 - Local isram End Register ADDRESS : x76 - Local dsram End Register Bit R/W Description Default 31 : R/W SRAM End Address h 3.2.4 Internal SRAM Register Setting Internal SRAM 레지스터의설정은 GAP 를이용하기때문에 co-processor 레지스터접근명령어인 MVTC 와 MVFC 를사용하게된다. 예제. //#################################################### //## Internal SRAM Global Register Setting //#################################################### asm( ldi x7, %r ); asm( mvtc x, %r3 ); asm( ldi x2121, %r ); //#ON //#Num of Memory Bank: 4 asm( mvtc x, %r4 ); 28 3 Memory Architecture and Booting modes 3.2 Embedded Memories Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr 3.3 Peripheral Memory Map Register 영역은 8_h 부터존재하며각기능 Block 당 1Kbyte 씩할당되어있다. Memory mapped I/O 의형태로자세한내용은아래와같다 (Table 3-1) Table 3-1 Peripheral Memory Map Offset Address Block BUS Remark x8_ Flash Controller x8_4 SDRAM Controller x8_8 Reserved 1st x8_c Reserved AHB x8_1 Reserved x8_14 DMA Controller x82_ Watchdog Timer x82_4 Timer 2 Channels x82_8 UART (2nd ch. IrDA) 2 Channels x82_c ~x82_17ff Reserved x82_18 TWI x82_1c Reserved ~x82_23ff 1st x82_24 CRTC APB x82_28 ~x82_33ff Reserved x82_34 Pin Mux x82_38 RTC x82_3c System Control x83_ ~x83_ffff Reserved Offset Address Block BUS Remark xa_ USB Host xa_4 Reseved xa_8 SPI LCD 2nd xa_c NAND Flash Controller AHB xa_1 SDHC xa_14 Reserved xa_18 USB Device xa2_1 SPI xa2_14 Reserved xa2_18 Reserved xa2_1c Sound Mixer xa2_2 2nd Reserved ~xa2_37ff APB xa2_38 ADC Controller 12-bit ADC xa2_3c Reserved xa3_ ~xa3_ffff Reserved xffff_ (1) Interrupt Controller xffff_1 (1) Core Timer xffff_3 (1) GPIO (1) 녹색영역은 CPU 에의해내부적으로디코딩되고, 실제로버스에연결되어있지않다. 그래서 다른마스터에의해 access 되지않는다. 29 3.3 Peripheral Memory Map 3 Memory Architecture and Booting modes Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr 3.4 Boot Modes 외부 External Reset 이풀리는순간 CFG[4:] 핀의전압 Level 을통하여 booting 모드를 결정하고해당모드로부팅하게된다. Configuration 핀의할당순서는다음과같다. Table 3-2 부팅모드별로외부신호를나열하고각각의기능을설명. Table 3-2 Signals for boot mode Pin Functional Name Pin Name (refer to datasheet for pin numbers) CFG[] #2_GP. Debugger Mode or Boot Mode CFG[1] #21_GP.1 Boundary Scan or SWD logic selection CFG[2] #27_GP.2 Serial Flash Boot or Nand Flash Boot CFG[3] #29_GP.4 CFG[4] #3_GP.5 3.4.1 Debugger Mode CFG[]= 인경우에 Debugger mode 로부팅된다. 이모드에서는 CPU 는정지상태에놓여있으며사용자가 Debugger 를통하여 CPU 의프로그램수행동작을제어하게된다. 3.4.2 Boot Mode CFG[]=1 인경우에 Normal mode 로부팅된다. 이모드에서 CPU 는일반적인프로그램수행동작을진행한다. 부팅메모리는 CFG[4:2] 에의해정해진다. 3.4.3 Serial Flash Boot CFG[4:2] = 111 인경우에 Serial Flash 로부팅된다. 3.4.4 NAND Flash Boot CFG[4:2] 이 111 이나 11 이아닌경우에 NAND Flash 로부팅된다. 이모드에서는최초 NAND Flash 의 부트코드가내부 2KB 크기의 Internal SRAM 에복사가되며, 복사가끝나면 CPU 가복사된프로그램을 수행하게된다. CFG[4:2] NAND Boot Mode NAND Flash Type Small type 3-Cycle NAND Flash Small type Address 3 cycles 1 Small type 4-Cycle NAND Flash Small type Address 4 cycles 1 Large type 4-Cycle NAND Flash Large type Address 4 cycles 11 Large type 5-Cycle NAND Flash Large type Address 5 cycles 1 MLC 4-Bit ECC NAND Flash MLC type 4-bit ECC 11 MLC 24-Bit ECC NAND Flash MLC type 24-bit ECC 3.4.5 SWD Seleciton CFG[1] 핀을사용하여 PinMux 설정없이 JTAG, SWD 핀을선택할수있다. CFG[1] = 인경우 PinMux 설정은 JTAG(Boundary scan용 ) 이설정된다. CFG[1] = 1 인경우 PinMux 설정은 SWD(Debug 용 ) 가설정된다. 3 3 Memory Architecture and Booting modes 3.4 Boot Modes Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr 4 SYSTEM CONTROL System control 는 reset control, clock control, power control, and low-power modes 를포함한다. 4.1 Reset Control Reset controller 는 External Reset, Power on Reset, Debugger Reset 그리고 Watchdog Reset 으로구성되어 있다. 아래그림에전체 reset 들이표시되어있다. RESET# pin 은외부리셋신호에응답 (active LOW). device 는 reset 상태를벗어나면실행을시작한다. reset 중부트모드가결정되며, device 는부트모드를실행하기시작한다. config_done int_resetx ext_clk ext_resetx por_resetx wdt_resetx dbg_resetx all_resetx reset counter poc_resetx boot_resetx config_done sys_resetx Figure 4-1 Reset 시스템의 debugger reset 은 SWD 내부레지스터에 write 함으로써실행된다. 4.1.1 System Reset System Reset은다음과같은사항에서발생한다. 1. External Reset 2. Debugger Reset 3. Watchdog Reset 4. POR Reset 31 4.1 Reset Control 4 System Control Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr 4.1.2 Power On Start Time VDD33 에 3.3V 전원이인가되고, 내부 LDO 출력을통해 VDD18 에 1.8V 가안정적으로인가되면, POR Reset 이 release 된다. 이때, External Reset 이 release 되면, External Clock 으로동작하는 Startup 회로가동작하게된다. 이 Startup 회로는 Xin 이안정화되기전의오동작을방지하며, 내부 logic 에동시에 system reset 을 release 시켜준다. System reset 은 POR Reset 과 External Reset 이 release 되고 Xin clock 기준 124-cycle 이지난후 release 된다. 3.3V VDDIO (VDD33) CoreVDD (VDD18).9V 1.62V 1.8V 75ms 3ms POR Resetn External Resetn External Clock (Xin) Internal System Resetx Startup counter 124 cycles of Xin Figure 4-2 Power On Start Time Diagram 32 4 System Control 4.1 Reset Control Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr 4.2 Clock control Device 는두개의 on-chip PLL, 두개의 on-chip oscillators 를가지고있다. 세가지기본 clock source 가있다. 첫번째 clock input 은 main oscillator 에의해생성되고, 두번째 clock input 은선택사항으로 GP6.2(DOTCLK_I) input 이고, LCD module 등에사용된다. 세번째 clock 은 RTC oscillator clock input(32.768khz) 으로 RTC module 에사용된다. device 는두개의 PLL 이있다. 각각의 PLL 은 PLLCONx 레지스터에의해제어된다. PLL reference clock 은 XIN pin 으로부터받고, PLL1 reference clock 은외부 XIN input pin(dotclk_i input pin) 이고, 내부 clk16_ 은외부 XIN input pin(dotclk_i input pin) 으로부터온다. 모든 PLL 은 reset 후, power down 이된다. hclk_src_sel g hclk_cpu hclk_div_val[3:] g hclk_sdrctrl XIN #24 #25 XOUT Main OSC PLL 1 pll_clk 1/1~ 1/16 HCLK Max. 12MHz 1/2 PCLK Max. 6MHz g g g g g hclk_sdram hclk_intc hclk_gpio hclk_dma hclk_sf #94 GP6.2 (DOTCLK_I) clk16 sel[1:] clk16 div_val[3:] g g hclk_spi9 hclk_jpeg pll_clk 1/1 ~ 1/16 clk16_ g g hclk_usbd hclk_usbh g hclk_lcd clk16_1_sel[1:] clk16_1_div_val[3:] 1/1 ~ 1/16 clk16_1 g g g hclk_nand hclk_sdhc hclk_sys pll1_src_sel[1:] g g pclk_wd pclk_tm RTC_XIN #57 RTC OSC clk16_ PLL1 RTC Block pll1_clk g g g g g g g pclk_uart pclk_spi pclk_spi1 pclk_twi pclk_pmux (Digital Amp) pclk_lcd pclk_rtc #58 RTC_XOUT g pclk_sys Figure 4-3 Clock Scheme 대부분의경우, PLL 은높은성능을선정하지만, 전력소모의증가를초래할수있다. 낮은성능및전력 소비를줄이기위해, crystal clock 이선택될수있다. main crystal clock 과 PLL 는 HCLK and PCLK peripherals reference clock sources 로써사용된다. 33 4.2 Clock control 4 System Control Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr HCLK 과 PCLK 은각각 AHB 영역과 APB 영역에클럭을공급한다. 두클럭은동일한위상이며 2:1 의 주파수비의관계를갖고있다. HCLK 의최대주파수는 12Mhz 이며 PCLK 의최대주파수는 6Mhz 이다. HCLK 도메인은 CPU 와 AHB peripherals 에사용된다. PCLK domain 은 APB peripherals 에사용된다. HCLK 와 PCLK reference 는 main crystal clock 또는 PLL clock output 이될수있습니다. PCLK 은실제로 HCLK 도메인에서분주됩니다. 그래서, PCLK 과 HCLK 은 synchronous 이다. 모든 APB peripheral 은 PCLK 을사용하며, PCLK 도메인으로간주된다. 4.2.1 Main oscillator main oscillator 는 PLL 및 PLL1 대한 clock 소스로사용될수있다. 내부 PLL 를사용하지않는경우의 main oscillator 의주파수는 32 KHz 에서 27MHz. 이다. 내부의 PLL 을 사용하는경우 crystal 은 6KHz 부터 2.25MHz 의주파수범위이어야한다. main oscillator clock 을생성하기 위해사용될때, Figure 4-4 와같이 2 개의부하 capacitors 와함께외부크리스털 XIN 및 XOUT 핀사이에 연결할필요가있다. main oscillator 입력은대부분의내부모듈에사용된다. # 24 XIN # 25 XOUT 1M ~ 1M 32KHz ~ 27MHz 6KHz ~ 2.25MHz for PLL 1pf ~ 3pf 1pf ~ 3pf Figure 4-4 Main Oscillator Circuit 4.2.2 RTC oscillator (32KHz) RTC oscillator 는 RTC 블럭의 clock source 로사용된다. RTC oscillator 는 Static mode 를제외한모든 전력모드에서사용할수있다. Figure 4-5 에도시된바와같이 oscillator 는 RTC clock 을생성하는외부 크리스털회로가필요하다 # 57 RTC_XIN # 58 RTC_XOUT Rf 1Mohm Rd 6Kohm C1 8pF X-tal 32.768KHz C2 8pF Figure 4-5 32.768-KHz Oscillator Circuit 34 4 System Control 4.2 Clock control Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr 4.2.3 PLL PLL 은 reference 클럭으로 Main oscillator 를받는다. PLL 은 6KHz 에서 2.25MHz 범위의입력 clock 주파수를사용한다. PLL 은소프트웨어에의해사용할수있다. 프로그램으로 PLL 를활성화해야합니다. PLL lock 을기다린다음 clock 소스로 PLL 에연결한다. External LPF C1 47 nf # 13 PLL_VCTR C2 1.3 uf R2 68 Ω # 12 PLL_AVDD18 Main OSC CLK XIN 6KHz~ 2.25MHz PLL FOUT pll_clk PD OD[1:] R[3:] N[11:] PLLCON [28] [25:24] [19:16] [11:] Figure 4-6 PLL with External Filter PLL 가활성화되기전에올바르게설정해야합니다. 주요 OSC clock 은 PLL reference clock 의 source 이다. PLL 출력주파수는다음식으로부터계산된다 : Fout = XIN N R OD R 은입력분주비이고, 이는 R[3:] 에의해조절될수있다 : R[3:] Input Divider Ratio (R) 1 2 11 3 111 13 111 14 1111 15 N 은피드백루프의분할비율을나타낸다 (multiplier). 이는 N[11:] 에의해조절될수있다 N[11:] Feedback Divider Ratio (N),,1 2,,11 3 1111,1111,111 493 1111,1111,111 494 1111,1111,1111 495 35 4.2 Clock control 4 System Control Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr OD 출력분배기이고, 이는 OD[1:] 에의해조절될수있다 OD[1:] Output Divider Ratio (OD) Normal operation 1 divide by 2 1 divide by 4 11 divide by 8 예를들어, 만약 XIN이 1MHz이고, R[3:] 은 1, N[11:] 은 1, OD[1:] is 11 이면, Fout = 1 124 8 = 16 MHz 8 PLL을설정 ( PLL는 PLLCON 레지스터의 PLL power down bit를 으로 write하여사용할수있다 ) 4.2.4 PLL1 PLL1 은 6KHz 에서 2.25MHz 범위의입력 clock 주파수를사용한다. PLL1 은 disabled 은 reset 에 powered off 된다. External LPF C1 47 nf # 16 PLL1_VCTR C2 1.3 uf R2 68 Ω # 15 PLL1_AVDD18 pll1_src_sel[1:] clk_sel Main OSC clk GP6.2 XIN PLL 1 FOUT pll1_clk System clock clk 16_ 6KHz ~ 2.24MHz PD OD[1:] R[5:] N[11:] Main OSC clk PLLCON1 [28] [25:24] [21:16] Figure 4-7 PLL1 with External Filter PLL1 소스선택필드 (pll1_src_sel) 는레퍼런스클럭의소스를선택한다. 출력주파수의계산에대한자세한내용은 PLL 섹션을참조. [11:] 4.2.5 PLLx Clock Change 사용자는 System이동작하는중간에도 PLL clock의주파수를변경할수있다. PLL Clock Source를변경하거나 PLL 설정을변경하면 PLL Clock의주파수는변경된다. 그런데동작중에 PLL 주파수를변경하는것은시스템을불안정하게만들기때문에안정적인변경을위해서는시스템클럭을 External clock 동작시킨후에 PLL의주파수를변경해야한다. External Clock 과 PLL Clock 사이에변경은 Glitch Free Mux를통해이루어지므로언제든안정적인변경이가능하다. PLL 의설정을변경하게되면 PLL 에서변경된주파수의 Clock 이나오기까지 Lock time 이소요된다. Lock time 은 Max 2ms 이다. 사용자는 PLL 변경한후 Lock time 이지난후에시스템클럭을 PLL 클럭으로변경해야한다. 36 4 System Control 4.2 Clock control Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr 4.2.6 Clock gating 각각의주변장치는개별클럭과시스템제어기및 HCLKEN PCLKEN 레지스터비트를이용하여게이트 on/off 할수있다. 이비트는모든 reset 후삭제된다. Clock off 전에, peripheral 이실행되지않았는지확인 한다. 비활성화된클럭을가지고어떤버스액세스가 peripheral 에에러종료를생성한다. 4.2.7 Additional Clock Divider 각고정된디바이더의정수값또는분별값으로입력기준주파수를분할하는기능을갖는다. 레퍼런스클럭주파수는원하는출력주파수를달성하도록선택되어야한다. clk15_sel[1:] clk25_sel[1:] main osc clk GP6.2 input pll_clk pll1_clk 1/1.5 clk15 main osc clk GP6.2 input pll_clk pll1_clk 1 / 2.5 clk25 clk45_sel[1:] clk5_sel[1:] main osc clk GP6.2 input pll_clk pll1_clk 1 / 4.5 clk45 main osc clk GP6.2 input pll_clk pll1_clk 1 / 5 clk5 clk256_sel[1:] main osc clk GP6.2 input pll_clk pll1_clk 1 / 256 clk256 Figure 4-8 Additional Clock Divider 37 4.2 Clock control 4 System Control Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr 4.2.8 USB Clock USB Host/Device 는 Figure 4-9 에도시된바와같이두개의 clock source 에서 clock 이공급된다. usb_clk_sel usb_clk_div_val pll_clk pll1_clk 96MHz 1/2 48MHz 48MHz A B Z usb48_clk g g usb48_clk device usb48_clk host 48MHz 96MHz 1/4 1/8 12MHz 12MHz A B Z usb12_clk g g usb12_clk device usb12_clk host Figure 4-9 USB Clock Figure 4-9 에도시된바와같이, USB 클럭에대한두가지소스는두개의 PLL 에서각각 clock 을 받는다. usb48_clk 주파수는 48MHz 로해야하며, usb12_clk 주파수는작동을위해 12MHz 로해야한다. 4.2.9 TFT LCD Clock LCD 컨트롤러는세가지기본클럭을사용한다 : hclk_lcd, pclk_lcd, DOTCLK. hclk_lcd 과 DOTCLK 은비동기이다 LCD module 은 Figure 4-1 에도시된바와같다. lcd_clk_sel[2:] clk16_ clk16_1 clk15 clk25 clk45 clk5 clk256 main osc clk lcd_clk_div_val[3:] 1/1~ 1/16 g A Z B A S DOTCLK LCDCON[22] Figure 4-1 TFT LCD Clock LCD Controller SPI 9bit clk Z GP5.6 (DOTCLK) #9 Figure 4-1 에도시된바와같이, DOTCLK 에대한 8 개의가능한소스가있다. 선택된클럭은추가로 LCD 모듈에가기전에 1 ~ 1/16 까지모든비율로분할될수있다. DOTCLK 또한핀에출력된다. 38 4 System Control 4.2 Clock control Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr 4.2.1 Sound Mixer Clock Sound Mixer module 은 Figure 4-11 에도시된바와같이 clock 을생성할수있다. clk16_ clk16_1 clk15 clk25 clk45 clk5 clk256 main osc clk dm_clk_sel[2:] dm_clk_div_val[3:] 1/1~ 1/16 g MCLK Figure 4-11 Sound Mixer Clock Sound Mixer Clock Figure 4-11 에도시된바와같이, MCLK 를위한 8 개의가능한소스가있다. 선택된클럭은추가로음향 믹서모듈가기전에 1 ~ 1/16 까지모든비율로분할될수있다. 4.2.11 Protection Mechanism adstar-l 은시스템제어레지스터에 write 접근하기위해두단계절차를필요로한다. 첫번째는절차는 GLOCK 레지스터에 xe5511acc 값을 write 하여 unlock 을시켜야한다. 이것은모듈의 모든레지스터들을해제한다. (GLOCK 레지스터는시스템제어모듈에서중요한레지스터에우발적인쓰기를방지하기위해필요하다.) 두번째절차는필요한각각의레지스터를 write 하려면 WREN 레지스터의각각의비트를활성화하여야 한다. 39 4.2 Clock control 4 System Control Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr 4.3 Power modes 전력관리컨트롤러의다수의전원옵션은사용자가필요한사용자애플리케이션에대한전력소비를 최적화할수있도록제공한다. 파워모드는인수로모드인덱스번호를취하는정지명령에의해선택된다. Modes CPU Clock Main OSC Main domain Power RTC OSC RTC domain power Sleep(Halt3) Off On On On On RESET#, Interrupt Source Stop(Halt2) Off Off On On On RESET# Event Source, Wake-up Shutdown(Halt1) Off Off Off On On RTC Alarm Wake-up Reboot from Power-up Static(Halt) Off Off Off Off On Wake-up Reboot from Power-up Exit 4.3.1 RUN mode Run mode 는칩에대한정상작동모드이다. 이모드는모든리셋후입력된다. RUN mode 는모든 clocks 을활성화하고, 소프트웨어실행및주변동작을허용한다. 이모드에서전력소비를줄여야한다면, 사용하지않는클럭은그에상응하는클럭의제어에서사용하지않도록레지스터를설정하여전력소모를줄일수있다. (AHBCLKEN, APBCLKEN). 4.3.2 Sleep mode Halt3 명령은 CPU 와 SPM 의 memorys 을중단한다. CPU clock 은정지하고, 칩의나머지는동작을수행한다 wake up 소스는인터럽트이다. 인터럽트는 active high level 이어야 wake up 소스로사용할수있다. - CPU is disabled. - SPM is disabled. Wake-up from Sleep mode(halt3) 4 4 System Control 4.3 Power modes Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr debug irq cap over irq rtc alarm irq rtc irq wdt irq dma irq[5] or GP3 or GP6 irq dma irq[4] or GP2 or GP5 irq dma irq[3] uart irq[1] INTC Interrupt CPU GP1 or GP4 irq adc irq dma irq[2] pmc irq timer irq[1] dma irq[1] : no effect 1 : Wake-up bit-wise AND Main Power Management Controller (MPMC) Wake-up process from Sleep mode uart irq[] GP irq IWEFH3R dma irq[] timer irq[] EIRQ[] Figure 4-12 Wake-up process from Sleep mode 4.3.3 Stop mode 모든 clock 은정지하지만 RTC oscillator 와 RTC block 은동작한다. Wake up 소스는 RTC 또는외부입력 핀이다. - The PLLs are disabled - The Main OSC is disabled - RAM is retention Wake-up from Stop mode(halt2) #55 WAKEUP pin usb rx rtc alarm irq GP6.2 GP6.1 GP4.7 / EIRQ[1] GP4.6 / EIRQ[] GP3.7 / DBG SDA GP2.5 / UART RX GP2.2 / TWI SDA GP.1 / UART RX1 Polarity/ Mask EWEFH2R Main Power Management Controller (MPMC) PMC irq Figure 4-13 Wake-up process from Stop mode INTC CPU 41 4.3 Power modes 4 System Control Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr 4.3.4 Shutdown mode 메인전력도메인의전력이제거되고, 누설전류를감소한다. RTC 발진기, RTC 로직블록을포함하여소량의전원만유지한다. 외부전압조정기가파워다운과함께사용되는경우에만, shutdown 모드가가능하다. RTC 블록은 VBAT 에의해구동. 장치가셧다운모드에진입하면, 외부레귤레이터는턴오프된다. adstar-l VDD_SDRAM VDD_Flash Main Power Domain VDDIO Power Supply IN OUT 3.3V VDDIN LDO PD 3.3V Regulator off on VDDOUT VDDCORE 1.8V wakeup event Power Management PIN_rpd off on External Wakeup signal PIN_rwake RTC Power Doamin VDD_RTC 1.8V~3.6V Backup Battery + - Figure 4-14 Power Off for Shutdown/Static mode Wake-up sources 는 RTC interrupts, external wake-up pin 이다 Wake-up from Shutdown mode (Halt1) #55 WAKEUP pin rtc irq RTC Power Management Controller Power-up Power-on Reset CPU Booting rtc alarm irq * Do not use both rtc_irq and rtc_alarm_irq simultaneously. One of them must be used as wake-up signal. Figure 4-15 Wake-up process from Standby mode 42 4 System Control 4.3 Power modes Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr 4.3.5 Static mode RTC 발진기및 RTC 블록을포함한모든클럭은중지된다. Wake up 소스는외부 wake up pin 이다. - RTC OSC is disabled. Wake-up from Static mode (Halt) #55 WAKEUP pin RTC Power Management Controller Power-up Power-on Reset CPU Booting * Both rtc_irq and rtc_alarm_irq should be de-active when using Halt Figure 4-16 Wake-up process from Static mode 4.4 System Control Registers system register 에접근하기위해서는해당비트를셋해줘야한다. 4.4.1 System Control Global Lock Register (GLOCK) Address : x82_3c 31: W xe5511acc 를 write 하면 unlock 이된다. Unlock 된상태여야다른레지스터에쓰기가허용된다. Lock 은그외값을쓰게되면 lock 상태가된다. R Read 동작은 lock 상태인지를확인할수있다. : lock 상태 1 : unlock 43 4.4 System Control Registers 4 System Control Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr 4.4.2 System Control Write Enable Register (WREN) Address : x82_3c4 31:2 R Reserved - 19 R/W DM Clock Divider register 18 R/W LCD Clock Divider register 17 R/W CLK16_1 Divider register 16 R/W CLK16_ Divider register 15 R/W HCLK Divider register 14 R Reserved - 13 R/W USB PHY Control Register Write Enable 12 R/W PCLK Control Register Write Enable 11 R/W HCLK Control Register Write Enable 1 R/W Sound Clock Control Register Write Enable 9 R/W PLL Control Register Write Enable 8 R/W Clock Control Register Write Enable 7:4 R Reserved - 3 R/W OSC stable counter Register Write Enable - 2 R/W Interrupt Wakeup Enable register 1 R/W Reserved - R/W halt register enable (Effective CPU halt instruction enable bit) 1 - Disable write protection for the corresponding register. - Enables write protection for the corresponding register * 이레지스터를사용하려면, GLOCK 레지스터의잠금을해제해야한다. * CPU 의 Halt 명령으로 PMC 를제어하기위해서는 bit[] 를 1 로 set 해야한다. * Halt 명령으로 sleep mode 가된 core 를깨우려면, 인터럽트를발생시켜야한다. 4.4.3 Halt Register Address : x82_3c8 31:5 R Reserved - 4: W 1 : halt 11 : halt1 12 : halt2 13 : halt3 (cpu, spm clock off) PCLK 의 one pulse 신호이다. write 된 data 가유지되지않는다. * 이레지스터를사용하려면, WREN register 에 halt register enable 비트를 enable 시켜줘야한다. * CPU halt 명령어도이 register 를접근하기때문에, 쓰기접근이활성화되어있어야한다. * Halt 명령으로 sleep mode 가된 core 를깨우려면, 인터럽트를발생시켜야한다. 44 4 System Control 4.4 System Control Registers Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr 4.4.4 Halt Status Register Address : x82_3cc 31:11 R Reserved - 1 R PMC IRQ 인터럽트발생유무를알수있다. PMU Status reg[] 에서도확인할수있다. 9 R RTC wakeup event latch. Halt나 Halt1에서깨어났음을알수있다. 8 R/W Cpu only clock disable during halt3 : cpu, spm clock off when halt3 excuting 1 : cpu only clock off 7:5 R Reserved. - 4: R 12 : halt2 13 : halt3 수행된 halt 모드를알수있다. Main 파워가 off 되는 halt 와 halt1 은상태를알수없다. 모두 clear 가되기때문이다. * 이레지스터를사용하려면, WREN register 에해당하는비트를 enable 시켜줘야한다 45 4.4 System Control Registers 4 System Control Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr 4.4.5 Interrupt Wake up Enable Register Address : x82_3c1 Halt 3 모드에서만, - Wakeup 시사용할 Interrupt 종류를선택한다. IRQ 는 reg 순서와동일하다. 깨어날때사용할 IRQ 를선택하면된다. (debug irq 가포함 ) PMC irq 도포함. RTC irq RTC wakeup irq 여기서활성화된인터럽트에의해서만 CPU 의 HCLK 가살아나게됨. 인터럽트처리와는무관하다. CPU 클럭만살린다. 해당하는인터럽트에의해서 Halt3 이후 ISR 처리를위해서는인터 럽트컨트롤러를적절히설정해야지만처리가된다. 이 register 단지 cpu 클럭만깨우는데관여한다. ISR 과는무관하다. 31 R/W SWD Interrupt Use edge method Clock_ctrl_r[] 3 R/W MJPEG 1 Interrupt 29 R/W Capture Over Interrupt 28 R/W SPI LCD Interrupt 27 R/W RTC Alarm Interrupt 26 R/W RTC Interrupt 25 R/W TWI Interrupt 24 R/W NAND Interupt 23 R/W WDT Interrupt 22 R/W DMA CH5 Interrupt, GPIO 3 interrupt, GPIO 6 interrupt 21 R/W SDCard Interrupt 2 R/W DMA CH4 Interrupt, GPIO 2 Interrupt, GPIO 5 Interrupt 19 R/W MJPEG Interrupt 18 R/W SPI Interrupt 17 R/W DMA CH3 Interrupt 16 R/W UART 1 Interrupt 15 R/W GPIO 1 Interrupt, GPIO 4 Interrupt 14 R/W USB host interrupt, Device Interupt 13 R/W ADC Interrupt 12 R/W DMA CH2 Interrupt 11 R/W PMC interrupt 1 R/W Timer 1 Interrupt 9 R/W DMA CH1 Interrupt 8 R/W UART Interrupt 7 R/W GPIO Interrupt 6 R/W DMA CH Interrupt 5 R/W LCD Frame sync Interrupt 4 R/W EIRQ1 Interrupt 3 R/W Sound Mixer Interrupt 2 R/W Timer Interrupt 1 R/W Core timer Interrupt R/W EIRQ Interrupt (Highest Priority) * 이레지스터를사용하려면, WREN register 에해당하는비트를 enable 시켜줘야한다. * halt3 (sleep mode) 상태에서 wakeup 할때, 어떤 interrupt 에의해 wakeup 할지결정해주는 register 이다. 46 4 System Control 4.4 System Control Registers Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr 4.4.6 Event Wake up Enable Register Address : x82_3c14 31:27 R Always awake by the RTC wakeup signal. This is not an option - 26 R/W SWD interrupt mask : mask 1: unmask 25 R/W Usb receive data mask : mask 1: unmask 24 R/W Rtc alarm interrupt mask : mask 1: unmask 23 R/W Gp6.2 mask : mask 1: unmask 22 R/W GP6.1 mask : mask 1: unmask 21 R/W GP4.7 mask : mask 1: unmask 2 R/W GP4.6 mask : mask 1: unmask 19 R/W GP3.7 mask : mask 1: unmask 18 R/W GP2.5 mask : mask 1: unmask 17 R/W GP2.2 mask : mask 1: unmask 16 R/W GP.1 mask : mask 1: unmask 15:11 R Reserved _ 1 R/W SWD interrupt Polarity : active low 1: active high 9 R/W Usb receive data Polarity : active low 1: active high 8 R/W Rtc alarm interrupt Polarity : active high 1: active low 7 R/W GP6.2 Polarity : active low 1: active high 6 R/W GP6.1 Polarity : active low 1: active high 5 R/W GP4.7 Polarity : active low 1: active high 4 R/W GP4.6 Polarity : active low 1: active high 3 R/W GP3.7 Polarity : active low 1: active high 2 R/W GP2.5 Polarity : active low 1: active high 1 R/W GP2.2 Polarity : active low 1: active high R/W GP.1 Polarity : active low 1: active high * 이레지스터를사용하려면, WREN register 에해당하는비트를 enable 시켜줘야한다 * halt2 (stop mode) 상태에서 wakeup 할때, 어떤 interrupt 에의해 wakeup 할지결정해주는 register 이다. * 이신호는 PCM_IRQ 로통합된다. PMC ISR 루틴이수행된다. 그리고이 register 를읽으면어떤 wake up source 에의해 wake up 이발생했는 지알수있다. Halt2 상태로진입중에발생한 wake up event 는무시가된다. 진입이완벽하게이뤄진뒤에 wake up event 가발생하면, 깨어나기시작한다. 47 4.4 System Control Registers 4 System Control Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr 4.4.7 PMC Status Register Address : x82_3c18 31:2 R Reserved. - 1 R/W RTC s/w reset : release reset(normal operation state) 1 : reset asserted R/W PMC IRQ clear bit Read 하면 IRQ 발생유무확인 1 을 Write 하면 clear 함.( write 할필요없음, 자동 clear 됨 ) PMC IRQ 는 halt2, halt1, halt 에서발생한다. Halt3 에서는발생하지않는다. Halt 3 에서는 Wake 를한블록의 irq 를고려하면된다. 4.4.8 OSC Stable Counter Register Address : x82_3c1c 31:11 R Reserved. - 1 : R/W Wake 시사용될 osc stable coutner 의 value 이다. 11 h7ff * 이레지스터를사용하려면, WREN register 에해당하는비트를 enable 시켜줘야한다 4.4.9 Clock Control Register (CLKCON) Address : x82_3c2 31:24 R Reserved. - 23:2 R/W ADC Clock divider : System Clock 1: System Clock / 2 1: System Clock / 3 11: System Clock / 4 111: System Clock / 15 1111: System Clock / 16 12:8 R/W PLL Lock Counter value for halt2 5 h1f 7:4 R Reserved. - 5 : 4 R/W PLL1 clock source select. These bits select the PLL1 clock source. :xin clock selected 1:GPIO clock selected 1x:clk16_ clock selected 3 R/W USB Clock Enable : USB clock is off 1: USB clock is on 2 R/W USB Clock divider. USB requires 48MHz clock. : USB Source Clock (when source clock is 48MHz) 1: USB Source Clock / 2 (when source clock is 96MHz) 1 R/W USB Source Clock Select. : pll_clk selected 1: pll1_clk selected R/W Select clock source for HCLK domain : XIN input selected 1: PLL clock selected * 이레지스터를사용하려면, WREN register 에해당하는비트를 enable 시켜주고, GLOCK register 를해제 시켜줘야한다 48 4 System Control 4.4 System Control Registers Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr 4.4.1 PLL Control Register (PLLCON) Address : x82_3c24 31 : 29 Reserved - 28 R/W PLL Power Down 1 : normal operation 1 : power down 27 : 26 R Reserved - 25 : 24 R/W OD (Output divider). These bits set the output divider value for the PLL. : divide by 1 1 : divide by 4 1 : divide by 2 11 : divide by 8 23 : 2 R Reserved - 19 : 16 R/W R (Input divider). These bits set the input divider value for the PLL. 2h R must be >=2 or unpredictable operation results. 15 : 12 R Reserved - 11 : R/W N (Multiplier). These bits set the multiplier value for the PLL. N must be >=2 or unpredictable operation results. 2h * 이레지스터를사용하려면, WREN register 에해당하는비트를 enable 시켜주고, GLOCK register 를해제 시켜줘야한다 * FOUT = (XIN*N)/(R*OD) 49 4.4 System Control Registers 4 System Control Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr 4.4.11 Clock Divider Control Register (CLKDCON) Address : x82_3c28 31:28 R Reserved - 27:25 R/W DM clock source select. : clk16_ 1: clk16_1 1: clk15 11: clk25 1: clk45 11: clk5 11: clk256 111: XIN 24:22 R/W LCD clock source select. : clk16_ 1: clk16_1 1: clk15 11: clk25 1: clk45 11: clk5 11: clk256 111: XIN 21:2 R/W CLK16_1 clock source select. : XIN 1 : GPIO 1 : PLL1 19:18 R/W CLK16_ clock source select. : XIN 1 : GPIO 1 : PLL 17:16 R/W CLK256 clock source select. : xin 1: GPIO clock 1: pll 11: pll1 15:14 R/W CLK5 clock source select. : xin 1: GPIO clock 1: pll 11: pll1 13:12 R/W CLK45 clock source select. 1 : xin 1: GPIO clock 1: pll 11: pll1 11:1 R/W CLK25 clock source select. : xin 1: GPIO clock 1: pll 11: pll1 9:8 R/W CLK15 clock source select. : xin 1: GPIO clock 1: pll 11: pll1 7: R Reserved - * 이레지스터를사용하려면, WREN register 에해당하는비트를 enable 시켜주고, GLOCK register 를해제 시켜줘야한다. 5 4 System Control 4.4 System Control Registers Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr 4.4.12 AHB Clock Enable Register (HCLKEN) Address : x82_3c2c 31 R/W bus clock enable 1 3:16 R Reserved. - 15 R/W SD Card IO clock enable 1 14 R/W NAND clock enable 1 13 R/W CRTC clock enable 1 12 R/W USB Host Clock Enable 1 (12MHz, 48MHz, bus clock) 11 R/W USB Device Clock Enable 1 (12MHz, 48MHz, bus clock) 1 R Reserved. - 9 R Reserved. - 8 R/W H/W JPEG AHB Clock Enable 1 7 R/W SPI LCD Clock Enable 1 6 R/W Flash Controller Clock Enable 1 5 R/W DMA Clock Enable 1 4 R/W GPIO Clock Enable 1 3 R/W Interrupt Controller Clock Enable 1 2 R/W SDRAM Clock Enable 1 1 R/W SDRAM Controller Clock Enable 1 R Reserved. 1 * 이레지스터를사용하려면, WREN register 에해당하는비트를 enable 시켜주고, GLOCK register 를해제 시켜줘야한다. 4.4.13 APB Clock Enable Register (PCLKEN) Address : x82_3c3 31 R/W Bus clock Enable 1 PMU block signal. Power management is not available without this clock.(halt3) 3:16 R Reserved. - 14 R/W RTC interface clock enable 1 13 R/W CRTC clock enable 1 12 R/W Pin MUX Clock Enable 1 11 R/W ADC APB Clock Enable 1 1 R Reserved. - 9 R Reserved. - 8 R/W Sound Mixer APB Clock Enable 1 7 R/W TWI Clock Enable 1 6 R/W Reserved. 1 5 R/W SPI Clock Enable 1 4 R/W UART Clock Enable 1 3 R/W Timer Clock Enable 1 2 R/W Watch Dog Timer Clock Enable 1 1 R Reserved. - R Reserved. - * 이레지스터를사용하려면, WREN register 에해당하는비트를 enable 시켜주고, GLOCK register 를해제 시켜줘야한다. 51 4.4 System Control Registers 4 System Control Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr 4.4.14 USB PHY Control Register (USBPHYCON) Address : x82_3c34 31:18 R Reserved - 17 R/W Reserved 1 16 R/W Reserved 15: 9 R Reserved - 8 R/W USB Function Select bit : USB Device 1: USB Host 7 R USB PHY suspend bit : No effect 1: Suspend 6 R/W D- Pull-down Enable bit : Pull-down Disable 1: Pull-down Enable 5 R/W D+ Pull-down Enable bit : Pull-down Disable 1: Pull-down Enable 4 R/W Receive Enable bit : USB PHY 가외부신호를받아들이지않는다. 1: USB PHY가외부신호를받아들인다. 3 R/W D- Weak Pull-up Enable bit : Pull-up Disable 1: Pull-up Enable 2 R/W D- Pull-up Enable bit : Pull-up Disable 1: Pull-up Enable 1 R/W D+ Weak Pull-up Enable bit : Pull-up Disable 1: Pull-up Enable R/W D+ Pull-up Enable bit : Pull-up Disable 1: Pull-up Enable * 이레지스터를사용하려면, WREN register 에해당하는비트를 enable 시켜주고, GLOCK register 를해제 시켜줘야한다. 4.4.15 Boot mode status register(bmst) Address : x82_3c38 31:1 R Reserved - R Boot mode : normal mode or debug mode.. etc 1: nandboot mode 1 * 이레지스터를사용하려면, WREN register 에해당하는비트를 enable 시켜주고, GLOCK register 를해제 시켜줘야한다. 4.4.16 Boot mode config register(bmct) Address : x82_341c (pin mux register) 31:5 R Reserved - 4 : 2 R : NAND Boot Small 3C 111b 1 : NAND Boot Small 4C 1 : NAND Boot Large 4C 11 : NAND Boot Large 5C 1 : NAND Boot MLC 4-bit 11 : NAND Boot MLC 24-bit 11 : Serial Flash boot 111 : Serial Flash boot 1 R Reserved 1 R : Debug boot 1 : Normal boot 1 52 4 System Control 4.4 System Control Registers Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr 4.4.17 HCLK clock divide register(hclkdiv) Address : x82_3c3c 31:5 R Reserved - 4 R/W Synchronization bit 1로설정하면 synch 가되고, 다시 으로반드시설정해준다. 3: R/W AHB Clock Select : Source Clock 1: Source Clock / 2 1: Source Clock / 3 11: Source Clock / 4 111: Source Clock / 15 1111: Source Clock / 16 * 이레지스터를사용하려면, WREN register 에해당하는비트를 enable 시켜주고, GLOCK register 를해제 시켜줘야한다. 4.4.18 CLK16_ clock divide register(clk16div) Address : x82_3c4 31:5 R Reserved - 4 R/W Synchronization bit 1로설정하면 synch 가되고, 다시 으로반드시설정해준다. 3: R/W CLK16_ Clock Select : Source Clock 1: Source Clock / 2 1: Source Clock / 3 11: Source Clock / 4 111: Source Clock / 15 1111: Source Clock / 16 * 이레지스터를사용하려면, WREN register 에해당하는비트를 enable 시켜주고, GLOCK register 를해제 시켜줘야한다. 4.4.19 CLK16_1 clock divide register(clk16div1) Address : x82_3c44 31:5 R Reserved - 4 R/W Synchronization bit 1로설정하면 synch 가되고, 다시 으로반드시설정해준다. 3: R/W CLK16_1 Clock Select : Source Clock 1: Source Clock / 2 1: Source Clock / 3 11: Source Clock / 4 111: Source Clock / 15 1111: Source Clock / 16 * 이레지스터를사용하려면, WREN register 에해당하는비트를 enable 시켜주고, GLOCK register 를해제 시켜줘야한다. 4.4.2 LCD clock divide register(lcddiv) Address : x82_3c48 31:5 R Reserved - 4 R/W Synchronization bit 1로설정하면 synch 가되고, 다시 으로반드시설정해준다. 3: R/W LCD Clock Select : Source Clock 1: Source Clock / 2 1: Source Clock / 3 11: Source Clock / 4 111: Source Clock / 15 1111: Source Clock / 16 * 이레지스터를사용하려면, WREN register 에해당하는비트를 enable 시켜주고, GLOCK register 를해제 시켜줘야한다. 53 4.4 System Control Registers 4 System Control Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr 4.4.21 Sound Mixer clock divide register(smdiv) Address : x82_3c4c 31:5 R Reserved - 4 R/W Synchronization bit 1로설정하면 synch 가되고, 다시 으로반드시설정해준다.. 3: R/W DM Clock Select : Source Clock 1: Source Clock / 2 1: Source Clock / 3 11: Source Clock / 4 111: Source Clock / 15 1111: Source Clock / 16 * 이레지스터를사용하려면, WREN register 에해당하는비트를 enable 시켜주고, GLOCK register 를해제 시켜줘야한다. 4.4.22 PLL1 Control Register (PLLCON1) Address : x82_3c5 31 : 29 Reserved - 28 R/W PLL Power Down 1 : normal operation 1 : power down 27 : 26 R Reserved - 25 : 24 R/W OD (Output divider) 에대한 PLL1 출력분주값을설정. : divide by 1 1 : divide by 4 1 : divide by 2 11 : divide by 8 23 : 2 R Reserved - 19 : 16 R/W R (Input divider). 에대한입력 PLL1 디바이더값을설정. 2h R must be >=2 or unpredictable operation results. 15 : 12 R Reserved - 11 : R/W N (Multiplier) PLL1 승수값을설정. N must be >=2 or unpredictable operation results. 2h * 이레지스터를사용하려면, WREN register 에해당하는비트를 enable 시켜주고, GLOCK register 를해제 시켜줘야한다. * FOUT = (XIN*N)/(R*OD) 54 4 System Control 4.4 System Control Registers Copyright 215, Advanced Digital Chips, Inc.

A H B B U S adstar-l www.adc.co.kr 5 SPI FLASH MEMORY CONTROLLER 5.1 Introduction Flash 메모리는메모리의용량제한은 512k bytes 이며, 메모리의동작속도는최대 8Mhz 까지이지만 Flash Memory Controller 는 AHB clock 을분주하여사용하므로최대시스템 clock 의 2 분주로동작하게된다. Flash controller 는 2 개의 bus interface 가존재한다 : [memory interface & register interface] Memory interface 는 CPU 와 DMA 가직접접근하여, flash memory 의 data 를 read 또는 write 한다. XIP (execute In Place) Register interface 는 SPI flash mode 를설정하거나, flash memory 에 read/write/erase 를수행할수있다. _h ~ FFF_FFFFh Memory Access MEM_IF CLK_GEN CLK 4_h ~ 4FFF_FFFFh DAT_BUF SDIO[3:] Internal/ External SPI Flash Memory 8_h ~ 8_3FFh Register Access REG_IF SF_CTRL CSx Figure 5-1 Flash Memory Controller Block Diagram 5.2 Feature SPI flash controller 의주요기능 - Single, Double 및 Quad mode - H / W 및 S / W 통한 flash erase 및 flash program - XIP 제공 (execute In Place) 55 5.1 Introduction 5 SPI Flash Memory Controller Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr 5.3 Functional Description 5.3.1 Register Interface register interface 를통해 operation mode selection register 및 command/data register 를설정할수있다. Register interface 기능 - Flash erase operation - Flash program operation - Read/Write status operation. - Read data operation 5.3.2 Memory Interface memory interface range 안에서, flash memory 에직접 read/write 를수행한다. (XIP mode) read 동작이수행되면, controller 는 read 가완료될때까지, next access 를하지않으며, wait 상태를유지 한다. Memory interface 기능 - Flash program operation - Read data operation 5.3.3 Internal Flash Memory Internal flash memory 기능 - 4M-bit/512K-byte - 256-byte per programmable page - Uniform 4KB Sectors, 32KB & 64KB Blocks - More than 1, erase/write cycles - More than 2-year data retention SFDP Register Security Register 1-3 h xxffh xxfh xxefh xxeh xxdfh xxdh Sector 15 (4KB) Sector 14 (4KB) Sector 13 (4KB) FFh xxffffh xxfffh xxefffh xxeffh xxdfffh xxdffh 3h 2h 1h 7FFh 7h Block 7 (64KB) 3FFh 2FFh 1FFh 7FFFFh 7FFh xx2fh xx2h xx1fh xx1h xxfh xxh Sector 2 (4KB) Sector 1 (4KB) Sector (4KB) xx2fffh xx2ffh xx1fffh xx1ffh xxfffh xxffh 4FFh 4h 3FFh 3h FFh h Figure 5-2 Internal Serial Flash Memory Block 4 (64KB) Block 3 (64KB) Block (64KB) 4FFFFh 4FFh 3FFFFh 3FFh FFFFh FFh 56 5 SPI Flash Memory Controller 5.3 Functional Description Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr 5.3.4 Internal Flash Memory Commands Instruction NAME Table 5-1 Instruction Set Table 1 (Erase, Program Instructions) BYTE 1 (CODE) BYTE2 BYTE3 BYTE4 BYTE5 BYTE6 Write Enable Write Enable for Volatile Status Register Write Disable 6h 5h 4h Read Status Register-1 5h (S7-S) Read Status Register-2 35h (S15-S8) Write Status Register 1h S7-S S15-S8 Page Program 2h A23-A16 A15-A8 A7-A D7-D Quad Page Program 32h A23-A16 A15-A8 A7-A D7-D, Sector Erase (4KB) 2h A23-A16 A15-A8 A7-A Block Erase (32KB) 52h A23-A16 A15-A8 A7-A Block Erase (64KB) D8h A23-A16 A15-A8 A7-A Chip Erase Erase / Program Suspend Erase / Program Resume Power-down Continuous Read Mode Reset C7/6h 75h 7Ah B9h FFh FFh 57 5.3 Functional Description 5 SPI Flash Memory Controller Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr Instruction NAME Release Power Down/ Device ID Manufacturer/ Device ID Manufacturer/Device ID by Dual I/O Manufacturer/Device ID by Quad I/O JEDEC ID Table 5-2 Instruction Set Table 2 (Read Instructions) BYTE 1 BYTE2 BYTE3 BYTE4 BYTE5 BYTE6 (CODE) ABh dummy dummy dummy (ID7-ID) 9h dummy dummy h (MF-MF) (ID7-ID) 92h 94h 9Fh A23-A8 A23-A, M[7:] (MF7-MF) manufacturer A7-A, M[7:] xxx,(mf[7:], ID[7:]) (D15-ID8) Memory Type (MF[7:], ID[7:]) (MF[7:], ID[7:], ) (ID7-ID) Capacity Read Unique ID 4Bh dummy dummy dummy dummy (ID63-ID) Read SFDP Register 5Ah h h A7-A dummy (D7-D) Erase Security Registers Program Security Registers Read Security Registers 44h A23-A16 A15-A8 A7-A 42h A23-A16 A15-A8 A7-A D7-D D7-D 48h A23-A16 A15-A8 A7-A dummy D7-D Instruction NAME Release Power Down/ Device ID Manufacturer/ Device ID Manufacturer/Device ID by Dual I/O Manufacturer/Device ID by Quad I/O JEDEC ID Table 5-3 Instruction Set Table 3 (ID, Security Instructions) BYTE 1 BYTE2 BYTE3 BYTE4 BYTE5 BYTE6 (CODE) ABh dummy dummy dummy (ID7-ID) 9h dummy dummy h (MF-MF) (ID7-ID) 92h 94h 9Fh A23-A8 A23-A, M[7:] (MF7-MF) manufacturer A7-A, M[7:] xxx,(mf[7:], ID[7:]) (D15-ID8) Memory Type (MF[7:], ID[7:]) (MF[7:], ID[7:], ) (ID7-ID) Capacity Read Unique ID 4Bh dummy dummy dummy dummy (ID63-ID) Read SFDP Register 5Ah h h A7-A dummy (D7-D) Erase Security Registers Program Security Registers Read Security Registers 44h A23-A16 A15-A8 A7-A 42h A23-A16 A15-A8 A7-A D7-D D7-D 48h A23-A16 A15-A8 A7-A dummy D7-D 58 5 SPI Flash Memory Controller 5.3 Functional Description Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr 5.3.5 Flash Status Register Flash Status Register (FLSTS) S7 S6 S5 S4 S3 S2 S1 S SRP SEC TB BP2 BP1 BP WEL BUSY STATUS REGISTER PROTECT (non-vlolatile) SECTOR PROTECT (non-vlolatile) TOP/BOTTOM PROTECT (non-vlolatile) BLOCK PROTECT BITS (non-volatile) WRITE ENABLE LATCH ERASE/WRITE IN PROGRESS Figure 5-3 Serial Flash Memory Status Register 1 위의레지스터는플래시상태레지스터의하위 1 바이트를 access 한것이다. 기록동작이완료되지않는것은 [] 번비트 (BUSY) 를사용하여확인한다. Flash 2nd Status Register (FLSTS2) S15 S14 S13 S12 S11 S1 S9 S8 SUS CMP LB3 LB2 LB1 LB QE SRP1 SUSPEND STATUS COMPLEMENT PROTECT (non-vlolatile) SECURITY REGISTER LOCK BITS (non-vlolatile OTP) QUAD ENABLE (non-volatile) STATUS REGISTER PROTECT 1 (non-volatile Figure 5-4 Serial Flash Memory Status Register 2 위의레지스터는플래시상태레지스터의상위 1 바이트에 access 한것이다. 쿼드모드사용은 [1] 번비트를설정하여수행할수있다 (QE). - 플래시상태레지스터 [9] 번비트사용. 59 5.3 Functional Description 5 SPI Flash Memory Controller Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr Table 5-4 Serial Flash Memory Status Register Description Bit Signal Name Description 15 SUS Erase/Program Suspend Status The suspend Status bit is a read only bit in the status register (S15) that is set to 1 after executing a Erase/Program Suspend (75h) instruction. The SUS status bit is cleared to by Erase/Program Resume (7Ah) instruction as well as a power-down, power-up cycle. 14 CMP Complement Protect The Complement Protect bit (CMP) is a non-volatile read/write bit in the status register (S14). It is used in conjunction with SEC, TB, BP2, BP1 and BP bits to provide more flexibility for the array protection. Once CMP is set to 1, previous array protection set by SEC, TB, BP2, BP1 and BP will be reversed. For instance, when CMP=, a top 4KB sector can be protected while the rest of the array is not; when CMP=1, the top 4KB sector will become unprotected while the rest of the array become read-only, Please refer to the Status Register Memory Protection table for details. The default setting is CMP=. 13 12 11 1 LB3 LB2 LB1 LB Security Register Lock Bits The Security Register Lock Bits (LB3, LB2, LB1, LB) are non-volatile One Time Program (OTP) bits in Status Register (S13, S12, S11, S1) that provide the write protect control and status to the Security Registers. The default state of LB3- is, security Registers are unlocked. LB3- can be set to 1 individually using the Write Status Register instruction. LB3- are One Time Programmable (OTP), once it s set to 1, the corresponding 256-Byte Security Register will become read-only permanently. 9 QE Quad Enable The Quad Enable (QE) bit is a non-volatile read/write bit in the status register (S9) that allows Quad SPI operation. When the QE bit is set to a state (factory default), the /WP pin and /HOLD are enable. When the QE bit is set to a 1, the Quad IO2 and IO3 pins are enabled. 8 SRP1 Status Register Protect 7 SRP The Status Register Protect bits (SRP1 and SRP) are non-volatile read/write bits in the status register (S8 and S7). The SRP bits control the method of write protection: software protection, hardware protection, power supply lock-down or one time programmable (OTP) protection. 6 SEC Sector/Block Protect The non-volatile Sector/Block Protect bit (SEC) controls if the Block Protect Bits (BP2, BP1, BP) protect either 4KB Sectors (SEC=1) or 64KB Blocks (SEC=) in the Top (TB=) or the Bottom (TB=1) of the array as shown in the Status Register Memory Protection table. The default setting is SEC=. 5 TB Top/Bottom Block Protect The non-volatile Top/Bottom bit (TB) controls if the Block Protect Bits (BP2, BP1, BP) protect from the Top (TB=) or the Bottom (TB=1) of the array as shown in the Status Register Memory Protection table. The factory default setting is TB=. The TB bit can be set with the Write Status Register Instruction depending on the state of the SRP, SRp1 and WEL bits. 4 BP2 Block Protect Bits 3 BP1 2 BP The Block Protect Bits (BP2, BP1, BP) are non-volatile read/write bits in the status register (S4, S3, and S2) that provide Write Protection control and status. Block Protect bits can be set using the Write Status Register Instruction (see tw in AC characteristics).; All, none or a portion of the memory array can be protected from Program and Erase instructions (see Status Register memory Protection table). The factory default setting for the Block Protection Bits is, none of the array protected. 1 WEL Write Enable Latch Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to 1 after executing a Write Enable Instruction. The WEL status bit is cleared to when the device is write disabled. A write disable state occurs upon power-up or after any of the following instructions: Write Disable, Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Erase Security Register and Program Security Register. BUSY BUSY is a read only bit in the status register (S) that is set to a 1 state when the device is executing a Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register or Erase/Program Security Register instruction. During this time the device will ignore further instructions except for the Read Status Register and Erase/Program Suspend instruction (see TW, tpp, tse,tbe, and tce in AC Characteristics). When the program, erase or write status/security register instruction has completed, the BUSY bit will be cleared to a state indicating the device is ready for further instruction. 6 5 SPI Flash Memory Controller 5.3 Functional Description Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr 5.3.6 Chip Erasing Flash memory Using FLCMD register (entire flash memory) - Write 6h command to the FLCMD register. - Write C7h/6h command to the FLCMD register. Using SFDAT register (entire flash memory) - Set the chip select bit in the SFMOD register to x(chip select low). - Write 6h command to the SFDAT register. - Set the chip select bit in the SFMOD register to x1(chip select high). - Set the chip select bit in the SFMOD register to x(chip select low). - Write C7h/6h command to the SFDAT register. - Set the chip select bit in the SFMOD register to x1(chip select high) - Poll the busy status bit of the FLSTS register until this operation has completed (Chip Erase complete). 5.3.7 Sector/Block Erasing Flash memory Using FLSEA register (4KB) - Set the address associated with the Flash memory region. Using FLBEA register (64KB) - Set the address associated with the Flash memory region. Using SFDAT register (4KB, 32KB, 64KB) - Set the chip select bit in the SFMOD register to x(chip select low). - Write 6h command to the SFDAT register. - Set the chip select bit in the SFMOD register to x1(chip select high). - Set the chip select bit in the SFMOD register to x(chip select low). - Write 2h(4KB) or 52h(32KB) or D8h(64KB) command to the SFDAT register - Write the target address [23:16] to the SFDAT register. - Write the target address [15:8] to the SFDAT register. - Write the target address [7:] to the SFDAT register. - Set the chip select bit in the SFMOD register to x1(chip select high). - Poll the busy status bit of the FLSTS register until this operation has completed (Sector/Block Erase complete) 5.3.8 Programing Flash memory Using SFDAT register - Set the chip select bit in the SFMOD register to x(chip select low). - Write 6h command to the SFDAT register. - Set the chip select bit in the SFMOD register to x1(chip select high). - Set the chip select bit in the SFMOD register to x(chip select low). - Write 2h command to the SFDAT register - Write the target address [23:16] to the SFDAT register. - Write the target address [15:8] to the SFDAT register. - Write the target address [7:] to the SFDAT register - Write a 32-bit, 16-bit or 8-bit data up to 256 byte. - Set the chip select bit in the SFMOD register to x1(chip select high). - Poll the busy status bit of the FLSTS register until this operation has completed (Erase complete) 61 5.3 Functional Description 5 SPI Flash Memory Controller Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr 5.3.9 Reading Flash memory Using SFDAT register - Set the chip select bit in the SFMOD register to x(chip select low). - Write 3h command to the SFDAT register. - Write the target address [23:16] to the SFDAT register. - Write the target address [15:8] to the SFDAT register. - Write the target address [7:] to the SFDAT register - Read a 32-bit, 16-bit or 8-bit data up to 256 byte. - Set the chip select bit in the SFMOD register to x1(chip select high). 5.3.1 Power Down and Release Power Down Using SFDAT register (Power down) - Set the chip select bit in the SFMOD register to x(chip select low). - Write B9h command to the SFDAT register. - Set the chip select bit in the SFMOD register to x1(chip select high). Using SFDAT register (Release Power down) - Set the chip select bit in the SFMOD register to x(chip select low). - Write ABh command to the SFBAT register. - SFDAT(8bit, 16bit, 32bit access 가능 ) Read - Set the chip select bit in the SFMOD register to x1(chip select high). 5.3.11 Flash Mode Register (FLMOD) Flash 동작모드결정 (Single, Dual, Quad) 5.3.12 Flash Baudrate Register (FLBRT) Flash baudrate(high pulse 및 low pulse) register Chip Select High Pulse Width CSx SCK High Pulse Width SCK SCK Low Pulse Width Figure 5-5 SCK and CS timing 5.3.13 Flash Chip Select High Pulse Width Register (FLCSH) flash memory chip select high time 을설정하는 register 이다. [deselect 시전류의변화는없을것이다.] Program/Erase 후 read 동작시, 또는 read 후다음 read 동작시까지, 5ns 의 deselect time 이필요하다. adstar-l 의 external flash memory 의값은, flash type 마다다르므로, 해당 flash memory deselect time 을 check 해야한다. 62 5 SPI Flash Memory Controller 5.3 Functional Description Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr 5.3.14 Flash WIP Check Period Register (FLWCP) Flash memory 를 program 하거나 erase 시 hardware 적으로 flash memory 의상태를확인하는 period 를결정하는 register 이다. Status memory 의 bit 와도관련이있으며 flash controller 의 status register 를통해서도확인이가능하다. 5.3.15 Flash Clock Delay Register (FLCKDLY) Serial Flash Controller D SET sfclkout Q Serial Flash Memory SCK CLR Q Q SET D sfclkfd Q CLR sfclkout SCK sfclkfd Figure 5-6 Flash Clock Delay Timing 이 register 는 read timing 을정정해준다. register 의값에따라 read clock 이 delay 된다. 63 5.3 Functional Description 5 SPI Flash Memory Controller Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr 5.4 Register Description 5.4.1 Flash Mode Register (FLMOD) Address : x8_ 31:9 R Reserved - 8 R/W Chip select control 1b 1: Chip select 신호가 H/W 에의해제어 : Chip select 신호를 Low level로고정 7 R/W Bus Error Enable 1: Flash 에 Write 접근이일어날시, Bus Error 를발생 : Flash에 Write 허용 6 R Reserved - 5 R EQIO Mode Flag; Checks whether or not this feature is available in flash memory. 1: EQIO Mode : Normal Mode Command Register 에 EQIO(38h) 를 write 하면 Flash 는 EQIO 모드로 전환된다. 4 R Performance Enhance Mode (Flash 지원여부확인 ) 1: Performance Enhance Mode 가적용. : Normal Mode. 적용되지않음. FLPEM Register 에 1 을 write 하여 Performance Enhance Mode 를 Enable하였을경우, Quad Read이거나 EQIO 모드일때만적용된다. 3 R/W Bus Ready Control : Write 동작의경우, bus ready 를제어. S/W 가 flash 의 status 를확인 할필요없음. 1: Write 동작후, S/W에서 flash의 status를확인하도록설정. 2 R Reserved - 1: R/W Flash Read Mode b : Single Read Mode 1: Dual Read Mode 1: Quad Read Mode 11: Reserved 1b b 64 5 SPI Flash Memory Controller 5.4 Register Description Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr 5.4.2 Flash Baudrate Register (FLBRT) Address : x8_4 31:8 R Reserved - 7:4 R/W SCK High Pulse Width 111b : 1clock 1: 2clocks 1: 3clocks 111: 15clocks 1111: 16clocks 3: R/W SCK Low Pulse Width 111b : 1clock 1: 2clocks 1: 3clocks 111: 15clocks 1111: 16clocks 5.4.3 Flash Chip Select High Pulse Width Register (FLCSH) Address : x8_8 31:8 R Reserved - 7: R/W Chip Select High Pulse Width (It need 1ns) FFh Delay in hclk_sf clocks for the length that the chip select output is deasserted between transactions. The minimum delay is always the deselect period to ensure the chip select is never re-asserted within the deselect period. : 1clock 1: 2clocks 1: 3clocks 1111111: 255clocks 11111111: 256clocks 5.4.4 Flash Performance Enhance Mode Register (FLPEM) Address : x8_c 31:1 R Reserved - R/W Performance Enhance Mode 1: Enabled : Disabled b 5.4.5 Flash Command Register (FLCMD) Address : x8_1 31:8 R Reserved - 7: R/W Flash Command b 5.4.6 Flash Status Register (FLSTS) Address : x8_14 31:8 R Reserved - 7: R/W Flash Status b 5.4.7 Flash Sector Erase Address Register (FLSEA) Address : x8_18 31:24 R Reserved - 23: R/W Flash Sector Address to Erase b 65 5.4 Register Description 5 SPI Flash Memory Controller Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr 5.4.8 Flash Block Erase Address Register (FLBEA) Address : x8_1c 31:24 R Reserved - 23: R/W Flash Block Address to Erase b 5.4.9 Flash Data Register (FLDAT) Address : x8_2 31: R/W Flash Data (8, 16, 32-bit supported) b 5.4.1 Flash WIP Check Period Register (FLWCP) Address : x8_24 31: R/W Flash WIP Status Check Period FFFh 5.4.11 Flash Clock Delay Register (FLCKDLY) Address : x8_28 31:4 R Reserved - 3: R/W Serial Flash Feed-back Clock Delay Value h 5.4.12 Flash 2nd Status Register (FLSTS2) Address : x8_2c 31:8 R Reserved - 7: R Flash 2nd Status (Winbond only) - 5.4.13 Flash ID Read Register (FLIDR) Address : x8_3 31:24 R Reserved - 23: R Serial Flash JEDEC ID Read h 66 5 SPI Flash Memory Controller 5.4 Register Description Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr 5.4.14 Flash Memory Size Write Register (SFMSIZE) Address : x8_34 31:9 R Reserved - 8 R/W 두개의 Flash 접근방법을결정한다. 1: bit 4 에의해서결정한다. : Flash의사이즈에따라서결정한다. 7:5 R Reserved - 4 R/W 두개의 flash 사용시원하는 flash를선택할수있다. Flash1 의시 작주소는 x 이다. Flash 의시작주소도 x 이다. 1: Flash 1 : Flash 3: R/W 첫번째 flash 의크기를결정한다. 이크기보다큰접근은 4 Flash1 로접근하게된다. :32Kbyte 1: 64Kbyte 1: 128Kbyte 11: 256Kbyte 1: 512Kbyte 11: 1Mbyte 11: 2Mbyte 111: 4Mbyte 1: 8Mbyte 11: 16Mbyte adstar-l 시리즈에서 Flash, Flash1 의의미는다음그림과같다. Chip Select(CS) 신호의기호도주의해서봐야한다. Internal Flash / External Flash External Flash Only L8MF512 / L16MF512 I_cs_n Flash L8M / L16M No flash adstar-l adstar-l CS_n Flash 1 CS_n Flash CS1_n Flash 1 Figure 5-7 Access Two Flash 67 5.4 Register Description 5 SPI Flash Memory Controller Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr 6 GPIO (GENERAL PURPOSE I/O) GPIO Ports 는 8-bit 으로구성된 6 개블록과 7-bit 으로구성된 1 개의블록으로총 55 개의 I/O Ports 를 제공한다. 각 Ports 는레지스터설정으로쉽게구성될수있으며, 다양한입출력응용과시스템구성에 사용된다. 6.1 Features GP.x has 8 I/O Ports GP1.x has 8 I/O Ports GP2.x has 8 I/O ports GP3.x has 8 I/O ports GP4.x has 8 I/O Ports GP5.x has 8 I/O Ports GP6.x has 7 I/O ports 6.2 Block Diagram GPxPUS GPxAF Alternate Function (Direction) GPxODIR/GPxIDIR VDD33 Alternate Function (Output) GPxOHIGH/GPxOLOW Alternate Function (Input) 1 GND GPxCMOS GPxSCHMT GPxEDS GPxILEV Edge Detect SYNCHRONIZER Q D Q D F/F Latch G GPxRED GRxFED CLK GPxPDS Figure 6-1 GPIO Block Diagram 68 6 GPIO (General Purpose I/O) 6.1 Features Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr 6.3 Functional Description 6.3.1 Port Control GPIO Ports 는 GPxODIR 레지스터를통해각 Port 별로 Output mode 로설정되고또한 GPxIDIR 레지스터에의해각 Port 별로 Input mode 로설정된다. 각 Port 의설정상태는 GPxDIR 레지스터를통해확인할수있다. GPxODIR 레지스터와 GPxIDIR 레지스터설정시 1 인비트만해당동작으로설정되고, 인비트는어떠한영향을미치지못한다. GPIO Ports 의출력레벨은 Output mode 로설정된상태에서 GPxOHIGH 레지스터를통해 High Level 로 설정되고, GPxOLOW 레지스터를통해 Low Level 로설정된다. Output level 의설정상태는 GPxOLEV 레지스터를통해확인할수있다. GPIO Ports 의입력레벨은 GPxILEV 레지스터를통해확인할수있다. 각 Port 에연결된 Pull-up 저항은 외부입력이존재하거나출력인경우에는 Pull-up 을제거하면, 신호레벨이 Low 일때누설전류를줄일수 있다. Table 6-1 Internal Pull-up Resistance Characteristics Parameter Min Typ Max Unit Pull-Up Resistance 34 41 64 K Pull-Down Resistance 33 44 79 K 6.3.2 Port Edge Detect EIRQ 핀을통한외부인터럽트이외에 GPIO 의 Port Edge Detect 을통해각각의그룹별로외부 인터럽트를수행할수있다. Port 들은 Rising Edge, Falling Edge 그리고 Any Edge 모드를지원한다. 69 6.3 Functional Description 6 GPIO (General Purpose I/O) Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr 6.4 Register Description 6.4.1 Port Direction Registers ( GPxDIR ) Address: xffff_3 / xffff_34 / xffff_38 / xffff_3c / xffff_31 / xffff_314 / xffff_318 31 : 9 R Reserved - 8 R GPx.OMD : GPx. Output Control Mode bit : Control individual ports 1 : Control a group of 8 ports 7 : R GPx.yDIR : GPx.y Direction bit : Input 1 : Output x 6.4.2 Port Direction Output Mode Setting Registers ( GPxODIR ) Address: xffff_3 / xffff_34 / xffff_38 / xffff_3c / xffff_31 / xffff_314 / xffff_318 31 : 9 R Reserved - 8 W GPx.OPRT : Output Control by Port Mode Setting bit - 7 W GPx.7ODIR : GPx.7 Direction Output Mode Setting bit - 6 W GPx.6ODIR : GPx.6 Direction Output Mode Setting bit - 5 W GPx.5ODIR : GPx.5 Direction Output Mode Setting bit - 4 W GPx.4ODIR : GPx.4 Direction Output Mode Setting bit - 3 W GPx.3ODIR : GPx.3 Direction Output Mode Setting bit - 2 W GPx.2ODIR : GPx.2 Direction Output Mode Setting bit - 1 W GPx.1ODIR : GPx.1 Direction Output Mode Setting bit - W GPx.ODIR : GPx. Direction Output Mode Setting bit - * Port Direction Output Mode Setting bit : No effect 1 : Set to output mode the corresponding bit 6.4.3 Port Direction Input Mode Setting Registers ( GPxIDIR ) Address: xffff_34 / xffff_344 / xffff_384 / xffff_3c4 / xffff_314 / xffff_3144 / xffff_3184 31 : 9 R Reserved - 8 W GPx.IPRT : Iutput Control by Port Mode Setting bit - 7 W GPx.7IDIR : GPx.7 Direction Input Mode Setting bit - 6 W GPx.6IDIR : GPx.6 Direction Input Mode Setting bit - 5 W GPx.5IDIR : GPx.5 Direction Input Mode Setting bit - 4 W GPx.4IDIR : GPx.4 Direction Input Mode Setting bit - 3 W GPx.3IDIR : GPx.3 Direction Input Mode Setting bit - 2 W GPx.2IDIR : GPx.2 Direction Input Mode Setting bit - 1 W GPx.1IDIR : GPx.1 Direction Input Mode Setting bit - W GPx.IDIR : GPx. Direction Input Mode Setting bit - * 포트방향입력모드설정비트. :No effect 1 : PxDIR 레지스터의입력모드에해당하는비트를설정. 6.4.4 Port Output Data Level Registers ( GPxOLEV ) Address: xffff_38 / xffff_348 / xffff_388 / xffff_3c8 / xffff_318 / xffff_3148 / xffff_3188 31 : 8 R Reserved - 7 : R GPx.yOLEV : GPx.y Output Level bit xff : Low Level 1 : High Level 7 6 GPIO (General Purpose I/O) 6.4 Register Description Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr 6.4.5 Port Output Data Registers ( GPxDOUT ) Address: xffff_38 / xffff_348 / xffff_388 / xffff_3c8 / xffff_318 / xffff_3148 / xffff_3188 31 : 8 R Reserved - 7 : R/W GPx.DO : GPx.Port Output Data xff * GPxDIR 의 8 번 bit 가 1 인경우, 이 register 를이용해 GPIO Port output 을결정한다. 6.4.6 Port Output Data High Level Setting Registers ( GPxOHIGH ) Address: xffff_38 / xffff_348 / xffff_388 / xffff_3c8 / xffff_318 / xffff_3148 / xffff_3188 31 : 8 R Reserved - 7 W GPx.7OH : GPx.7 Output Data High Level Setting bit - 6 W GPx.6OH : GPx.6 Output Data High Level Setting bit - 5 W GPx.5OH : GPx.5 Output Data High Level Setting bit - 4 W GPx.4OH : GPx.4 Output Data High Level Setting bit - 3 W GPx.3OH : GPx.3 Output Data High Level Setting bit - 2 W GPx.2OH : GPx.2 Output Data High Level Setting bit - 1 W GPx.1OH : GPx.1 Output Data High Level Setting bit - W GPx.OH : GPx. Output Data High Level Setting bit - * Port Output Data High Level Setting bit (GPxDIR 의 8 번 bit 가 인경우유효하다.) : No effect 1 : output data 에해당하는비트를 high level 설정. 6.4.7 Port Output Data Low Level Setting Registers ( GPxOLOW ) Address: xffff_3c / xffff_34c / xffff_38c / xffff_3cc / xffff_31c / xffff_314c / xffff_318c 31 : 8 R Reserved - 7 W GPx.7OL : GPx.7 Output Data Low Level Setting bit - 6 W GPx.6OL : GPx.6 Output Data Low Level Setting bit - 5 W GPx.5OL : GPx.5 Output Data Low Level Setting bit - 4 W GPx.4OL : GPx.4 Output Data Low Level Setting bit - 3 W GPx.3OL : GPx.3 Output Data Low Level Setting bit - 2 W GPx.2OL : GPx.2 Output Data Low Level Setting bit - 1 W GPx.1OL : GPx.1 Output Data Low Level Setting bit - W GPx.OL : GPx. Output Data Low Level Setting bit - * Port Output Data Low Level Setting bit (It is effective only when GPxDIR[8] is.) : No effect 1 : output data 에해당하는비트를 low level 설정. 71 6.4 Register Description 6 GPIO (General Purpose I/O) Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr 6.4.8 Port Input Data Level Registers ( GPxILEV ) Address: xffff_31 / xffff_35 / xffff_39 / xffff_3d / xffff_311 / xffff_315 / xffff_319 31 : 8 R Reserved - 7 R GPx.7ILEV : GPx.7 Input Level bit - : Low Level 1 : High Level 6 R GPx.6ILEV : GPx.6 Input Level bit - : Low Level 1 : High Level 5 R GPx.5ILEV : GPx.5 Input Level bit - : Low Level 1 : High Level 4 R GPx.4ILEV : GPx.4 Input Level bit - : Low Level 1 : High Level 3 R GPx.3ILEV : GPx.3 Input Level bit - : Low Level 1 : High Level 2 R GPx.2ILEV : GPx.2 Input Level bit - : Low Level 1 : High Level 1 R GPx.1ILEV : GPx.1 Input Level bit - : Low Level 1 : High Level R GPx.ILEV : GPx. Input Level bit - : Low Level 1 : High Level 6.4.9 Port Pull-up Status Registers ( GPxPUS ) Address: xffff_318 / xffff_358 / xffff_398 / xffff_3d8 / xffff_3118 / xffff_3158 / xffff_3198 31 : 8 R Reserved - 7 : R GPx.yUP : GPx.y Pull-up Status bit x : Pull-up Disable 1 : Pull-up Enable 6.4.1 Port Pull-up Enable Registers ( GPxPUEN ) Address: xffff_318 / xffff_358 / xffff_398 / xffff_3d8 / xffff_3118 / xffff_3158 / xffff_3198 31 : 8 R Reserved - 7 W GPx.7PUEN : GPx.7 Pull-up enable bit - 6 W GPx.6PUEN : GPx.6 Pull-up enable bit - 5 W GPx.5PUEN : GPx.5 Pull-up enable bit - 4 W GPx.4PUEN : GPx.4 Pull-up enable bit - 3 W GPx.3PUEN : GPx.3 Pull-up enable bit - 2 W GPx.2PUEN : GPx.2 Pull-up enable bit - 1 W GPx.1PUEN : GPx.1 Pull-up enable bit - W GPx.PUEN : GPx. Pull-up enable bit - * Port Pull-up enable bit : No effect 1 : 해당하는비트의 pull_up 을설정한다. 6.4.11 Port Pull-up Disable Registers ( GPxPUDIS ) Address: xffff_31c / xffff_35c / xffff_39c / xffff_3dc / xffff_311c / xffff_315c / xffff_319c 31 : 8 R Reserved - 7 W GPx.7PUDIS : GPx.7 Pull-up disable bit - 6 W GPx.6PUDIS : GPx.6 Pull-up disable bit - 5 W GPx.5PUDIS : GPx.5 Pull-up disable bit - 4 W GPx.4PUDIS : GPx.4 Pull-up disable bit - 3 W GPx.3PUDIS : GPx.3 Pull-up disable bit - 2 W GPx.2PUDIS : GPx.2 Pull-up disable bit - 1 W GPx.1PUDIS : GPx.1 Pull-up disable bit - W GPx.PUDIS : GPx. Pull-up disable bit - * Port Pull-up disable bit : No effect. 1 : 해당하는비트의 pull_up 을 Disable 한다. 72 6 GPIO (General Purpose I/O) 6.4 Register Description Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr 6.4.12 Port Rising Edge Detect Registers ( GPxRED ) Address: xffff_32 / xffff_36 / xffff_3a / xffff_3e / xffff_312 / xffff_316 / xffff_31a 31 : 8 R Reserved - 7 R/W GPx.7RED : GPx.7 Rising Edge Detect bit : Disable 1 : Enable 6 R/W GPx.6RED : GPx.6 Rising Edge Detect bit : Disable 1 : Enable 5 R/W GPx.5RED : GPx.5 Rising Edge Detect bit : Disable 1 : Enable 4 R/W GPx.4RED : GPx.4 Rising Edge Detect bit : Disable 1 : Enable 3 R/W GPx.3RED : GPx.3 Rising Edge Detect bit : Disable 1 : Enable 2 R/W GPx.2RED : GPx.2 Rising Edge Detect bit : Disable 1 : Enable 1 R/W GPx.1RED : GPx.1 Rising Edge Detect bit : Disable 1 : Enable R/W GPx.RED : GPx. Rising Edge Detect bit : Disable 1 : Enable * Rising Edge 와 Falling Edge 가동시에설정되었을때는 Any Edge mode 가된다. 6.4.13 Port Falling Edge Detect Registers ( GPxFED ) Address: xffff_324 / xffff_364 / xffff_3a4 / xffff_3e4 / xffff_3124 / xffff_3164 / xffff_31a4 31 : 8 R Reserved - 7 R/W GPx.7FED : GPx.7 Falling Edge Detect bit : Disable 1 : Enable 6 R/W GPx.6FED : GPx.6 Falling Edge Detect bit : Disable 1 : Enable 5 R/W GPx.5FED : GPx.5 Falling Edge Detect bit : Disable 1 : Enable 4 R/W GPx.4FED : GPx.4 Falling Edge Detect bit : Disable 1 : Enable 3 R/W GPx.3FED : GPx.3 Falling Edge Detect bit : Disable 1 : Enable 2 R/W GPx.2FED : GPx.2 Falling Edge Detect bit : Disable 1 : Enable 1 R/W GPx.1FED : GPx.1 Falling Edge Detect bit : Disable 1 : Enable R/W GPx.FED : GPx. Falling Edge Detect bit : Disable 1 : Enable * Rising Edge 와 Falling Edge 가동시에설정되었을때는 Any Edge mode 가된다.. 6.4.14 Port Edge Detect Status Registers ( GPxEDS ) Address: xffff_328 / xffff_368 / xffff_3a8 / xffff_3e8 / xffff_3128 / xffff_3168 / xffff_31a8 31 : 8 R Reserved - 7 R/W GPx.7EDS : GPx.7 Edge Detect Status bit 6 R/W GPx.6EDS : GPx.6 Edge Detect Status bit 5 R/W GPx.5EDS : GPx.5 Edge Detect Status bit 4 R/W GPx.4EDS : GPx.4 Edge Detect Status bit 3 R/W GPx.3EDS : GPx.3 Edge Detect Status bit 2 R/W GPx.2EDS : GPx.2 Edge Detect Status bit 1 R/W GPx.1EDS : GPx.1 Edge Detect Status bit R/W GPx.EDS : GPx. Edge Detect Status bit * Port Edge Detect Status bit : No edge detect has occurred on port 1 : Edge detect has occurred on port * 상태비트는 write 하여 clear 됩니다., * 을 write 하면효과없음. 73 6.4 Register Description 6 GPIO (General Purpose I/O) Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr 6.4.15 Port Open Drain Mode Control Registers ( GPxODM ) Address: xffff_32c / xffff_36c / xffff_3ac / xffff_3ec / xffff_312c / xffff_316c / xffff_31ac 31 : 8 R Reserved - 7 : R/W GPx.yOD : GPx.y Open Drain Mode Setting bit : Normal 1 : Open Drain 6.4.16 Port Schmitt Input Enable Registers ( GPxSHMT ) Address: xffff_334 / xffff_374 / xffff_3b4 / xffff_3f4 / xffff_3134 / xffff_3174 / xffff_31b4 31 : 8 R Reserved - 7 W GPx.7SHMT : GPx.7 Schmitt input enable bit 6 W GPx.6SHMT : GPx.6 Schmitt input enable bit 5 W GPx.5SHMT : GPx.5 Schmitt input enable bit 4 W GPx.4SHMT : GPx.4 Schmitt input enable bit 3 W GPx.3SHMT : GPx.3 Schmitt input enable bit 2 W GPx.2SHMT : GPx.2 Schmitt input enable bit 1 W GPx.1SHMT : GPx.1 Schmitt input enable bit W GPx.SHMT : GPx. Schmitt input enable bit * Port Schmitt input enable bit : CMOS input mode 1 : Schmitt input mode 6.4.17 Port Pull-down Status Registers ( GPxPDS ) Address: xffff_33 / xffff_37 / xffff_3b / xffff_3f / xffff_313 / xffff_317 / xffff_31b 31 : 8 R Reserved - 7 : R GPx.yDN : GPx.y Pull-down Status bit x : Pull-down Disable 1 : Pull-down Enable 6.4.18 Port Pull-down Enable Registers ( GPxPDEN ) Address: xffff_33 / xffff_37 / xffff_3b / xffff_3f / xffff_313 / xffff_317 / xffff_31b 31 : 8 R Reserved - 7 W GPx.7PDEN : GPx.7 Pull-down enable bit - 6 W GPx.6PDEN : GPx.6 Pull-down enable bit - 5 W GPx.5PDEN : GPx.5 Pull-down enable bit - 4 W GPx.4PDEN : GPx.4 Pull-down enable bit - 3 W GPx.3PDEN : GPx.3 Pull-down enable bit - 2 W GPx.2PDEN : GPx.2 Pull-down enable bit - 1 W GPx.1PDEN : GPx.1 Pull-down enable bit - W GPx.PDEN : GPx. Pull-down enable bit - * Port Pull-down enable bit : No effect 1 : 해당하는비트의 Pull-down 을 Enable 한다. 74 6 GPIO (General Purpose I/O) 6.4 Register Description Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr 6.4.19 Port Pull-down Disable Registers ( GPxPDDIS ) Address: xffff_31c / xffff_35c / xffff_39c / xffff_3dc / xffff_311c / xffff_315c / xffff_319c 31 : 8 R Reserved - 7 W GPx.7PDDIS : GPx.7 Pull-down disable bit - 6 W GPx.6PDDIS : GPx.6 Pull-down disable bit - 5 W GPx.5PDDIS : GPx.5 Pull-down disable bit - 4 W GPx.4PDDIS : GPx.4 Pull-down disable bit - 3 W GPx.3PDDIS : GPx.3 Pull-down disable bit - 2 W GPx.2PDDIS : GPx.2 Pull-down disable bit - 1 W GPx.1PDDIS : GPx.1 Pull-down disable bit - W GPx.PDDIS : GPx. Pull-down disable bit - * Port Pull-down disable bit : No effect 1 : 해당하는비트의 Pull-down 을 Disable 한다. 75 6.4 Register Description 6 GPIO (General Purpose I/O) Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr 7 PIN MUX 일반입력 / 출력 (GPIO) 기능과함께핀당최대세가지 peripheral function 을사용할수있다. 7.1 Pin Mux register Register GP Mux x8234 GP1 Mux x82344 GP2 Mux x82348 GP3 Mux x8234c GP4 Mux x82341 GP5 Mux x823414 GP6 Mux x823418 bit 1st 2nd 3rd 4th Default 1 1 11 value 1: uart_tx[1] cap_in[] PG. 3:2 uart_rx[1] cap_in[1] PG.1 5:4 Spi_lcd_cs PG.2 7:6 Spi_lcd_sdi nand_d[7] PG.3 9:8 Spi_lcd_sdo nand_d[6] PG.4 11:1 Spi_lcd_scl nand_d[5] PG.5 13:12 nand_d[4] sd_clk PG.6 15:14 spi_sdo nand_d[3] sd_d[3] PG.7 1: spi_sdi nand_d[2] sd_d[2] PG1. 3:2 spi_cs nand_d[1] sd_d[1] PG1.1 5:4 spi_scl nand_d[] sd_d[] PG1.2 7:6 sf_hold (d3) nand_wrx PG1.3 9:8 sf_clk nand_ale PG1.4 11:1 sf_di (d) nand_cle PG1.5 13:12 sf_cs1 nand_cs PG1.6 15:14 sf_wp (d2) nand_rdx PG1.7 1: sf_do (d1) nand_busy PG2. 3:2 sf_cs sd_cmd PG2.1 5:4 twi_sda usb_host_in PG2.2 7:6 twi_scl usb_host_out PG2.3 9:8 uart_tx[] PG2.4 11:1 uart_rx[] PG2.5 13:12 lcd_r[] PG2.6 15:14 lcd_r[1] PG2.7 1: lcd_r[2] PG3. 3:2 lcd_r[3] PG3.1 5:4 lcd_r[4] PG3.2 7:6 lcd_r[5] PG3.3 x5fff 9:8 lcd_r[6] PG3.4 11:1 lcd_r[7] PG3.5 13:12 lcd_g[] dbg_sck PG3.6 15:14 lcd_g[1] dbg_sda PG3.7 1: lcd_g[2] PG4. 3:2 lcd_g[3] PG4.1 5:4 lcd_g[4] PG4.2 7:6 lcd_g[5] PG4.3 xffff 9:8 lcd_g[6] PG4.4 11:1 lcd_g[7] PG4.5 13:12 lcd_b[] ext_irq[] PG4.6 15:14 lcd_b[1] ext_irq[1] PG4.7 1: lcd_b[2] PG5. 3:2 lcd_b[3] PG5.1 5:4 lcd_b[4] PG5.2 7:6 lcd_b[5] PG5.3 xffff 9:8 lcd_b[6] PG5.4 11:1 lcd_b[7] PG5.5 13:12 dotclk PG5.6 15:14 disp_en PG5.7 xffff or x557f (nand boot) x3f or x5555 (nand boot) xfff or xfffd (nand boot) 1: hsync PG6. 3:2 vsync tm_out[] PG6.1 5:4 lcd_clk_in tm_out[1] PG6.2 xffff 7:6 pwm_p PG6.3 9:8 pwm_n PG6.4 11:1 pwm_p1 PG6.5 13:12 pwm_n1 PG6.6 76 7 Pin Mux 7.1 Pin Mux register Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr 8 INTERRUPT CONTROLLER adstar-l 는 32 개채널의인터럽트입력을가지며, 이입력들은 Timer, SPI, TWI, UART 등과같은내부 장치에서발생하는 3 개의인터럽트와외부 2 개의인터럽트로구성된다. 8.1 Features - 32 채널의인터럽트 (2 채널의외부인터럽트와 3채널의내부인터럽트 ) - 외부인터럽트에대한동작조건설정 (5가지) - 내부인터럽트에대한동작조건설정 (2가지) - 채널별인터럽트 Enable 기능 - 채널별인터럽트 Mask 기능 - 개별적으로프로그램가능한인터럽트우선순위 8.2 Functional Description 인터럽트의순차처리는다음과같은과정을통하여이루어진다. 1. 각인터럽트소스들은인터럽트제어기에인터럽트를요청한다. 2. Interrupt Enable Register에의해선별된후, Interrupt Pending Register에저장한다. 3. 인터럽트우선순위를판단한후, CPU에인터럽트를요청한다. 4. 인터럽트를요청받으면 CPU의인터럽트가비활성화되며인터럽트벡터주소를읽어서해당 Interrupt Service Routine(ISR) 으로진입한다. 5. ISR 을수행한다. 6. ISR 수행이끝나면 Interrupt Pending Clear Register에해당 Vector값을씀으로써 Interrupt Pending Register에저장된인터럽트값을지운다. 7. ISR을빠져나오면서 CPU의인터럽트가활성화된다. 인터럽트의중첩처리는다음과같은과정을통하여이루어진다. 1. 각인터럽트소스들은인터럽트제어기에인터럽트를요청한다. 2. Interrupt Enable Register에의해선별된후, Interrupt Pending Register에저장한다. 3. 인터럽트우선순위를판단한후, CPU에인터럽트를요청한다. 4. 인터럽트를요청받으면 CPU의인터럽트가비활성화되며인터럽트벡터주소를읽어서해당 Interrupt Service Routine(ISR) 으로진입한다. 5. 인터럽트의중첩을허용하기위해 Interrupt Pending Clear Register에해당 Vector값을씀으로써 Interrupt Pending Register에저장된인터럽트값을지우고 asm( set 13 ) 을통해 CPU의인터럽트를 활성화시킨다. 6. ISR을수행한다. 7. 만약, 현재 ISR의수행도중다시인터럽트가발생하면중첩처리가허용되어해당 ISR로진입한 다. 8. 새롭게진입한 ISR의수행이끝나면이전 ISR로복귀하여나머지수행을진행한다. 9. ISR 수행이끝나면완전히빠져나온다. 77 8.1 Features 8 Interrupt Controller Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr 8.2.1 Interrupt Vector and Priority 인터럽트우선순위는 EIRQ 가가장높다. 인터럽트벡터주소는 CPU 가 32bit Addressing 을하기때문에 각각 4bytes 의크기를가진다. Table 8-1 Interrupt Vector & Priority Index Vector No. Description Vector Address 31 x3f SWD Interrupt xfc Use edge method Clock_ctrl_r[] 3 x3e MJPEG 1 Interrupt xf8 29 x3d Capture Over Interrupt xf4 28 x3c SPI LCD Interrupt xf 27 x3b RTC Alarm Interrupt xec 26 x3a RTC Interrupt xe8 25 x39 TWI Interrupt xe4 24 x38 NAND Interupt xe 23 x37 WDT Interrupt xdc 22 x36 DMA CH5 Interrupt, xd8 GPIO 3 interrupt, GPIO 6 interrupt 21 x35 SDCard Interrupt xd4 2 x34 DMA CH4 Interrupt, xd GPIO 2 Interrupt, GPIO 5 Interrupt 19 x33 MJPEG Interrupt xcc 18 x32 SPI Interrupt xc8 17 x31 DMA CH3 Interrupt xc4 16 x3 UART 1 Interrupt xc 15 x2f GPIO 1 Interrupt, xbc GPIO 4 Interrupt 14 x2e USB host interrupt, xb8 Device Interupt 13 x2d ADC Interrupt xb4 12 x2c DMA CH2 Interrupt xb 11 x2b PMC interrupt xac 1 x2a Timer 1 Interrupt xa8 9 x29 DMA CH1 Interrupt xa4 8 x28 UART Interrupt xa 7 x27 GPIO Interrupt x9c 6 x26 DMA CH Interrupt x98 5 x25 LCD Frame sync Interrupt x94 4 x24 EIRQ1 Interrupt x9 3 x23 Sound Mixer Interrupt x8c 2 x22 Timer Interrupt x88 1 x21 Core timer Interrupt x84 x2 EIRQ Interrupt (Highest Priority) x8 78 8 Interrupt Controller 8.2 Functional Description Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr 8.2.2 External Interrupt (EIRQx) External Interrupt 는 EINTMOD 레지스터의설정에의해 5 가지형태의외부인터럽트를받아들인다. - Low Level Mode에서는 External Interrupt 신호가 Low 를유지하는동안에매 System Cycle 마다인터럽트발생시킨다. - High Level Mode에서는 External Interrupt 신호가 High 를유지하는동안에매 System Cycle 마다인터럽트를발생시킨다. - Falling Edge Mode에서는 External Interrupt 신호가 High->Low 로바뀔때인터럽트를발생시킨다. - Rising Edge Mode에서는 External Interrupt 신호가 Low->High 로바뀔때인터럽트를발생시킨다. - Any Edge Mode에서는 External Interrupt 신호가 High->Low 또는 Low-> High 로바뀔때인터럽트를발생시킨다. External Interrupt Low Level Interrupt Event High Level Interrupt Event Falling Edge Interrupt Event Rising Edge Interrupt Event Any Edge Interrupt Event Figure 8-1 External Interrupt Mode 8.2.3 Internal Interrupt Mode 내부인터럽트는모두 Rising Edge 로동작한다. 그러나사용자가 High Level 로인터럽트를처리를원할 경우에 Internal Interrupt Mode Registers 를통해설정할수있다. 79 8.2 Functional Description 8 Interrupt Controller Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr 8.2.4 Interrupt Pending and Interrupt Pending Clear 각인터럽트의발생상태는 Interrupt Pending Registers 를통해확인할수있다. 일단한번발생한인터럽트는 Interrupt Pending Clear Register 에의해 Clear 되기전까지는계속 Interrupt Pending Register 에저장된다. 또한현재발생한인터럽트보다높은우선순위의인터럽트가 Masking 되지않은상태로 Interrupt Pending Registers 에저장되어있을경우에는높은우선순위의인터럽트가모두 Clear 될때까지 Interrupt Pending Registers 에저장되어자신의우선순위가되기를기다린다. Interrupt Pending Registers 에저장된인터럽트들을 Clear 하기위해서는 Interrupt Pending Clear Register 를통해해당인터럽트벡터번호값을 Write 하면된다. 8.2.5 Interrupt Enable Interrupt Mask Registers 에의해 Mask 되어있는인터럽트는 Interrupt Pending Registers 에계속저장되는데비해, Interrupt Enable Registers(IENR) 에의해 Disable 된인터럽트는 Interrupt Pending Registers 에저장되지않는다. 따라서이레지스터는전혀받아들이고싶지않은인터럽트에대해 Disable 하는데사용한다. 8.2.6 Interrupt Mask Set/Clear Register Set 이면 Request 가 Enable 되고, Clear 이면 Request 가 Disable 된다. 각인터럽트는 Interrupt Mask Registers 에의해해당인터럽트에대한 Request 를수행할수있다. Interrupt Mask Set bit 가 1 일경우에는 Interrupt Pending Register 에저장된 Interrupt 를 CPU 로요청하고, Interrupt Mask Clear bit 가 1 일경우에는 Interrupt Pending Register 에저장되어있는 Interrupt 를 CPU 로요청하지못한다. 설정되지않은나머지 Interrupt 들은요청될수있다. Mask bit 가 으로설정된인터럽트라도 Interrupt Pending Registers(IPR) 에는저장되기때문에 Mask bit 을 1 로재설정하면 Interrupt Pending Registers 에저장되어있는인터럽트가우선순위에의해 인터럽트를다시요청한다. 8 8 Interrupt Controller 8.2 Functional Description Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr 8.3 Register Description 8.3.1 Interrupt Pending Clear Register (INTPENDCLR) Address : xffff_ 31 : 8 R Reserved - 7 : W Interrupt Pending Register Clear Value (x2 ~ x3f) xff * Interrupt Pending Register 를 Clear 하기위해서는 Interrupt Vector No. 값으로 clear 해야한다. (Interrupt Vector No. 참고 ) 8.3.2 External Interrupt Mode and External PIN Level Register (EINTMOD) Address : xffff_4 31:8 R Reserved - 7 R EIRQ1ST : EIRQ1 PIN Level - 6 : 4 R/W EIRQ1MOD : EIRQ1 Active State 1 : Low Level 1 : High Level 1 : Falling Edge 11 : Rising Edge 1xx : Any Edge 3 R EIRQST : EIRQ PIN Level - 2 : R/W EIRQMOD : EIRQ Active State 1 : Low Level 1 : High Level 1 : Falling Edge 11 : Rising Edge 1xx : Any Edge 81 8.3 Register Description 8 Interrupt Controller Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr 8.3.3 Internal Interrupt Mode Register (IINTMODn) Address : xffff_8 31 R/W Vector No. x3f Interrupt Mode bit 3 R/W Vector No. x3e Interrupt Mode bit 29 R/W Vector No. x3d Interrupt Mode bit 28 R/W Vector No. x3c Interrupt Mode bit - 27 R/W Vector No. x3b Interrupt Mode bit 26 R/W Vector No. x3a Interrupt Mode bit 25 R/W Vector No. x39 Interrupt Mode bit 24 - Reserved - 23 R/W Vector No. x37 Interrupt Mode bit 22 R/W Vector No. x36 Interrupt Mode bit 21 R/W Vector No. x35 Interrupt Mode bit 2 R/W Vector No. x34 Interrupt Mode bit - 19 R/W Vector No. x33 Interrupt Mode bit 18 R/W Vector No. x32 Interrupt Mode bit 17 R/W Vector No. x31 Interrupt Mode bit 16 - Reserved - 15 R/W Vector No. x2f Interrupt Mode bit 14 R/W Vector No. x2e Interrupt Mode bit 13 R/W Vector No. x2d Interrupt Mode bit 12 R/W Vector No. x2c Interrupt Mode bit - 11 R/W Vector No. x2b Interrupt Mode bit 1 R/W Vector No. x2a Interrupt Mode bit 9 R/W Vector No. x29 Interrupt Mode bit 8 - Reserved - 7 R/W Vector No. x27 Interrupt Mode bit 6 R/W Vector No. x26 Interrupt Mode bit 5 R/W Vector No. x25 Interrupt Mode bit 4 R/W Vector No. x24 Interrupt Mode bit - 3 R/W Vector No. x23 Interrupt Mode bit 2 R/W Vector No. x22 Interrupt Mode bit 1 R/W Vector No. x21 Interrupt Mode bit - Reserved - * Internal Interrupt Mode bit : High Level Mode 1 : Rising Edge Mode 82 8 Interrupt Controller 8.3 Register Description Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr 8.3.4 Interrupt Pending Register (INTPENDn) Address : xffff_c 31 R Vector No. x3f Interrupt Pending bit - 3 R Vector No. x3e Interrupt Pending bit - 29 R Vector No. x3d Interrupt Pending bit - 28 R Vector No. x3c Interrupt Pending bit - 27 R Vector No. x3b Interrupt Pending bit - 26 R Vector No. x3a Interrupt Pending bit - 25 R Vector No. x39 Interrupt Pending bit - 24 R Vector No. x38 Interrupt Pending bit - 23 R Vector No. x37 Interrupt Pending bit - 22 R Vector No. x36 Interrupt Pending bit - 21 R Vector No. x35 Interrupt Pending bit - 2 R Vector No. x34 Interrupt Pending bit - 19 R Vector No. x33 Interrupt Pending bit - 18 R Vector No. x32 Interrupt Pending bit - 17 R Vector No. x31 Interrupt Pending bit - 16 R Vector No. x3 Interrupt Pending bit - 15 R Vector No. x2f Interrupt Pending bit - 14 R Vector No. x2e Interrupt Pending bit - 13 R Vector No. x2d Interrupt Pending bit - 12 R Vector No. x2c Interrupt Pending bit - 11 R Vector No. x2b Interrupt Pending bit - 1 R Vector No. x2a Interrupt Pending bit - 9 R Vector No. x29 Interrupt Pending bit - 8 R Vector No. x28 Interrupt Pending bit - 7 R Vector No. x27 Interrupt Pending bit - 6 R Vector No. x26 Interrupt Pending bit - 5 R Vector No. x25 Interrupt Pending bit - 4 R Vector No. x24 Interrupt Pending bit - 3 R Vector No. x23 Interrupt Pending bit - 2 R Vector No. x22 Interrupt Pending bit - 1 R Vector No. x21 Interrupt Pending bit - R Vector No. x2 Interrupt Pending bit - * Interrupt Pending Register 의각비트의값은해당인터럽트가발생하였음을나타낸다. Interrupt Pending Register 의 값은 Interrupt Pending Clear 레지스터에의해 Clear 된다. 일반적으로해당 Interrupt 가끝날때 Clear 한다. 83 8.3 Register Description 8 Interrupt Controller Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr 8.3.5 Interrupt Enable Register (INTENn) Address : xffff_1 31 R/W Vector No. x3f Interrupt Enable bit 3 R/W Vector No. x3e Interrupt Enable bit 29 R/W Vector No. x3d Interrupt Enable bit 28 R/W Vector No. x3c Interrupt Enable bit 27 R/W Vector No. x3b Interrupt Enable bit 26 R/W Vector No. x3a Interrupt Enable bit 25 R/W Vector No. x39 Interrupt Enable bit 24 R/W Vector No. x38 Interrupt Enable bit 23 R/W Vector No. x37 Interrupt Enable bit 22 R/W Vector No. x36 Interrupt Enable bit 21 R/W Vector No. x35 Interrupt Enable bit 2 R/W Vector No. x34 Interrupt Enable bit 19 R/W Vector No. x33 Interrupt Enable bit 18 R/W Vector No. x32 Interrupt Enable bit 17 R/W Vector No. x31 Interrupt Enable bit 16 R/W Vector No. x3 Interrupt Enable bit 15 R/W Vector No. x2f Interrupt Enable bit 14 R/W Vector No. x2e Interrupt Enable bit 13 R/W Vector No. x2d Interrupt Enable bit 12 R/W Vector No. x2c Interrupt Enable bit 11 R/W Vector No. x2b Interrupt Enable bit 1 R/W Vector No. x2a Interrupt Enable bit 9 R/W Vector No. x29 Interrupt Enable bit 8 R/W Vector No. x28 Interrupt Enable bit 7 R/W Vector No. x27 Interrupt Enable bit 6 R/W Vector No. x26 Interrupt Enable bit 5 R/W Vector No. x25 Interrupt Enable bit 4 R/W Vector No. x24 Interrupt Enable bit 3 R/W Vector No. x23 Interrupt Enable bit 2 R/W Vector No. x22 Interrupt Enable bit 1 R/W Vector No. x21 Interrupt Enable bit R/W Vector No. x2 Interrupt Enable bit * Interrupt Enable bit : Interrupt Disable and Pending Clear 1 : Interrupt Enable 84 8 Interrupt Controller 8.3 Register Description Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr 8.3.6 Interrupt Mask Status Register (INTMASKn) Address : xffff_14 31 : R Interrupt Mask Status Register x_ * 모든 Mask bit 의상태를확인할수있다. 8.3.7 Interrupt Mask Set Register (INTMASKSETn) Address : xffff_14h 31 W Vector No. x3f Interrupt Request Set bit 3 W Vector No. x3e Interrupt Request Set bit 29 W Vector No. x3d Interrupt Request Set bit 28 W Vector No. x3c Interrupt Request Set bit 27 W Vector No. x3b Interrupt Request Set bit 26 W Vector No. x3a Interrupt Request Set bit 25 W Vector No. x39 Interrupt Request Set bit 24 W Vector No. x38 Interrupt Request Set bit 23 W Vector No. x37 Interrupt Request Set bit 22 W Vector No. x36 Interrupt Request Set bit 21 W Vector No. x35 Interrupt Request Set bit 2 W Vector No. x34 Interrupt Request Set bit 19 W Vector No. x33 Interrupt Request Set bit 18 W Vector No. x32 Interrupt Request Set bit 17 W Vector No. x31 Interrupt Request Set bit 16 W Vector No. x3 Interrupt Request Set bit 15 W Vector No. x2f Interrupt Request Set bit 14 W Vector No. x2e Interrupt Request Set bit 13 W Vector No. x2d Interrupt Request Set bit 12 W Vector No. x2c Interrupt Request Set bit 11 W Vector No. x2b Interrupt Request Set bit 1 W Vector No. x2a Interrupt Request Set bit 9 W Vector No. x29 Interrupt Request Set bit 8 W Vector No. x28 Interrupt Request Set bit 7 W Vector No. x27 Interrupt Request Set bit 6 W Vector No. x26 Interrupt Request Set bit 5 W Vector No. x25 Interrupt Request Set bit 4 W Vector No. x24 Interrupt Request Set bit 3 W Vector No. x23 Interrupt Request Set bit 2 W Vector No. x22 Interrupt Request Set bit 1 W Vector No. x21 Interrupt Request Set bit W Vector No. x2 Interrupt Request Set bit * Interrupt Request Set bit : No Effect interrupt Mask. 1 : pending 인터럽트가활성화되도록허용 (interrupts sent to CPU). 85 8.3 Register Description 8 Interrupt Controller Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr 8.3.8 Interrupt Mask Clear Register (INTMASKCLRn) Address : xffff_18 31 W Vector No. x3f Interrupt Req. Clear bit 3 W Vector No. x3e Interrupt Req. Clear bit 29 W Vector No. x3d Interrupt Req. Clear bit 28 W Vector No. x3c Interrupt Req. Clear bit 27 W Vector No. x3b Interrupt Req. Clear bit 26 W Vector No. x3a Interrupt Req. Clear bit 25 W Vector No. x39 Interrupt Req. Clear bit 24 W Vector No. x38 Interrupt Req. Clear bit 23 W Vector No. x37 Interrupt Req. Clear bit 22 W Vector No. x36 Interrupt Req. Clear bit 21 W Vector No. x35 Interrupt Req. Clear bit 2 W Vector No. x34 Interrupt Req. Clear bit 19 W Vector No. x33 Interrupt Req. Clear bit 18 W Vector No. x32 Interrupt Req. Clear bit 17 W Vector No. x31 Interrupt Req. Clear bit 16 W Vector No. x3 Interrupt Req. Clear bit 15 W Vector No. x2f Interrupt Req. Clear bit 14 W Vector No. x2e Interrupt Req. Clear bit 13 W Vector No. x2d Interrupt Req. Clear bit 12 W Vector No. x2c Interrupt Req. Clear bit 11 W Vector No. x2b Interrupt Req. Clear bit 1 W Vector No. x2a Interrupt Req. Clear bit 9 W Vector No. x29 Interrupt Req. Clear bit 8 W Vector No. x28 Interrupt Req. Clear bit 7 W Vector No. x27 Interrupt Req. Clear bit 6 W Vector No. x26 Interrupt Req. Clear bit 5 W Vector No. x25 Interrupt Req. Clear bit 4 W Vector No. x24 Interrupt Req. Clear bit 3 W Vector No. x23 Interrupt Req. Clear bit 2 W Vector No. x22 Interrupt Req. Clear bit 1 W Vector No. x21 Interrupt Req. Clear bit W Vector No. x2 Interrupt Req. Clear bit * Interrupt Request Clear bit : No Effect Interrupt Mask. 1 : Pending 인터럽트가활성화되는것을마스킹 (interrupts not sent to CPU). 86 8 Interrupt Controller 8.3 Register Description Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr 9 CORE TIMER adstar_l 은 MCU 에밀접하게붙은 32-bit Core_Timer 가내장되어있다. 9.1 Features 15-bit Pre-scaler 32-bit Timer/Counter Core timer 는 CPU halt(halt3) 되면, counter 또한동작을멈춘다. CPU resume 되면 counter resume 된다. 9.2 15-bit Pre-scaler with clock source selection Pre-scaler 는 15-bit Pre-scaler 를통해 1/2 ~ 1/32768 배분주된클럭을생성하여 Timer/Counter 로 전달한다. Timer/Counter 는 Pre-scaler 를통해분주된클럭을선택하여 32-bit Counter 를구동한다. Pre-scaler 에서분주되는클럭의정확한위상이필요할경우에는 TPCON 레지스터의 CNTCLR 비트를 통하여 Pre-scaler counter 를초기화한후사용한다. Figure 9-1 Pre-scaler Block Diagram 87 9.1 Features 9 Core Timer Copyright 215, Advanced Digital Chips, Inc.

www.adc.co.kr 9.3 Timer/Counter Pre-scaler 에의해분주된 Clock 을사용하여설정된 Timer Counter register value 에서매 clock 마다 counter value 을 1 씩감소하여 x 에도달하면 interrupt 를발생하고, 다시사용자가설정한 Timer Counter register value 부터 1 씩감소하기시작한다. (Down Counter) (TMCNT : 사용자가설정한 timer counter register value) Figure 9-2 Timer Operation Timer 주기는선택된클럭, Pre-scaler 그리고 Timer Counter 에의해결정된다. 1 1 Timer Period TMCNT sec Clock Source Frequency Pr e scaler Factor 1 1 Timer Period TMCNT 1 sec Clock Source Frequency Pr e scaler Factor Pr e scaler Factor 3 Pr e scaler Factor 3 Timer Period Example : - Clock Source Frequency : 12MHz System Clock - Pre-scaler Factor : 1 / 124 - Timer Counter Value (TMCNT) : 1 => 1/12MHz X 124 X 1 = 85.333msec = 11.718Hz Timer Counter 로동작시키기위하여설정되어야하는레지스터는다음과같다. - TMRST : 필요에따라 Pre-scaler를 clear 한다. - TMCON s PFSEL : Timer Counter에서사용할 Clock을결정한다. - TMCON s TMEN : Timer Counter를 Enable 한다. - TMCNT : Timer Counter의시작 Counter 값을결정한다. Timer Counter 는다음순서로설정하여동작시킨다. - TMCNT 설정 - TMCTRL 설정 - 필요에따라 TMRST s CNTCLR 비트설정 88 9 Core Timer 9.3 Timer/Counter Copyright 215, Advanced Digital Chips, Inc.