1 - PDF Free Download

A0 A1 A2 CS0#, CS1# CS2#, CS3# CTS0#, CTS1# CTS2, CTS3# D7~D3, D2~D0 DCD0#, DCD1# DCD2#, DCD3# DSR0#, DSR1# DSR2#, DSR3# DTR0#, DTR1# DTR2#, DTR3# 34 (48) 33 (47) 32 (46) 16,20 (28, 33) 50,54 (68, 73) 11,25 (23, 38) 45,59 (63, 78) 66~68(15~11) 1~ 5 (9~7) 9,27 (19, 42) 43, 61 (59, 2) 10,26 (22, 39) 44,60 (62, 79) 12, 24(24, 37) 46, 58(64,77) GND 6, 23 (16,36) 40, 57 (56,76) INTN# 65 (6) I INT0, INT1 INT2, INT3 15,21(27,34) 19,55(67,74) O 52 (70) I IOW# 18 (31) I RESET 37 (53) I RI0#, RI1# RI2#, RI3# RTS0#, RTS1# RTS2#, RTS3# 8, 28 (18,43) 42, 62 (58, 3) 14, 22 (26,35) 48, 56 (66,75) Data Sheet Copyright2002, SystemBase Co, Ltd - 2 -

RXD0, RXD1 RXD2, RXD3 7, 29 (17, 44) 41, 63 (57, 4) RXRDY# 38 (54) TXD0, TXD1 TXD2, TXD3 17, 19 (29,32) 51, 53 (69,72) TXRDY# 39 (55) VCC 13, 30 (5, 25) 47, 64 (45,65) XTAL1 35 (50) XTAL2 36 (51) Data Sheet Copyright2002, SystemBase Co, Ltd - 3 -

ADDRESS REGISTER MNEMONIC REGISTER ADDRESS 0 RBR (read only) Data bit 7 (MSB) Data bit 6 Data bit 5 Data bit 4 Data bit 3 Data bit 2 Data bit 1 Data bit 0 (LSB) 0 THR (write only) Data bit 7 Data bit 6 Data bit 5 Data bit 4 Data bit 3 Data bit 2 Data bit 1 Data bit 0 0 DLL Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1 DLM Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 1 IER 0 0 0 0 2 FCR 2 IIR 3 LCR (write only) (read only) Receiver Trigger (MSB) FIFOs Enabled (DLAB) Divisor latch access bit Receiver Trigger (LSB) FIFOs Enabled 4 MCR 0 0 0 5 LSR 6 MSR Error in receiver FIFO (DCD) Data carrier detect (EDSSI) Enable modem status interrupt Reserved Reserved DMA mode select 0 0 Interrupt Set break Stick Parity (EPS) (TEMT) Transmitter registers empty (RI) Ring indicator (THRE) Transmitter holding register empty (DSR) Data set Ready Even parity select Loop (BI) Break interrupt (CTS) Clear to Send ID Bit (3) (PEN) Parity Enable OUT2 Enable external interrupt (INT) (FE) Framing Error ( DCD) Delta data carrier detect (ERLSI) Enable receiver line interrupt Transmit status FIFO reset Interrupt ID Bit (2) (STB) Number of Stop bits Reserved (PE) Parity Error (TERI) Trailing Edge indicator ring (ETBEI) Enable Transmitter Holding register empty interrupt Receiver FIFO reset Interrupt ID Bit (1) (WLSB1) Word length select bit 1 (RTS) Request to Send (OE) Overrun error ( DSR) Delta data set ready 7 SCR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DLAB = 1 FIFOdisable 0. (ERBI) Enable received data available interrupt FIFO enable 0 if interrupt pending (WLSB0) Word length select bit 0 (DTR) Data terminal ready (DR) Data ready ( CTS) Delta clear to send Data Sheet Copyright2002, SystemBase Co, Ltd - 4 -

LCR LCR LCR LCR LCR LCR LCR LCR 7 6 5 4 3 2 1 0 Word Length 0 0 = 5 Data Bits 0 1 = 6 Data Bits 1 0 = 7 Data Bits 1 1 = 8 Data Bits Stop Bit 0 = 1 Stop Bit 1 = data bit 5 1.5 Stop Bit data bit 6,7,8 2 Stop Bit 0 = Parity Disabled Parity Enable 1 = Parity Enabled 0 = 1 = 0 = 1 = 0 = 1 = Divisor Latch 0 = Access Bit 1 = Divisor Latch 1.8432MHz, 3.6864MHz, 7.3728MHz14.7456MHz crystal divisor. 38400 baud. baud rate crystalfrequency. Divisor 0. Data Sheet Copyright2002, SystemBase Co, Ltd - 7 -

FIFO mode only Interrupt Identification Register set / reset Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 1 - - - - 0 1 1 0 1 Receiver Line Status 0 1 0 0 2 Receiver Data Available 1 1 0 0 2 Character Timeout Indication 0 0 1 0 3 Transmitter Holding Register Empty OE, PE, FE, BI LSR 0 0 0 0 4 Modem Status CTS, DSR, RI, DCD Data Sheet Copyright2002, SystemBase Co, Ltd - 10 -

DSR0# CTS0# DTR0# VCC RTS0# INT0 CS0# TXD0 IOW# TXD1 CS1# INT1 RTS1# GND DTR1# CTS1# DSR1# 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 10 60 11 59 12 58 13 57 14 56 15 55 16 54 17 53 18 52 19 51 20 50 21 49 22 48 23 47 24 46 25 45 26 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 DSR3# CTS3# DTR3# GND RTS3# INT3 CS3# TXD3 TXD2 CS2# INT2 RTS2# VCC DTR2# CTS2# DSR2# DCD1# RI1# RXD1 VCC A2 A1 A0 XTAL1 XTAL2 RESET RXRDY# TXRDY# GND RXD2 RI2# DCD2# DCD0# RI0# RXD0 GND D7 D6 D5 D4 D3 D2 D1 D0 INTN# VCC RXD3 RI3# DCD3# - No internal connection Data Sheet Copyright2002, SystemBase Co, Ltd - 12 -

D5 TXD2 DCD2# 75 DSR3# 55 40 22 34 69 31 RXD2 4 INTN# 71 1 2 30 73 41 20 A2 32 DSR2# 14 27 44 79 70 GND 50 62 DSR0# CTS1# 33 56 43 39 21 D4 GND RXD0 DSR1# TXRDY# 76 7 RXD1 49 10 47 INT0 64 - No internal connection 66 RI1# RI3# 25 35 GND 63 17 CS1# 77 80 RTS0# TXD1 13 D7 RTS1# 29 D2 DTR2# 36 60 INT1 42 8 CTS3# 51 D6 INT3 65 38 53 VCC D3 D1 TXD0 45 16 XTAL1 11 RTS3# 26 CS3# IOW# 24 CS0# 78 6 68 67 D0 DCD3# 57 VCC DTR0# 15 VCC RI2# 59 VCC GND XTAL2 RXD3 A1 54 37 48 CS2# 18 3 CTS2# 28 TXD3 58 DTR1# 19 23 RTS2# 74 DTR3# 12 61 9 5 DCD1# CTS0# INT2 72 A0 RESET RXRDY# RI0# 46 52 DCD0# Data Sheet Copyright2002, SystemBase Co, Ltd - 13 -

Vcc V IH(CLK V IL(CLK) V IH V IL f CLOCK T A t rd t csr t ar t ra t rcs t frc t rc t ar +t rd +t rc t wr t csw t aw t ds t wa t wcs t dh t fwc t wc t aw +t wr +t wc t rvd t hz Data Sheet Copyright2002, SystemBase Co, Ltd - 14 -

t irs t sti t si t sxa t hr t ir t wxi RCLK cycles RCLK cycles RCLK cycles RCLK cycles MIN MAX t sint Delay time, stop bit to INTxor stop bit to RXRDY# or read RBR to set interrupt t rint Propagation delay time, Read RBR/LSR to INTx /LSR interrupt t rint Propagation delay time, RCLKto RXRDY# t mdo Propagation delay time, IOW#(WR MCR)to RTSx#, DTRx# t sim Propagation delay time, modem input CTSx#, DSRx#, and DCDx# to INTx t rim Propagation delay time, (RD MSR)to interrupt t sim Propagation delay time, Rix#to INTx# A[2:0] VALID ADDRESS tra CSx# t csr tar t frc trcs ACTIVE trd trc IOW# trvd thz D[7:0] VALID DATA Data Sheet Copyright2002, SystemBase Co, Ltd - 15 -

A[2:0] VALID ADDRESS t wa CSx# tcsw taw tfwc twcs twr twc IOW# ACTIVE tds tdh D[7:0] VALID DATA TXDx START DATA(5-8) PARITY STOP(1-2) START tirs t sti INTx t hr tsi thr IOW# (WR THR) tir (RD IIR) IOW# (WR THR) BYTE #1 TXDx DATA PARITY STOP START TXRDY# twxi t sxa Data Sheet Copyright2002, SystemBase Co, Ltd - 16 -

IOW# (WR THR) BYTE #16 TXDx DATA PARITY STOP START TXRDY# FIFO FULL twxi tsxa RXDx START DATA(5-8) PARITY STOP Sample Clock INTx(TRIGGER LEVEL INTERRUPT (FCR6, 7 = 0, 0) tsint t rint (FIFO AT OR ABOVE TRIGGER LEVEL) (FIFO BELOW TRIGGER LEVEL) LSI INTERRUPT (RD LSR) trint (RD RBR) RXDx STOP Sample Clock TIMEOUT OR TRIGGER LEVEL INTERRUPT tsint trint (FIFO AT OR ABOVE TRIGGER LEVEL) (FIFO BELOW TRIGGER LEVEL) LSI INTERRUPT (RD LSR) t sint TOP BYTE OF FIFO trint (RD RBR) PREVIOUS BYTE READ FROM FIFO Data Sheet Copyright2002, SystemBase Co, Ltd - 17 -

(RD RBR) RXDx (FIRST BYTE) STOP Sample Clock RXRDY# tsint trint (RD RBR) RXDx (FIRST BYTE THAT REACHES THE TRIGGER LEVEL) Sample Clock STOP RXRDY# tsint trint IOW# (WR MCR) tmdo tmdo RTSx#, DTRx# CTSx#, DSRx#, DCDx# INTx tsim trim tsim trim tsim (RD MSR) RIx# Data Sheet Copyright2002, SystemBase Co, Ltd - 18 -

0.995 (25,273) 0.985 (25,019) 0.956 (24,282) 0.950 (24,130) 0.032 (0.081) 0.026 (0,66) 0.18 (4,57) MAX 0.120 (3,05) 0.090 (2,29) 0.02 (0,51) MIN 0.995 (25,273) 0.985 (25,019) 0.956 (24,282) 0.950 (24,130) 0.469 (11,913) 0.469 (11,913) 0.441 (11,201) 0.441 (11,201) Data Sheet Copyright2002, SystemBase Co, Ltd 0.050 (1,27) 0.021 (0,53) 0.013 (0,33) - 20 -