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1 (Regular Paper) 18 6, (JBE Vol. 18, No. 6, November 2013) ISSN (Online) ISSN (Print) HEVC a), a), b), b), b), a) Study of Parallelization Methods for Software based Real-time HEVC Encoder Implementation Yong-Jo Ahn a), Tae-Jin Hwang a), Dongkyu Lee b), Sangmin Kim b), Seoung-Jun Oh b), and Dong-Gyu Sim a) ISO/IEC MPEG ITU-T VCEG JCT-VC (Joint Collaborative Team on Video Coding) HEVC (High Efficiency Video Coding) H.264/AVC 2.,. HEVC, HEVC. HEVC SIMD, CPU GPU., HEVC. HM (HEVC reference model) ~30fps, ~10fps. Abstract Joint Collaborative Team on Video Coding (JCT-VC), which have founded ISO/IEC MPEG and ITU-T VCEG, has standardized High Efficiency Video Coding (HEVC). Standardization of HEVC has started with purpose of twice or more coding performance compared to H.264/AVC. However, flexible and hierarchical coding block and recursive coding structure are problems to overcome of HEVC standard. Many fast encoding algorithms for reducing computational complexity of HEVC encoder have been proposed. However, it is hard to implement a real-time HEVC encoder only with those fast encoding algorithms. In this paper, for implementation of software-based real-time HEVC encoder, data-level parallelism using SIMD instructions and CPU/GPU multi-threading methods are proposed. And we also proposed appropriate operations and functional modules to apply the proposed methods on HM 10.0 software. Evaluation of the proposed methods implemented on HM 10.0 software showed 20-30fps for sequences and 5-10fps for sequences, respectively. Keyword : HEVC, encoder, real-time, parallelization
2 (JBE Vol. 18, No. 6, November 2013). FHD (full high definition) UHD (ultra high definition), ISO/IEC MPEG (moving picture experts group) ITU-T VCEG (video coding expert group) JCT-VC (joint collaborative team on video coding) H.264/AVC 2 HEVC (high efficiency video coding) [1][2]. HEVC, H.264/AVC, MPEG-2, 4 CU (coding unit), PU (prediction unit), TU (trans- form unit)., HEVC 64 64, 32 32, 16 16, 8 8 CU.,,, -.,,., (RDO: rate-distortion optimization) cost. HEVC a) (Dept. of Computer Engineering, Kwangwoon university) b) (Dept. of Electronic Engineering, Kwangwoon university) Corresponding Author : (Dong-Gyu Sim) dgsim@kw.ac.kr Tel: ( ).[ , 3D ] Manuscript received September 10, 2013 Revised October 23, 2013 Accepted October 23, 2013., HEVC [3][4][5]. HEVC HM 50~60%., HEVC. HEVC, SIMD (single instruction multiple data) (DLP: data level parallelism), CPU GPU (multi threading),.. 2 SIMD HEVC, 3 CPU GPU HEVC., 4 2, 3 HEVC HM, HEVC. 5 HEVC.. SIMD HEVC HEVC SIMD. SIMD. SIMD
![[6][7][8]. SIMD HEVC, - cost, (transform) - (inverse-transform), (interpolation filter). SIMD. 1.](/docs-images/104/163771250/images/3-1.jpg "Cost HEVC - SAD (sum of absolute difference), SATD (sum of absolute transformed difference), SSE (sum of square error) cost. cost HEVC HM 30% [9]. HM cost., SAD SATD, HM SAD 10~12%, SATD 15~16%.")
3 [6][7][8]. SIMD HEVC, - cost, (transform) - (inverse-transform), (interpolation filter). SIMD. 1. Cost HEVC - SAD (sum of absolute difference), SATD (sum of absolute transformed difference), SSE (sum of square error) cost. cost HEVC HM 30% [9]. HM cost., SAD SATD, HM SAD 10~12%, SATD 15~16%., SSE - HM 2~3%., SIMD SAD, SSE 4 4, 8 8 SATD SIMD., SAD. 8, SAD 128 PSADBW. PSADBW PSADBW Fig. 1. PSADBW instruction 2. Butterfly 2 2 SATD Fig SATD using butterfly method
4 (JBE Vol. 18, No. 6, November 2013) 8 SAD 16, 8 SAD 16. SATD. HM SATD butterfly , SIMD. SSE. SSE 16 8 PSUBW, PMADDWD cost SIMD -. HEVC - (quad-tree) TU. HEVC , , HM - partial butterfly / -., - TU. - SIMD. - SIMD SIMD. 3 -., HEVC cost, - 3. SIMD Fig inverse-transform using SIMD instruction
![30%. HEVC 8-tap 7-tap DCT-IF, 4-tap DCT-IF. DCT-IF, DCT,. HEVC DCT-IF tap HEVC [10]., SIMD DLP,. 8 4 15, 4. SIMD Fig. 4. Horizontal directional interpolation filter using SIMD instruction 5.](/docs-images/104/163771250/images/5-0.jpg "SIMD Fig. 5. Vertical directional interpolation filter using SIMD instruction")
5 30%. HEVC 8-tap 7-tap DCT-IF, 4-tap DCT-IF. DCT-IF, DCT,. HEVC DCT-IF tap HEVC [10]., SIMD DLP, , 4. SIMD Fig. 4. Horizontal directional interpolation filter using SIMD instruction 5. SIMD Fig. 5. Vertical directional interpolation filter using SIMD instruction
6 (JBE Vol. 18, No. 6, November 2013) ,, PADDW PMULLW.. CPU/GPU HEVC HEVC CPU GPU. 2 SIMD DLP CPU GPU SIMD. 1 OpenMP CPU, 2 CUDA GPU, GPU GPU (block partition). 1. CPU multi-threading / OpenMP CPU API - (fork-join). HEVC CPU OpenMP.,,,.,.,.,.,. HEVC,. HEVC version HEVC MP (main profile) WPP (wave-front parallel processing)., HEVC,, WPP., HEVC DLP WPP,.,,.,,., HEVC,. 6,. 6
![, GPU GPU 3D GPGPU (general- purpose computing on GPU). NVidia CUDA (compute unified device architecture) GPU [11]. CUDA,, GPU, 1. Table 1.](/docs-images/104/163771250/images/7-1.jpg "Required classes and roles of instances for parallel processing of slice and tile TEncSearch TComTrQuant TComRdCost TEncEntropyCoder TEncCavlc TEncSbac TEncBinCABAC")
7 (a) (b) 6. ((a) 4, (b) 4 ) Fig. 6. Threads allocation and coding order according to parallel processing of slice and tile ((a) 4 slices, (b) 4 tiles), CTU Z-. HM OpenMP,. 1 HM. HM TEncTop, (GOP,, CU ). 1 CU., CABAC, RDO CABAC CABAC RDO CABAC. 2. GPU GPU (graphics processing unit) CPU (central processing unit)., GPU GPU 3D GPGPU (general- purpose computing on GPU). NVidia CUDA (compute unified device architecture) GPU [11]. CUDA,, GPU, 1. Table 1. Required classes and roles of instances for parallel processing of slice and tile TEncSearch TComTrQuant TComRdCost TEncEntropyCoder TEncCavlc TEncSbac TEncBinCABAC TBinCABACCounter TEncBitCounter TEncSlice TEncCu RD-cost CAVLC CABAC Bin CABAC Bin (* ) CU
8 (JBE Vol. 18, No. 6, November 2013) 7. GPU HEVC Fig. 7. HEVC encoder flow chart using GPU-based motion estimation.,, - [12][13][14]. HM 70~80%, GPU. GPU GPU CPU GPU., GPU. HEVC GPU,. PU. GPU, HEVC CU PU. HEVC AMVP (advanced motion vector prediction) CTU PU (MVP : motion vector predictor),., CU 8. GPU Fig. 8. HEVC encoder flow chart using GPU-based motion estimation and block partition decision
9 CU AMVP. CU CTU MVP. (co-located) CTU TMVP (temporal MVP) CTU MVP., CTU PU MVP. (full-search), PU SAD PU SAD SAD (hierarchical SAD computing) - CPR (concurrent parallel reduction) [15]., [16] GPU. GPU CPU. 7 GPU HEVC. HEVC. GPU GPU, CPU. CPU RDO. GPU - RDO CTU,,. CPU RDO,,. 8 GPU. HM 10.0 C SIMD, OpenMP CPU, CUDA GPU. HEVC 2 HEVC [17]. PC, (FPS : frames per second)., (1) ATS (average time saving). Etime anchor, Etime proposed. 3 SIMD. SIMD 45.92% ATS. SIMD, SAD, SATD, SSE cost 4, - partial butterfly 3~4 2. HEVC Table 2. Test environment for parallel processing of HEVC encoder CPU CPU ( ) Intel(R) CoreTM i7-3960x 6 (12: hyper threading). Clock OS 3.3GHz 48 GB (DDR3) Windows 8 (64-bit) HEVC. HEVC, HEVC Intel 64-bit GPU NVIDIA GeForce GTX 660 Ti CUDA CUDA toolkit 5.0
10 (JBE Vol. 18, No. 6, November 2013) 3. SIMD DLP HEVC Table 3. Average time saving of HEVC encoder according to DLP using SIMD instructions Sequence QP Bitrate PSNR Y PSNR U PSNR V Enc. time Anchor SIMD ATS (%) Kimono ParkScene Cactus Basketball Drive BQTerrace Average ATS (%) GPU Table 4. Speed up of integer-pel motion estimation execution time using GPU multi-threading Sequence QP HM full search (ms) GPU (ms) speed up HM fast search (ms) GPU (ms) speed up Kimono ParkScene Cactus BasketballDrive BQTerrace Average
11 ., 4. 9 CPU. 16, , 8 4.5, CPU,.. GPU. GPU anchor HM GPU CPU GPU. Geforce GTX HM GPU. 364, GPU HM 11. SIMD DLP CPU GPU HEVC. SIMD cost, -, DLP., CUDA GPU. OpenMP CPU. HEVC 5. LDP (low-delay P) (a) 9. Fig. 9. Speed up of encoding time according to the number of slices and tiles (b)
12 (JBE Vol. 18, No. 6, November 2013) 5. HEVC Table 5. Encoding time of HEVC encoder with proposed parallel processing methods Class Sequence Frame QP FPS Kimono ParkScene B Cactus BasketballDrive BQTerrace BasketballDrill BQMall C PartyScene RaceHorses , QP 22, 27, 32, 37., 1, CTU HEVC,. cost, -, SIMD DLP. SIMD DLP HEVC 2., OpenMP CPU, CUDA GPU
13 . OpenMP CPU 4 3.5, HEVC ~30fps, ~10fps. SIMD DLP cost, -,,, SIMD., CPU GPU , 2K 4K HEVC. (References) [1] G. J. Sulivan, J.-R. Ohm, Recent developments in standardization of high efficiency video coding (HEVC), SPIE Application of Digital Image Proc. XXXIII, vol. 7798, pp , Aug [2] JCT-VC, Report of subjective test results of responses to the joint call for proposals (CfP) on Video coding technology for high efficiency video coding (HEVC), Document JCTVC-A204, Dresden, DE, Apr [3] R. H. Gweon, Y.-L. Lee, J. Lim, "Early termination of CU encoding to reduce HEVC complexity, ITU-T/ISO/IEC Joint Collaborative Team on Video Coding (JCT-VC) document JCTVC-F045, Jul [4] K. Choi, E. S. Jang, Coding tree pruning based CU early termination, ITU-T/ISO/IEC Joint Collaborative Team on Video Coding (JCT-VC) document JCTVC-F092, Jul [5] J. Wang, J. Kim, K. won, H. Lee, B. Jeon, Early skip detection for HEVC, ITU-T/ISO/IEC Joint Collaborative Team on Video Coding (JCT-VC) document JCTVC-G543, Jul [6] L. Yan, Y. Duan, J. Sun and Z. Guo, Implementation of HEVC decoder on x86 processor with SIMD optimiation, CVIP, pp. 1-6, Nov [7] K. Chen, Y. Duan, L. Yan, J. Sun, and Z. Guo, Efficient SIMD optimization of HEVC encoder over x86 processor, APSIPA ASC 2012 Asia-pacific, pp. 1-4, Dec [8] M. Alvarez-Mesa, C. C. chi, V. George, T. Schierl, and B. Juurlink, Parallel video decoding in the emerging HEVC standard, Proceedings of International Conference on Acoustics, Speech, and Signal Processing (ICASSP 2012), Kyoto, Japan, March [9] Y. J. Ahn, T. J. Hwang, S. E. Yoo, W. -J. Han, and D. G. Sim, "Statistical characteristics and complexity analysis of HEVC encoder software," Journal of Broadcasting & Electronic Media, vol. 17, no. 6, pp , Nov [10] Y. J. Ahn, W. J. Han, and D. G. Sim, Study of decoder complexity for HEVC and AVC standards based on tool-by-tool comparision, SPIE Applications of Digital Image Proc. XXXV, vol. 8499, pp , Aug [11] NVIDIA, CUDA C programming guide, document PG _ v5.0, Oct [12] W.-N. Chen and H.-M. Hang, H.264/AVC motion estimation implementation on compute unified device architecture (CUDA), IEEE International Conference on Multimedia and Expo 2008 (ICME'08), pp , April [13] N.-M. Cheung, X. Fan, O. C. Au, and M.-C. Kung, Video coding on multi-core graphics processors, in Proc. IEEE Siganl Process. Mag., 2010, pp [14] Z. Jing, J. Liangbao, and C. Xuehong, Implementation of parallel full search algorithm for motion estimation on multi-core processors. The 2nd International Conference on Next Generation Information Technology (ICNIT), pp , June [15] D.-K. Lee and S.-J. Oh, Variable block size motion estimation implementation on compute unified device architecture (CUDA), IEEE International Conference on Consumer Electronics, pp , Jan [16] S. Kim, D. Lee, Y. Ahn, T.-J. Hwang, D. Sim, and S.-J. Oh, DCT-based interpolation filter for HEVC on Graphics processing units, International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), pp , July [17] F. Bossen, Common test conditions and software reference configuration, ITU-T/ISO/IEC Joint Collaborative Team on Video Coding (JCT-VC) document JCTVC-G1200, Nov
14 848 방송공학회논문지 제18권 제6호, 2013년 11월 (JBE Vol. 18, No. 6, November 2013) 저자소개 안용조 년 2월 : 광운대학교 컴퓨터공학과 학사 년 2월 : 광운대학교 컴퓨터공학과 석사 년 3월 ~ 현재 : 광운대학교 컴퓨터공학과 박사과정 주관심분야 : 영상압축, 최적화 및 병렬화 황태진 년 2월 : 광운대학교 컴퓨터공학과 학사 년 3월 ~ 현재 : 광운대학교 컴퓨터공학과 석사과정 주관심분야 : 영상압축, 멀티미디어시스템 이동규 년 2월 : 광운대학교 전자공학과 학사 년 3월 ~ 현재 : 광운대학교 전자공학과 석사과정 주관심분야 : 영상압축, 컴퓨터비전 김상민 년 2월 : 광운대학교 전자공학과 학사 년 3월 ~ 현재 : 광운대학교 전자공학과 석사과정 주관심분야 : 영상압축, 최적화 및 병렬화 오승준 - 년 2월 : 서울대학교 전자공학과 학사 년 2월 : 서울대학교 전자공학과 석사 년 5월 : 미국 Syracuse University 전기/컴퓨터공학과 박사 년 3월 ~ 1992년 8월 : 한국전자통신연구원 멀티미디어연구실 실장 년 7월 ~ 1986년 8월 : NSF Supercomputer Center 초청 학생연구원 년 5월 ~ 1988년 5월 : Northeast Parallel Architecture Center 학생연구원 년 3월 ~ 1992년 8월 : 충남대학교 컴퓨터공학부 겸임교수 년 9월 ~ 현재 : 광운대학교 전자공학과 교수 년 3월 ~ 현재 : SC29-Korea 의장 및 MPEG Forum 부의장 주관심분야 : 비디오 데이터 처리, 영상압축, 멀티미디어시스템
15 : : : ~ : ~ : ~ : University of Washington Senior research engineer ~ : - :,,
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3 : HEVC GPU (Sangmin Kim et al. : Adaptive Search Range Decision for Accelerating GPU-based Integer-pel Motion Estimation in HEVC Encoders) (Regular Paper) 19 5, 2014 9 (JBE Vol. 19, No. 5, September
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그림 2. 최근 출시된 스마트폰의 최대 확장 가능한 내장 및 외장 메모리 용량 원한다. 예전의 피쳐폰에 비해 대용량 메모리를 채택하고 있지 만, 아직 데스크톱 컴퓨터 에 비하면 턱없이 부족한 용량이다. 또한, 대용량 외장 메모리는 그 비용이 비싼 편이다. 그러므로 기존
스마트폰을 위한 A/V 신호처리기술 편집위원 : 김홍국 (광주과학기술원) 스마트폰을 위한 동영상 압축 기술 호요성, 최정아 광주과학기술원 요 약 스마트폰이 대중화되면서 이동통신 시장은 일대 혁신을 맞이 했다. 최근 출시되는 스마트폰이 크고 선명한 화면과 빠른 프로 세서를 잇따라 탑재하면서 고해상도 및 고품질 영상에 대한 사 용자들의 수요가 급증하고 있다. 하지만
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방송시스템 13 주차 MPEG2 1 개요 MPEG2의 I, P, B picture에대해이해한다. 움직임예측과움직임보상에대해이해한다. MPEG2의압축율가변요소를이해한다. 프로파일과레벨의의미를이해한다. 2 목차 1. Compression overview 2. MPEG structure 3. Basic MPEG Video Compression Algorithms
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리눅스 환경에서Solid-State Disk 성능 최적화를 위한 디스크 입출력요구 변환 계층 김태웅 류준길 박찬익 Taewoong Kim Junkil Ryu Chanik Park 포항공과대학교 컴퓨터공학과 {ehoto, lancer, cipark}@postech.ac.kr 요약 SSD(Solid-State Disk)는 여러 개의 낸드 플래시 메모리들로 구성된
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