Introduction AMBA Coreconnect WISHBONE Sonics µnetworks Open Core Protocol PI-Bus CoreFrame 참고문헌 2

Transcription

1 Module 12 Communication-Centric SoC Platform Architectu re 조준동교수 ( 성균관대학교 )

2 Introduction AMBA Coreconnect WISHBONE Sonics µnetworks Open Core Protocol PI-Bus CoreFrame 참고문헌 2

3 Introduction 1 System-On-Chip 설계에서이미설계된코어들을연결시켜시스템을구성하기위해가장필요한기술중에하나는 on chip bus 기술이다. Bus 란 Processor 와다른 device (input/output device, memory 등 ) 를연결하는 communication channel 을의미한다. Bus 의기본 3 요소 address bus data bus control bus 3

4 Blocking/Non-Blocking Communication We distinguish between blocking and non-blocking communication: blocking communication: the process element initiating the communication goes in a waiting state until communication end. non-blocking communication: the process element initiating the communication can execute other useful tasks during an ongoing communication. both types of communication are useful. 4

5 Two major communication s shared memory message passing 5

6 Predefined master/slave devices device 1 is master and initiates communication device 2 is slave send or receive is possible data bus is bidirectional 6

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8 Shared communication chan nel (Shared bus) Request MASTER #1 MASTER #2 MASTER #3 GRANT Communication Channel (BUS) Arbiter SLAVE #1 SLAVE #2 SLAVE #3 8

9 Typical Processor Bus a bus is a colle ction of wires a s well as a prot ocol microprocessor buses build on handshake prot ocol basic bus oper ations are readi ng and writing system clock h elps to increase data transfer s peed 9

10 Bus With DMA Controller DMAcontrollers perform dir ect data transfers between devices without CPU invol vement four-cycle-handshake wit h processor to get bus master (interrupt processor when finished) used for high speed requir ements to prevent to block the pr ocessor too long, partial block transfer mode possib le, 16, 32 or 256 words bus DMA controller is a b us with 2 masters 10

11 Bus bridge: Module 12. Communication-Centric SoC platform architecture slave at fast bus, master at slow bus high-speed buses provide wider data connections high-speed buses require more expensive circuitry and conne ctors. The cost of low-speed devices can be held down by usin g lower-speed, lower-cost bus. The bridge may allow the buses to operate independently, there by providing some parallelism in processing an I/O operations. 11

12 Standard SoC Bus! Avalon from Altera Inc., used for Nios! AMBATM bus from AMD Inc., used for ARM! CoreConnectTM from IBM Inc., used for PowerPC Creating an SoC is easier. Cores already speak the same language Improves reusability of IP cores More usage means lesser bugs Improves portability Between languages Between technologies Improves reliability Lesser bugs Less error prone handlings (wrappers, bridges, etc) 12

13 Bus architecture type Common memory-i/o bus Independent I/O bus MCU System bus Bridge Peripheral bus I/O Device I/O Device Main memory 13

14 AMBA (Advanced Microcontroller Bu s Architecture) The advanced high-performance bus (AHB)! high-performance! pipelined operation! multiple bus master! burst transfer! split transactions The Advanced System Bus (ASB) dito, but no split transactions The Advanced Peripheral Bus (APB)! low-power! latched address and control! simple interface! suitable for many peripherals AMBA 는 embedded microcontroller 의설계를위한 on-chip communication 의표준안이되고있다. 14

15 AMBA A typical AMBA-based microcontroller High-performance ARM processor High-bandwidth on-chip RAM UART Timer High-bandwidth External Memory Interface AHB or ASB DMA bus Master Bridge AHB to APB Bridge or ASB to APB Bridge Keypad APB PIO AMBA AHB - High performance - Pipelined operation - Multiple bus masters - Burst transfers - Split transactions AMBA ASB - High performance - Pipelined operation - Multiple bus masters AMBA APB - Low power - Latched address and control - Simple interface - Suitable for many peripherals 15

16 AMBA Bus Interconnection MASTER #1 HADDR HWDATA HRDATA Arbiter HADDR HWDATA HRDATA Slave #1 MASTER #2 MASTER #3 HADDR HWDATA HRDATA HADDR HWDATA HRDATA Address and control mux Write data mux Read data mux HADDR HWDATA HRDATA HADDR HWDATA HRDATA HADDR HWDATA HRDATA Slave #2 Slave #3 Slave #4 Decoder 16

17 AMBA Signals H : AHB signal 임을의미한다 B : ASB signal 임을의미한다 A : ASB 의 arbiter 와 master 간에사용되는 signal 임을의미한다 D : ASB 의 decoder 에사용되는 signal 임을의미한다. P : APB signal 임을의미한다. 예를들어서 HREADY 라함은 AHB 의 HIGH 에서동작하는 signal 임을의미하고, BnRES 라함은 ASB 의 LOW 에서동작하는 reset signal 임을알수있다. 17

18 AMBA AHB signal list 신호명 Source 설명 HCLK clock AHB bus clock, 모든 bus transfer 의 timing, realted to t he rising edge of HCLK HRESETn reset // reset system and bus, active LOW HADDR[31:0] master // 32bit address bus HTRANS[31: 0] // // transfer type, NONSEQ/SEQ/IDLE/BUSY HWRITE // // transfer 방향, HIGH : write transfer, LOW : read t ransfer HSIZE[2:0] // // transfer 크기, byte/half-word/word HBURST[2:0] // // burst type, burst 의일부분여부를알려줌. 4/8/16bi t burst HPROT[3:0] // // protection control, opcode fetch/data access, priv ileged/user mode access. HWDATA[31: 0] // // write data bus(32bit), data 를 write operation 동안 master 에서 slave 로전달 HSELx decode r // slave sel, 각 slave 의선택신호, 간단히 address bus 의 combinational decode 18

19 HRDATA[31:0] slave // HREADY // // HRESP[1:0] // // read data bus, data 를 read operation 동안 slave 에서 mas ter 로전달 transfer done, HIGH : bus 에서 transfer 완료. bus 의 slave 는신호입출력에이신호를요구한다. transfer response, 전달상태정보. OKAY/ERROR/RETRY/SPLIT HBUSREQx master Arbi- trate bus request, master x 가 bus 를요구한다고 arbiter 에보내는신호, 최대 16 개 HLOCKx // // locked transfer, HIGH : master 가 locked access 를요구, 다른 master 는 bus 를사용할수없다 HGRANTx arbiter // bus grant, master x 가현재 priority mater 임. address/co ntrol 신호의소유는전송의끝에서 HREADY 가 HIGH 이면바뀌게된다. 따라서한 master 는 (HREADYandH RANTx=1) 일때 access 할수있다. HMASTER[3:0] // // HMASTERLOCK // // HSPLITx[15:0] slave // master number, arbiter 로부터의현재전송을하고있는 m aster 의정보 현 master 가 locked 전송 sequence 라는것을알려주는신호 split completion request, 어떤 bus master 가 split 전송을재시도하기위해사용되어야하는지를 slave 에서 arbite r 로전달 (16) 19

20 신호명 비고 설명 PCLK APB bus clock, APB 의 timing, rising-edge PRESETn // system bus reset 에직접연결되는 bus reser, active LOW PADDR[3 1:0] PSELx // // APB address bus, peripheral bus bridge 에의해 drive 되는 32bit ad dress peripheral bus bridge unit 내의두번째 decoder 로부터각 peripheral bus slave x 에전달되는신호, 이신호는 slave 가선택되고, data 전달이요구된다는것을의미한다. PENABLE // APB strobe, peripheral bus 상의 timing 을 strobe. APB 전송의두번째 cycle 을알려준다. PWRITE // APB 전송방향, HIGH : APB write access, LOW : read access PRDATA PWDATA // // APB read data bus, read cycle 동안선택된 slave 에의해 drive 된다.( PWRITE : LOW 시 ) write data bus, write cycle 동안 peripheral bus bridge unit 에의해 d rive 된다.(PWRITE : HIGH) 20

21 Advanced High-Performance Bus (AHB)! AHB master:! able to initiate read and write transfers! only one bus master is allowed to control the bus! AHB slave:! responds to read and write operations in a given address space! signals back to the master: success, failure or waiting of the data transfer! AHB arbiter:! ensures that only one master at a time is allowed to control bus! any arbitration algorithm can be used, like highest priority, fair access, etc! AHB decoder:! decodes address and generates device select signals! single centralized decoder is required 21

22 AMBA AMBA AHB system 을구성하는요소는다음과같다. 구성요소 설 명 AHB Mast er Bus Master 는 Address 나 control signal 들을내보냄으로 read 나 write 의 o peration 을할수있도록해주는장치이다. 한번에하나의 Master 만이전송을가능하게한다 AHB Slave Bus Slave 는주어진 address-space 안에서 read 와 write 를가능하게해주는장치이다. Slave 는 ready 등의 signal 을통해서 master 로하여금기다리게하거나전송이잘못되었음을알린다 AHB arbite r AHB deco der Bus Arbiter 는한번에오직하나의 Master 가선택되도록하는역할을한다. 고유의 priority algorithm 을가지고이러한 arbitration 을하게되는데, AH B 에는오직하나의 arbiter 가존재하게된다. AHB decoder 의역할은 Master 로나오는 Address 의상위비트를가지고서적절한 slave 를선택해주는것이다. AHB 에는역시하나의 Decoder 가존재한다 22

23 AMBA AHB Interconnection Schema arbiter determines bus master central multiplexor schema central decoder for read data additional characteristics: single cycle bus master handover single clock edge operation non-tristate implementation wider data bus configuration (64/128 bits) 23

24 Basic AHB Transfer Phases: address & control phase one or more data phase Slave can delay transfer with HREADY address source is master: HADDR[31:0] data source for write operations is master: HWDATA[31:0] data source for read operations is slave: HRDATA[31:0] 24

25 AHB Transfer Example Master shows transfer type with HTRANS[1:0] IDLE ( 00 ): no data transfer is required BUSY ( 01 ): master is delaying an ongoing transfer NONSEQUENTIAL ( 10 ): first transfer of a burst or single transfer SEQ ( 11 ): remaining transfers of a burst! Delaying transfer! master delays transfer with HTRANS[1:0]! slave delays transfer with HREADY! incremental burst of unspecified length is shown 25

26 AHB Transfer Example (4-beat wrapping burst) Master defines bus operation with HBURST[2:0]! SINGLE ( 000 ): single transfer! INCR ( 001 ): increment burst of unspecified length! WRAP4 ( 010 ): 4-beat wrapping burst! INCR4 ( 011 ): 4-beat incrementing burst! WRAP8 ( 100 ): 8-beat wrapping burst! INCR8 ( 101 ): 8-beat incrementing burst! WRAP16 ( 110 ): 16-beat wrapping burst! INCR16 ( 111 ): 16-beat incrementing burst Burst must not cross 1kB address boundary Module 12. Communication-Centric SoC platform architecture 26

27 AHB Transfer Example with Response slave can complete a transfer in a number of ways:! complete the transfer immediately! insert wait states! signal an error to indicate transfer has failed! delay the completion of the transfer, but allow master/slave to back off bus slave shows status of transfer with HRESP[1:0] in combination with HREADY! OKAY: transfer is progressing normally! ERROR: transfer has been unsuccessful! RETRY and SPLIT: both indicate that transfer cannot complete immediately! ERROR, RETRY and SPLIT are at least two-cycles 27

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29 AHB Transfer type HTRAN [1:0] Type Description 00 IDLE 아무런전송이필요하지않음을의미한다. 즉해당 master에게 grant가이루어졌지만아무런전송을하지않으려할때에 IDLE transfer를하게된다. Slave는 zero wait state의 OKAY response를하며 transfer는 sl ave에의해서무시되어진다. 01 BUSY BUSY transfer 는 burst transfer 의중간에 IDLE cycle 을넣으려고할때나타난다. 즉 master 가계속하여 burst transfer 를하려고하지만즉시다음전송이이루어질수없는상황에서 BUSY 을나타낸다. BUSY 의 cy cle 에서는현재의모든 control signal 들이다음 cycle 로전달되며 BU SY 상태의전송은 slave 에의해서모두무시되어야한다. Slave 는 IDL E 상태와같이 zero wait state 의 OKAY response 를해야한다. 10 NON SEQ Burst transfer 의첫번째전송을의미하거나 single transfer 를의미한다. 또한현재 Address 와 control signal 들은전의 transfer 와상관이없음을알려준다. 11 SEQ Burst transfer의나머지는모두 SEQUENTIAL로나타나며이것은전의 ad dress와 control이현재의 transfer와상관이있다는것을알려준다. 그리하여현재의 address는전의 address에서 transfer size 만큼이더해져서나타나게된다. 29

30 Burst operation HBURST[2:0] Type Description 000 SINGLE Single transfer 001 INCR Incrementing burst of unspecified length 010 WRAP4 4-beat wrapping burst 011 INCR4 4-beat incrementing burst 100 WRAP8 8-beat wrapping burst 101 INCR8 8-beat incrementing burst 110 WRAP16 16-beat wrapping burst 111 INCR16 16-beat incrementing burst 30

31 Transfer direction & size HWRITE 가 HIGH 일때, 이 signal 은 HWDATA[31:0] 을사용하여 write 하는과정임을알려준다. HWRITE 가 LOW 일때는 HRDATA[31:0] 을사용하여 read 하는과정임을알려준다. HSIZE[2:0] Size Description bits Byte bits Half word bits Word bits bits 4-word line bits 8-word line bits bits 31

32 Protection control HPROT[3:0] 은 opcode fetch 인지 data access 인지또는 privile ged mode access 인지 user mode 인지등을알려주기위한것이다 HPROT[3] cacheable HPROT[2] bufferable HPROT[1] privileged HPROT[0] Data/opcode Description Opcode fetch Data access User access Privileged access Not bufferable Bufferable Not cacheable cacheable 32

33 Address decoding 각각의 slave 에붙어있는 HSELx 의 signal 을 enable 해주기위한장치 Select signal 은 high-order address signals 을사용하여구현된다. slave 는 HREADY 가 HIGH 일때에만 HSELx 의 signal 을바꾸어야한다는것이다. 경우에따라서는 HREADY 가 LOW 일때 HSELx signal 을바꾸어도되지만이경우에는 Slave 쪽에서마지막전송이끝날때에만선택되는 slave 가바뀌어야한다. 하나의 slave 가가질수있는 address 의 boundary 는 1kB 이다. Bus master 는 1kB 의 boundary 를넘어서 burst 를할수없도록 design 되어있기때문에이러한설정이가능하다. 이경우에도 default slav e 가있어야하는데 master 가잘못된영역의 address 에쓰려고하는경우에이 default slave 가선택이되어야하며선택된 slave 는 SEQ UENTIAL 이나 NONSEQUENTIAL 일경우에는 ERROR response 를 I DLE 이나 BUSY 일경우에는 OKAY response 를내보내주어야한다. 33

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35 Slave select signals 35

36 Slave transfer responses Transfer done : HREADY를통해서 AHB는 transfer를 extend시키거나끝을알릴수있다. 그러나 extend되는것에는미리예측할수있는 Maximum이있어서그이상을넘어가면서 HREADY를 LOW로지속할수는없다. 권장되는 maximum wait state s는 16이다. Transfer response :HREADY가 HIGH일때와 OKAY response는 transfer가정상적으로이루어졌음을의미한다. 그리고 ERROR response는 ROM에다쓰려고하는등잘못된 address에데이터를 access하려고할때나타난다. SPLIT과 RETRY는 trans fer를 delay하기위한것이다. HRESP[1:0] Type Description 00 OKAY OKAY response와 HREADY가 HIGH이면정상적으로전송이이루어졌음 을의미한다. 또한 OKAY를통하여추가적인 cycle을삽입하기위하 여사용되기도한다. 01 ERROR Master 에게 transfer 가 Error 가발생하였고더이상같은영역에 transfer 를계속할수없음을알린다. Error condition 을위해서 2-cycle 이필요하다. 10 RETRY Transfer가아직성공적으로끝나지않았음을알리고 transfer를다시할 것을알리는 response이다. Retry condition을위해서 2-cycle이필요하다. 11 SPLIT Transfer가아직성공적으로끝나지않았음을알리고다른 transfer를원 하는 master에게그소유권을넘겨주기위한 response이다. Split condition을위해서 2-cycle이필요하다. 36

37 AHB Bus Arbitration Master 가 Bus 에대한 Access 를얻는가를설정 Master 는 REQUEST/GRANT interface 를가지고있어야하며, Arbiter 에게 Request 를했을때, Arbiter 는고유의 Priority scheme 을가지고, 어떤 Master 가가장높은 Pri ority 를갖는가를계산해서그해당 Master 에게 Grant Si gnal 을보낸다. 또한각각의 Master 는 HLOCKx signal 을갖는데이것은 Master 가 bus 의독점적인 access 를하려고할때발생된다. 즉현재 Grant 된 Master 의 LOCK 이 enable 상태일때에는다른 Priority 가높은 Master 가 Bus 를요구했을지라도현재의 Master 의전송이끝날때까지는 Bus 를넘겨주지않는다. 37

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39 AMBA AHB Arbiter Signal Description Name Source Description HBUSREQx Bus Request HLOCKx HMASTER[3: 0] Master Master Arbiter HMASTLOCK Arbiter bus Master 가 bus 에대한 access 를요청할때사용된다. 각각의 bus master 는각각 HBUSREQx 라는 interface 를가지게되며, Arbiter 는최고 16 개의 Master 를다룰수있다. 즉 HBUSREQ[15:0] 까자사용할수있다. bus Request 신호와동시에인가된다. master 가 burst trans 를하려고할 때, 중간에다른 Master 에게 bus 의소유를넘기지않을것을위해서사용. Locked transfer 의첫번째전송이시작되면 Arbiter 는현재의전송을끝마 치기전에는다른 Master 에게 bus 의사용권을넘겨주지않을것이다. 현재어떤 Maser 가선택되어져있는가는 HMASTER[3:0] 신호를이용해 서알수있다. 이것은 master 들이연결되는 MUX 에사용되어진다. Maser number 는또한 SPLIT-capable slave 에의해서도주어진다. 이것은 Master 로하여금 SPLIT 전송을마무리할수있도록하는데사용된다. HMASTLOCK 신호는현재전송하는것이 locked transfer 인지를알려준다. 이것은 address 와 control signal 과동시에나오게된다. HSPLIT[15:0 ] Slave (SPLIT-capabl e) 16bit 의 Split bus 는 SPLIT-capable slave 에의해서주어진다. 이를통해서 SPLIT 전송을마무리할수있도록하는데사용된다. HGRANTx Arbiter Grant 신호는 arbiter에의해서발생된다. 이것은가장높은 priority를가진 master에게만 HIGH를준다. 그렇지만 Grant를얻었다고해서바로전송을 시작할수있는것은아니다. HREADY가HIGH일때에만비로소전송을시 작할수있게된다. 39

40 Requesting Bus Access Arbiter는 Request 신호를매번 cycle의 rising edge에서 sampling 하게된다. 그때마다내부 priority algorithm을가지고서다음 grant 를결정하게된다. 보통의경우에있어서 Arbiter는burst가끝났을때에 grant신호를바꾸게된다. 그렇지만어떤경우에있어서는 burst를갑자기종료하고다른 priority가높은 master에게 access를넘기기도한다. 이와같은이유에서원래는 burst를위해서한번만 Request를하면되지만, Re-Request를해야하는경우가발생하게된다. 즉중간에 burst가종료되었으면, 그나머지를전송하기위해서 Master는다시 Request를해야한다. 예를들어처음에 8개의전송을하다가 4개까지전송하고중단되었다면 4개짜리 burst나 1개짜리 burst를 4번요청하는등의방법으로새로운 burst를시작해야한다. 만약아무런 Request가없는경우에도 Grant의어떠한 bit는항상 H IGH로 setting을해주어야하는데이를위해서 Default Master가필요하다. 이때는 Request를하지않는경우이므로 Master의 HTRA NS 값은 IDLE상태를나타내야한다. 40

41 Granting Bus Access Module 12. Communication-Centric SoC platform architecture with no wait states HREADY 가 HIGH 일때 HMASTER[3:0] 값이바뀌면서전송을시작하게될것이다. 이에대한그림이그림 3-4 에나와있다 41

42 Data bus ownership 42

43 Reset HRESETn 신호는 AHB 에있어서유일한 active LOW sig nal 이다. Reset 은언제나발생할수있지만 AHB 가알게되는것은 HCLK 의 rising edge 에서 sampling 하게된다. Reset 이되는동안에 HTRANS[1:0] 은 IDLE 을나타내어야하며 address 와 control signal 들은 valid level 에있어야한다. 43

44 AHB bus interface 44

45 AHB bus master interface 45

46 AHB bus arbiter interface 46

47 AHB bus decoder interface 47

48 AMBA APB Minimal power consumption and reduced interface complexi ty Handles the bus handshake and control signal retiming Low bandwidth and do not require the high performance of a pipelined bus interface. All signal transitions are only related to the rising edge of th e clock 48

49 AMBA APB All other modules on the APB are APB slaves. The APB slaves have the following interface specification address and control valid throughout the access (unpipelined) zero-power interface during non-peripheral bus activity (periph eral bus is static when not in use) timing can be provided by decode with strobe timing (unclocke d interface) write data valid for the whole access (allowing glitch-free trans parent latch implementations) 49

50 AMBA APB IDEL : Peripheral bus 의 default sta te SETUP : 전송요구와있을때 PSEL x 에의해 bus 는 SETUP 상태로옮아가게되며, 한 clock cycle 만유지하고 ENABLE 상태로바뀐다. ENABLE : PENABLE 신호가보내지며, 더이상의전송요구가없으면 ID LE 상태로바뀐다. SETUP 에서 ENA BLE 로상태가바뀔때, address, wri te 그리고 select 신호는안정된상태를유지한다. 50

51 Write transfer Write transfer 는 address, write data, write 신호와 select 신호가 PCLK 의 rising 과함께바뀌며시작된다. 첫 cycle 은 SETUP 으로두번째 rising 에 PE NABLE 신호가생성된다. 이 cycle 동안전송은완료되며, address, data, 그리고 control 신호는그값을유지한다. PENABLE 신호는전송의완료와함께 LOW 로되며, 이때 PSEL 또한 LOW 가된다. 전력소모를줄이기위해그다음 access 까지 address 와 write 신호는변하지않는다 51

52 Read transfer 52

53 APB bridge Bridge 만이 APB 에서 master 의역할을한다. 또한 bridge 는 AHB 에서의 slave. a. address 를 AHB 로부터 APB 로전달 b. address 를 decode 하고 PSELx 를발생. transfer 하는동안한 slave 만선택 c. write transfer 동안 AHP 에서 APB 로 data 를이동. d. read transfer 동안 APB 에서 AHB 로 data 를이동. e. 전송을위한 timing 신호인 PENABLE 신호를생성. 53

54 APB bridge transfer 54

55 AMBA AMBA AHB Features Bus name AMBA AHB Data bus width bit Address bus width 32 bit architecture Data bus protocol Timing Interconnection Supported intercon nections Multi Master / Multi Slave Single read/write transfer, Burst transfer (4,8,16 Byt es) Pipelined Byte/Half-word/word transfer support Synchronous Multiplexed implementation Non-tristate, Separate data read & write bus require d 55

56 AMBA AMBA APB Features Bus name Data bus width AMBA APB bit Address bus width 32 bit architecture Data bus protocol Timing Interconnection Supported intercon nections Power Single Master (bridge) / Multi Slave 2 cycle read/write transfer, No Burst transfer Non-Pipelined Synchronous Not defined Non-tristate bus recommended Separate data read & write bus recommended Zero power when not in use 56

57 APB Interface Diagrams recommended to i mplement APB dat a bus as! multiplexed or! OR-bus schema! tri-state is possible but not recommen ded 57

58 Read Transfer from AHB to APB 58

59 AMBA Test Interface 59

60 AMBA Test Interface Write Cycl e 60

61 Coreconnect TM Bus Architecture Coreconnect CoreConnect is an IBM-developed on-chip bus communica tions link that enables chip cores from multiple sources to b e interconnected to create entire new chips. The CoreConnect technology eases the integration and reus e of processor, system, and peripheral cores within standar d product platform designs to achieve overall greater syste m performance. 61

62 Coreconnect TM Bus Architecture Coreconnect SRAM/ROM Peripheral controller External Bus Master Controller I2C UART USB GPIO FPU OPB Arbiter On-chip peripheral bus 32 bit PPC440 CPU Inst Data Interrupt Controller OPB Bridge DMA Controller MAL 10/100 Ethernet PLB Arbiter Processor local bus 128 bit Device Control Register Bus PC133/DDR133 SDRAM Controller PCI-X Bridge SRAM Controller Custom Logic Reset Clock control Power Mgmt SRAM 62

63 Coreconnect TM Bus Architecture Coreconnect The CoreConnect bus architecture includes : processor local bus (PLB) on-chip peripheral bus (OPB) device control register bus (DCR) 63

64 Coreconnect TM Bus Architecture Coreconnect PLB Features Bus name Data bus width Address bus wid th architecture Data bus protoc ol Timing Interconnection Supported interc onnections Coreconnect PLB bit 32 bit (With address pipelining, reducing latency) Multi Master (Max 8) / Multi Slave Single read/write transfer, Burst transfer (16, 64 Bytes) Overlapped read/write (2 transfers/cycle) Pipelined Fully Synchronous Crossbar switch Non-tristate, Separate data read & write bus 64

65 Coreconnect TM Bus Architecture Coreconnect OPB Features Bus name Data bus width Address bus wid th architecture Data bus protoc ol Timing Interconnection Supported interc onnections Coreconnect OPB bit 32 bit Multi Master (arbiter) / Multi Slave Dynamic bus sizing possible Single read/write transfer, Burst transfer Retry support DMA support Fully Synchronous Multiplexed implementation Non-tristate, Separate data read & write bus 65

66 Coreconnect TM Bus Architecture Coreconnect DCR Features Bus name Data bus width Address bus wid th Interconnection Purpose Coreconnect DCR 32 bit 10 bit Multiplexed implementation Transfer data between the CPU s general purpose re gisters (GPR) and other (peripheral) registers, not me ant for real data transfers Designed to reduce load o n PLB and OPB 66

67 WISHBONE Overview The WISHBONE System-on-Chip (SoC) interconnection arc hitecture for portable IP cores is a flexible design methodolo gy for use with semiconductor IP cores. WISHBONE System-on-Chip Interconnect Architectu re Simple architecture Truly open specification Silicore placed specifications in the public domain In September 2002 Silicore handed stewardship over to OpenC ores Patent & Royalty free 67

68 WISHBONE WISHBONE Interconnect Architecture Slave Master Master Slave Master Slave WishBone interconnection (Intercon) Point to Point Data flow Shared bus Crossbar switch The WishBone interconnection is created by the system integrator, who has total control of its design. Master Slave Syscon 68

69 WISHBONE The point-to-point interconnection WISHBONE MASTER WISHBONE SLAVE The data flow interconnection IP CORE A IP CORE B IP CORE C WISHBONE SLAVE WISHBONE MASTER WISHBONE SLAVE WISHBONE MASTER WISHBONE SLAVE WISHBONE MASTER Direction of Data Flow 69

70 WISHBONE Shared Bus interconnection Crossbar switch interconnection WISHBONE MASTER MA WISHBONE MASTER MB WISHBONE MASTER MA Note : Dotted lines indicate one possible connection option WISHBONE MASTER MB SHARED BUS CROSSBAR SWITCH INTERCONNECTION WISHBONE MASTER SA WISHBONE MASTER SB WISHBONE MASTER SC WISHBONE MASTER SA WISHBONE MASTER SB WISHBONE MASTER SC 70

71 WISHBONE WISHBONE Features Bus name Data bus width Address bus width architecture Data bus protocol Timing Interconnection Supported intercon nections Wishbobe 8 to 64 bits 8 to 64 bits Multi Master / Multi Slave Single read/write transfer, Block transfer cycle RMW(Read-Modify-Write) cycle Up to one data transfer per clock cycle Synchronous Point-to-Point, Data flow, Shared bus, Crossbar switch Unidirectional bus, Bi-directional bus Multiplexer based interconnections Tristate based interconnections 71

72 Sonics µnetworks µnetwork Features The key concept governing the Sonics architecture is the co mbining : a fully pipelined, fixed-latency bus a Time-Division Multiple Access (TDMA) bandwidth allocation s cheme into a single communications protocol The main protocols are : Open Core Protocol(OCP) Interface SiliconBackplane µnetwork 72

73 Sonics µnetworks The advantages of the Sonics µnetwork architecture Configured to the Application Cost and Performance Verification, Validation, and Testing 73

74 Sonics µnetworks The SiliconBackplane µnetwork (SB) consists of a ph ysical interconnect bus configured with a combinatio n of agents. DMA CPU DSP MPEG Service agent Open Core Protocol Initiator agent SiliconBackplane Target agent C Memory I O O 74

75 Sonics µnetworks InitiatorAgent This agent serves as the interface between the SB and an att ached master core such as a CPU, DSP core or DMA controll er. TargetAgent This agent interfaces the physical bus to a slave device such as memory and UART engines to the SiliconBackplane µnet work ServiceAgent The ServiceAgent is an enhanced InitiatorAgent that provides debug and test capabilities 75

76 Sonics µnetworks SiliconBackplane is composed of : System Bandwidth Latency Bandwidth allocation Thread management Arbitration addressing 76

77 Open Core Protocol An overview of Open Core Protocol The Open Core Protocol defines a high-performance, bus-in dependent interface between IP cores. Open Core Protocol Achieve the goal of IP design reuse. Optimizes die area Simplifies system verification and testing 77

78 Open Core Protocol Open Core Protocol System initiator System initiator/target System target Core Core Core Master Master Slave Slave OCP Response Request Bus wrapper interface module Slave Slave Master Master Bus initiator Bus initiator/target Bus Target On-chip Bus 78

79 Open Core Protocol Operation of OCP 1 Point-to-Point synchronous interface Bus independence Commands Address/Data Pipelining 79

80 Open Core Protocol Operation of OCP 2 Response Burst In-band information Threads and Connections Interrupts, Errors, and other Sideband signaling 80

81 Open Core Protocol OCP interface signals Dataflow signal Sideband signal Test signal The basic OCP signals A small set of the signals from the dataflow The Optional OCP signals To support additional core communication requirements 81

82 PI-Bus An overview of Peripheral Interconnect Bus A European on-chip interconnection bus for silicon systems resulting from the ESPRIT Open Microprocessor Systems Initi ative. Target of PI-Bus High speed on-chip interconnect Promotion of design reuse Integration of designs from different organizations 82

83 PI-Bus High performance Features Synchronous Non-multiplexed address and data scheme Pipelined burst mode operation Only technology limitations clock speeds Multi-master capability 83

84 PI-Bus PI-Bus Check & Power control Processor core (Bus master) Alternative core (Bus master) Test & Debug control PI-Bus Bus control unit Memory controller (Bus slave) Graphics processor (Bus slave) Display controller (Bus slave) Video compression (Bus slave) Audio reproduction (Bus slave) System memory Graphics frame buffer Compression memory 84

85 PI-Bus PI-Bus VHDL toolkit methodlogy Slave, master and master/slave Bus control unit Master based test support Transaction spy 85

86 CoreFrame (Palmchip) The CoreFrame architecture is a low-power, high-pe rformance on-chip interconnect architecture for inte gration of SOC (system-on-chip) blocks in a synthe sis friendly environment. CPU subsystem CPU memory CPU CPU Bus PalmBus controller Cache or Bridge M Bus PalmBus Memory subsystem Shared memory DMA channel DMA channel DMAC Non-DMA peripheral Non-DMA peripheral DMA peripheral DMA peripheral 86

87 CoreFrame (Palmchip) CoreFrame Features PalmBus : Designed for lowspeed accesses from the CPU c ore to peripheral blocks. MBus : Designed for highspeed accesses to shared memory from the CPU core and peripheral blocks. The CoreFrame architecture is processor independent. The PalmBus Controller and Cache both act as a bridge betw een the CPU subsystem and the CoreFrame subsystem. 87

88 CoreFrame (Palmchip) CoreFrame channels interface between the MBus an d the Memory subsystem and provide a number of fu nctions : Channel Address control Channel interface Request/Grant control MBus Channel status logic FIFO 88

89 [1] 이진, 박신종, Principle of SoC (II), SITI Newsletters, 제 1 권 2 호, 2002 [2] AMBA Specification Revision 2.0, ARM Ltd., 1999 [3] IBM, [4] Opencore, WISHBONE, Revision B.3 Specification, wishbone/ [5] OCP-IP association, OCP IP Open Core Protocol Specification 2.0, 2003 [6] Sonics, Sonics µnetworks Technical Overview, June, 2000 [7] PalmChip Corp., CoreFrame view white paper: Overview of the CoreFrame Arch itecture. [8] [9] OMI. PI Bus v3.1 Documentation,

90 M. Shalan and V. Mooney, " Hardware Support for Real-Time Embedded Multiprocessor System-on-a-Chip Memory Management," CODES'02, pp 79-84, May 2002 Baghdadi, A.; Lyonnard, D., Zergainoh, N.-E., Jerraya, A.A. An efficient archite cture model for systematic design of application-specific multiprocessor SoC D ATE, pp 55-62, March 2001 Gharsalli, F., Lyonnard, D., Meftali, A., Rousseau, F., Jerraya, A.A, Unifying me mory and processor wrapper architecture in multiprocessor SoC design, ISSS 2 002, Page(s): 26-31, Oct, 2002 Christou, C.S. Fast computations on a low-cost DSP-based shared-memory m ultiprocessor system Electronics, Circuits and Systems, 17-20, Page(s): Dec scorpio user s manual 90