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1 Internet Embedded MCU W7100 Datasheet version WIZnet Co., Inc. All Rights Reserved. For more information, visit our website at Copyright 2009 WIZnet Co., Inc. All rights reserved. 1

2 Document History Information Version Date Descriptions Ver βeta Sep Release with W7100 launching Ver Dec Delete about How to program FLASH memory in W7100 document Section 2.4.7, APP Entry RD/WR Enable => APP Entry(0xFFF7 ~ 0xFFFF) RD/WR Enable Section 3 I/O Ports, Delete about three-state signals in I/O pins Ver Feb Modify the XTLP0 and XTLP1 explaination Ver Apr Modify the Sn_IMR initial value 0x00 => 0xFF Add the INTLEVEL register to TCPIPCore common register. Ver May Delete about PPPoE protocol cause of errata Copyright Notice Copyright 2009 WIZnet, Inc. All Rights Reserved. Technical Support: support@wiznet.co.kr Sales & Distribution: sales@wiznet.co.kr For more information, visit our website at Copyright 2009 WIZnet Co., Inc. All rights reserved. 2

3 WIZnet s online Technical Support If you have any questions regarding WIZnet s Products, please write down your question on our Q&A Board under the Support menu in the WIZnet website ( We will respond to your questions as soon as possible. Click Copyright 2009 WIZnet Co., Inc. All rights reserved. 3

4 Table of Contents 1 Overview Introduction W7100 Features W7100 Block Diagram & Features ALU (Arithmetic Logic Unit) TCPIPCore Pin Description Pin Layout Pin Description Configuration Timer UART DoCD Compatible Debugger Interrupt / Clock GPIO Media Interface Network Indicator LED Power Supply Signal Memory Code Memory Code Memory Wait States Data Memory Data Memory Wait States Internal Data Memory and SFR SFR definition Program Code Memory Write Enable Bit Program Code Memory Wait States Register Data Pointer Extended Registers Data Pointer Registers Clock Control Register Stack Pointer New & Extended SFR Peripheral Registers Interrupt I/O Ports Timers Copyright 2009 WIZnet Co., Inc. All rights reserved. 4

5 5.1 Timers 0, Overview Interrupts Timer0 Mode Timer0 Mode Timer0 Mode Timer0 Mode Timer1 Mode Timer1 Mode Timer1 Mode Timer1 Mode Timer Overview Interrupts UART Interrupts Mode0, Synchronous Mode 1, 8-Bit UART, Variable Baud Rate, Timer 1 or 2 Clock Source Mode 2, 9-Bit UART, Fixed Baud Rate Mode 3, 9-Bit UART, Variable Baud Rate, Timer1 or 2 Clock Source Examples of Baud Rate Setting Watchdog Timer Overview Interrupts Watchdog Timer Reset Simple Timer System Monitor Watchdog Related Registers Watchdog Control Clock Control Timed Access Registers TCPIPCore Memory Map TCPIPCore Registers Common Registers SOCKET Registers Register Description Mode Register Copyright 2009 WIZnet Co., Inc. All rights reserved. 5

6 8.3.2 SOCKET Registers Functional Description Initialization Data Communication TCP TCP SERVER TCP CLIENT UDP Unicast & Broadcast Multicast IPRAW MACRAW Electrical Specification IR Reflow Temperature Profile (Lead-Free) Package Descriptions Appendix: Performance Improvement about W Summary Bit Arithmetic Functions Addition Subtraction Multiplication Division Bit Arithmetic Functions Addition Subtraction Multiplication bit Arithmetic Functions Addition Subtraction Multiplication Copyright 2009 WIZnet Co., Inc. All rights reserved. 6

7 List of Figures Figure 1.1 W7100 Block Diagram Figure 1.2 Accumulator A Register Figure 1.3 B Register Figure 1.4 Program Status Word Register Figure 1.5 PSW Register Figure 1.6 TCPIPCore Block Diagram Figure 1.7 W7100 Pin Layout Figure 1.8 Power Design Figure 2.1 Code / Data Memory Connections Figure 2.2. Boot Sequence Flowchart Figure 2.3 Code Memory Map Switching Figure 2.4 APP Entry Process Figure 2.5 Changing the code memory Status at RB = Figure 2.6 Data Memory Map Figure 2.11 Internal Memory Map Figure 2.12 SFR Memory Map Figure 2.13 PWE bit of PCON Register Figure 2.14 Code memory Wait States Register Figure 2.15 Waveform for code memory Synchronous Read Cycle with Minimal Wait States (WTST = 3 ) Figure 2.16 Waveform for code memory Synchronous Write Cycle with Minimal Wait States(WTST = 3 ) Figure 2.17 Data Pointer Extended Register Figure 2.18 Data Pointer Extended Register Figure 2.19 Extended Register Figure 2.20 Data Pointer Register DPTR Figure 2.21 Data Pointer 1 Register DPTR Figure 2.22 Data Pointer Select Register Figure 2.23 Clock Control Register STRETCH bits Figure 2.24 Stack Pointer Register Figure 2.26 W7100 Configuration Register Figure 3.1 Interrupt Enable Register Figure 3.2 Interrupt Priority Register Figure 3.3 Timer 0, 1 Configuration Register Figure 3.4 UART Configuration Register Figure 3.5 Extended Interrupt Enable Register Copyright 2009 WIZnet Co., Inc. All rights reserved. 7

8 Figure 3.6 Extended Interrupt Priority Register Figure 3.7 Extended Interrupt Flag Register Figure 3.8 Watchdog Control Register Figure 4.1 Port0 Register Figure 4.2 Port1 Register Figure 4.3 Port2 Register Figure 4.4 Port3 Register Figure 4.5 Usage of the GPIO pins in the W Figure 5.1 Timer 0, 1 Control Mode Register Figure 5.2 Timer 0, 1 Configuration Register Figure 5.3 Interrupt Enable Register Figure 5.4 Interrupt Priority Register Figure 5.5 Timer 0, 1 Configuration Register Figure 5.6 Timer Counter0, Mode0: 13-Bit Timer/Counter Figure 5.7 Timer/Counter0, Mode1: 16-Bit Timer/Counter Figure 5.8 Timer/Counter0, Mode2: 8-Bit Timer/Counter with Auto-Reload Figure 5.9 Timer/Counter0, Mode3: Two 8-Bit Timers/Counters Figure 5.10 Timer/Counter1, Mode0: 13-Bit Timer/Counter Figure 5.11 Timer/Counter1, Mode1: 16-Bit Timers/Counters Figure 5.12 Timer/Counter1, Mode2: 8-Bit Timer/Counter with Auto-Reload Figure 5.13 Timer2 Configuration Register Figure 5.14 Timer/Counter2, 16-Bit Timer/Counter with Auto-Reload Figure 5.15 Interrupt Enable Register Timer Figure 5.16 Interrupt Priority Register Timer Figure 5.17 Timer2 Configuration Register TF Figure 5.18 Timer/Counter2, 16-Bit Timer/Counter with Capture Mode Figure 5.19 Timer2 for Baud Rate Generator Mode Figure 6.1 UART Buffer Register Figure 6.2 UART Configuration Register Figure 6.3 UART Bits in Power Configuration Register Figure 6.4 UART Bits in Interrupt Enable Register Figure 6.5 UART Bits in Interrupt Priority Register Figure 6.6 UART Configuration Register Figure 6.7 Timing Diagram for UART Transmission Mode0 (clk = MHz) Figure 6.8 Timing Diagram for UART Transmission Mode Figure 6.9 Timing Diagram for UART Transmission Mode Figure 6.10 Timing Diagram for UART Transmission Mode Figure 7.1 Watchdog Timer Structure Copyright 2009 WIZnet Co., Inc. All rights reserved. 8

9 Figure 7.2 Interrupt Enable Register Figure 7.3 Extended Interrupt Enable Register Figure 7.4 Extended interrupt Priority Register Figure 7.5 Watchdog Control Register Figure 7.6 Watchdog Control Register Figure 7.7 Clock Control register Watchdog bits Figure 8.1 TCPIPCore Memory Map Figure 8.2 SOCKET n Status transition Figure 8.3 Calculate Physical Address Figure 9.1 Allocation Internal TX/RX memory of SOCKET n Figure 9.2 TCP SERVER & TCP CLIENT Figure 9.3 TCP SERVER Operation Flow Figure 9.5 TCP CLIENT Operation Flow Figure 9.6 UDP Operation Flow Figure 9.7 The received UDP data format Figure 9.8 IPRAW Operation Flow Figure 9.9 The received IPRAW data format Figure 9.10 MACRAW Operation Flow Figure 9.11 The received MACRAW data format Figure 10.1 Waveform for data memory Read Cycle with Minimal Wait States(CKCON = 2 ) 126 Figure 10.2 Waveform for data memory Write Cycle with Minimal Wait States(CKCON = 2 ) 127 Copyright 2009 WIZnet Co., Inc. All rights reserved. 9

10 List of Tables Table 2.1 WTST Register Values Table 2.2 DPTR0, DPTR1 Operations Table 2.3 MD[2:0] Bit Values Table 3.1 External Interrupt Pin Description Table 3.2 W7100 Interrupt Summary Table 4.1 I/O Ports Pin Description Table 4.2 Read-Modify-Write Instructions Table 5.1 Timers 0, 1 Pin Description Table 5.2 Timers 0, 1 Mode Table 5.3 Timer0, 1 interrupts Table 5.4 Timer2 Pin Description Table 5.5 Timer2 Modes Table 5.6 Timer2 Interrupt Table 6.1 UART Pin Description Table 6.2 UART Modes Table 6.3 UART Baud Rates Table 6.4 UART Interrupt Table 6.5 Examples of Baud Rate Setting Table 7.1 Watchdog Interrupt Table 7.2 Summary for Watchdog Related Bits Table 7.4 Watchdog Intervals Table 7.5 Timed Access Registers Table 12.1 Timer / Counter Mode Table 12.2 Baud rate Table 12.3 Mode of UART Copyright 2009 WIZnet Co., Inc. All rights reserved. 10

11 1 Overview 1.1 Introduction imcu W , 64KB SRAM hardwired TCP/IP Core one-chip. Hardwired TCP/IP Ethernet MAC PHY TCP/IP stack. W7100 Hardwired TCP/IP stack TCP, UDP, IPv4, ICMP, ARP, IGMP. 1.2 W7100 Features Fully software compatible with industrial standard 8051 Pipelined architecture which enables execution of instructions 4~5 times faster than a standard Data Pointers (DPTRs) for fast memory blocks processing Advanced INC & DEC modes Auto-switch of current DPTR 64KBytes Data Memory (RAM) 256Bytes data FLASH 64KBytes Code Memory 2KBytes Boot Code Memory Interrupt controller 2 priority levels 4 external interrupt sources 1 Watchdog interrupt Four 8-bit I/O Ports Three timers/counters Full-duplex UART Programmable Watchdog Timer DoCD compatible debugger Hardwired TCP/IP Protocols: TCP, UDP, ICMP, IPv4 ARP, IGMP, Ethernet 10BaseT/100BaseTX Ethernet PHY embedded Auto Negotiation (Full-duplex and half duplex) Auto MDI/MDIX 8 independent sockets which are running simultaneously 32Kbytes Data buffer for the Network Network status LED outputs (TX, RX, Full/Half duplex, Collision, Link, and Speed) Not supports IP fragmentation Copyright 2009 WIZnet Co., Inc. All rights reserved. 11

12 1.3 W7100 Block Diagram & Features Figure 1.1 W7100 Block Diagram W : ALU,. Accumulator (ACC) Program Status Word (PSW), B, arithmetic unit, logic unit, multiplier, divider Logic. SFR Special function register., register logic. direct addressing mode access (read, write, modify) ALU (Arithmetic Logic Unit) W microcontroller.. W7100. W7100 MCU ALU data 8-bit ALU, ACC (0xE0) register, B (0xF0) register PSW (0xD0) register. ACC (0xE0) Reset ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0 0x00 Figure 1.2 Accumulator A Register Copyright 2009 WIZnet Co., Inc. All rights reserved. 12

13 B register., B register SFR. B (0xF0) Reset B.7 B.6 B.5 B.4 B.3 B.2 B.1 B.0 0x00 Figure 1.3 B Register ALU,,, (increment), (decrement), BCD-decimal-add-adjust, (compare). unit AND, OR, Exclusive OR, complement, rotation. Boolean set, clear, complement, jump-if-not-set, jump-if-set-and-clear move to/from carry bit. PSW (0xD0) Reset CY AC F0 RS1 RS0 OV F1 P 0x00 Figure 1.4 Program Status Word Register CY Carry flag AC Auxiliary carry F0 General purpose flag 0 Register bank select bits RS[1:0] Function Description RS[1:0] 00 -Bank 0, data address 0x00-0x Bank 1, data address 0x08-0x0F 10 -Bank 2, data address 0x10-0x Bank 3, data address 0x18-0x1F OV Overflow flag F1 General purpose flag 1 P Parity flag Figure 1.5 PSW Register PSW register MCU bit. Copyright 2009 WIZnet Co., Inc. All rights reserved. 13

14 1.3.2 TCPIPCore Figure 1.6 TCPIPCore Block Diagram Ethernet PHY W BaseT/100BaseTX Ethernet PHY. Half-duplex Full duplex Auto-negotiation Auto MDI/MDIX. Link, TX, RX, Collision, Speed Duplex 6 indicator LED. TCPIP Engine TCPIP WIZnet Hardwired logic Ethernet MAC(Media Access Control) CSMA/CD (Carrier Sense Multiple Access with Collision Detect) 48-bit source/destination MAC address. ARP(Address Resolution Protocol) ARP IP address MAC address resolution protocol. MAC address ARP-reply ARP-request. IP (Internet Protocol) IP (layer). IP fragmentation fragmented packet. TCP Copyright 2009 WIZnet Co., Inc. All rights reserved. 14

15 UDP number. TCP UDP hardwired embedded TCPIP stack. ICMP(Internet Control Message Protocol) ICMP information, unreachable destination. Ping request ICMP packet, Ping reply ICMP packet. IGMPv1/v2(Internet Group Management Protocol version 1/2) IGMP Join/Leave IGMP. IGMP UDP multicast mode. Version 1 2 IGMP logic. IGMP, IGMP IP. UDP(User Datagram Protocol) UDP. unicast, multicast, broadcast. TCP(Transmission Control Protocol) TCP. TCP mode. Copyright 2009 WIZnet Co., Inc. All rights reserved. 15

16 1.4 Pin Description Pin Layout Package type: LQFP 100 Figure 1.7 W7100 Pin Layout Copyright 2009 WIZnet Co., Inc. All rights reserved. 16

17 1.4.2 Pin Description Pin. unidirectional Three state pin. Type Description I O 8mA driving IO / (Bidirectional) Pu 75KΩ pulled-up Pd 75KΩ pulled-down Configuration Pin name Num I/O Type Pu/Pd Description nrst 8 I - Global asynchronous reset, Active low TM3-0 1,2, 3,4 PM2-0 70, 71, 72 I Pd W7100 mode Normal mode : 0000 I Pd PHY Mode PM Description Reserved Normal Operation Mode Auto-negotiation 100 BASE-TX FDX/HDX Autonegotiation 10 BASE-T FDX/HDX Autonegotiation BASE-TX FDX BASE-TX HDX BASE-T FDX BASE-T HDX FDX : Full-Duplex, HDX : Half-Duplex BOOTEN 5 I Pd Boot Enable/Disable 0 Application Code FLASH 0x0000 jump 1- Enable Boot Boot ROM Boot code Copyright 2009 WIZnet Co., Inc. All rights reserved. 17

18 PLOCK 77 O - PLL Lock line, PLL locked F64EN 6 I - 4.7KΩ pull-down Timer Pin name Num I/O Type Pu/Pd Description Timer 0, 1 Interface T0 9 I - Timer0 clock T1 10 I - Timer1 clock GATE0 11 I - Timer0 gate GATE1 12 I - Timer1 gate Timer 2 Interface T2 13 I - Timer2 clock T2EX 14 I - Timer2 Capture/Reload UART Pin name Num I/O Type Pu/Pd Description RXD 15 IO Pu Serial TXD 17 O - Serial DoCD Compatible Debugger Pin name Num I/O Type Pu/Pd Description DCDCLK 18 O - DoCD clock DCDDI 19 I - DoCD DCDDO 20 O - DoCD Interrupt / Clock Pin name Num I/O Type Pu/Pd Description nint0 22 I - interrupt0 nint1 23 I - interrupt1 nint2 24 I - interrupt2 nint3 25 I - interrupt3 XTLN0 61 I - Ethernet PHY crystal /, oscillator XTLP0 62 I - 25MHz crystal XTLN1 67 I - W7100 crystal /, oscillator XTLP1 66 I MHz crystal Copyright 2009 WIZnet Co., Inc. All rights reserved. 18

19 GPIO Pin name Num I/O Type Pu/Pd Description P IO Pu Port0 / P IO Pu Port0 / P IO Pu Port0 / P IO Pu Port0 / P IO Pu Port0 / P IO Pu Port0 / P IO Pu Port0 / P IO Pu Port0 / P IO Pu Port1 / P IO Pu Port1 / P IO Pu Port1 / P IO Pu Port1 / P IO Pu Port1 / P IO Pu Port1 / P IO Pu Port1 / P IO Pu Port1 / P IO Pu Port2 / P IO Pu Port2 / P IO Pu Port2 / P IO Pu Port2 / P IO Pu Port2 / P IO Pu Port2 / P IO Pu Port2 / P IO Pu Port2 / P IO Pu Port3 / P IO Pu Port3 / P IO Pu Port3 / P IO Pu Port3 / P IO Pu Port3 / P IO Pu Port3 / P IO Pu Port3 / P IO Pu Port3 / : GPIO driving 2.5V, 3.3V pull-up. 10. Electrical Specification. Copyright 2009 WIZnet Co., Inc. All rights reserved. 19

20 Media Interface Pin name Num I/O Type Pu/Pd Description TXON 52 O - TXON/TXOP, differential TXOP 53 O - TXON/TXOP RXIN 55 I - RXIN/RXIP, differential RXIP 56 I - RXIN/RXIP RESETBG 59 I - PHY Off-chip, 12.3±1%, Reference schematic, 1. RXIP/RXIN (RX) 2. TXOP/TXON (TX) 3. RXIP RXIN 4. TXIP TXIN 5. RX TX noisy W5100 Layout Guide.pdf Network Indicator LED Pin name Num I/O Type Pu/Pd Description SPDLED 45 O - Link speed LED 100Mbps low 10Mbps high, Auto negotiation PM[2:0] FDXLED 46 O - Full duplex LED Full-duplex low half-duplex high, Auto negotiation PM[2:0] COLLED 47 O - Collision LED, Active low collision low (, half-duplex ) RXLED 48 O - Receive activity LED, Active low RXIP/RXIN low TXLED 49 O - Transmit activity LED, Active low TXOP/TXON low LINKLED 50 O - Link LED, Active low Link (10/100M) low Copyright 2009 WIZnet Co., Inc. All rights reserved. 20

21 Power Supply Signal Pin name Num I/O Type Pu/Pd Description VCC3A3 58, 75 Power - Analog 3.3V power supply VCC3A3 GNDA 10uF tantalum capacitor VCC3V3 21, 38, 73, 87, 100 Power - Digital 3.3V power supply VCC GND 0.1uF decoupling capacitor, VCC3V3 VCC3A3 1uH ferrite bead VCC1A8 54, 60, 64 Power - Analog 1.8V power supply Core power (filtering) VCC1A8 GNDA 10uF tantalum capacitor 0.1uF capacitor VCC1V8 16, 44, 68, 83 Power - Digital 1.8V power supply VCC GND 0.1uF decoupling capacitor GNDA 51, 57, 63, 65, 76 Power - Analog ground PCB analog ground GND 6, 7, Power - Digital ground 36, 69, 92 PCB digital ground 1V8O 74 Power - 1.8V regulated output voltage Core operation regulator 1.8V/150mA (VCC1A8, VCC1V8) 1V8O GND 3.3uF tantalum capacitor noise decoupling 0.1uF capacitor VCC1V8 1V80 1uH ferrite bead VCC1A8 <Notice> 1V80 W7100 device Copyright 2009 WIZnet Co., Inc. All rights reserved. 21

22 3.3V Power Source VCC3V3 10uF 0.1uF VCC1V8 Ferrite Bead 1uH Ferrite Bead 1uH VCC3A3 10uF VCC1A8 VCC3V3 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF VCC1V8 Ferrite Bead 1V8O 1uH 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 3.3uF 10uF Ferrite Bead 10uF 0.1uF 1uH Figure 1.8 Power Design Copyright 2009 WIZnet Co., Inc. All rights reserved. 22

23 2 Memory W7100 Code Memory Data Memory. W7100 Memory Figure 2.1. Figure 2.1 Code / Data Memory Connections 2.1 Code Memory Code Memory 0x0000 0x07FF Boot ROM 0x0000 0xFFFF Code FLASH. reset BOOTEN. Figure 2.2 BOOTEN BootROM flow. BOOTEN = 1 ISP APP, BOOTEN = 0 APP Entry APP. APP Entry Memory map switching APP Entry Figure 2.3 Memory map switching. Figure 2.2. Boot Sequence Flowchart Copyright 2009 WIZnet Co., Inc. All rights reserved. 23

24 Figure 2.3 Code Memory Map Switching W7100 Figure 2.3 Boot ROM / APP Entry FLASH., Boot ROM / APP Entry FLASH Memory address. 0x0000 ~ 0x07FF 0xFFF7 ~ 0xFFFF. W7100 Boot ROM / APP Entry code memory FLASH data memory. FLASH memory data memory application code FLASH. FLASH code memory. FLASH memory map switching. BOOTEN = 0 APP. Boot ROM APP Entry jump. APP Entry Boot ROM un-map FLASH map Code FLASH. Figure 2.3. code memory map switching APP Entry Code FLASH 0x0000 jump. Figure 2.4. Figure 2.4 APP Entry Process Copyright 2009 WIZnet Co., Inc. All rights reserved. 24

25 APP mode, Figure 2.4 Code FLASH 64KB code memory. FLASH APP Entry address, FLASH 64KB APP Entry un-map. startup code WCONF(0xFF) RB 0. Figure 2.5 APP Entry un-map. Figure 2.5 Changing the code memory Status at RB = 0 WCONF (0xFF) Reset RB ISPEN F64EN FB BE 0x00 Code FLASH 0xFFF7, startup code., W7100 system reset APP Entry address disable. ANL 0FFH, #07FH ; Clear Reboot flag BOOTEN 0 Startup code WCONF register RB clear Code FLASH memory 64KB code memory Code Memory Wait States Code memory wait state WTST (0x92) register wait state WTST register section. 2.2 Data Memory W KB RAM, 64KB TCPIPCore, 256Byte Data FLASH. Data FLASH IP address, MAC, subnet mask, port. memory MOVX access. Figure 2.6 W7100 Data Memory map. Copyright 2009 WIZnet Co., Inc. All rights reserved. 25

26 2.2.1 Data Memory Wait States Data memory wait state CKCON (0x8E) register section. Timing 10 section. Figure 2.6 Data Memory Map 2.3 Internal Data Memory and SFR memory Special Function Register (SFR) map. The Figure below shows the Internal Memory and Special Function Registers (SFR) map. Figure 2.11 Internal Memory Map W7100 RAM 0x00 ~ 0x1F 8 register 4 register bank, 0x20 128bits (16bytes) bit-addressable 208bytes scratchpad. Indirect addressing mode 0x80 0xFF addressing, 128 Bytes memory accessing. direct addressing mode 0x80 0xFF addressing SFR memory accessing. Copyright 2009 WIZnet Co., Inc. All rights reserved. 26

27 Figure 2.12 SFR Memory Map New SFR New additional SFR Extended SFR Standard 8051 SFR Standard Standard 8051 SFR Figure SFR bit addressable register. 2.4 SFR definition section W7100 SFR. standard SFR section peripheral SFR Program Code Memory Write Enable Bit PCON register Program Write Enable (PWE) bit MOVX Program Write signal. PWE bit 1 A accumulator register DPTR (active DPH:DPL) register code memory address write. A accumulator register P2 (bits 15:8) register RX(bits 7:0) register code memory address write. PCON (0x87) Reset SMOD0 - - PWE x00 Figure 2.13 PWE bit of PCON Register Note: 1. PCON.2 ~ PCON.0 bit reserved 1. Copyright 2009 WIZnet Co., Inc. All rights reserved. 27

28 2.4.2 Program Code Memory Wait States Register Wait state register code memory access time. WTST (0x92) Reset WTST.2 WTST.1 WTST.0 0x07 Figure 2.14 Code memory Wait States Register Note: 1. bit program fetch MOVC. Code memory write MOVX, CKCON register CODE-WR pulse width. 2. Read cycle 4 clock 8 clock. Table 2.1 WTST Register Values WTST[2:0] Access Time [clk] Not Used 1 Not Used 0 Not Used fetching, code memory MOVC access. Code memory 3 wait states read. Timing. Figure 2.15 Waveform for code memory Synchronous Read Cycle with Minimal Wait States (WTST = 3 ) Note: 1. clk clock ( MHz) 2. ADDRESS program byte 3. CODE_RD Code memory read 4. CODE Data write to the actual modified program byte Copyright 2009 WIZnet Co., Inc. All rights reserved. 28

29 Code memory 3 wait states MOVX write. W7100 core wait state memory. Timing diagram. Figure 2.16 Waveform for code memory Synchronous Write Cycle with Minimal Wait States(WTST = 3 ) Note: 1. clk clock ( MHz) 2. ADDRESS program byte 3. CODE Data write to the actual modified program byte 4. CODE_WR Code memory write 5. PRG Code memory Data Pointer Extended Registers Data pointer extended register DPX0, DPX1, MXAX 64KB accessing memory address. Reset DPX0, DPX1, MXAX 0x00. DPX0 (0x93) Reset DPXP.7 DPX.6 DPX.5 DPX.4 DPX.3 DPX.2 DPX.1 DPX.0 0x00 Figure 2.17 Data Pointer Extended Register DPX1 (0x95) Reset DPX1.7 DPX1.6 DPX1.5 DPX1.4 DPX1.3 DPX1.2 DPX1.1 DPX1.0 0x00 Figure 2.18 Data Pointer Extended Register MXAX (0xEA) Reset MXAM.7 MXAX.6 MXAX.5 MXAX.4 MXAX.3 MXAX.2 MXAX.1 MXAX.0 0x00 Figure 2.19 Extended Register MOVX DPTR0/DPTR1 register, address A[23:16] DPX0(0x93)/DPX1(0x95). MOVX R0 R1 register, address A[23:16] MXAX(0xEA) A[15:8] P2(0xA0) Copyright 2009 WIZnet Co., Inc. All rights reserved. 29

30 Data Pointer Registers Dual data pointer register data block copy. DPTR0 DPTR1 4 SFR. Active DPTR register SEL bit (0x86.0). SEL bit 0, DPTR0 (0x83:0x82). SEL bit 1 DPTR1 (0x85:0x04). DPTR0(0x83:0x82) DPH0(0x83) DPL0(0x82) Reset x0000 Figure 2.20 Data Pointer Register DPTR0 DPTR1(0x85:0x84) DPH1(0x85) DPL1(0x84) Reset x0000 Figure 2.21 Data Pointer 1 Register DPTR1 DPS (0x86) Reset ID1 ID0 TSL SEL 0x00 Figure 2.22 Data Pointer Select Register Note: TSL - Toggle select enable. When TSL is set, this bit toggles the SEL bit by executing the following instructions. INC DPTR MOV DPTR, #data16 MOVC + DPTR A MOVX When TSL = 0, DPTR related instructions will not affect the state of the SEL bit. Unimplemented bit - Read as 0 or 1. Table 2.2 DPTR0, DPTR1 Operations ID1 ID0 SEL = 0 SEL = INC DPTR INC DPTR1 0 1 DEC DPTR INC DPTR1 1 0 INC DPTR DEC DPTR1 1 1 DEC DPTR DEC DPTR1 Copyright 2009 WIZnet Co., Inc. All rights reserved. 30

31 data pointer register. A MOVX MOVC + DPTR + DPTR INC DPTR MOV DPTR, #data Clock Control Register Clock control register CKCON (0x8E) data memory read/write signal pulse width MD[2:0] bit. CKCON (0x8E) Reset WD1 WD MD2 MD1 MD0 0x07 Figure 2.23 Clock Control Register STRETCH bits Data memory read/write signal MOVX. MD[2:0] bit slow RAM, LCD display I/O device. Reset MD[2:0] bit 0x07, device. MD[2:0] I/O device. program MD[2:0]. Table 2.3 MD[2:0] Bit Values MD[2:0] Pulse Width[clock] Not Used 0 Not Used Read/write pulse width 3 clock 8 clock. Timing 10. Electrical specification Stack Pointer W7100 RAM 8-bit stack pointer SP(0x81). SP (0x81) Reset SP.7 SP.6 SP.5 SP.4 SP.3 SP.2 SP.1 SP.0 0x07 Figure 2.24 Stack Pointer Register Copyright 2009 WIZnet Co., Inc. All rights reserved. 31

32 pointer data PUSH CALL, pop POP, RET, RETI., stack pointer stack byte New & Extended SFR ISPID(0xF1) : ID Register for ISP. ISPADDR16(0xF2) : 16bit Address Register for ISP ISPDATA(0xF4) : Data Register for ISP. CKCBK(0xF5) : CKCON Backup Register. DPX0BK(0xF6) : DPX0 Backup Register. DPX1BK(0xF7) : DPX1 Backup Register. DPSBK(0xF9) : DPX Backup Register. RAMBA16(0xFA) : RAM Base Address Register. RAMEA16(0xFC) : RAM End Address Register. WCONF (0xFF) Reset RB ISPEN F64EN FB BE 0x00 Figure 2.26 W7100 Configuration Register Note: RB : 0 No Reboot / 1 Reboot after the ISP done (APP Entry(0xFFF7 ~ 0xFFFF) RD/WR Enable) ISPEN : 0 Enable ISP in Boot built in W7100 / 1 Disable - : Reserved, must be set to 000 F64EN : Always 0. Read only. FB : FLASH Busy Flag for ISP. Read only. BE : Boot Enable (1 Boot Running / 0 Apps Running). Read only Peripheral Registers P0, P1, P2, P3 : Port register. section 4. I/O Ports. TCON(0x88) : Timer 0, 1 configuration register. section 5.1 Timer 0, 1. TMOD(0x89) : Timer 0, 1 control mode register. section 5.1 Timer 0, 1. TH0(0x8C), TL0(0x8A) : Timer 0 Counter register. section 5.1 Timer 0, 1. TH1(0x8D), TL1(0x8B) : Timer 1 Counter register. section 5.1 Timer 0, 1. SCON(0x98) : UART Configuration Register. section 6 UART. SBUF(0x99) : UART Buffer Register. section 6 UART. Copyright 2009 WIZnet Co., Inc. All rights reserved. 32

33 IE(0xA8) : UART Bits in Interrupt Enable Register. section 6 UART. IP(0xB8) : UART Bits in Interrupt Priority Register. section 6 UART. TA(0xC7) : Timed Access Register. section 7. Watchdog Timer. T2CON(0xC8) : Timer 2 Configuration Register. section 5.2 Timer 2. RLDH(0xCB), RLDL(0xCA) : Capture Registers of Timer 2. section 5.2 Timer 2. TH2(0xCD), TL2(0xCC) : Counter Register of Timer 2. section 5.2 Timer 2. PSW(0xD0) : Program Status Word Register. section ALU. WDCON(0xD8) : Watchdog Control Register. section 7. Watchdog Timer. Copyright 2009 WIZnet Co., Inc. All rights reserved. 33

34 3 Interrupt Interrupt pin. pin (unidirectional), output pin three-state. Table 3.1 External Interrupt Pin Description Pin Active Type Pu/Pd Description nint0/fa6 Low/Falling I - External interrupt 0 nint1/fa7 Low/Falling I - External interrupt 1 nint2/fa8 Falling I - External interrupt 2 nint3/fa9 Falling I - External interrupt 3 nint4 - Reserved TCPIPCore (nint5) Falling I - Interrupt Request Signal for TCPIPCore (internally connected) W7100 core level interrupt priority control. interrupt IP (0xB8) EIP(0xF8) register clear high low level priority group. interrupt pin falling edge signal activate. Interrupt request system clock rising edge sampling. Table 3.2 W7100 Interrupt Summary Interrupt Function Active Flag Reset Vector Interrupt Natural Flag Level/Edge Number Priority IE0 Device pin INT0 Low/Falling Hardware 0x TF0 Internal, Timer0 - Hardware 0x0B 1 2 IE1 Device pin INT1 Low/Falling Hardware 0x TF1 Internal, Timer1 - Hardware 0x1B 3 4 TI0 & RI0 Internal, UART - Software 0x TF2 Internal, Timer2 - Software 0x2B 5 6 INT2F Device Pin INT2 Falling Software 0x INT3F Device Pin INT3 Falling Software 0x4B 9 8 INT4F INT5F TCPIPCore WDIF Reserved Interrupt for TCPIPCore Internal, WATCHDOG Falling Software 0x5B Software 0x Copyright 2009 WIZnet Co., Inc. All rights reserved. 34

35 Each interrupt IE (0xA8) EIE (0xE8) register bit enable disable. IE register global interrupt system disable(0)/enable(1) bit EA. IE (0xA8) Reset EA - ET2 ES ET1 EX1 ET0 EX0 0x00 Figure 3.1 Interrupt Enable Register Note: EA - Enable global interrupt EX0 - Enable INT0 interrupt ET0 - Enable Timer0 interrupt EX1 - Enable INT1 interrupt ET1 - Enable Timer1 interrupt ES Enable UART interrupt ET2 - Enable Timer2 interrupt Interrupt enable bit software clear set, hardware., interrupt software (, IE0 IE1 flag ). interrupt0, interrupt1 level-activated program, IE0 IE1 source pin nint0/fa6 nint1/fa7. IP (0xB8) Reset - - PT2 PS PT1 PX1 PT0 PX0 0x00 Figure 3.2 Interrupt Priority Register Note: PX0 - INT0 priority level control (high level at 1) PT0 - Timer0 priority level control (high level at 1) PX1 - INT1 priority level control (high level at 1) PT1 - Timer1 priority level control (high level at 1) PS - UART priority level control (high level at 1) PT2 Timer2 priority level control (high level at 1) Unimplemented bit - Read as 0 or 1 TCON (0x88) Reset TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 0x00 Figure 3.3 Timer 0, 1 Configuration Register Note: IT0 - INT0 level (at 0)/edge (at 1) sensitivity IT1 - INT1 level (at 0)/edge (at 1) sensitivity IE0 - INT0 interrupt flag processor interrupt routine Copyright 2009 WIZnet Co., Inc. All rights reserved. 35

36 hardware clear. IE1 INT1 interrupt flag processor interrupt routine hardware clear. TF0 - Timer 0 interrupt (overflow) flag processor interrupt routine hardware clear. TF1 Timer 1 interrupt (overflow) flag processor interrupt routine hardware clear. SCON (0x98) Reset SM0 SM1 SM2 REN TB8 RB8 TI RI 0x00 Figure 3.4 UART Configuration Register Note: RI - UART receiver interrupt flag TI - UART transmitter interrupt flag EIE (0xE8) Reset EWDI EINT5 EINT4 EINT3 EINT2 0x00 Figure 3.5 Extended Interrupt Enable Register Note: EINT2 - Enable INT2 Interrupt EINT3 - Enable INT3 Interrupt EINT4 Must be 0, if use the EIE register EINT5 - Enable TCPIPCore Interrupt EWDI - Enable WATCHDOG Interrupt EIP (0xF8) Reset PWDI PINT5 PINT4 PINT3 PINT2 0x00 Figure 3.6 Extended Interrupt Priority Register Note: PINT2 - INT2 priority level control (high level at 1) PINT3 - INT3 priority level control (high level at 1) PINT4 Must be set to 0, if use the EIP register PINT5 - TCPIPCore Interrupt priority level control (high level at 1) PWDI - WATCHDOG priority level control (high level at 1) Copyright 2009 WIZnet Co., Inc. All rights reserved. 36

37 EIF (0x91) Reset INT5F INT4F INT3F INT2F 0x00 Figure 3.7 Extended Interrupt Flag Register Note: INT2F - INT2 interrupt flag. Must be cleared by software INT3F INT3 interrupt flag. Must be cleared by software INT4F Must be set to 0. if use the EIF register INT5F - TCPIPCore Interrupt flag. Must be cleared by software WDCON (0xD8) Reset WDIF WTRF EWT RWT 0x00 Figure 3.8 Watchdog Control Register Note: WDIF Watchdog interrupt flag. WDIF, Watchdog interrupt enable bit (EIE.4), EWT Watchdog Timer event interrupt. bit interrupt service routine software clear. interrupt. WDIF enable software, Watchdog interrupt. Enabled software-set WDIF Watchdog interrupt. Timed access register procedure bit. Copyright 2009 WIZnet Co., Inc. All rights reserved. 37

38 4 I/O Ports I/O port pin. Table 4.1 I/O Ports Pin Description Pin Active Type Pu/Pd Description P0[7:0] - IO Pu Port0 input / output Recommends additional pull-up resister P1[7:0] - IO Pu Port1 input / output Recommends additional pull-up resister P2[7:0] - IO Pu Port2 input / output Recommends additional pull-up resister P3[7:0] - IO Pu Port3 input / output Recommends additional pull-up resister P0 (0x80) Reset P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 0xFF Figure 4.1 Port0 Register P1 (0x90) Reset P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 0xFF Figure 4.2 Port1 Register P2 (0xA0) Reset P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 0xFF Figure 4.3 Port2 Register P3 (0xB0) Reset P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 0xFF Figure 4.4 Port3 Register I/O port Read write access SFR: P0 (0x80), P1 (0x90), P2 (0xA0), P3 (0xB0). port-reading port pin read data register read. Read-Modify-Write data register. Table 4.2 Read-Modify-Write Instructions Copyright 2009 WIZnet Co., Inc. All rights reserved. 38

39 Instruction ANL ORL XRL JBC CPL INC, DEC DJNZ MOV Px.y, C CLR Px.y SETB Px.y Function Description Logic AND Logic OR Logic exclusive OR Jump if bit is set and cleared Complement bit Increment, decrement byte Decrement and jump if not zero Move carry bit to bit y of port x Clear bit y of port x Set bit y of port x port pin (exclusively) read. port GPIO (General Purpose Input Output). GPIO mode WCONF register reserved bit 000. Figure 4.5 W7100 GPIO. GPIO output driving voltage 2.5V, 3.3V output driving voltage pull-up. Figure 4.5 Usage of the GPIO pins in the W7100 Copyright 2009 WIZnet Co., Inc. All rights reserved. 39

40 5 Timers W bit timer/counter, Timer0 Timer1. timer mode, timer register 12clock period. counter mode, timer register pin (T0, T1) falling transition pin clock. 5.1 Timers 0, Overview Timer0, 1 pin. pin (unidirectional) three-state pin. Table 5.1 Timers 0, 1 Pin Description Pin Active Type Pu/Pd Description T0/FCS Falling I - Timer0 clock GATE0/FOE High I - Timer0 clock gate control T1/FAE Falling I - Timer1 clock GATE1/FA0 High I - Timer1 clock gate control Timer0 Timer timer. timer 2 8-bit register TH0 (0x8C), TL0 (0x8A), TH1 (0X8D), TL1 (0X8B). Timer 4. Table 5.2 Timers 0, 1 Mode M1 M0 Mode Function Description THx 32 prescaler (TLx 5bit) 8-bit timer/counter bit timer/counter. THx, TLx TLx 8-bit timer/counter, THx TLx autoreload bit timer/counter, TL0 Timer0 bit TH0 Timer1 bit TMOD (0x89) Timer1 Timer Reset GATE CT M1 M0 GATE CT M1 M0 0x00 Figure 5.1 Timer 0, 1 Control Mode Register Note: GATE - Gating control Copyright 2009 WIZnet Co., Inc. All rights reserved. 40

41 1: GATE pin TRx pin 1 Timer x 0: TRx pin 1 Timer x CT - Counter or timer select bit 1: Counter mode, Timer x Tx pin counting 0: Timer mode, clock M1, M0 Mode bits TCON (0x88) Reset TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 0x00 Figure 5.2 Timer 0, 1 Configuration Register Note: TR0 - Timer 0 bit 1: Enabled 0: Disabled TR1 - Timer 1 bit 1: Enabled 0: Disabled pin, GATE0 GATE1 pulse Interrupts Timer0, 1 interrupt bit. IE register interrupt toggle. interrupt IP register. IE (0xA8) Reset EA - ET2 ES ET1 EX1 ET0 EX0 0x00 Figure 5.3 Interrupt Enable Register Note: EA - Enable global interrupts ET0 - Enable Timer0 interrupts ET1- Enable Timer1 interrupts IP (0xB8) Reset - - PT2 PS PT1 PX1 PT0 PX0 0x00 Figure 5.4 Interrupt Priority Register Note: PT0 - Enable global interrupts PT1 - Enable Timer0 interrupts Unimplemented bit - Read as 0 or 1 Copyright 2009 WIZnet Co., Inc. All rights reserved. 41

42 TCON (0x88) Reset TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 0x00 Figure 5.5 Timer 0, 1 Configuration Register Note: TF0 Timer0 interrupt (overflow) flag processor interrupt routine hardware clear. TF1 Timer1 interrupt (overflow) flag processor interrupt routine hardware clear. Interrupt bit hardware software set clear., interrupt software. Table 5.3 Timer0, 1 interrupts Interrupt Function Active Flag Resets Vector Natural Priority Flag Level/Edge TF0 Internal, Timer0 - Hardware 0x0B 2 TF1 Internal, Timer1 - Hardware 0x1B Timer0 Mode0 Timer0 13bit register (8bit: Timer, 5bit: prescaler). count (valid bits) 1 0, Timer0 interrupt flag TF0 set. Timer TCON.4 = 1 TMOD.3 = 0 GATE0 = 1. TMOD.3 = 1 GATE0 Timer0 pulse width. Mode0 13bit register TH0 8bit TL0 5bit. TL0 3bit. Figure 5.6 Timer0 mode0. Figure 5.6 Timer Counter0, Mode0: 13-Bit Timer/Counter Copyright 2009 WIZnet Co., Inc. All rights reserved. 42

43 5.1.4 Timer0 Mode1 Mode1 timer register 16bit Mode0. Figure Timer0 Mode2 Figure 5.7 Timer/Counter0, Mode1: 16-Bit Timer/Counter Mode2 TL0 8bit timer/counter register. Overflow TL0 TH0 reload. TH0 reload. Figure 5.8 Timer/Counter0, Mode2: 8-Bit Timer/Counter with Auto-Reload Timer0 Mode3 TL0 TH0 counter. Figure Timer0 Mode3. TL0 Timer0 control bit (C/T, GATE, TR0, GATE0, TF0). TH0 Timer1 TR1 interrupt TF1 (interrupt flag). Mode3 8-bit timer/counter. Timer0 Mode3, Timer1 Mode3 turn on/off, serial Copyright 2009 WIZnet Co., Inc. All rights reserved. 43

44 channel baud-rate generator. Timer1 application Timer1 Mode0 Figure 5.9 Timer/Counter0, Mode3: Two 8-Bit Timers/Counters Timer1 13bit register (8bit: Timer, 5bit: prescaler). count (valid bits) 1 0, Timer1 interrupt flag TF1 set. Timer TCON.6 = 1 TMOD.6 = 0 GATE1 = 1. TMOD.7 = 1 GATE1 Timer1 pulse width. Mode0 13bit register TH1 8bit TL1 5bit. TL1 3bit. Figure 5.10 Timer1 mode0. Figure 5.10 Timer/Counter1, Mode0: 13-Bit Timer/Counter Copyright 2009 WIZnet Co., Inc. All rights reserved. 44

45 5.1.8 Timer1 Mode1 Mode1 timer register 16bit Mode0. Figure Timer1 Mode2 Figure 5.11 Timer/Counter1, Mode1: 16-Bit Timers/Counters Mode2 TL1 8bit. Overflow TF1 set TL1 8bit TH1 8bit reload. Reload TH1. Figure 5.12 Timer/Counter1, Mode2: 8-Bit Timer/Counter with Auto-Reload Timer1 Mode3 Timer1 Mode3, Timer0 Mode3 Timer1 TR Timer0-Mode3. Copyright 2009 WIZnet Co., Inc. All rights reserved. 45

46 5.2 Timer Overview Timer2 pin. pin (unidirectional) three-state pin. Table 5.4 Timer2 Pin Description Pin Active Type Pu/Pd Description T2/FA1 Falling I - Timer2 external clock input T2EX/FA2 Falling I - Timer2 capture/reload trigger W7100 Timer Timer2. Timer2 TH2/TL2 (0xCD/0xCC) counter registers, RLDH/RLDL (0xCB, 0xCA) capture registers, T2CON (0xC8) control register 5 SFR. Timer2 T2CON register bit 3 mode. Table 5.5 Timer2 Modes RCLK,TCLK CPRL2 TR2 Function Description bit auto-reload mode. TF2 bit Timer2 overflow set, TH2 TL2 register RLDH RLDL reload bit capture mode. Timer2 overflow TF2 bit set EXEN2=1, T2EX pin falling edge, TH2 TL2register RLDH RLDL. 1 X 1 UART interface Baud rate generator mode X X 0 Timer2 is off. T2CON (0xC8) Reset TF2 EXF2 RCLK TCLK EXEN2 TR2 CT2 CPRL2 0x00 Figure 5.13 Timer2 Configuration Register Note: EXF2 EXEN2=1, T2EX pin falling edge EXF2 set. software clear. RCLK - Receive clock enable 0: UART receiver Timer1 overflow pulses clock 1: UART receiver Timer2 overflow pulses clock TCLK - Transmit clock enable 0: UART transmitter Timer1 overflow pulses clock 1: UART transmitter Timer2 overflow pulses clock EXEN2 - Enable T2EX pin functionality Copyright 2009 WIZnet Co., Inc. All rights reserved. 46

47 0: Ignore T2EX events 1: T2EX pin falling edge capture reload TR2 - Start/Stop Timer2 0: Stop 1: Start CT2 - Timer/Counter select 0: Internally clocked timer 1: External event counter, Clock source T2 pin CPRL2 - Capture/Reload select 0: Timer2 overflow T2EX pin falling edge EXEN2=1 reload. RCLK TCLK set, bit Timer2 overflow reload 1: EXEN2=1 T2EX pin falling edge capture Interrupts Figure 5.14 Timer/Counter2, 16-Bit Timer/Counter with Auto-Reload Timer2 interrupt bit. IE register interrupt toggle, interrupt IP register. IE (0xA8) Reset EA - ET2 ES ET1 EX1 ET0 EX0 0x00 Figure 5.15 Interrupt Enable Register Timer2 Note: EA - Enable global interrupts ET2 - Enable Timer2 interrupts Copyright 2009 WIZnet Co., Inc. All rights reserved. 47

48 IP (0xB8) Reset - - PT2 PS PT1 PX1 PT0 PX0 0x00 Figure 5.16 Interrupt Priority Register Timer2 Note: PT2 Timer2 interrupt priority level control (high level at 1) Unimplemented bit - Read as 0 or 1 T2CON (0xC8) Reset TF2 EXF2 RCLK TCLK EXEN2 TR2 CT2 CPRL2 0x00 Figure 5.17 Timer2 Configuration Register TF2 Note: TF2 Timer2 interrupt (overflow) flag, software clear. flag RCLK TCLK set set. Figure 5.18 Timer/Counter2, 16-Bit Timer/Counter with Capture Mode Interrupt bit hardware software clear set., interrupt software. Table 5.6 Timer2 Interrupt Interrupt Function Active Flag Resets Vector Natural Priority Flag Level/Edge TF2 Internal, Timer2 - Software 0x2B 6 EXEN2 bit set T2EX pin falling edge Timer2 interrupt. 0x2B vector EXF2 interrupt set. TF2 flag. Copyright 2009 WIZnet Co., Inc. All rights reserved. 48

49 Figure 5.19 Timer2 for Baud Rate Generator Mode Copyright 2009 WIZnet Co., Inc. All rights reserved. 49

50 6 UART W7100 UART receiving transmitting full duplex mode. W7100 double-buffer receiver, overrun. Read, SBUF receive register. Send SBUF transmit register load. W7100 UART 4 mode 3. Mode2 3 multiprocessor communication. SCON register SM2 bit setting. Master processor address byte slave processor. Address byte 9 bit 1 data byte 9 bit 0. SM2 = 1 data byte slave interrupt address byte slave interrupt. interrupt slave SM2 bit clear data byte. Interrupt slave SM2 bit set data byte. UART pin. Table 6.1 UART Pin Description Pin Active Type Pu/Pd Description RXD - IO Pu Serial receiver input / output TXD - O - Serial transmitter W7100 UART 8051 UART. register SBUF (0x99), SCON (0x98), PCON (0x87), IE (0xA8), IP (0xB8). UART data buffer (SBUF) transmit, receive 2 register. SBUF transmit register send SBUF receive register receive. SBUF (0x99) Reset SB7 SB6 SB5 SB4 SB3 SB2 SB1 SB0 0x00 Figure 6.1 UART Buffer Register SCON (0x98) Reset SM0 SM1 SM2 REN TB8 RB8 TI RI 0x00 Note: Figure 6.2 UART Configuration Register SM2 - Enable a multiprocessor communication feature SM1 - Set baud rate SM0 - Set baud rate Copyright 2009 WIZnet Co., Inc. All rights reserved. 50

51 REN 1 : enable serial receive 0 : disable serial receive TB8 Mode2 3 9 data bit. bit MCU (parity check, multiprocessor communication, etc.). RB8 Mode2 3 9 bit. Mode1 SM2 0 RB08 stop bit, Mode0 bit. UART 4 mode. Table 6.2 UART Modes SM0 SM1 Mode Description Baud Rate Shift register f osc / bit UART Variable bit UART f osc /32 or / bit UART Variable UART baud rate. Table 6.3 UART Baud Rates Mode Baud Rate Mode0 f osc /12 Mode1,3 Time1 overflow rate Timer2 overflow rate Mode2 SMOD0 = 0 f osc /64 SMOD0 = 1 f osc /32 SMOD0 bit PCON register. PCON (0x87) Reset SMOD0 SMOD1 - PWE x00 Figure 6.3 UART Bits in Power Configuration Register Note: SMOD0 - Bit for UART baud rate Unimplemented bit - Read as 0 or 1 Bits Interrupts UART interrupt bit. Interrupt IE register toggle interrupt IP register. Copyright 2009 WIZnet Co., Inc. All rights reserved. 51

52 IE (0xA8) Reset EA - ET2 ES ET1 EX1 ET0 EX0 0x00 Figure 6.4 UART Bits in Interrupt Enable Register Note: ES - RI0 & TI0 interrupt enable flag IP (0xB8) Reset - - PT2 PS PT1 PX1 PT0 PX0 0x00 Figure 6.5 UART Bits in Interrupt Priority Register Note: SMOD0 - Bit for UART baud rate Unimplemented bit - Read as 0 or 1 SCON (0x98) Reset SM0 SM1 SM2 REN TB08 RB08 TI RI 0x00 Figure 6.6 UART Configuration Register Note: TI Transmit interrupt flag, serial hardware set, software clear RI Receive interrupt flag, serial hardware set, software clear Interrupt bit hardware software clear set., interrupt software. Table 6.4 UART Interrupt Interrupt Function Active Flag Resets Vector Natural Priority Flag Level/Edge TI & RI Internal, UART - software 0x Mode0, Synchronous TXD shift clock. Mode0 baud rate CLK clock 1/12. LSB bit 8bit. SCON RI = 0, REN = 1. Copyright 2009 WIZnet Co., Inc. All rights reserved. 52

53 Figure 6.7 Timing Diagram for UART Transmission Mode0 (clk = MHz) 6.3 Mode 1, 8-Bit UART, Variable Baud Rate, Timer 1 or 2 Clock Source bit ( 0), 8bit (LSB ), bit (1) 10bit. bit. 8bit SBUF bit SFR SCON (0x98) RB08 flag trigger. Baud rate Timer1 2. Timer2 T2CON (0xC8) register TCLK RCLK bit set. Figure 6.8 Timing Diagram for UART Transmission Mode1 6.4 Mode 2, 9-Bit UART, Fixed Baud Rate Mode2 Baud rate CLK clock 1/32 1/64 mode1. Mode2 bit ( 0), 8 bit (LSB ), programmable bit (9 th bit), bit ( 1) 11bit. Programmable 9 th bit parity check bit. Mode2 9 th bit SCON TB08 bit. 9 th bit SCON RB08 bit. Figure 6.9 Timing Diagram for UART Transmission Mode2 Copyright 2009 WIZnet Co., Inc. All rights reserved. 53

54 6.5 Mode 3, 9-Bit UART, Variable Baud Rate, Timer1 or 2 Clock Source Mode3 baud rate mode2. REN = 1 baud rate Timer1 Timer2. Timer2 clock T2CON (0xC8) register TCLK RCLK bit. Figure 6.10 Timing Diagram for UART Transmission Mode3 6.6 Examples of Baud Rate Setting Table 6.5 Examples of Baud Rate Setting Timer 1 / Mode 2 Timer 2 Baud Rate(bps) TH1(0x8D) RLDH(0xCB), RLDL(0xCA) SMOD = 0 SMOD = (0xA0) 64(0x40) 64384(0XFB80) (0xD0) 160(0xA0) 64960(0xFDC0) (0xE8) 208(0xD0) 65248(0xFEE0) (0xF0) 224(0xE0) 65344(0XFF40) (0xF4) 232(0xE8) 65392(0XFF70) (0xF8) 240(0xF0) 65440(0xFFA0) (0xFA) 244(0xF4) 65464(0XFFB8) (0xFC) 248(0xF8) 65488(0xFFD0) (0xFE) 252(0xFC) 65512(0xFFE8) (0xFF) 254(0xFE) 65524(0xFFF4) Note: Baud Rate calculation formula Using Timer1 Baud Rate = ( 2 SMOD / 32 ) * ( Clock Frequency / 12( 256 TH1 ) ) Using Timer2 Baud Rate = Clock Frequency / ( 32 * ( ( RLDH, RLDL ) ) ) Copyright 2009 WIZnet Co., Inc. All rights reserved. 54

55 7 Watchdog Timer 7.1 Overview Watchdog Timer Figure 7.1 main clock divider. Divider CKCON (0xC8) register WD[1:0] bit timeout. Timeout, interrupt flag set reset. Interrupt enable bit global interrupt enable, interrupt. Reset interrupt. timeout. 7.2 Interrupts Figure 7.1 Watchdog Timer Structure Watchdog interrupt bit. Interrupt IE (0xA8) EIE (0xE8) register, interrupt EIP (0xF8) register. IE EA bit global interrupt. IE (0xA8) Reset EA - ET2 ES ET1 EX1 ET0 EX0 0x00 Figure 7.2 Interrupt Enable Register EIE (0xE8) Reset EWDI EINT5 EINT4 EINT3 EINT2 0x00 Figure 7.3 Extended Interrupt Enable Register Copyright 2009 WIZnet Co., Inc. All rights reserved. 55

56 Note: EA - Enable global interrupt EWDI - Enable Watchdog interrupt EIP (0xF8) Reset PWDI PINT5 PINT4 PINT3 PINT2 0x00 Figure 7.4 Extended interrupt Priority Register Note: PWDI - Watchdog priority level control (high level at 1) Unimplemented bit - Read as 0 or 1 WDCON (0xD8) Reset WDIF WTRF EWT RWT 0x00 Figure 7.5 Watchdog Control Register Note: WDIF - Watchdog Interrupt Flag. WDIF EIE register EWDI bit. EWT Watchdog interrupt. bit interrupt service software clear. interrupt. Software WDIF, interrupt enable Watchdog interrupt. bit Timed Access Register. interrupt bit hardware software set clear., interrupt software. Table 7.1 Watchdog Interrupt Interrupt Flag Function Active Level/Edge Flag Reset Vector Natural Priority WDIF Internal, Watchdog - Software 0x Watchdog Timer Reset Watchdog Timer reset. Timeout interval system reset Watchdog RWT bit reset. EWT (Enable Watchdog Timer reset = WDCON.1) bit reset mode. timer timeout software Watchdog Timer reset. Timeout RWT (Reset Watchdog Timer = WDCON.0) bit set reset timer. timeout RWT bit set, Watchdog MCU reset. Software RWT bit set, hardware RWT bit clear. Reset, WTRF (Watchdog Timer reset Flag = WDCON.2) bit set., bit software clear. Copyright 2009 WIZnet Co., Inc. All rights reserved. 56

57 7.4 Simple Timer Watchdog Timer reset mode (EWT = 0) interrupt (EWDI = 0) timer. Timer WD[1:0] count timeout Watchdog interrupt flag set. RWT bit timer. WDIF bit software reset clear. Watchdog interrupt timer. Interrupt EWDI (Enable WatchDog timer Interrupt = EIE.4) bit enable, timeout Watchdog Timer WDIF bit set. EA bit enable interrupt. WDIF Watchdog reset 512 clock set. Watchdog interrupt software clear. Watchdog interrupt, error monitor. 7.5 System Monitor Watchdog Timer monitor, Watchdog reset. interrupt, Watchdog. Watchdog interrupt code. Interrupt MCU vectoring interrupt system back. Watchdog RETI RET processor code return. Watchdog reset processor, code return. 7.6 Watchdog Related Registers Watchdog Timer SFR bit. bit reset source, interrupt source, software polled timer. Reset interrupt status flag. Watchdog timer bit. Table 7.2 Summary for Watchdog Related Bits Bit Name Register Bit Position Description EWDI EIE EIE.4 Enable Watchdog Timer Interrupt PWDI EIP EIP.4 Priority of Watchdog Timer Interrupt WD[1:0] CKCON CKCON.7-6 Watchdog Interval RWT WDCON.0 Reset Watchdog Timer EWT WDCON WDCON.1 Enable Watchdog Timer reset WTRF WDCON.2 Watchdog Timer reset flag WDIF WDCON.3 Watchdog Interrupt flag Copyright 2009 WIZnet Co., Inc. All rights reserved. 57

58 Watchdog Timer Watchdog timeout reset disable timer. software Watchdog set. Watchdog bit. 7.7 Watchdog Control Watchdog bit. register access (write) 7.8 Timed Access Registers. WDCON (0xD8) Reset WDIF WTRF EWT RWT 0x00 Figure 7.6 Watchdog Control Register Note: WDIF - Watchdog Interrupt Flag. WDIF EIE register EWDI bit. EWT Watchdog interrupt. bit interrupt service software clear. interrupt. Software WDIF, interrupt enable Watchdog interrupt. bit Timed Access Register. WTRF Watchdog Timer reset flag. flag hardware enable Watchdog Timer reset. software flag enable Watchdog Timer reset trigger. Reset flag software clear. EWT bit clear Watchdog Timer. EWT Enable the Watchdog Timer reset. bit Watchdog Timer microcontroller reset. Watchdog Timer Watchdog interrupt. bit Timed Access. 0: Watchdog Timer timeout microcontroller reset 1: Watchdog Timer timeout microcontroller reset RWT Watchdog Timer reset. RWT Watchdog Timer count reset. Watchdog Timer expire Timed Access. RWT enable Reset interrupt. Unimplemented bit - Read as 0 or 1 Copyright 2009 WIZnet Co., Inc. All rights reserved. 58

59 Watchdog control bit. Table 7.3 Watchdog Bits and Actions EWT EWDI WDIF Result X X 0 Watchdog Watchdog timeout interrupt Watchdog interrupt Watchdog timeout interrupt Timeout 512 clock RWT bit set Watchdog Timer reset Watchdog interrupt, Timeout 512 clock RWT bit set Watchdog Timer reset Clock Control Watchdog timeout WD[1:0] bit. WD[1:0] bit CKCON register. CKCON (0x8E) Reset WD1 WD MD2 MD1 MD0 0x03 Figure 7.7 Clock Control register Watchdog bits Watchdog CLK pin clock PMM mode timeout. Watchdog CLK clock 4 timeout. Timeout CLK. Table 7.4 Watchdog Intervals WD[1:0] Watchdog Interval Number of Clocks Watchdog reset enable interrupt timeout 512 clock reset. Watchdog timeout Watchdog interval 512 clock. 7.8 Timed Access Registers Timed Access register accidental wirte. TA SFR address 0xC7, register write sequence Copyright 2009 WIZnet Co., Inc. All rights reserved. 59

60 . MOV TA, #0xAA MOV TA, #0x55 ;Any direct addressing instruction writing timed access register Program wait state,, (time elapsed). sequence, protection. time protected register write open. register read. Timed Access register. Table 7.5 Timed Access Registers Register name Description WDCON(0xD8) Watchdog configuration Copyright 2009 WIZnet Co., Inc. All rights reserved. 60

61 8 TCPIPCore 8.1 Memory Map TCPIPCore Common register SOCKET register, TX memory, RX memory. Figure 8.1 TCPIPCore Memory Map 8.2 TCPIPCore Registers Common Registers Address offset Symbol Description 0xFE0000 MR Mode Register 0xFE0001 0xFE0002 0xFE0003 0xFE0004 GAR0 GAR1 GAR2 GAR3 GAR (Gateway Address Register) 0xFE0005 SUBR0 SUBR (Subnet Mask Register) 0xFE0006 SUBR1 Copyright 2009 WIZnet Co., Inc. All rights reserved. 61

62 0xFE0007 SUBR2 SUBR (Subnet Mask Register) 0xFE0008 SUBR3 0xFE0009 SHAR0 0xFE000A SHAR1 0xFE000B SHAR2 SHAR (Source Hardware Address Register) 0xFE000C SHAR3 0xFE000D SHAR4 0xFE000E SHAR5 0xFE000F SIPR0 0xFE0010 SIPR1 0xFE0011 SIPR2 SIPR (Source IP Address Register) 0xFE0012 SIPR3 0xFE0013 0xFE0014 Reserved 0xFE0015 IR Interrupt Register 0xFE0016 IMR Interrupt Mask Register 0xFE0017 0xFE0018 RTR0 RTR1 RTR (Retransmission Timeout-value Register) 0xFE0019 RCR RCR (Retransmission Retry-count Register) 0xFE001A 0xFE001B Reserved 0xFE001C 0xFE001D 0xFE001E Reserved 0xFE001F VERSIONR W7100 Version Register 0xFE0020 ~ 0xFE002D 0xFE002E 0xFE002F 0xFE0030 0xFE0031 0xFE0032 0xFE0033 UPORT0 UPORT1 INTLEVEL0 INTLEVEL1 Reserved UPORT (Unreachable Port Register in UDP mode) Interrupt Low Level Timer Register Reserved 0xFE0034 IR2 SOCKET Interrupt Register Copyright 2009 WIZnet Co., Inc. All rights reserved. 62

63 8.2.2 SOCKET Registers Address offset Symbol Description 0xFE4000 S0_MR SOCKET 0 Mode Register 0xFE4001 S0_CR SOCKET 0 Command Register 0xFE4002 S0_IR SOCKET 0 Interrupt Register 0xFE4003 S0_SR SOCKET 0 SOCKET Status Register 0xFE4004 S0_PORT0 0xFE4005 S0_PORT1 S0_PORT (SOCKET 0 Source Port Register) 0xFE4006 S0_DHAR0 0xFE4007 S0_DHAR1 0xFE4008 0xFE4009 0xFE400A 0xFE400B 0xFE400C 0xFE400D 0xFE400E 0xFE400F 0xFE4010 0xFE4011 0xFE4012 0xFE4013 0xFE4014 S0_DHAR2 S0_DHAR3 S0_DHAR4 S0_DHAR5 S0_DIPR0 S0_DIPR1 S0_DIPR2 S0_DIPR3 S0_DPORT0 S0_DPORT1 S0_MSSR0 S0_MSSR1 S0_PROTO S0_DHAR (SOCKET 0 Destination Hardware Address Register) S0_DIPR (SOCKET 0 Destination IP Address Register) S0_DPORT (SOCKET 0 Destination Port Register) S0_MSSR (SOCKET 0 Maximum Segment Size Register) SOCKET 0 Protocol of IP Header Field Register in IP raw mode 0xFE4015 S0_TOS SOCKET 0 IP Type of Service(TOS) Register 0xFE4016 S0_TTL SOCKET 0 IP Time to Live(TTL) Register 0xFE4017 ~ 0xFE401D Reserved 0xFE401E S0_RXMEM_SIZE SOCKET 0 Receive Memory Size Register 0xFE401F S0_TXMEM_SIZE SOCKET 0 Transmit Memory Size Register 0xFE4020 0xFE4021 S0_TX_FSR0 S0_TX_FSR1 S0_TX_FSR (SOCKET 0 Transmit Free Memory Size Register) 0xFE4022 S0_TX_RD0 S0_TX_RD0 Copyright 2009 WIZnet Co., Inc. All rights reserved. 63

64 0xFE4023 S0_TX_RD1 (SOCKET 0 Transmit Memory Read Pointer Register) 0xFE4024 S0_TX_WR0 S0_TX_WR 0xFE4025 S0_TX_WR1 (SOCKET 0 Transmit Memory Write Pointer Register) 0xFE4026 S0_RX_RSR0 S0_RX_RSR 0xFE4027 S0_RX_RSR1 (SOCKET 0 Received Data Size Register) 0xFE4028 S0_RX_RD0 S0_RX_RD 0xFE4029 S0_RX_RD1 (SOCKET 0 Receive Memory Read Pointer Register) 0xFE402A S0_RX_WR0 S0_RX_WR 0xFE402B S0_RX_WR1 (SOCKET 0 Receive Memory Write Pointer Register) 0xFE402C S0_IMR SOCKET 0 Interrupt Mask Register 0xFE402D S0_FRAG0 S0_FRAG 0xFE402E S0_FRAG1 (SOCKET 0 Fragment Field Value in IP Header Register) 0xFE402F ~ 0xFE40FF Reserved 0xFE4100 S1_MR SOCKET 1 Mode Register 0xFE4101 S1_CR SOCKET 1 Command Register 0xFE4102 S1_IR SOCKET 1 Interrupt Register 0xFE4103 S1_SR SOCKET 1 SOCKET Status Register 0xFE4104 0xFE4105 0xFE4106 0xFE4107 0xFE4108 0xFE4109 0xFE410A 0xFE410B 0xFE410C 0xFE410D 0xFE410E 0xFE410F 0xFE4110 0xFE4111 0xFE4112 0xFE4113 S1_PORT0 S1_PORT1 S1_DHAR0 S1_DHAR1 S1_DHAR2 S1_DHAR3 S1_DHAR4 S1_DHAR5 S1_DIPR0 S1_DIPR1 S1_DIPR2 S1_DIPR3 S1_DPORT0 S1_DPORT1 S1_MSSR0 S1_MSSR1 S1_PORT (SOCKET 1 Source Port Register) S1_DHAR (SOCKET 1 Destination Hardware Address Register) S1_DIPR (SOCKET 1 Destination IP Address Register) S1_DPORT (SOCKET 1 Destination Port Register) S1_MSSR (SOCKET 1 Maximum Segment Size Register) Copyright 2009 WIZnet Co., Inc. All rights reserved. 64

65 0xFE4114 S1_PROTO SOCKET 1 Protocol of IP Header Field Register in IP raw mode 0xFE4115 S1_TOS SOCKET 1 IP Type of Service(TOS) Register 0xFE4116 S1_TTL SOCKET 1 IP Time to Live(TTL) Register 0xFE4117 ~ Reserved 0xFE411D 0xFE411E S1_RXMEM_SIZE SOCKET 1 Receive Memory Size Register 0xFE411F S1_TXMEM_SIZE SOCKET 1 Transmit Memory Size Register 0xFE4120 S1_TX_FSR0 0xFE4121 S1_TX_FSR1 S1_TX_FSR (SOCKET 1 Transmit Free Memory Size Register) 0xFE4122 S1_TX_RD0 S1_TX_RD 0xFE4123 S1_TX_RD1 (SOCKET 1 Transmit Memory Read Pointer Register) 0xFE4124 S1_TX_WR0 S1_TX_WR 0xFE4125 S1_TX_WR1 (SOCKET 1 Transmit Memory Write Pointer Register) 0xFE4126 S1_RX_RSR0 S1_RX_RSR 0xFE4127 S1_RX_RSR1 (SOCKET 1 Received Data Size Register) 0xFE4128 S1_RX_RD0 S1_RX_RD 0xFE4129 S1_RX_RD1 (SOCKET 1 Receive Memory Read Pointer Register) 0xFE412A S1_RX_WR0 S1_RX_WR (SOCKET 1 Receive Memory Write Pointer 0xFE412B S1_RX_WR1 Register) 0xFE412C S1_IMR SOCKET 1 Interrupt Mask Register 0xFE412D S1_FRAG0 S1_FRAG 0xFE412E S1_FRAG1 (SOCKET 1 Fragment Field Value in IP Header Register) 0xFE412F ~ 0xFE41FF Reserved 0xFE4200 S2_MR SOCKET 2 Mode Register 0xFE4201 S2_CR SOCKET 2 Command Register 0xFE4202 S2_IR SOCKET 2 Interrupt Register 0xFE4203 S2_SR SOCKET 2 SOCKET Status Register 0xFE4204 0xFE4205 0xFE4206 0xFE4207 S2_PORT0 S2_PORT1 S2_DHAR0 S2_DHAR1 S2_PORT (SOCKET 2 Source Port Register) S2_DHAR (SOCKET 2 Destination Hardware Address Register) Copyright 2009 WIZnet Co., Inc. All rights reserved. 65

66 0xFE4208 0xFE4209 0xFE420A 0xFE420B 0xFE420C 0xFE420D 0xFE420E 0xFE420F 0xFE4210 0xFE4211 0xFE4212 0xFE4213 S2_DHAR2 S2_DHAR3 S2_DHAR4 S2_DHAR5 S2_DIPR0 S2_DIPR1 S2_DIPR2 S2_DIPR3 S2_DPORT0 S2_DPORT1 S2_MSSR0 S2_MSSR1 S2_DIPR (SOCKET 2 Destination IP Address Register) S2_DPORT (SOCKET 2 Destination Port Register) S2_MSSR (SOCKET 2 Maximum Segment Size Register) 0xFE4214 S2_PROTO S2_PROTO (SOCKET 2 Protocol of IP Header Field Register in IP raw mode) 0xFE4215 S2_TOS SOCKET 2 IP Type of Service(TOS) Register 0xFE4216 S2_TTL SOCKET 2 IP Time to Live(TTL) Register 0xFE4217 ~ 0xFE421D Reserved 0xFE421E S2_RXMEM_SIZE SOCKET 2 Receive Memory Size Register 0xFE421F S2_TXMEM_SIZE SOCKET 2 Transmit Memory Size Register 0xFE4220 0xFE4221 S2_TX_FSR0 S2_TX_FSR1 S2_TX_FSR (SOCKET 2 Transmit Free Memory Size Register) 0xFE4222 S2_TX_RD0 S2_TX_RD 0xFE4223 S2_TX_RD1 (SOCKET 2 Transmit Memory Read Pointer Register) 0xFE4224 S2_TX_WR0 S2_TX_WR 0xFE4225 S2_TX_WR1 (SOCKET 2 Transmit Memory Write Pointer Register) 0xFE4226 0xFE4227 S2_RX_RSR0 S2_RX_RSR1 S2_RX_RSR (SOCKET 2 Received Data Size Register) 0xFE4228 S2_RX_RD0 S2_RX_RD 0xFE4229 S2_RX_RD1 (SOCKET 2 Receive Memory Read Pointer Register) 0xFE422A S2_RX_WR0 S2_RX_WR 0xFE422B S2_RX_WR1 (SOCKET 2 Receive Memory Write Pointer Register) 0xFE422C S2_IMR SOCKET 2 Interrupt Mask Register 0xFE422D S2_FRAG0 SOCKET 2 Fragment Field Value in IP Header Register Copyright 2009 WIZnet Co., Inc. All rights reserved. 66

67 0xFE422E S2_FRAG1 0xFE422F ~ Reserved 0xFE42FF 0xFE4300 S3_MR SOCKET 3 Mode Register 0xFE4301 S3_CR SOCKET 3 Command Register 0xFE4302 S3_IR SOCKET 3 Interrupt Register 0xFE4303 S3_SR SOCKET 3 SOCKET Status Register 0xFE4304 S3_PORT0 0xFE4305 S3_PORT1 S3_PORT (SOCKET 3 Source Port Register) 0xFE4306 S3_DHAR0 0xFE4307 0xFE4308 0xFE4309 0xFE430A 0xFE430B 0xFE430C 0xFE430D 0xFE430E 0xFE430F 0xFE4310 0xFE4311 0xFE4312 0xFE4313 0xFE4314 S3_DHAR1 S3_DHAR2 S3_DHAR3 S3_DHAR4 S3_DHAR5 S3_DIPR0 S3_DIPR1 S3_DIPR2 S3_DIPR3 S3_DPORT0 S3_DPORT1 S3_MSSR0 S3_MSSR1 S3_PROTO S3_DHAR (SOCKET 3 Destination Hardware Address Register) S3_DIPR (SOCKET 3 Destination IP Address Register) S3_DPORT (SOCKET 3 Destination Port Register) S3_MSSR (SOCKET 3 Maximum Segment Size Register) SOCKET 3 Protocol of IP Header Field Register in IP raw mode 0xFE4315 S3_TOS SOCKET 3 IP Type of Service(TOS) Register 0xFE4316 S0_TTL SOCKET 3 IP Time to Live(TTL) Register 0xFE4317 ~ 0xFE431D Reserved 0xFE431E S3_RXMEM_SIZE SOCKET 3 Receive Memory Size Register 0xFE431F S3_TXMEM_SIZE SOCKET 3 Transmit Memory Size Register 0xFE4320 0xFE4321 S3_TX_FSR0 S3_TX_FSR1 S3_TX_FSR (SOCKET 3 Transmit Free Memory Size Register) Copyright 2009 WIZnet Co., Inc. All rights reserved. 67

68 0xFE4322 S3_TX_RD0 S3_TX_RD 0xFE4323 S3_TX_RD1 (SOCKET 3 Transmit Memory Read Pointer Register) 0xFE4324 S3_TX_WR0 S3_TX_WR 0xFE4325 S3_TX_WR1 (SOCKET 3 Transmit Memory Write Pointer Register) 0xFE4326 S3_RX_RSR0 0xFE4327 S3_RX_RSR1 S3_RX_RSR (SOCKET 3 Received Data Size Register) 0xFE4328 S3_RX_RD0 S3_RX_RD 0xFE4329 S3_RX_RD1 (SOCKET 3 Receive Memory Read Pointer Register) 0xFE432A S3_RX_WR0 S3_RX_WR 0xFE432B S3_RX_WR1 (SOCKET 3 Receive Memory Write Pointer Register) 0xFE432C S3_IMR SOCKET 3 Interrupt Mask Register 0xFE432D 0xFE432E 0xFE432F ~ 0xFE43FF S3_FRAG0 S3_FRAG1 SOCKET 3 Fragment Field Value in IP Header Register Reserved 0xFE4400 S4_MR SOCKET 4 Mode Register 0xFE4401 S4_CR SOCKET 4 Command Register 0xFE4402 S4_IR SOCKET 4 Interrupt Register 0xFE4403 S4_SR SOCKET 4 SOCKET Status Register 0xFE4404 0xFE4405 0xFE4406 0xFE4407 0xFE4408 0xFE4409 0xFE440A 0xFE440B 0xFE440C 0xFE440D 0xFE440E 0xFE440F 0xFE4410 0xFE4411 S4_PORT0 S4_PORT1 S4_DHAR0 S4_DHAR1 S4_DHAR2 S4_DHAR3 S4_DHAR4 S4_DHAR5 S4_DIPR0 S4_DIPR1 S4_DIPR2 S4_DIPR3 S4_DPORT0 S4_DPORT1 S4_PORT (SOCKET 4 Source Port Register) S4_DHAR (SOCKET 4 Destination Hardware Address Register) S4_DIPR (SOCKET 4 Destination IP Address Register) S4_DPORT (SOCKET 4 Destination Port Register) 0xFE4412 S4_MSSR0 S4_MSSR (SOCKET 4 Maximum Segment Size Register) Copyright 2009 WIZnet Co., Inc. All rights reserved. 68

69 0xFE4413 S4_MSSR1 0xFE4414 S4_PROTO SOCKET 4 Protocol of IP Header Field Register in IP raw mode 0xFE4415 S4_TOS SOCKET 4 IP Type of Service(TOS) Register 0xFE4416 S4_TTL SOCKET 4 IP Time to Live(TTL) Register 0xFE4417 ~ Reserved 0xFE441D 0xFE441E S4_RXMEM_SIZE SOCKET 4 Receive Memory Size Register 0xFE441F S4_TXMEM_SIZE SOCKET 4 Transmit Memory Size Register 0xFE4420 0xFE4421 S4_TX_FSR0 S4_TX_FSR1 S4_TX_FSR (SOCKET 4 Transmit Free Memory Size Register) 0xFE4422 S4_TX_RD0 S4_TX_RD 0xFE4423 S4_TX_RD1 (SOCKET 4 Transmit Memory Read Pointer Register) 0xFE4424 S4_TX_WR0 S4_TX_WR 0xFE4425 S4_TX_WR1 (SOCKET 4 Transmit Memory Write Pointer Register) 0xFE4426 0xFE4427 S4_RX_RSR0 S4_RX_RSR1 S4_RX_RSR (SOCKET 4 Received Data Size Register) 0xFE4428 S4_RX_RD0 S4_RX_RD 0xFE4429 S4_RX_RD1 (SOCKET 4 Receive Memory Read Pointer Register) 0xFE442A S4_RX_WR0 S4_RX_WR 0xFE442B S4_RX_WR1 (SOCKET 4 Receive Memory Write Pointer Register) 0xFE442C S4_IMR SOCKET 4 Interrupt Mask Register 0xFE442D 0xFE442E 0xFE442F ~ 0xFE44FF S4_FRAG0 S4_FRAG1 SOCKET 4 Fragment Field Value in IP Header Register Reserved 0xFE4500 S5_MR SOCKET 5 Mode Register 0xFE4501 S5_CR SOCKET 5 Command Register 0xFE4502 S5_IR SOCKET 5 Interrupt Register 0xFE4503 S5_SR SOCKET 5 SOCKET Status Register 0xFE4504 0xFE4505 S5_PORT0 S5_PORT1 S5_PORT (SOCKET 5 Source Port Register) Copyright 2009 WIZnet Co., Inc. All rights reserved. 69

70 0xFE4506 0xFE4507 0xFE4508 0xFE4509 0xFE450A 0xFE450B 0xFE450C 0xFE450D 0xFE450E 0xFE450F S5_DHAR0 S5_DHAR1 S5_DHAR2 S5_DHAR3 S5_DHAR4 S5_DHAR5 S5_DIPR0 S5_DIPR1 S5_DIPR2 S5_DIPR3 S5_DHAR (SOCKET 5 Destination Hardware Address Register) S5_DIPR (SOCKET 5 Destination IP Address Register) 0xFE4510 0xFE4511 S5_DPORT0 S5_DPORT1 S5_DPORT (SOCKET 5 Destination Port Register) 0xFE4512 0xFE4513 S5_MSSR0 S5_MSSR1 S5_MSSR (SOCKET 5 Maximum Segment Size Register) 0xFE4514 S5_PROTO SOCKET 5 Protocol of IP Header Field Register in IP raw mode 0xFE4515 S5_TOS SOCKET 5 IP Type of Service(TOS) Register 0xFE4516 S5_TTL SOCKET 5 IP Time to Live(TTL) Register 0xFE4517 ~ 0xFE451D Reserved 0xFE451E S5_RXMEM_SIZE SOCKET 5 Receive Memory Size Register 0xFE451F S5_TXMEM_SIZE SOCKET 5 Transmit Memory Size Register 0xFE4520 0xFE4521 S5_TX_FSR0 S5_TX_FSR1 S5_TX_FSR (SOCKET 5 Transmit Free Memory Size Register) 0xFE4522 S5_TX_RD0 S5_TX_RD 0xFE4523 S5_TX_RD1 (SOCKET 5 Transmit Memory Read Pointer Register) 0xFE4524 S5_TX_WR0 S5_TX_WR 0xFE4525 S5_TX_WR1 (SOCKET 5 Transmit Memory Write Pointer Register) 0xFE4526 0xFE4527 S5_RX_RSR0 S5_RX_RSR1 S5_RX_RSR (SOCKET 5 Received Data Size Register) 0xFE4528 S5_RX_RD0 S5_RX_RD 0xFE4529 S5_RX_RD1 (SOCKET 5 Receive Memory Read Pointer Register) 0xFE452A 0xFE452B S5_RX_WR0 S5_RX_WR1 S5_RX_WR (SOCKET 5 Receive Memory Write Pointer Register) Copyright 2009 WIZnet Co., Inc. All rights reserved. 70

71 0xFE452C S5_IMR SOCKET 5 Interrupt Mask Register 0xFE452D S5_FRAG0 S5_FRAG 0xFE452E S5_FRAG1 (SOCKET 5 Fragment Field Value in IP Header Register) 0xFE452F ~ Reserved 0xFE45FF 0xFE4600 S6_MR SOCKET 6 Mode Register 0xFE4601 S6_CR SOCKET 6 Command Register 0xFE4602 S6_IR SOCKET 6 Interrupt Register 0xFE4603 S6_SR SOCKET 6 SOCKET Status Register 0xFE4604 S6_PORT0 0xFE4605 S6_PORT1 S6_PORT (SOCKET 6 Source Port Register) 0xFE4606 0xFE4607 0xFE4608 0xFE4609 0xFE460A 0xFE460B 0xFE460C 0xFE460D 0xFE460E 0xFE460F 0xFE4610 0xFE4611 0xFE4612 0xFE4613 0xFE4614 S6_DHAR0 S6_DHAR1 S6_DHAR2 S6_DHAR3 S6_DHAR4 S6_DHAR5 S6_DIPR0 S6_DIPR1 S6_DIPR2 S6_DIPR3 S6_DPORT0 S6_DPORT1 S6_MSSR0 S6_MSSR1 S6_PROTO S6_DHAR (SOCKET 6 Destination Hardware Address Register) S6_DIPR (SOCKET 6 Destination IP Address Register) S6_DPORT (SOCKET 6 Destination Port Register) S6_MSSR (SOCKET 6 Maximum Segment Size Register) SOCKET 6 Protocol of IP Header Field Register in IP raw mode 0xFE4615 S6_TOS SOCKET 6 IP Type of Service(TOS) Register 0xFE4616 S6_TTL SOCKET 6 IP Time to Live(TTL) Register 0xFE4617 ~ 0xFE461D Reserved 0xFE461E S6_RXMEM_SIZE SOCKET 6 Receive Memory Size Register 0xFE461F S6_TXMEM_SIZE SOCKET 6 Transmit Memory Size Register Copyright 2009 WIZnet Co., Inc. All rights reserved. 71

72 0xFE4620 S6_TX_FSR0 0xFE4621 S6_TX_FSR1 S6_TX_FSR (SOCKET 6 Transmit Free Memory Size Register) 0xFE4622 S6_TX_RD0 S6_TX_RD 0xFE4623 S6_TX_RD1 (SOCKET 6 Transmit Memory Read Pointer Register) 0xFE4624 S6_TX_WR0 S6_TX_WR 0xFE4625 S6_TX_WR1 (SOCKET 6 Transmit Memory Write Pointer Register) 0xFE4626 S6_RX_RSR0 0xFE4627 S6_RX_RSR1 S6_RX_RSR (SOCKET 6 Received Data Size Register) 0xFE4628 S6_RX_RD0 S6_RX_RD 0xFE4629 S6_RX_RD1 (SOCKET 6 Receive Memory Read Pointer Register) 0xFE462A S6_RX_WR0 S6_RX_WR 0xFE462B S6_RX_WR1 (SOCKET 6 Receive Memory Write Pointer Register) 0xFE462C S6_IMR SOCKET 6 Interrupt Mask Register 0xFE462D S6_FRAG0 S6_FRAG 0xFE462E S6_FRAG1 (SOCKET 6 Fragment Field Value in IP Header Register) 0xFE462F ~ 0xFE46FF Reserved 0xFE4700 S7_MR SOCKET 7 Mode Register 0xFE4701 S7_CR SOCKET 7 Command Register 0xFE4702 S7_IR SOCKET 7 Interrupt Register 0xFE4703 S7_SR SOCKET 7 SOCKET Status Register 0xFE4704 0xFE4705 0xFE4706 0xFE4707 0xFE4708 0xFE4709 0xFE470A 0xFE470B 0xFE470C 0xFE470D 0xFE470E 0xFE470F S7_PORT0 S7_PORT1 S7_DHAR0 S7_DHAR1 S7_DHAR2 S7_DHAR3 S7_DHAR4 S7_DHAR5 S7_DIPR0 S7_DIPR1 S7_DIPR2 S7_DIPR3 S7_PORT (SOCKET 7 Source Port Register) S7_DHAR (SOCKET 7 Destination Hardware Address Register) S7_DIPR (SOCKET 7 Destination IP Address Register) Copyright 2009 WIZnet Co., Inc. All rights reserved. 72

73 0xFE4710 S7_DPORT0 0xFE4711 S7_DPORT1 S7_DPORT (SOCKET 7 Destination Port Register) 0xFE4712 S7_MSSR0 0xFE4713 S7_MSSR1 S7_MSSR (SOCKET 7 Maximum Segment Size Register) 0xFE4714 S0_PROTO SOCKET 7 Protocol of IP Header Field Register in IP raw mode 0xFE4715 S7_TOS SOCKET 7 IP Type of Service(TOS) Register 0xFE4716 S7_TTL SOCKET 7 IP Time to Live(TTL) Register 0xFE4717 ~ 0xFE471D Reserved 0xFE471E S7_RXMEM_SIZE SOCKET 7 Receive Memory Size Register 0xFE471F S7_TXMEM_SIZE SOCKET 7 Transmit Memory Size Register 0xFE4720 0xFE4721 S7_TX_FSR0 S7_TX_FSR1 S7_TX_FSR (SOCKET 7 Transmit Free Memory Size Register) 0xFE4722 S7_TX_RD0 S7_TX_RD 0xFE4723 S7_TX_RD1 (SOCKET 7 Transmit Memory Read Pointer Register) 0xFE4724 S7_TX_WR0 S7_TX_WR 0xFE4725 S7_TX_WR1 (SOCKET 7 Transmit Memory Write Pointer Register) 0xFE4726 0xFE4727 S7_RX_RSR0 S7_RX_RSR1 S7_RX_RSR (SOCKET 7 Received Data Size Register) 0xFE4728 S7_RX_RD0 S7_RX_RD 0xFE4729 S7_RX_RD1 (SOCKET 7 Receive Memory Read Pointer Register) 0xFE472A S7_RX_WR0 S7_RX_WR 0xFE472B S7_RX_WR1 (SOCKET 7 Receive Memory Write Pointer Register) 0xFE472C S7_IMR SOCKET 7 Interrupt Mask Register 0xFE472D S7_FRAG0 S7_FRAG 0xFE472E S7_FRAG1 (SOCKET 7 Fragment Field Value in IP Header Register) 0xFE472F ~ 0xFE47FF Reserved 8.3 Register Description Mode Register MR (Mode Register) [R/W] [0xFE0000] [0x00] MR S/W reset, ping block mode. Copyright 2009 WIZnet Co., Inc. All rights reserved. 73

74 RST PB Bit Symbol Description 7 RST S/W Reset bit 1 register reset clear 6 Reserved Reserved 5 Reserved Reserved 4 PB Ping Block Mode 0 : Disable Ping block 1 : Enable Ping block If the bit is set as 1, there is no response to the ping request. 3 Reserved Reserved 2 Reserved Reserved 1 Reserved Reserved 0 Reserved Reserved GAR (Gateway IP Address Register) [R/W] [0xFE0001 0xFE0004] [0x00] GAR default gateway address. Ex) In case of xFE0001 0xFE0002 0xFE0003 0xFE (0xC0) 168 (0xA8) 0 (0x00) 1 (0x01) SUBR (Subnet Mask Register) [R/W] [0xFE0005 0xFE0008] [0x00] SUBR subnet mask address. Ex) In case of xFE0005 0xFE0006 0xFE0007 0xFE (0xFF) 255 (0xFF) 255 (0xFF) 0 (0x00) SHAR (Source Hardware Address Register) [R/W] [0xFE0009 0xFE000E] [0x00] SHAR Source Hardware address. Ex) In case of DC xFE0009 0xFE000A 0xFE000B 0xFE000C 0xFE000D 0xFE000E 0x00 0x08 0xDC 0x01 0x02 0x03 SIPR (Source IP Address Register) [R/W] [0xFE000F 0xFE0012] [0x00] Copyright 2009 WIZnet Co., Inc. All rights reserved. 74

75 SIPR Source IP address. Ex) In case of xFE000F 0xFE0010 0xFE0011 0xFE (0xC0) 168 (0xA8) 0 (0x00) 2 (0x02) IR (Interrupt Register) [R] [0xFE0015] [0x00] IR interrupt W7100 MCU access. IR bit set INT5(nINT5: TCPIPcore interrupt) low asserted IR bit clear high. IR MCU interrupt CONFLICT UNREACH Reserved Reserved Reserved Reserved Reserved Reserved Bit Symbol Description 7 CONFLICT IP Conflict ARP Source IP address IP address, bit 1 set. bit 1 write 0 clear. 6 UNREACH Destination unreachable W7100 UDP destination IP address ICMP (Destination Unreachable) packet. IP address port number Unreachable IP address register (UIPR) Unreachable port register (UPORT). UNREACH bit 1 set. bit 1 write 0 clear. 5 Reserved Reserved 4 Reserved Reserved 3 Reserved Reserved 2 Reserved Reserved 1 Reserved Reserved 0 Reserved Reserved IMR (Interrupt Mask Register) [R/W] [0xFE0016] [0x00] IMR (Interrupt Mask Register) interrupt. interrupt mask bit Interrupt register2 (IR2) bit. Interrupt mask bit set, IR2 bit set interrupt. IMR 0 set, IR2 bit set interrupt S7_INT S6_INT S5_INT S4_INT S3_INT S2_INT S1_INT S0_INT Bit Symbol Description 7 S7_INT IR(S7_INT) Interrupt Mask Copyright 2009 WIZnet Co., Inc. All rights reserved. 75

76 6 S6_INT IR(S6_INT) Interrupt Mask 5 S5_INT IR(S5_INT) Interrupt Mask 4 S4_INT IR(S4_INT) Interrupt Mask 3 S3_INT IR(S3_INT) Interrupt Mask 2 S2_INT IR(S2_INT) Interrupt Mask 1 S1_INT IR(S1_INT) Interrupt Mask 0 S0_INT IR(S0_INT) Interrupt Mask RTR (Retry Time-value Register) [R/W] [0xFE0017 0xFE0018] [0x07D0] RTR timeout. register 1 100us. Default timeout 2000 (0x07D0), 200ms. Ex) For 400ms configuration, set as 4000(0x0FA0) 0xFE0017 0xFE0018 0x0F 0xA0 peer timeout delay. RCR (Retry Count Register) [R/W] [0xFE0019] [0x08] RCR. RCR, Timeout Interrupt. (SOCKETn Interrupt Register (Sn_IR) TIMEOUT bit 1 ) VERSIONR (W7100 Chip Version Register) [R] [0xFE001F] [0x02] VERSIONR W7100 chip version register. UIPR (Unreachable IP Address Register) [R] [0xFE002A 0xFE002D] [0x00] UDP, destination IP address ICMP (Destination Unreachable) packet. IP address port number Unreachable IP address register(uipr) Unreachable port register(uport). Ex) For the case of x002A 0x002B 0x002C 0x002D 192 (0xC0) 168 (0xA8) 0 (0x00) 11 (0x0B) UPORT (Unreachable Port Register) [R] [0xFE002E 0xFE002F] [0x0000] Unreachable IP address register (UIPR). Ex) For the case of 5000(0x1388) 0xFE002E 0xFE002F Copyright 2009 WIZnet Co., Inc. All rights reserved. 76

77 0x13 0x88 INTLEVEL (Interrupt Low Level Timer Register)[R/W][0xFE0030 0xFE0031][0x0000] INTLEVEL register Interrupt Assert wait time(i AWT ). interrupt (I AWT ) INT5 Low assert. TCP/IP Core interrupt, register 0x2B00. MCU TCP/IP Core interrupt. I AWT = (INTLEVEL0 + 1) * PLL_CLK (when INTLEVEL0 > 0) a. 0 interrupt (S0_IR(3) = 1 IR2 bit 1 set INT5 Low assert. b. 1 interrupt (S1_IR1(0) = 1 ) IR2 bit 1 set. c. MCU S0_IR1 clear(s0_ir1 = 0x00) IR2 bit clear. INT5 High De-assert. d. S0_IR1 clear, socket1 interrupt IR2 0x00. INT5 Low assert. INTLEVEL register 0x000F INT5 I AWT (16 PLL_CLK) time Low assert. IR2 (W7100 SOCKET Interrupt Register) [R/W] [0xFE0034] [0x00] IR2 W7100 SOCKET interrupt register. Interrupt, IR2 bit set. IR2 bit 0 clear INT5(nINT5: TCPIPCore interrupt) low. Sn_IR bit IR2 register clear INT5 high Copyright 2009 WIZnet Co., Inc. All rights reserved. 77

78 S7_INT S6_INT S5_INT S4_INT S3_INT S2_INT S1_INT S0_INT Bit Symbol Description 7 S7_INT Occurrence of SOCKET 7 Interrupt SOCKET 7 interrupt, bit 1 interrupt S7_IR2. bit S7_IR2 0x00 clear clear. 6 S6_INT Occurrence of SOCKET 6 Interrupt SOCKET 6 interrupt, bit 1 interrupt S6_IR2. bit S6_IR2 0x00 clear clear. 5 S5_INT Occurrence of SOCKET 5 Interrupt SOCKET 5 interrupt, bit 1 interrupt S5_IR2. bit S5_IR2 0x00 clear clear. 4 S4_INT Occurrence of SOCKET 4 Interrupt SOCKET 4 interrupt, bit 1 interrupt S4_IR2. bit S4_IR2 0x00 clear clear. 3 S3_INT Occurrence of SOCKET 3 Interrupt SOCKET 3 interrupt, bit 1 interrupt S3_IR2. bit S3_IR2 0x00 clear clear. 2 S2_INT Occurrence of SOCKET 2 Interrupt SOCKET 2 interrupt, bit 1 interrupt S2_IR2. bit S2_IR2 0x00 clear clear. 1 S1_INT Occurrence of SOCKET 1 Interrupt SOCKET 1 interrupt, bit 1 interrupt S1_IR2. bit S1_IR2 0x00 clear clear. 0 S0_INT Occurrence of SOCKET 0 Interrupt SOCKET 0 interrupt, bit 1 interrupt S0_IR2. bit S0_IR2 0x00 clear clear. Copyright 2009 WIZnet Co., Inc. All rights reserved. 78

79 8.3.2 SOCKET Registers Sn_MR (SOCKET n Mode Register)[R/W][0xFE x100n][0x0000] Sn_MR SOCKET n option protocol type MULTI MF ND / MC P3 P2 P1 P0 Bit Symbol Description 7 MULTI Multicasting 0 : disable Multicasting 1 : enable Multicasting UDP (P3-P0 : 0010 ) Multicasting OPEN SOCKET n destination IP port register multicast group address port number write 6 MF MAC Filter 5 ND/MC Use No Delayed ACK 0 : Disable No Delayed ACK option 1 : Enable No Delayed ACK option, TCP (P3-P0: 0001 ) bit 1 set peer packet ACK packet. bit 0 ACK packet timeout Multicast 0 : using IGMP version 2 1 : using IGMP version 1 bit MULTI bit enable UDP (P3-P0: 0010 ) multicast IGMP message Join/Leave/Report version number Multicast group 4 Reserved Reserved 3 P3 Protocol SOCKET TCP, UDP, IPRAW protocol Symbol P3 P2 P1 P0 Meaning Sn_MR_CLOSE Closed 2 P2 Sn_MR_TCP TCP Sn_MR_UDP UDP 1 P1 Sn_MR_IPRAW IPRAW S0_MR_MACRAW MAC RAW Copyright 2009 WIZnet Co., Inc. All rights reserved. 79

80 S0_MR_MACRAW SOCKET 0 0 P0 Sn_CR (SOCKET n Command Register) [R/W] [0xFE x100n] [0x00] Sn_CR OPEN, CLOSE, CONNECT, LISTEN, SEND, RECEIVE SOCKET n. W7100 Sn_CR W7100 clear. Sn_CR 0x00 clear,. Sn_CR Sn_IR Sn_SR. Value Symbol Description SOCKET n Sn_MR (P3:P0) protocol open. Sn_MR Sn_SR. Sn_MR(P3:P0) Sn_SR 0x01 OPEN Sn_MR_CLOSE - Sn_MR_TCP SOCK_INIT Sn_MR_UDP SOCK_UDP Sn_MR_IPRAW SOCK_IPRAW S0_MR_MACRAW SOCK_MACRAW 0x02 0x04 LISTEN CONNECT LISTEN TCP mode (Sn_MR(P3:P0) = Sn_MR_TCP), SOCKET n TCP CLIENT connection-request (SYN packet) TCP server. Sn_SR SOCKET_INIT SOCKET_LISTEN. Client connection-request established Sn_SR SOCK_LISTEN SOCK_ESTABLISHED Sn_IR(0) 1. connection failure (SYN/ACK packet ) Sn_IR(3) 1 set Sn_SR SOCK_CLOSED. cf> connection request TCP client destination port, W7100 RST packet Sn_SR. CONNECT TCP mode(sn_mr(p3:p0) = Sn_MR_TCP) SOCKET n TCP CLIENT. CONNECT Sn_DIPR Sn_DPORTR TCP SERVER Connectrequest(SYN packet). Connect-request (SYN/ACK packet ), Sn_IR(0)= 1 Sn_SSR SOCK_ESTABLISHED. Connect-request 3. - ARP-process Destination hardware address Copyright 2009 WIZnet Co., Inc. All rights reserved. 80

81 ARP TO (Sn_IR(3)= 1 ) - SYN/ACK packet TCP TO (Sn_IR(3)= 1 ) - SYN/ACK packet RST packet. Sn_SR SOCK_CLOSED. DISCON TCP mode. W7100 TCP SERVER TCP CLIENT, Disconnect-request(FIN packet) (Active close), Disconnect-request(FIN packet) (Passive 0x08 DISCON close), W7100 FIN packet (Disconnect-process). Disconnect-request (FIN/ACK packet ), Sn_SR SOCK_CLOSED. Disconnect-request, TCP TO (Sn_IR(3)= 1 ) Sn_SR SOCK_CLOSED. cf> DISCON CLOSE, Disconnect-process(disconnectrequest ), Sn_SR SOCK_CLOSED. RST packet, Sn_SR SOCK_CLOSED. 0x10 CLOSE SOCKET n close. Sn_SR SOCK_CLOSED. 0x20 SEND SEND TX memory buffer. SOCKET n TX Free Size Register (Sn_TX_FSR0), SOCKET n TX Write Pointer Register (Sn_TX_WR0), SOCKET n TX Read Pointer Register(Sn_TX_RD0). SEND_MAC UDP mode. SEND. SEND ARP-process 0x21 SEND_MAC Destination hardware address Data, SEND_MAC Host Sn_DHAR Destination hardware address Data. 0x22 SEND_KEEP SEND_KEEP TCP mode. 1byte connection. connection connection. Timeout interrupt. 0x40 RECV RECV RX read pointer register (Sn_RX_RD0) SERVER mode Receiving Process SOCKET n RX Received Size Register (Sn_RX_RSR0), SOCKET n RX Write Pointer Register(Sn_RX_WR0), and SOCKET n RX Read Pointer Register(Sn_RX_RD0). Copyright 2009 WIZnet Co., Inc. All rights reserved. 81

82 Sn_IR (SOCKET n Interrupt Register)[R/W][0xFE x100n][0x00] Sn_IR register SOCKET n interrupt (establishment, termination, receiving data, timeout) type. Interrupt Sn_IMR mask bit 1 Sn_IR interrupt bit 1. Sn_IR bit clear, bit 1 write. Sn_IR bit clear, IR(n) clear. Sn_IR MCU INT5 (nint5: TCPIPCore interrupt) Reserved Reserved Reserved SEND_OK TIMEOUT RECV DISCON CON Bit Symbol Description 7 Reserved Reserved 6 Reserved Reserved 5 Reserved Reserved 4 SENDOK SEND OK Interrupt, SEND 3 TIMEOUT TIMEOUT Interrupt, ARP TO TCP TO 2 RECV Receive Interrupt, peer packet 1 DISCON Disconnect Interrupt, peer FIN/ACK packet FIN 0 CON Connect Interrupt, peer Sn_SR (SOCKET n Status Register)[R][0xFE x100n][0x00] Sn_SR SOCKETn SOCKET. SOCKET status Sn_CR Command, packet. SOCKET n. Value Symbol Description 0x00 SOCK_CLOSED SOCKET n resource release DISCON, CLOSE command ARP TO,TCP TO. 0x13 SOCK_INIT SOCKET n TCP mode open TCP initialize. LISTEN CONNECT. Sn_MR(P3:P0) Sn_MR_TCP OPEN, Sn_SR SOCK_INIT. 0x14 SOCK_LISTEN SOCKET n TCP server mode, TCP CLIENT connection-request(syn packet). LISTEN, Sn_SR SOCK_LISTEN. SOCK_LISTEN TCP CLIENT Connect- Copyright 2009 WIZnet Co., Inc. All rights reserved. 82

83 request (SYN packet) Sn_SR SOCK_ESTABLISHED, TCP TO (Sn_IR(TIME OUT)= 1 ) SOCK_CLOSED. 0x17 SOCK_ESTABLISHED TCP SOCK_LISTEN TCP CLIENT SYN packet CONNECT command Sn_SR SOCK_ESTABLEISHED. DATA packet. SEND RECV command. 0x1C SOCK_CLOSE_WAIT Peer disconnect-request(fin packet) TCP connection disconnect half close DATA packet. TCP connection disconnect DISCON. SOCKET close CLOSE. 0x22 SOCK_UDP SOCKET n UDP mode Open, Sn_MR(P3:P0) = Sn_MR_UDP OPEN Sn_SR SOCK_UDP. TCP mode SOCKET connection-process DATA packet. (3 way handshake) 0x32 SOCK_IPRAW SOCKET n IPRAW mode Open, Sn_MR(P3:P0) = Sn_MR_IPRAW OPEN Sn_SR SOCK_IPRAW. UDP mode SOCKET connection-process IP packet. 0x42 SOCK_MACRAW SOCKET 0 MACRAW mode Open, S0_MR(P3:P0) = S0_MR_MACRAW OPEN Sn_SR SOCK_MACRAW. UDP mode SOCKET connection-process MAC packet (Ethernet frame). Sn_SR. Value Symbol Description 0x15 SOCK_SYNSENT SOCK_SYNSENT TCP SERVER Connect-request (SYN packet), CONNECT Sn_SR SOCK_INIT SOCK_ESTABLISEHD. Copyright 2009 WIZnet Co., Inc. All rights reserved. 83

84 TCP SEVER Connect-accept (SYN/ACK packet) SOCK_ ESTABLISHED. TCP SEVER TCP TO (Sn_IR(TIMEOUT)= 1 ) SYN/ACK packet SOCK_CLOSED. 0x16 SOCK_SYNRECV SOCK_SYNRECV TCP CLIENT connect-request (SYN packet), W7100 connect-request connect-accept (SYN/ACK packet) TCP CLIENT SOCK_ESTABLISHED. Timeout interrupt (Sn_IR(TIME OUT)= 1 ) SOCK_CLOSED. 0x18 SOCK_FIN_WAIT SOCKETn Closing, Active close Passive 0x1A SOCK_CLOSING close Disconnect-process. 0X1B SOCK_TIME_WAIT Disconnect-process, Timeout 0X1D SOCK_LAST_ACK interrupt (Sn_IR(TIMEOUT)= 1 ) SOCK_ CLOSED. 0x11 0x21 0x31 SOCK_ARP Destination hardware address peer ARPrequest SOCK_UDP SOCK_IPRAW SEND. Peer Hardware address (ARP-response ), SOCK_UDP, SOCK_IPRAW, SOCK_SYNSENT, timeout interrupt (Sn_IR(TIMEOUT)= 1 ), UDP IPRAW mode Status SOCK_UDP SOCK_IPRAW, TCP SOCK_CLOSED. cf> SOCK_UDP SOCK_IPRAW, SEND command Sn_DIPR SEND command Sn_DIPR ARP-process. Copyright 2009 WIZnet Co., Inc. All rights reserved. 84

85 Figure 8.2 SOCKET n Status transition Sn_PORT (SOCKET n Source Port Register)[R/W][(0xFE x100n) (0xFE x100n)][0x0000] Sn_PORT source port number. SOCKETn TCP UDP mode, mode. OPEN Command. Ex) In case of SOCKET 0 port = 5000(0x1388), configure as below, 0xFE4004 0xFE4005 0x13 0x88 Sn_DHAR (SOCKET n Destination Hardware Address Register)[R/W][(0xFE x100n) (0xFE400B + 0x100n)][FF.FF.FF.FF.FF.FF] Sn_DHAR SOCKET n Destination hardware address. UDP IPRAW mode SEND_MAC command SOCKETn Destination hardware address. TCP, UDP, IPRAW mode Sn_DHAR CONNECT SEND command ARPprocess Destination hardware address. Host CONNECT SEND Copyright 2009 WIZnet Co., Inc. All rights reserved. 85

86 command Sn_DHAR Destination hardware address. EX) In case of SOCKET 0 Destination Hardware address = DC , configuration is as below, 0xFE4006 0xFE4007 0xFE4008 0xFE4009 0xFE400A 0xFE400B 0x00 0x08 0xDC 0x01 0x02 0x10 Sn_DIPR (SOCKET n Destination IP Address Register)[R/W][(0xFE400C + 0x100n) (0xFE400F + 0x100n)][ ] Sn_DIPR SOCKETn Destination IP address. Sn_DIPR TCP, UDP, IPRAW, MACRAW mode. TCP mode, TCP CLIENT TCP SERVER IP address, CONNECT command. TCP SERVER TCP CLIENT TCP CLIENT IP address. UDP IPRAW mode, Sn_DIPR UDP IP DATA packet Destination IP address SEND SEND_MAC command. Ex) In case of SOCKET 0 Destination IP address = , configure as below, 0xFE400C 0xFE400D 0xFE400E 0xFE400F 192 (0xC0) 168 (0xA8) 0 (0x00) 11 (0x0B) Sn_DPORT (SOCKET n Destination Port Register)[R/W][(0xFE x100n) (0xFE x100n)][0x0000] Sn_DIPR SOCKETn Destination port number. Sn_DIPR TCP, UDP mode, mode. TCP mode, TCP CLIENT TCP SERVER Listen port number, CONNECT command. UDP mode, Sn_DPORTR UDP DATA packet Port number SEND SEND_MAC command. Ex) In case of SOCKET 0 Destination Port = 5000(0x1388), configure as below, 0xFE4010 0xFE4011 0x13 0x88 Sn_MSSR (SOCKET n Maximum Segment Size Register)[R/W][(0xFE x100n) (0xFE x100n)][0x0000] Sn_MSSR SOCKETn MTU(Maximum Transfer Unit), MTU. Host Sn_MSSR Default MTU. Sn_MSSR TCP UDP mode. IPRAW MACRAW MTU Default MTU, Host Default MTU Data Data Default MTU (Manually). TCP UDP mode Host Data MTU, W7100 Copyright 2009 WIZnet Co., Inc. All rights reserved. 86

87 MTU Data (Automatically). MTU TCP mode MSS, MSS TCP connection Host-Written-Value(Host ) MSS. UDP mode TCP mode Connection-process Host-Written-Value. MTU, W7100 ICMP(Fragment MTU) packet. IR(FMTU)= 1 Host FMTUR Fragment MTU. IR(FMTU)= 1 UDP, SOCKET close FMTU Sn_MSSR OPEN command open. Normal Mode Default MTU Range TCP ~ 1460 UDP ~ 1472 IPRAW 1480 MACRAW 1514 Ex) In case of SOCKET 0 MSS = 1460(0x05B4), configure as below, 0xFE4012 0xFE4013 0x05 0xB4 Sn_PROTO (SOCKET n Protocol Number Register)[R/W][0xFE x100n][0x00] Sn_PROTO 1 byte register IP layer IP header Protocol number field. IPRAW mode, mode. Sn_PROTOR OPEN command. IPRAW mode Open SOCKETn Sn_PROTOR Protocol number Data. Sn_PROTOR 0x00 ~ 0xFF, W7100 TCP(0x06), UDP(0x11) protocol number. Protocol number IANA (Internet Assigned Numbers Authority), IANA online document ( ). Ex) Internet Control Message Protocol(ICMP) = 0x01, Internet Group Management Protocol = 0x02 Sn_TOS (SOCKET n TOS Register)[R/W][0xFE x100n][0x00] Sn_TOS IP layer IP header TOS(Type of service) field. Sn_TOS OPEN command. Sn_TTL (SOCKET n TTL Register)[R/W][0xFE x100n][0x80] Copyright 2009 WIZnet Co., Inc. All rights reserved. 87

88 Sn_TTL IP layer IP header TTL(Time to live) field. Sn_TTL OPEN command. Sn_RXMEM_SIZE (SOCKET n Receive Memory Size Register)[R/W][0xFE401E + 0x100n][0x02] Sn_RXMEM_SIZE SOCKET RX memory size. SOCKET RX memory 1, 2, 4, 8Kbyte. Reset 2Kbyte. Sn_RXMEM_SIZE SUM ( Sn_RXMEM_SIZE ) 16Kbyte. Ex1) SOCKET 0 : 8KB, SOCKET 1 : 2KB 0xFE401E 0xFE411E 0x08 0x02 Ex2) SOCKET 2 : 1KB, SOCKET 3 : 1KB 0xFE421E 0xFE431E 0x01 0x01 Ex3) SOCKET 4 : 1KB, SOCKET 5 : 1KB 0xFE441E 0xFE451E 0x01 0x01 Ex4) SOCKET 6 : 1KB, SOCKET 7 : 1KB 0xFE461E 0xFE471E 0x01 0x01 As shown above ex1) ~ ex4), total size of each SOCKET s RX memory (Sn_RXMEM_SIZE SUM ) is 16Kbytes. Sn_TXMEM_SIZE (SOCKET n Transmit Memory Size Register)[R/W][0xFE401F + 0x100n][0x02] Sn_TXMEM_SIZE SOCKET TX memory size. SOCKET TX memory 1, 2, 4, 8Kbyte. Reset 2Kbyte. Sn_TXMEM_SIZE SUM ( Sn_TXMEM_SIZE ) 16Kbyte. Ex5) SOCKET 0 : 4KB, SOCKET 1 : 1KB 0xFE401F 0xFE411F 0x04 0x01 Ex6) SOCKET 2 : 2KB, SOCKET 3 : 1KB Copyright 2009 WIZnet Co., Inc. All rights reserved. 88

89 0xFE421F 0xFE431F 0x02 0x01 Ex7) SOCKET 4 : 2KB, SOCKET 5 : 2KB 0xFE441F 0xFE451F 0x02 0x02 Ex8) SOCKET 6 : 2KB, SOCKET 7 : 2KB 0xFE461F 0xFE471F 0x02 0x02 As shown above ex5) ~ ex8), total size of each SOCKET s TX memory (Sn_TXMEM_SIZE SUM ) is 16Kbytes. Sn_TX_FSR (SOCKET n TX Free Size Register)[R][(0xFE x100n) (0xFE n)][0x0000] Sn_TX_FSR SOCKET n Internal TX memory Free size( Byte size). Sn_TX_FIFOR Sn_TX_FSR Host-write. Sn_TX_FSR, Sn_TX_FSR SEND SEND_MAC command. TCP mode (DATA/ACK packet ), Sn_TX_FSR DATA packet. mode Sn_IR(SENDOK) = 1 Sn_TX_FSR Data size. Ex) In case of 2048(0x8000) in S0_TX_FSR, 0xFE4020 0xFE4021 0x08 0x00 Sn_TX_RD (SOCKET n TX Read Pointer Register)[R][(0xFE x100n) (0xFE x100n)][0x0000] Sn_TX_RD TX memory address. SOCKET n Command Register SEND Sn_TX_RD Sn_TX_WR.. Sn_TX_RD Sn_TX_WR. register, upper byte (0xFE4022, 0xFE4122, 0xFE4222, 0xFE4322, 0xFE4422, 0xFE4522, 0xFE4622, 0xFE4722) lower byte (0xFE4023, 0xFE4123, 0xFE4223, 0xFE4323, 0xFE4423, 0xFE4523, 0xFE4623, 0xFE4723). Sn_TX_WR (SOCKET n TX Write Pointer Register)[R/W][(0xFE x100n) (0xFE4025 Copyright 2009 WIZnet Co., Inc. All rights reserved. 89

90 + 0x100n)][0x0000] Sn_TX_WR write. register, upper byte (0xFE4024, 0xFE4124, 0xFE4224, 0xFE4324, 0xFE4424, 0xFE4524, 0xFE4624, 0xFE4724) lower byte (0xFE4025, 0xFE4125, 0xFE4225, 0xFE4325, 0xFE4425, 0xFE4525, 0xFE4625, 0xFE4725). Ex) In case of 2048(0x0800) in S0_TX_WR, 0xFE4024 0xFE4025 0x08 0x00 write physical address, physical address. 1. Sn_TXMEM_SIZE(n) SOCKET n TX Base Address (SBUFBASEADDRESS(n)) SOCKET n TX Mask Address (SMASK(n)). 2. bitwise-and operation, SOCKET TX memory Sn_TX_WR SMASK(n) offset address (dst_mask). 3. Dst_mask SBUFBASEADDRESS(n) physical address (dst_ptr)., dst_ptr write. ( SOCKET TX memory upper bound write, TX memory upper bound write. SBUFBASEADDRESS(n) physical address write., Sn_TX_WR writing. Sn_CR (SOCKET n Command Register) SEND. Copyright 2009 WIZnet Co., Inc. All rights reserved. 90

91 Figure 8.3 Calculate Physical Address Sn_RX_RSR (SOCKET n RX Received Size Register)[R][(0xFE x100n) (0xFE x100n)][0x0000] Sn_RX_RSR SOCKETn Internal RX memory byte size. SOCKET n Command Register (Sn_CR) RECV remote peer. register read, byte (0xFE4026, 0xFE4126, 0xFE4226, 0xFE4326, 0xFE4426, 0xFE4526, 0xFE4626, 0xFE4726) read byte (0xFE4027, 0xFE4127, 0xFE4227, 0xFE4327, 0xFE4427, Copyright 2009 WIZnet Co., Inc. All rights reserved. 91

92 0xFE4527, 0xFE4627, 0xFE4727) read. Ex) In case of 2048(0x0800) in S0_RX_RSR0, 0xFE4026 0xFE4027 0x08 0x00 Sn_RX_RSR RX memory size register. Sn_RX_RD (SOCKET n Read Pointer Register)[R/W][(0xFE x100n) (0xFE x100n)][0x0000] Sn_RX_RD read pointer. register read, read byte (0xFE4028, 0xFE4128, 0xFE4228, 0xFE4328, 0xFE4428, 0xFE4528, 0xFE4628, 0xFE4728) read byte (0xFE4029, 0xFE4129, 0xFE4229, 0xFE4329, 0xFE4429, 0xFE4529, 0xFE4629, 0xFE4729) read. Ex) In case of 2048(0x0800) in S0_RX_RD, 0x0428 0x0429 0x08 0x00 read physical address, physical address. 1. Sn_RXMEM_SIZE(n) SOCKET n RX Base Address (RBUFBASEADDRESS(n)) SOCKET n RX Mask Address (RMASK(n)). 2. bitwise-and operation, SOCKET RX memory Sn_RX_WR RMASK(n) offset address (src_mask). 3. src_mask RBUFBASEADDRESS(n) physical address (src_ptr)., src_ptr read. ( SOCKET RX memory upper bound read, RX memory upper bound read. RBUFBASEADDRESS(n) physical address read., Sn_RX_RD read. (, Sn_RX_RSR check.) Sn_CR (SOCKET n Command Register) RECV. Sn_RX_WR (SOCKET n RX Write Pointer Register)[R/W][(0xFE402A + 0x100n) (0xFE402B + 0x100n)][0x0000] Sn_RX_WR write pointer. register read, read byte (0xFE402A, 0xFE412A, 0xFE422A, 0xFE432A, 0xFE442A, 0xFE452A, 0xFE462A, 0xFE472A) read byte (0xFE402B, 0xFE412B, 0xFE422B, 0xFE432B, 0xFE442B, 0xFE452B, 0xFE462B, Copyright 2009 WIZnet Co., Inc. All rights reserved. 92

93 0xFE472B) read. Ex) In case of 2048(0x0800) in S0_RX_WR, 0xFE402A 0xFE402B 0x08 0x00 Sn_IMR (SOCKET n Interrupt Mask Register)[R/W][0xFE402C + 0x100n][0xFF] Sn_IMR Host SOCKET n Interrupt. Sn_IMR Interrupt mask bit Sn_IR Interrupt bit. SOCKET interrupt Sn_IMR bit 1 Sn_IR Bit 1. Sn_IMR Sn_IR bit 1 IR(n) = 1. IMR(n) = 1 Host Interrupt ( /INT signal low assert) Reserved Reserved Reserved SEND_OK TIMEOUT RECV DISCON CON Bit Symbol Description 7 Reserved Reserved 6 Reserved Reserved 5 Reserved Reserved 4 SENDOK Sn_IR(SENDOK) Interrupt Mask 3 TIMEOUT Sn_IR(TIMEOUT) Interrupt Mask 2 RECV Sn_IR(RECV) Interrupt Mask 1 DISCON Sn_IR(DISCON) Interrupt Mask 0 CON Sn_IR(CON) Interrupt Mask Sn_FRAG (SOCKET n Fragment Register)[R/W][(0xFE402D + 0x100n) (0xFE402E + 0x100n)][0x4000] Sn_FRAG IP layer IP header Fragment field. W7100 IP layer packet fragment. Sn_FRAG IP data fragment. Sn_FRAG OPEN command. Ex) Sn_FRAG0 = 0x4000 (Don t Fragment) 0xFE402D 0xFE402E 0x40 0x00 Copyright 2009 WIZnet Co., Inc. All rights reserved. 93

94 9 Functional Description W7100 general 8051 core TCPIPCore, Ethernet application. chapter W7100 Protocol(TCP, UDP, IPRAW, MACRAW) Pseudo code. 9.1 Initialization W MCU, Network, Internal TX/RX memory 3. STEP 1 : Initializes MCU 1. Interrupt setting 8051 enable / disable. 3. Interrupt System. 2. Memory Access timing setting Memory access timing 2. Data memory access timing CKCON(0x8E) Program memory access timing WTST(0x92) memory access timing. 0~7 W7100 CKCON 1~7, WTST 4~7,. W SFRs definition'. Ex) Setting:, 2 clock access time, 7 clock access time EA = 0; // Disable all interrupts CKCON = 0x01; // Set data memory access time WTST = 0x06; // Set code memory access time 3. Baud rate, register, interrupt setting for serial communication 1) For the serial communication, related registers of W7100 should be set. Serial W7100 TMOD, PCON, SCON. TMOD(89H): serial timer/counter. GATE C/T M 1 M 0 GATE C/T M 1 M 0 Copyright 2009 WIZnet Co., Inc. All rights reserved. 94

95 Table 12.1 Timer / Counter Mode M 1 M 0 Mode PCON(87H): serial rate SMOD bit. SMOD Table 12.2 Baud rate Mode SMOD = 0 SMOD = 1 1, 3 Timer/Counter 1 Timer/Counter 1 overflow overflow 1/2 2 XTAL 1/4 XTAL 1/2 SCON(98H): serial port serial port. SM 0 SM 1 SM 2 REN TB 8 RB 8 TI RI Table 12.3 Mode of UART SM 0 SM 1 Mode SM 2 : Mode 2, 3. bit 1, 9bit 1, 0. REN : enable bit( 1 ) TB 8 : 2, 3 8 bit RB 8 : 2, 3 8 bit TI : RI : 2) Serial. serial, serial disable. 3) Baud rate. W7100 Timer Copyright 2009 WIZnet Co., Inc. All rights reserved. 95

96 Baud rate 6.6 Examples of Baud Rate Setting. Timer1 TH1 = 256 ((K * MHz) / (384 * baud rate)) K = 1 at SMOD = 0, K = 2 at SMOD = 1 Timer2 (RCAP2H, RCAP2L) = ( MHz / (32 * baud rate)) Ex) Using timer mode 2, SMOD = 1, Clock speed = MHz, Baud rate = ET1= 0; // Timer1 INT disable TMOD = 0x20; // TIMER MODE 2 PCON = 0x80; // SMOD = 1 TH1 = 0xFC; // x (SMOD = 1) at MHz TR1 = 1; // Start the TIMER1 SCON = 0x50; // Serial MODE 1, REN = 1, TI = 0, RI = 0 ES = 0; // Serial interrupt disable RI = 0; // Receive interrupt disable TI = 0; // Transmit interrupt disable STEP 2 : Setting Network Information 1. Network : Network. SHAR(Source Hardware Address Register) SHAR Source hardware address Device Hardware address(ethernet MAC address) Ethernet MAC layer. MAC address IEEE, Network device Manufacture Network device IEEE MAC address. GAR(Gateway Address Register) SUBR(Subnet Mask Register) SIPR(Source IP Address Register) 2. Packet time & count. RTR(Retry Time-value Register), RTR 1 100us. RCR(Retry Count Register) STEP 3 : Allocation Internal TX/RX Memory for SOCKET n Copyright 2009 WIZnet Co., Inc. All rights reserved. 96

97 W7100 TX, RX 16KBytes. 16Kbytes 1KB, 2KB, 4KB, 8KB 8 TX, RX 8Kbyte. In case of, assign 2KB rx, tx memory per SOCKET { gs0_rx_base = 0xFE0000(Chip base address) + 0xFEC000(Internal RX buffer address); // Set base address of RX memory for SOCKET 0 Sn_RXMEM_SIZE(ch) = (uint8 *) 2; // Assign 2K rx memory per SOCKET gs0_rx_mask = 2K 1; // 0x07FF, for getting offset address within assigned SOCKET 0 RX memory gs1_rx_base = gs0_rx_base + (gs0_rx_mask + 1); gs1_rx_mask = 2K 1; gs2_rx_base = gs1_rx_base + (gs1_rx_mask + 1); gs2_rx_mask = 2K 1; gs3_rx_base = gs2_rx_base + (gs2_rx_mask + 1); gs3_rx_mask = 2K 1; gs4_rx_base = gs3_rx_base + (gs3_rx_mask + 1); gs4_rx_mask = 2K 1; gs5_rx_base = gs4_rx_base + (gs4_rx_mask + 1); gs5_rx_mask = 2K 1; gs6_rx_base = gs5_rx_base + (gs5_rx_mask + 1); gs6_rx_mask = 2K 1; gs7_rx_base = gs6_rx_base + (gs6_rx_mask + 1); gs7_rx_mask = 2K 1; gs0_tx_base = 0xFE0000(Chip base address) + 0xFE8000(Internal TX buffer address); // Set base address of TX memory for SOCKET 0 Sn_TXMEM_SIZE(ch) = (uint8 *) 2; // Assign 2K rx memory per SOCKET gs0_tx_mask = 2K 1; Same method, set gs1_tx_base, gs1_tx_mask, gs2_tx_base, gs2_tx_mask, gs3_tx_base, gs3_tx_mask, gs4_tx_base, gs4_tx_mask, gs5_tx_base, gs5_tx_mask, gs6_tx_base, gs6_tx_mask, gs7_tx_base, gs7_tx_mask. } Copyright 2009 WIZnet Co., Inc. All rights reserved. 97

98 Figure 9.1 Allocation Internal TX/RX memory of SOCKET n 3 W7100 Initialization, W7100 Ethernet Data communication. W7100 network Pingrequest packet Ping-reply. Copyright 2009 WIZnet Co., Inc. All rights reserved. 98

99 9.2 Data Communication Initialization W7100 TCP, UDP, IPRAW, MACRAW mode SOCKET open data. W7100 SOCKET 8. section mode TCP TCP Connection-oriented protocol. TCP IP address Port number IP address Port number Connection SOCKET, Connection SOCKET Data. Connection SOCKET TCP SERVER TCP CLIENT 2. connect-request(syn packet). TCP SERVER connect-request, connect-request accept Connection SOCKET (Passive-open). TCP CLIENT connect-request Connection SOCKET (Active-open). Figure 9.2 TCP SERVER & TCP CLIENT Copyright 2009 WIZnet Co., Inc. All rights reserved. 99

100 TCP SERVER Figure 9.3 TCP SERVER Operation Flow SOCKET Initialization TCP Data communication SOCKET Initialization. SOCKET open. SOCKET open W SOCKET SOCKET Protocol mode(sn_mr(p3:p0)) Source port number( TCP SERVER Listen port number ) Sn_PORT0, OPEN command. OPEN command Sn_SR SOCK_INIT SOCKET initialization. SOCKET initialization TCP SEVER TCP CLIENT. Socket n TCP mode Initialization. Copyright 2009 WIZnet Co., Inc. All rights reserved. 100

101 { START: Sn_MR = 0x0001; // sets TCP mode Sn_PORT0 = source_port; // sets source port number Sn_CR = OPEN; // sets OPEN command /* wait until Sn_SR is changed to SOCK_INIT */ if (Sn_SR!= SOCK_INIT) Sn_CR = CLOSE; goto START; } LISTEN LISTEN command TCP SERVER. { /* listen SOCKET */ Sn_CR = LISTEN; /* wait until Sn_SR is changed to SOCK_LISTEN */ if (Sn_SR!= SOCK_LISTEN) Sn_CR = CLOSE; goto START; } ESTABLISHMENT Sn_SR SOCK_LISTEN SYN packet Sn_SR SOCK_SYNRECV SYN/ACK packet Socket n Connection. Socket n Connection data communication. Socket n connection 2. First method : { if (Sn_IR(CON) == 1 ) Sn_IR(CON) = 1 ; goto ESTABLISHED stage; /* In this case, if the interrupt of SOCKET n is activated, interrupt occurs. Refer to IR, IMR Sn_IMR and Sn_IR. */ } Second method : { if (Sn_SR == SOCK_ESTABLISHED) goto ESTABLISHED stage; } ESTABLISHMENT: check TCP data. Copyright 2009 WIZnet Co., Inc. All rights reserved. 101

102 First method : { if (Sn_IR(RECV) == 1 ) Sn_IR(RECV) = 1 ; goto Receiving Process stage; /* In this case, if the interrupt of SOCKET n is activated, interrupt occurs. Refer to IR, IMR Sn_IMR and Sn_IR. */ } Second Method : { if (Sn_RX_RSR0!= 0x ) goto Receiving Process stage; } First method DATA packet Sn_IR(RECV) 1. Host DATA packet Sn_IR(RECV) W7100 DATA packet, Sn_IR(RECV) Host DATA packet Sn_IR(RECV). Host Sn_IR(RECV) DATA packet. ESTABLISHMENT: Receiving process RX memory TCP. TCP mode Data Socket n RX memory free size W7100 data, RX memory free size connection. Receive / Send process wizmemcpy memory copy routine W7100. wizmemcpy memory copy. W7100 data TCPIPCore internal. TCPIPCore RX data memory memory copy TCPIPCore internal 0xFE DPX0 0xFE. wizmemcpy W7100 Driver Guide. { /* first, get the received size */ len = Sn_RX_RSR0; // len is received size /* calculate offset address */ src_mask = Sn_RX_RD0 & gsn_rx_mask; // src_mask is offset address /* calculate start address(physical address) */ src_ptr = gsn_rx_base + src_mask; // src_ptr is physical start address Copyright 2009 WIZnet Co., Inc. All rights reserved. 102

103 } /* if overflow SOCKET RX memory */ If((src_mask + len) > (gsn_rx_mask + 1)) { /* copy upper_size bytes of get_start_address to destination_address */ upper_size = (gsn_rx_mask + 1) src_mask; wizmemcpy((0xfe src_ptr), (0x destination_address), upper_size); /* update destination_address */ destination_address += upper_size; /* copy left_size bytes of gsn_rx_base to destination_address */ left_size = len upper_size; wizmemcpy((0xfe src_ptr), (0x destination_address), left_size); } else { copy len bytes of src_ptr to destination_address */ wizmemcpy((0xfe src_ptr), (0x destination_address), len); } /* increase Sn_RX_RD0 as length of len */ Sn_RX_RD0 += len; /* set RECV command */ Sn_CR = RECV; ESTABLISHMENT: Check send data / Send process data Socket n Internal TX memory, data MSS MSS. data SEND command. SEND command SEND command. Data SEND command, Data. Send process receive process TCPIPCore internal 0xFE. { /* first, get the free TX memory size */ FREESIZE: freesize = Sn_TX_FSR0; if (freesize < len) goto FREESIZE; // len is send size Copyright 2009 WIZnet Co., Inc. All rights reserved. 103

104 } /* calculate offset address */ dst_mask= Sn_TX_WR0 & gsn_tx_mask; // dst_mask is offset address /* calculate start address(physical address) */ dst_ptr = gsn_tx_base + dst_mask; // dst_ptr is physical start address /* if overflow SOCKET TX memory */ if ( (dst_mask + len) > (gsn_tx_mask + 1) ) { /* copy upper_size bytes of source_addr to dst_ptr */ upper_size = (gsn_tx_mask + 1) dst_mask; wizmemcpy((0x source_addr), (0xFE dst_ptr), upper_size); /* update source_addr*/ source_addr += upper_size; /* copy left_size bytes of source_addr to gsn_tx_base */ left_size = len upper_size; wizmemcpy((0x source_addr), (0xFE gsn_tx_base), left_size); } else { /* copy len bytes of source_addr to dst_ptr */ wizmemcpy((0x source_addr), (0xFE dst_ptr), len); } /* increase Sn_TX_WR as length of len */ Sn_TX_WR0 += send_size; /* set SEND command */ Sn_CR = SEND; ESTABLISHMENT: Check disconnect-request(fin packet) disconnect-request(fin packet). FIN packet. First method : { if (Sn_IR(DISCON) == 1 ) Sn_IR(DISCON)= 1 ; goto CLOSED stage; /* In this case, if the interrupt of SOCKET n is activated, interrupt occurs. Refer to IR, IMR Sn_IMR and Sn_IR. */ } Copyright 2009 WIZnet Co., Inc. All rights reserved. 104

105 Second method : { if (Sn_SR == SOCK_CLOSE_WAIT) goto CLOSED stage; } ESTABLISHMENT : Check disconnect / disconnecting process data communication FIN packet connection SOCKET disconnect. { /* set DISCON command */ Sn_CR = DISCON; } ESTABLISHMENT: Check closed DISCON CLOSE command Socket n Disconnect close. First method : { if (Sn_IR(DISCON) == 1 ) goto CLOSED stage; /* In this case, if the interrupt of SOCKET n is activated, interrupt occurs. Refer to IR, IMR Sn_IMR and Sn_IR. */ } Second method : { if (Sn_SR == SOCK_CLOSED) goto CLOSED stage; } ESTABLISHMENT: Timeout Timeout connect-request(syn packet) (SYN/ACK packet), DATA packet (DATA/ACK packet), disconnect-request(fin packet) (FIN/ACK packet), TCP packet. RTR RCR Timeout packet TCP final timeout(tcp TO ) Sn_SR SOCK_CLOSED. TCP TO. First method : { if (Sn_IR(TIMEOUT bit) == 1 ) Sn_IR(TIMEOUT)= 1 ; goto CLOSED stage; /* In this case, if the interrupt of SOCKET n is activated, interrupt occurs. Refer to IR, IMR Sn_IMR and Sn_IR. */ Copyright 2009 WIZnet Co., Inc. All rights reserved. 105

106 } Second method : { if (Sn_SR == SOCK_CLOSED) goto CLOSED stage; } SOCKET close Disconnect-process disconnection SOCKET TCP TO Close SOCKET close, Host disconnect-process SOCKET close. { /* clear the remained interrupts of SOCKET n*/ Sn_IR = 0x00FF; IR(n) = 1 ; /* set CLOSE command */ Sn_CR = CLOSE; } Copyright 2009 WIZnet Co., Inc. All rights reserved. 106

107 TCP CLIENT TCP client CONNECT state state TCP SEVER TCP SERVER. Figure 9.5 TCP CLIENT Operation Flow CONNECT TCP SERVER connect-request (SYN packet). TCP SERVER Connection SOCKET ARP TO, TCP TO Timeout. { Sn_DIPR0 = server_ip; /* set TCP SERVER IP address*/ Sn_DPORT0 = server_port; /* set TCP SERVER listen port number*/ Sn_CR = CONNECT; /* set CONNECT command */ } Copyright 2009 WIZnet Co., Inc. All rights reserved. 107

108 9.2.2 UDP UDP Connection-less protocol. UDP TCP Connection SOCKET data. TCP data, UDP data datagram protocol. UDP connection SOCKET IP address Port number. datagram SOCKET, data data., Host data, data. UDP unicast, broadcast, multicast, flow. Figure 9.6 UDP Operation Flow Unicast & Broadcast Unicast UDP, Data., Broadcast Broadcast IP address( ) Data. A, B, C Data, Unicast A, B, C Data. A, B, C Destination hardware address (ARP-process) ARP TO, ARP TO Data. Broadcast IP address Data A, B, C Data. A, B, C Destination hardware address, ARP TO. Copyright 2009 WIZnet Co., Inc. All rights reserved. 108

109 SOCKET Initialization UDP data communication SOCKET initialization. SOCKET open. SOCKET open W SOCKET, SOCKET protocol mode(sn_mr(p3:p0)) source port number Sn_PORT0, OPEN command. OPEN command Sn_SR SOCK_UDP SOCKET initialization. { START: Sn_MR = 0x02; /* sets UDP mode */ Sn_PORT0 = source_port; /* sets source port number */ Sn_CR = OPEN; /* sets OPEN command */ /* wait until Sn_SR is changed to SOCK_UDP */ if (Sn_SR!= SOCK_UDP) Sn_CR = CLOSE; goto START; } Check received data UDP data. TCP. TCP Second method TCP SERVER. First method : { if (Sn_IR(RECV) == 1 ) Sn_IR(RECV) = 1 ; goto Receiving Process stage; /* In this case, if the interrupt of SOCKET n is activated, interrupt occurs. Refer to IR, IMR Sn_IMR and Sn_IR. */ } Second Method : { if (Sn_RX_RSR0!= 0x ) goto Receiving Process stage; } Receiving process Internal RX memory UDP Data. UDP data. Figure 9.7 The received UDP data format Copyright 2009 WIZnet Co., Inc. All rights reserved. 109

110 UDP data 8bytes PACKET-INFO data packet, PACKET-INFO (IP address, Port number) data packet. UDP UDP data. PACKET-INFO IP address broadcast. Host PACKET-INFO data packet. data SOCKET Internal RX memory free size data, fragment data. { /* first, get the received size */ len = Sn_RX_RSR0; // len is received size /* calculate offset address */ src_mask = Sn_RX_RD0 & gsn_rx_mask; // src_mask is offset address /* calculate start address(physical address) */ src_ptr = gsn_rx_base + src_mask; // src_ptr is physical start address /* read head information (8 bytes) */ header_size = 8; /* if overflow SOCKET RX memory */ if ( (src_mask + header_size) > (gsn_rx_mask + 1) ) { /* copy upper_size bytes of src_ptr to header_addr */ upper_size = (gsn_rx_mask + 1) src_mask; wizmemcpy((0xfe src_ptr), (0x header_addr), upper_size); /* update header_addr*/ header_addr += upper_size; /* copy left_size bytes of gsn_rx_base to header_addr */ left_size = header_size upper_size; wizmemcpy((0xfe gsn_rx_base), (0x header_addr), left_size); /* update src_mask */ src_mask = left_size; } else { /* copy header_size bytes of get_start_address to header_addr */ wizmemcpy((0xfe src_ptr), (0x header_addr), header_size); /* update src_mask */ src_mask += header_size; Copyright 2009 WIZnet Co., Inc. All rights reserved. 110

111 } } /* update src_ptr */ src_ptr = gsn_rx_base + src_mask; /* save remote peer information & received data size */ peer_ip = header[0 to 3]; peer_port = header[4 to 5]; get_size = header[6 to 7]; /* if overflow SOCKET RX memory */ if ( (src_mask + len) > (gsn_rx_mask + 1) ) { /* copy upper_size bytes of src_ptr to destination_addr */ upper_size = (gsn_rx_mask + 1) src_mask; wizmemcpy((0xfe src_ptr), (0x destination_addr), upper_size); /* update destination_addr*/ destination_addr += upper_size; /* copy left_size bytes of gsn_rx_base to destination_addr */ left_size = get_size upper_size; wizmemcpy((0xfe gsn_rx_base), (0x destination_addr), left_size); } else { /* copy len bytes of src_ptr to destination_addr */ wizmemcpy((0xfe src_ptr), (0x destination_addr), get_size); } /* increase Sn_RX_RD0 as length of len + header_size */ Sn_RX_RD0 = Sn_RX_RD0 + len + header_size; /* set RECV command */ Sn_CR = RECV; Check send data / Sending process data SOCKET internal TX memory, data MTU MTU. Broadcast Sn_DIPR { /* first, get the free TX memory size */ FREESIZE: Copyright 2009 WIZnet Co., Inc. All rights reserved. 111

112 } freesize = Sn_TX_FSR0; if (freesize < len) goto FREESIZE; // len is send size /* Write the value of remote_ip, remote_port to the SOCKET n Destination IP Address Register(Sn_DIPR), SOCKET n Destination Port Register(Sn_DPORT). */ Sn_DIPR0 = remote_ip; Sn_DPORT0 = remote_port; /* calculate offset address */ dst_mask = Sn_TX_WR0 & gsn_tx_mask; // dst_mask is offset address /* calculate start address(physical address) */ dst_ptr = gsn_tx_base + dst_mask; // dst_ptr is physical start address /* if overflow SOCKET TX memory */ if ( (dst_mask + len) > (gsn_tx_mask + 1) ) { /* copy upper_size bytes of source_address to dst_ptr */ upper_size = (gsn_tx_mask + 1) dst_mask; wizmemcpy((0x source_address), (0xFE dst_ptr), upper_size); /* update source_address */ source_address += upper_size; /* copy left_size bytes of source_address to gsn_tx_base */ left_size = send_size upper_size; wizmemcpy((0x source_address), (0xFE gsn_tx_base), left_size); } else { /* copy len bytes of source_address to dst_ptr */ wizmemcpy((0x source_address), (0xFE dst_ptr), len); } /* increase Sn_TX_WR0 as length of len */ Sn_TX_WR0 += len; /* set SEND command */ Sn_CR = SEND; Check complete sending / Timeout Data SEND command. Data SEND command, Data. UDP data ARP TO, ARP TO UDP data. Copyright 2009 WIZnet Co., Inc. All rights reserved. 112

113 First method : { /* check SEND command completion */ while(sn_ir(sendok)== 0 ) /* wait interrupt of SEND completion */ { /* check ARP TO */ if (Sn_IR(TIMEOUT)== 1 ) Sn_IR(TIMEOUT)= 1 ; goto Next stage; } Sn_IR(SENDOK) = 1 ; /* clear previous interrupt of SEND completion */ } Second method : { If (Sn_CR == 0x00) transmission is completed. If (Sn_IR(TIMEOUT bit) == 1 ) goto next stage; /* In this case, if the interrupt of SOCKET n is activated, interrupt occurs. Refer to Interrupt Register(IR), Interrupt Mask Register (IMR) and SOCKET n Interrupt Register (Sn_IR). */ } Check Finished / SOCKET close Socket n close. { /* clear remained interrupts */ Sn_IR = 0x00FF; IR(n) = 1 ; /* set CLOSE command */ Sn_CR = CLOSE; } Multicast Broadcast, multicast multicast-group. A, B, C multicast-group, A multicast-group data B, C A data. multicast IGMP protocol multicast-group. multicast-group group hardware address, Group IP address, group port number. Group hardware address IP address address, group port number. Copyright 2009 WIZnet Co., Inc. All rights reserved. 113

114 Group hardware address ( 01:00:5e:00:00:00 01:00:5e:7f:ff:ff ), Group IP address D-class IP address ( , 6bytes group hardware address 4bytes IP address 23bit., Group IP address group hardware address 01:00:5e:01:01:0b. RFC1112 ( W7100 multicast-group IGMP (Automatically). SOCKET n multicast mode open IGMP Join message, close Leave message. SOCKET open Report message. W7100 IGMP version 1 version 2 version, IPRAW mode SOCKET host IGMP. SOCKET Initialization Multicast 8 SOCKET, Sn_DHAR0 multicast-group hardware address Sn_DIPR0 multicast-group IP address. Sn_PORT0 Sn_DPORT0 multicast-group port number. Sn_MR(P3:P0) UDP Sn_MR (MULTI) 1 OPEN command. OPEN command Sn_SR SOCK_UDP SOCKET initialization. { START: /* set Multicast-Group information */ Sn_DHAR0 = 0x01; /* set Multicast-Group H/W address(01:00:5e:01:01:0b) */ Sn_DHAR1 = 0x00; Sn_DHAR2 = 0x5E; Sn_DHAR3 = 0x01; Sn_DHAR4 = 0x01; Sn_DHAR5 = 0x0B; Sn_DIPR0 = 211; /* set Multicast-Group IP address( ) */ Sn_DIPR1 = 1; Sn_DIPR2 = 1; Sn_DIRP3 = 11; Sn_DPORT0 = 0x0BB8; /* set Multicast-Group Port number(3000) */ Sn_PORT0 = 0x0BB8; /* set Source Port number(3000) */ Sn_MR = 0x02 0x80; /* set UDP mode & Multicast on SOCKET n Mode Register */ Copyright 2009 WIZnet Co., Inc. All rights reserved. 114

115 Sn_CR = OPEN; /* set OPEN command */ /* wait until Sn_SR is changed to SOCK_UDP */ if (Sn_SR!= SOCK_UDP) Sn_CR = CLOSE; goto START; } Check received data Unicast & Broadcast. Receiving process Unicast & Broadcast. Check send data / Sending Process SOCKET initialization multicast-group, unicast IP address port number. data internal TX memory copy SEND command. { /* first, get the free TX memory size */ FREESIZE: freesize = Sn_TX_FSR0; if (freesize < len) goto FREESIZE; // len is send size /* calculate offset address */ dst_mask = Sn_TX_WR0 & gsn_tx_mask; // dst_mask is offset address /* calculate start address(physical address) */ dst_ptr = gsn_tx_base + dst_mask; // dst_ptr is physical start address /* if overflow SOCKET TX memory */ if ( (dst_mask + len) > (gsn_tx_mask + 1) ) { /* copy upper_size bytes of source_addr to dst_ptr */ upper_size = (gsn_tx_mask + 1) dst_mask; wizmemcpy((0x source_addr), (0xFE dst_ptr), upper_size); /* update source_addr*/ source_addr += upper_size; /* copy left_size bytes of source_addr to gsn_tx_base */ left_size = len upper_size; wizmemcpy((0x source_addr), (0xFE gsn_tx_base), left_size); } else Copyright 2009 WIZnet Co., Inc. All rights reserved. 115

116 { /* copy len bytes of source_addr to dst_ptr */ wizmemcpy((0x source_addr), (0xFE dst_ptr), len); } /* increase Sn_TX_WR as length of len */ Sn_TX_WR0 += send_size; /* set SEND command */ Sn_CR = SEND; } Check complete sending / Timeout Data Protocol Host Timeout. { /* check SEND command completion */ while(s0_ir(sendok)== 0 ); /* wait interrupt of SEND completion */ S0_IR(SENDOK) = 1 ; /* clear previous interrupt of SEND completion */ } Check finished / SOCKET close Unicast & Broadcast IPRAW IPRAW TCP UDP protocol IP layer Data. IPRAW protocol number ICMP(0x01), IGMP(0x02) IP layer protocol. ICMP ping IGMP v1/v2 W7100 Hardware logic. Host Socket n IPRAW mode open. IPRAW mode SOCKET, protocol IP header protocol number field. Protocol number IANA ( ). Protocol number SOCKET Open Sn_PROTO. W7100 IPRAW mode TCP(0x06) UDP(0x11) protocol number. IPRAW mode SOCKET protocol number. ICMP SOCKET IGMP Protocol Data. Copyright 2009 WIZnet Co., Inc. All rights reserved. 116

117 Figure 9.8 IPRAW Operation Flow SOCKET Initialization SOCKET Protocol number. Sn_MR (P3:P0) IPRAW mode OPEN command. OPEN command Sn_SR SOCK_IPRAW SOCKET initialization. { START: /* sets Protocol number */ /* The protocol number is used in Protocol Field of IP Header. */ Sn_PROTO = protocol_num; /* sets IP raw mode */ Sn_MR = 0x03; /* sets OPEN command */ Sn_CR = OPEN; /* wait until Sn_SR is changed to SOCK_IPRAW */ if (Sn_SR!= SOCK_IPRAW) Sn_CR = CLOSE; goto START; } Check received data Unicast & Broadcast. Receiving process Internal RX Memory IPRAW Data. IPRAW Data Figure 9.9. Copyright 2009 WIZnet Co., Inc. All rights reserved. 117

118 Figure 9.9 The received IPRAW data format IPRAW data 6 bytes PACKET-INFO data packet, PACKET-INFO (IP address) data packet. IPRAW mode data UDP PACKET-INFO port number UDP data Unicast & Broadcast. Data SOCKET n RX memory free size data, fragmented data. Check send data / Sending process data SOCKET n internal TX memory, default MTU. IPRAW data UDP data destination port number Unicast & Broadcast. Complete sending / Timeout UDP, UDP. Check finished / SOCKET closed UDP, UDP MACRAW MACRAW Ethernet MAC protocol host. MACRAW mode SOCKET 0. SOCKET 0 MACRAW SOCKET 1 7 hardwired TCP/IP stack, SOCKET 0 NIC(Network Interface Controller) software TCP/IP stack. W7100 hardwired TCP/IP software TCP/IP hybrid TCP/IP stack. W SOCKET SOCKET, SOCKET hardwired TCP/IP stack, MACRAW mode software TCP/IP SOCKET. MACRAW mode SOCKET 0 SOCKET 1 7 protocol protocol. MACRAW Ethernet packet MACRAW protocol software TCP/IP stack. MACRAW data Ethernet MAC Copyright 2009 WIZnet Co., Inc. All rights reserved. 118

119 6bytes source hardware address, 6bytes destination hardware address, 2 bytes Ethernet type 14bytes. Figure 9.10 MACRAW Operation Flow SOCKET Initialization SOCKET Sn_MR(P3:P0) MACRAW mode OPEN command. OPEN command Sn_SR SOCK_MACRAW SOCKET initialization. (Source hardware address, Source IP address, Source port number, Destination hardware address, Destination IP address, Destination port number, Protocol header, ETC) MACRAW Data register. { START: /* sets MAC raw mode */ S0_MR = 0x04; /* sets OPEN command */ S0_CR = OPEN; /* wait until Sn_SR is changed to SOCK_MACRAW */ if (Sn_SR!= SOCK_MACRAW) S0_CR = CLOSE; goto START; } Check received data Unicast & Broadcast. Copyright 2009 WIZnet Co., Inc. All rights reserved. 119

120 Receiving process SOCKET 0 internal RX memory MACRAW data. MACRAW data Figure Figure 9.11 The received MACRAW data format MACRAW data 2 bytes PACKET-INFO, data packet, 4bytes CRC. PACKET- INFO data packet, data packet 6bytes destination MAC address, 6bytes source MAC address, 2bytes type, 46~1500 bytes payload. Data packet Payload Type ARP, IP Internet protocol. Type { /* first, get the received size */ len = Sn_RX_RSR0; // len is received size /* calculate offset address */ src_mask = Sn_RX_RD0 & gsn_rx_mask; // src_mask is offset address /* calculate start address(physical address) */ src_ptr = gsn_rx_base + src_mask; // src_ptr is physical start address /* if overflow SOCKET RX memory */ If((src_mask + len) > (gsn_rx_mask + 1)) { /* copy upper_size bytes of get_start_address to destination_address */ upper_size = (gsn_rx_mask + 1) src_mask; wizmemcpy((0xfe src_ptr), (0x destination_address), upper_size); /* update destination_address */ destination_address += upper_size; /* copy left_size bytes of gsn_rx_base to destination_address */ left_size = len upper_size; wizmemcpy((0xfe src_ptr), (0x destination_address), left_size); } else { /* copy len bytes of src_ptr to destination_address */ wizmemcpy((0xfe src_ptr), (0x destination_address), len); Copyright 2009 WIZnet Co., Inc. All rights reserved. 120

121 } /* increase Sn_RX_RD0 as length of len */ Sn_RX_RD0 += len; /* extract 4 bytes CRC from internal RX memory and then ignore it */ wizmemcpy((0xfe src_ptr), (0x dummy), len); /* set RECV command */ Sn_CR = RECV; } <Notice> Internal RX memory free size W7100 MACRAW data, MACRAW data PACKET-INFO data packet internal RX memory. sample code PACKET- INFO MACRAW data. internal RX memory Full. MACRAW data. Internal RX memory Full. SOCKET Initialization Sample code S0_MR MF(MAC Filter) bit MACRAW data. { START: /* sets MAC raw mode with enabling MAC filter */ S0_MR = 0x44; /* sets OPEN command */ S0_CR = OPEN; /* wait until Sn_SR is changed to SOCK_MACRAW */ if (Sn_SR!= SOCK_MACRAW) S0_CR = CLOSE; goto START; } Internal RX memory free size default MTU(1514)+PACKET-INFO(2) + data packet(8) + CRC(4) - SOCKET0 close MACRAW data SOCKET 0 open. SOCKET 0 close MACRAW data. { /* check the free size of internal RX memory */ if((sn_rxmem_size(0) * 1024) - Sn_RX_RSR0(0) < 1528) { recved_size = Sn_RX_RSR0(0); /* backup Sn_RX_RSR */ Copyright 2009 WIZnet Co., Inc. All rights reserved. 121

122 Sn_CR0 = CLOSE; /* SOCKET Closed */ while(sn_sr!= SOCK_CLOSED); /* wait until SOCKET is closed */ /* process all data remained in internal RX memory */ while(recved_size > 0) {/* calculate offset address */ src_mask = Sn_RX_RD0 & gsn_rx_mask; // src_mask is offset address /* calculate start address(physical address) */ src_ptr = gsn_rx_base + src_mask; // src_ptr is physical start address /* if overflow SOCKET RX memory */ If((src_mask + len) > (gsn_rx_mask + 1)) { /* copy upper_size bytes of get_start_address to destination_address */ upper_size = (gsn_rx_mask + 1) src_mask; wizmemcpy((0xfe src_ptr), (0x destination_address), upper_size); /* update destination_address */ destination_address += upper_size; /* copy left_size bytes of gsn_rx_base to destination_address */ left_size = len upper_size; wizmemcpy((0xfe src_ptr), (0x destination_address), left_size); } else { /* copy len bytes of src_ptr to destination_address */ wizmemcpy((0xfe src_ptr), (0x destination_address), len); } /* increase Sn_RX_RD0 as length of len */ Sn_RX_RD0 += len; /* extract 4 bytes CRC from internal RX memory and then ignore it */ wizmemcpy((0xfe src_ptr), (0x dummy), len); /* calculate the size of remained data in internal RX memory*/ recved_size = recved_size 2 len 4; } /* Reopen the SOCKET */ /* sets MAC raw mode with enabling MAC filter */ S0_MR = 0x44; /* or S0_MR = 0x04 */ /* sets OPEN command */ S0_CR = OPEN; Copyright 2009 WIZnet Co., Inc. All rights reserved. 122

123 /* wait until Sn_SR is changed to SOCK_MACRAW */ while (Sn_SR!= SOCK_MACRAW); } else /* process normally the DATA packet from internal RX memory */ {/* This block is same as the code of Receiving process stage*/ } } Check send data / Sending process Data SOCKET 0 internal TX memory, default MTU. Host Receiving process data packet MACRAW data data. data 60 bytes Ethernet packet 60bytes Zero padding. { /* first, get the free TX memory size */ FREESIZE: freesize = S0_TX_FSR0; if (freesize < send_size) goto FREESIZE; /* calculate offset address */ dst_mask = Sn_TX_WR0 & gsn_tx_mask; // dst_mask is offset address /* calculate start address(physical address) */ dst_ptr = gsn_tx_base + dst_mask; // dst_ptr is physical start address /* if overflow SOCKET TX memory */ if ( (dst_mask + len) > (gsn_tx_mask + 1) ) {/* copy upper_size bytes of source_addr to dst_ptr */ upper_size = (gsn_tx_mask + 1) dst_mask; wizmemcpy((0x source_addr), (0xFE dst_ptr), upper_size); /* update source_addr*/ source_addr += upper_size; /* copy left_size bytes of source_addr to gsn_tx_base */ left_size = len upper_size; wizmemcpy((0x source_addr), (0xFE gsn_tx_base), left_size); } else {/* copy len bytes of source_addr to dst_ptr */ Copyright 2009 WIZnet Co., Inc. All rights reserved. 123

124 wizmemcpy((0x source_addr), (0xFE dst_ptr), len); } /* increase Sn_TX_WR as length of len */ Sn_TX_WR0 += send_size; /* set SEND command */ S0_CR = SEND; } Check complete sending Data protocol host timeout. { /* check SEND command completion */ while(s0_ir(sendok)== 0 ); /* wait interrupt of SEND completion */ S0_IR(SENDOK) = 1 ; /* clear previous interrupt of SEND completion */ } Check finished / SOCKET close Unicast & Broadcast. Copyright 2009 WIZnet Co., Inc. All rights reserved. 124

125 10 Electrical Specification Absolute Maximum Ratings Symbol Parameter Rating Unit V DD DC supply voltage -0.5 to 3.6 V V IN DC input voltage -0.5 to 5.5 (5V tolerant) V V OUT 2 to 2.5 (GPIO) DC output voltage -0.5 to 3.6 (Others) V I IN DC input current 5 ma I OUT DC output current 2 to 8 ma T OP Operating temperature 0 to 80 C T STG Storage temperature -55 to 125 C *COMMENT: Device Absolute Maximum Ratings damage. GPIO driving voltage 2.5V, 3.3V driving voltage pull-up. DC Characteristics Symbol Parameter Test Condition Min Typ Max Unit V DD DC Supply voltage Junction V temperature is from -55 C to 125 C V IH High level input voltage V V IL Low level input voltage V V OH High level output voltage IOH = 2 ~ 16 ma 2.4 V V OL Low level output voltage IOL = -2 ~ -12 ma 0.4 V I I Input Current V IN = V DD 5 A I O Output Current V OUT = V DD 2 8 ma Power consumption(driving voltage 3.3V) Symbol Parameter Test Condition Max Unit I Boot Current consumption Booting 250 ma I Idle Current consumption Idle state 220 ma I Active Current consumption Whole 8 SOCKETs running 220 ma Copyright 2009 WIZnet Co., Inc. All rights reserved. 125

126 AC Characteristics Reset Timing Description Min Max 1 Reset Cycle Time 2 us - 2 PLL Lock-in Time 50 us 10 ms Data Memory Read Timing Data memory MOVX access. Memory access time ready input 2 wait state. Figure 10.1 Waveform for data memory Read Cycle with Minimal Wait States(CKCON = 2 ) Note: 1. clk system clock frequency (clk = MHz) 2. ADDRESS Actually read the memory address 3. DATA Data read form address 4. Read sample Data of data memory has been read from (address) cell into ACC register 5. DATA_RD Read strobe signal Copyright 2009 WIZnet Co., Inc. All rights reserved. 126

127 Data Memory Write Timing Figure 10.2 Waveform for data memory Write Cycle with Minimal Wait States(CKCON = 2 ) Note: 1. clk System clock period (clk = MHz) 2. ADDRESS Written in the memory address 3. DATA Data written into address 4. XDATA data memory cell Crystal Characteristics Parameter Frequency Frequency Tolerance (at 25) Shunt Capacitance Drive Level Load Capacitance Aging (at 25) Range 25 MHz ±30 ppm 7pF Max 1 ~ 500uW (100uW typical) 18pF ±3ppm / year Max Transformer Characteristics Parameter Transmit End Receive End Turn Ratio 1:1 1:1 Inductance 350 uh 350 uh Copyright 2009 WIZnet Co., Inc. All rights reserved. 127

128 PHY, Auto MDI/MDIX (Crossover) symmetric transformer. PHY, PHY specification transformer. Copyright 2009 WIZnet Co., Inc. All rights reserved. 128

129 11 IR Reflow Temperature Profile (Lead-Free) Moisture Sensitivity Level: 3 Dry Pack Required: Yes Average RAMp-Up Rate 3 C/second max. (Ts max to Tp) Preheat Temperature Min (Ts min ) 150 C Temperature Max (Ts max ) 200 C Time (ts min to ts max ) seconds Time maintained above: Temperature (TL) 217 C Time (tl) seconds Peak/Classification Temperature (Tp) C Time within 5 C of actual Peak Temperature (tp) seconds RAMp-Down Rate 6 C/second max. Time 25 C to Peak Temperature 8 minutes max. Copyright 2009 WIZnet Co., Inc. All rights reserved. 129